fsl_xcvr_trim.h

00001 /*
00002 * Copyright 2016-2017 NXP
00003 *
00004 * Redistribution and use in source and binary forms, with or without modification,
00005 * are permitted provided that the following conditions are met:
00006 *
00007 * o Redistributions of source code must retain the above copyright notice, this list
00008 *   of conditions and the following disclaimer.
00009 *
00010 * o Redistributions in binary form must reproduce the above copyright notice, this
00011 *   list of conditions and the following disclaimer in the documentation and/or
00012 *   other materials provided with the distribution.
00013 *
00014 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00015 *   contributors may be used to endorse or promote products derived from this
00016 *   software without specific prior written permission.
00017 *
00018 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00019 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00020 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00021 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00022 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00023 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00024 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00025 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00026 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00027 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00028 */
00029 #ifndef _FSL_XCVR_TRIM_H_
00030 /* Clang-format off. */
00031 #define _FSL_XCVR_TRIM_H_
00032 /* Clang-format on. */
00033 
00034 #include "fsl_device_registers.h"
00035 /*!
00036 * @addtogroup xcvr
00037 * @{
00038 */
00039 #ifdef __cplusplus
00040 extern "C" {
00041 #endif
00042 /*! @file*/
00043 
00044 /************************************************************************************
00045 *************************************************************************************
00046 * Public constant definitions
00047 *************************************************************************************
00048 ************************************************************************************/
00049 
00050 /************************************************************************************
00051 *************************************************************************************
00052 * Public type definitions
00053 *************************************************************************************
00054 ************************************************************************************/
00055 
00056 /* \brief  The enumerations used to define the I & Q channel selections. */
00057 typedef enum
00058 {
00059     I_CHANNEL = 0,
00060     Q_CHANNEL = 1,
00061     NUM_I_Q_CHAN = 2
00062 } IQ_t;
00063 
00064 typedef enum /* Enumeration of ADC_GAIN_CAL 2 */
00065 {
00066     NOMINAL2 = 0,
00067     BBF_NEG = 1,
00068     BBF_POS = 2,
00069     TZA_STEP_N0 = 3,
00070     TZA_STEP_N1 = 4,
00071     TZA_STEP_N2 = 5,
00072     TZA_STEP_N3 = 6,
00073     TZA_STEP_N4 = 7,
00074     TZA_STEP_N5 = 8,
00075     TZA_STEP_N6 = 9,
00076     TZA_STEP_N7 = 10,
00077     TZA_STEP_N8 = 11,
00078     TZA_STEP_N9 = 12,
00079     TZA_STEP_N10 = 13,
00080     TZA_STEP_P0 = 14,
00081     TZA_STEP_P1 = 15,
00082     TZA_STEP_P2 = 16,
00083     TZA_STEP_P3 = 17,
00084     TZA_STEP_P4 = 18,
00085     TZA_STEP_P5 = 19,
00086     TZA_STEP_P6 = 20,
00087     TZA_STEP_P7 = 21,
00088     TZA_STEP_P8 = 22,
00089     TZA_STEP_P9 = 23,
00090     TZA_STEP_P10 = 24,
00091 
00092     NUM_SWEEP_STEP_ENTRIES2 = 25 /* Including the baseline entry #0. */
00093 } DAC_SWEEP_STEP2_t;
00094 
00095 /* \brief  Defines an entry in an array of structs to describe TZA DCOC STEP and TZA_DCOC_STEP_RECIPROCAL. */
00096 typedef struct
00097 {
00098     uint16_t dcoc_step; 
00099     uint16_t dcoc_step_rcp; 
00100 //    uint16_t dcoc_step_q;
00101 //    uint16_t dcoc_step_rcp_q;
00102 } TZAdcocstep_t;
00103 
00104 typedef struct
00105 {
00106     int8_t step_value; /* The offset from nominal DAC value (see sweep_step_values[]) */
00107     int16_t internal_measurement; /* The value (average code) measured from DMA samples. */
00108 //    uint8_t valid; /* Set to TRUE (non zero) when a value is written to this table entry. */
00109 } GAIN_CALC_TBL_ENTRY2_T;
00110 
00111 /*******************************************************************************
00112 * Definitions
00113 ******************************************************************************/
00114 void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg);
00115 void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg);
00116 uint8_t rx_bba_dcoc_dac_trim_shortIQ(void);
00117 void XcvrCalDelay(uint32_t time);
00118 void rx_dc_est_average (int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber);
00119 uint8_t rx_bba_dcoc_dac_trim_DCest(void);
00120 void DCOC_DAC_INIT_Cal (uint8_t standalone_operation);
00121 
00122 
00123 
00124 
00125 /* @} */
00126 
00127 #if defined(__cplusplus)
00128 }
00129 #endif
00130 
00131 /*! @}*/
00132 
00133 #endif /* _FSL_XCVR_TRIM_H_ */
00134