fsl_xcvr_msk_config.c

00001 /*
00002  * Copyright 2016-2017 NXP
00003  *
00004  * Redistribution and use in source and binary forms, with or without modification,
00005  * are permitted provided that the following conditions are met:
00006  *
00007  * o Redistributions of source code must retain the above copyright notice, this list
00008  *   of conditions and the following disclaimer.
00009  *
00010  * o Redistributions in binary form must reproduce the above copyright notice, this
00011  *   list of conditions and the following disclaimer in the documentation and/or
00012  *   other materials provided with the distribution.
00013  *
00014  * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00015  *   contributors may be used to endorse or promote products derived from this
00016  *   software without specific prior written permission.
00017  *
00018  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00019  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00020  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00021  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00022  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00023  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00024  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00025  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00026  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00027  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00028  */
00029 
00030 #include "fsl_xcvr.h "
00031 
00032 /*******************************************************************************
00033  * Definitions
00034  ******************************************************************************/
00035 
00036 /*******************************************************************************
00037  * Prototypes
00038  ******************************************************************************/
00039 
00040 /*******************************************************************************
00041  * Variables
00042  ******************************************************************************/
00043 
00044 /*******************************************************************************
00045  * Code
00046  ******************************************************************************/
00047 /* MODE only configuration */
00048 const xcvr_mode_config_t msk_mode_config =
00049 {
00050     .radio_mode = MSK,
00051     .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK,
00052 
00053     /* XCVR_MISC configs */
00054     .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
00055                       XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK |
00056                       XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK,
00057     .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(9) |
00058                       XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(4) |
00059                       XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1),
00060 
00061     /* XCVR_PHY configs */
00062     .phy_pre_ref0_init = 0x79CDEB38,
00063     .phy_pre_ref1_init = 0xCE77DFF7,
00064     .phy_pre_ref2_init = 0x0000CEB7,
00065 
00066     .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) |
00067                      XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) |
00068                      XCVR_PHY_CFG1_FSK_BIT_INVERT(0) |
00069                      XCVR_PHY_CFG1_BSM_EN_BLE(0) |
00070                      XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) |
00071                      XCVR_PHY_CFG1_CTS_THRESH(208U) |
00072                      XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2),
00073 
00074     .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1)
00075 #if !RADIO_IS_GEN_2P1
00076                     | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0)
00077 #endif /* !RADIO_IS_GEN_2P1 */
00078      ,
00079 
00080     /* XCVR_RX_DIG configs */
00081     .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
00082                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */
00083                               XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0),
00084 
00085     .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */
00086                               XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */
00087 
00088     .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF),
00089 
00090     /* XCVR_TSM configs */
00091 #if (DATA_PADDING_EN)
00092     .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
00093 #else
00094     .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT),
00095 #endif /* (DATA_PADDING_EN) */
00096 
00097     /* XCVR_TX_DIG configs */
00098     .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) |
00099                     XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) |
00100                     XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) |
00101                     XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) |
00102                     XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) |
00103                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) |
00104                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) |
00105                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) |
00106                     XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0),
00107     .tx_gfsk_coeff1_26mhz = 0,
00108     .tx_gfsk_coeff2_26mhz = 0,
00109     .tx_gfsk_coeff1_32mhz = 0,
00110     .tx_gfsk_coeff2_32mhz = 0,
00111 };
00112 
00113 /* MODE & DATA RATE combined configuration */
00114 const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config =
00115 {
00116     .radio_mode = MSK,
00117     .data_rate = DR_1MBPS,
00118 
00119     .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
00120     .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
00121     .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
00122     .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ 
00123     .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
00124     .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */
00125 
00126     .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
00127                      XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) ,
00128 
00129     /* AGC configs */
00130     .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) |
00131                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00132                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00133                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00134                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00135                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00136     .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) |
00137                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00138                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00139                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00140                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00141                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00142 
00143     /* All constant values are represented as 16 bits, register writes will remove unused bits */
00144     /* MSK 1MBPS channel filter  @ 26MHz RF OSC */
00145     .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
00146     .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002,
00147     .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000,
00148     .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9,
00149     .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0,
00150     .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA,
00151     .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC,
00152     .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC,
00153     .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B,
00154     .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042,
00155     .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066,
00156     .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C,
00157 
00158     /* MSK 1MBPS channel filter  @ 32MHz RF OSC */
00159     .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
00160     .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
00161     .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002,
00162     .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC,
00163     .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2,
00164     .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9,
00165     .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9,
00166     .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7,
00167     .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016,
00168     .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040,
00169     .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069,
00170     .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082,
00171 
00172     .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
00173                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
00174                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
00175                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
00176                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
00177                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
00178                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
00179                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
00180     .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
00181                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
00182                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
00183                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
00184                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
00185                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
00186 
00187     .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
00188     .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
00189 };
00190 
00191 const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config =
00192 {
00193     .radio_mode = MSK,
00194     .data_rate = DR_500KBPS,
00195 
00196     .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
00197     .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
00198     .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
00199     .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
00200     .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
00201     .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
00202 
00203     .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
00204                      XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xa) ,
00205 
00206     /* AGC configs */
00207     .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) |
00208                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00209                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00210                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00211                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00212                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00213     .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
00214                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00215                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00216                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00217                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00218                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00219 
00220     /* All constant values are represented as 16 bits, register writes will remove unused bits */
00221     /* MSK 500KBPS channel filter @ 26MHz RF OSC */
00222     .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001,
00223     .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004,
00224     .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006,
00225     .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005,
00226     .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFC,
00227     .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED,
00228     .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2,
00229     .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE7,
00230     .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005,
00231     .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0038,
00232     .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F,
00233     .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0092,
00234 
00235     /* MSK 500KBPS channel filter @ 32MHz RF OSC */ 
00236     .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF,
00237     .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002,
00238     .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0006,
00239     .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0009,
00240     .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0003,
00241     .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF3,
00242     .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE2,
00243     .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE0,
00244     .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA,
00245     .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0031,
00246     .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0071,
00247     .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009C,
00248 
00249     .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
00250                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) |
00251                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) |
00252                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
00253                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
00254                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
00255                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) |
00256                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) ,
00257     .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
00258                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
00259                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
00260                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
00261                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) |
00262                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) ,
00263 
00264     .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
00265     .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
00266 };
00267 
00268 const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config =
00269 {
00270     .radio_mode = MSK,
00271     .data_rate = DR_250KBPS,
00272 
00273     .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
00274     .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */
00275     .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
00276     .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 
00277     .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
00278     .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 
00279 
00280     .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) |
00281                      XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) ,
00282 
00283     /* AGC configs */
00284     .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) |
00285                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00286                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) |
00287                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00288                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00289                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00290     .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) |
00291                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) |
00292                              XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) |
00293                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) |
00294                              XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) |
00295                              XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5),
00296 
00297     /* All constant values are represented as 16 bits, register writes will remove unused bits */
00298     .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002,
00299     .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF,
00300     .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8,
00301     .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA,
00302     .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A,
00303     .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019,
00304     .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009,
00305     .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB,
00306     .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1,
00307     .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6,
00308     .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072,
00309     .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD,
00310 
00311     /* MSK 250KBPS channel filter @ 32MHz RF OSC */ 
00312     .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002,
00313     .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003,
00314     .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC,
00315     .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4,
00316     .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD,
00317     .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016,
00318     .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A,
00319     .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC,
00320     .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC,
00321     .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0,
00322     .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069,
00323     .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED,
00324 
00325     .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) |
00326                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) |
00327                        XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) |
00328                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) |
00329                        XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) |
00330                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) |
00331                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) |
00332                        XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) ,
00333     .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) |
00334                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) |
00335                        XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) |
00336                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) |
00337                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) |
00338                        XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) ,
00339 
00340     .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9),
00341     .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800),
00342 };
00343