fsl_xcvr_common_config.c

00001 /*
00002  * Copyright (c) 2015, Freescale Semiconductor, Inc.
00003  * Copyright 2016-2017 NXP
00004  *
00005  * Redistribution and use in source and binary forms, with or without modification,
00006  * are permitted provided that the following conditions are met:
00007  *
00008  * o Redistributions of source code must retain the above copyright notice, this list
00009  *   of conditions and the following disclaimer.
00010  *
00011  * o Redistributions in binary form must reproduce the above copyright notice, this
00012  *   list of conditions and the following disclaimer in the documentation and/or
00013  *   other materials provided with the distribution.
00014  *
00015  * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00016  *   contributors may be used to endorse or promote products derived from this
00017  *   software without specific prior written permission.
00018  *
00019  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00020  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00021  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00022  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00023  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00024  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00025  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00026  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00027  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00028  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00029  */
00030 
00031 #include "fsl_xcvr.h "
00032 
00033 /*******************************************************************************
00034  * Definitions
00035  ******************************************************************************/
00036 
00037 /*******************************************************************************
00038  * Prototypes
00039  ******************************************************************************/
00040 
00041 /*******************************************************************************
00042  * Variables
00043  ******************************************************************************/
00044 
00045 /*******************************************************************************
00046  * Code
00047  ******************************************************************************/
00048 const xcvr_common_config_t xcvr_common_config =
00049 {
00050     /* XCVR_ANA configs */
00051     .ana_sy_ctrl1.mask = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK,
00052     .ana_sy_ctrl1.init = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL(3), /* PLL Analog Loop Filter */
00053 
00054 #define hpm_vcm_tx 0
00055 #define hpm_vcm_cal 1
00056 #define hpm_fdb_res_tx 0
00057 #define hpm_fdb_res_cal 1
00058 #define modulation_word_manual 0
00059 #define mod_disable 0
00060 #define hpm_mod_manual 0
00061 #define hpm_mod_disable 0
00062 #define hpm_sdm_out_manual 0
00063 #define hpm_sdm_out_disable 0
00064 #define channel_num 0
00065 #define boc 0
00066 #define bmr 1
00067 #define zoc 0
00068 #define ctune_ldf_lev 8
00069 #define ftf_rx_thrsh 33
00070 #define ftw_rx 0
00071 #define ftf_tx_thrsh 6
00072 #define ftw_tx 0
00073 #define freq_count_go 0
00074 #define freq_count_time 0
00075 #define hpm_sdm_in_manual 0
00076 #define hpm_sdm_out_invert 0
00077 #define hpm_sdm_in_disable 0
00078 #define hpm_lfsr_size 4
00079 #define hpm_dth_scl 0
00080 #define hpm_dth_en 1
00081 #define hpm_integer_scale 0
00082 #define hpm_integer_invert 0
00083 #define hpm_cal_invert 1
00084 #define hpm_mod_in_invert 1
00085 #define hpm_cal_not_bumped 0
00086 #define hpm_cal_count_scale 0
00087 #define hp_cal_disable 0
00088 #define hpm_cal_factor_manual 0
00089 #define hpm_cal_array_size 1
00090 #define hpm_cal_time 0
00091 #define hpm_sdm_denom 256
00092 #define hpm_count_adjust 0
00093 #define pll_ld_manual 0
00094 #define pll_ld_disable 0
00095 #define lpm_sdm_inv 0
00096 #define lpm_disable 0
00097 #define lpm_dth_scl 8
00098 #define lpm_d_ctrl 1
00099 #define lpm_d_ovrd 1
00100 #define lpm_scale 8
00101 #define lpm_sdm_use_neg 0
00102 #define hpm_array_bias 0
00103 #define lpm_intg 38
00104 #define sdm_map_disable 0
00105 #define lpm_sdm_delay 4
00106 #define hpm_sdm_delay 0
00107 #define hpm_integer_delay 0
00108 #define ctune_target_manual 0
00109 #define ctune_target_disable 0
00110 #define ctune_adjust 0
00111 #define ctune_manual 0
00112 #define ctune_disable 0
00113 
00114 /*-------------------------------------------------------------------------------------------------*/
00115 
00116     .pll_hpm_bump = XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(hpm_fdb_res_cal) |
00117                     XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(hpm_fdb_res_tx) |
00118                     XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(hpm_vcm_cal) |
00119                     XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(hpm_vcm_tx),
00120 
00121 /*-------------------------------------------------------------------------------------------------*/
00122 
00123     .pll_mod_ctrl = XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(hpm_mod_disable) |
00124                     XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(hpm_mod_manual) | 
00125                     XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(hpm_sdm_out_disable) |
00126                     XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(hpm_sdm_out_manual) |
00127                     XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(mod_disable) |
00128                     XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(modulation_word_manual),
00129 
00130 /*-------------------------------------------------------------------------------------------------*/
00131 
00132     .pll_chan_map = XCVR_PLL_DIG_CHAN_MAP_BMR(bmr) |
00133                     XCVR_PLL_DIG_CHAN_MAP_BOC(boc) |
00134                     XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel_num)
00135 #if !RADIO_IS_GEN_2P1
00136                   | XCVR_PLL_DIG_CHAN_MAP_ZOC(zoc)
00137 #endif /* !RADIO_IS_GEN_2P1 */
00138     ,
00139 
00140 /*-------------------------------------------------------------------------------------------------*/
00141 
00142     .pll_lock_detect = XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(ctune_ldf_lev) |
00143                        XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(freq_count_go) |
00144                        XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(freq_count_time) |
00145                        XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(ftf_rx_thrsh) |
00146                        XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(ftf_tx_thrsh) |
00147                        XCVR_PLL_DIG_LOCK_DETECT_FTW_RX(ftw_rx) |
00148                        XCVR_PLL_DIG_LOCK_DETECT_FTW_TX(ftw_tx),
00149 
00150 /*-------------------------------------------------------------------------------------------------*/
00151 
00152     .pll_hpm_ctrl = XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(hpm_cal_invert) |
00153                     XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(hpm_dth_en) |
00154                     XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(hpm_dth_scl) |
00155                     XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(hpm_integer_invert) |
00156                     XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE(hpm_integer_scale) |
00157                     XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(hpm_lfsr_size) |
00158                     XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(hpm_mod_in_invert) |
00159                     XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(hpm_sdm_in_disable) |
00160                     XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(hpm_sdm_in_manual) |
00161                     XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(hpm_sdm_out_invert),
00162 /*-------------------------------------------------------------------------------------------------*/
00163 #if !RADIO_IS_GEN_2P1
00164     .pll_hpmcal_ctrl = XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE(hp_cal_disable) |
00165                        XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE(hpm_cal_array_size) |
00166                        XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE(hpm_cal_count_scale) |
00167                        XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL(hpm_cal_factor_manual) |
00168                        XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED(hpm_cal_not_bumped) |
00169                        XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME(hpm_cal_time),
00170 #endif /* !RADIO_IS_GEN_2P1 */
00171 /*-------------------------------------------------------------------------------------------------*/
00172     .pll_hpm_sdm_res = XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(hpm_count_adjust) |
00173                        XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(hpm_sdm_denom),
00174 /*-------------------------------------------------------------------------------------------------*/
00175     .pll_lpm_ctrl = XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(lpm_d_ctrl) |
00176                     XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(lpm_d_ovrd) |
00177                     XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(lpm_disable) |
00178                     XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(lpm_dth_scl) |
00179                     XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(lpm_scale) |
00180                     XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(lpm_sdm_inv) |
00181                     XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(lpm_sdm_use_neg) |
00182                     XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(pll_ld_disable) |
00183                     XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(pll_ld_manual),
00184 /*-------------------------------------------------------------------------------------------------*/
00185     .pll_lpm_sdm_ctrl1 = XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(hpm_array_bias) |
00186                          XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(lpm_intg) |
00187                          XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(sdm_map_disable),
00188 /*-------------------------------------------------------------------------------------------------*/
00189     .pll_delay_match = XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(hpm_integer_delay) |
00190                        XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(hpm_sdm_delay) |
00191                        XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(lpm_sdm_delay),
00192 /*-------------------------------------------------------------------------------------------------*/
00193     .pll_ctune_ctrl = XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(ctune_adjust) |
00194                       XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(ctune_disable) |
00195                       XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(ctune_manual) |
00196                       XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(ctune_target_disable) |
00197                       XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(ctune_target_manual),
00198 /*-------------------------------------------------------------------------------------------------*/
00199 
00200     /* XCVR_RX_DIG configs */
00201     /* NOTE: Clock specific settings are embedded in the mode dependent configs */
00202     .rx_dig_ctrl_init = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) |
00203                         XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(0) |
00204 #if !RADIO_IS_GEN_2P1
00205                         XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) |
00206 #endif /* !RADIO_IS_GEN_2P1 */
00207                         XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) |
00208                         XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) |
00209                         XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) |
00210                         XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) |
00211                         XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) |
00212                         XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) |
00213                         XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) |
00214                         XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) |
00215                         XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1),
00216 
00217     .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) |
00218                        XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2) |
00219                        XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN(1) |
00220                        XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA(0) |
00221                        XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN(1) |
00222                        XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC(0) |
00223                        XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ(2) |
00224                        XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ(2) |
00225                        XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH(0xe7),
00226 
00227     .agc_ctrl_3_init = XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME(21) |
00228                        XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(2) |
00229                        XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(20) |
00230                        XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(6) |
00231                        XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(2),    
00232 
00233     /* DCOC configs */
00234     .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(16) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */
00235 #if (RADIO_IS_GEN_2P1)
00236                               XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) |
00237 #endif /* (RADIO_IS_GEN_2P1) */
00238                               XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) |
00239                               XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) |
00240                               XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) |
00241                               XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | 
00242                               XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1),
00243     .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(20) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */
00244 #if (RADIO_IS_GEN_2P1)
00245                               XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) |
00246 #endif /* (RADIO_IS_GEN_2P1) */
00247                               XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) |
00248                               XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) |
00249                               XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) |
00250                               XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) |  
00251                               XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1),
00252     
00253     .dcoc_ctrl_1_init = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(26),
00254 
00255     .dc_resid_ctrl_init = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(4) |
00256                           XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(1) |
00257                           XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(1) |
00258                           XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(26),
00259 
00260     .dcoc_cal_gain_init = XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1(1) |
00261                           XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1(1) |
00262                           XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2(1) |
00263                           XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2(2) |
00264                           XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3(3) |
00265                           XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3(1) ,
00266 
00267     .dcoc_cal_rcp_init = XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP(1) |
00268                          XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(711),
00269 
00270     .lna_gain_val_3_0 = XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0(0x1DU) |
00271                         XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1(0x32U) |
00272                         XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2(0x09U) |
00273                         XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3(0x38U),
00274 
00275     .lna_gain_val_7_4 = XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4(0x4FU) |
00276                         XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5(0x5BU) |
00277                         XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6(0x72U) |
00278                         XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7(0x8AU),
00279     .lna_gain_val_8 = XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8(0xA0U) |
00280                       XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9(0xB6U),
00281 
00282     .bba_res_tune_val_7_0 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0(0x0) |
00283                             XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1(0x0) |
00284                             XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2(0x0) |
00285                             XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3(0x0) |
00286                             XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4(0x0) |
00287                             XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5(0x0) |
00288                             XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6(0x0) |
00289                             XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7(0xF),
00290     .bba_res_tune_val_10_8 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8(0x0) |
00291                              XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9(0x1) |
00292                              XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10(0x2),
00293 
00294     .lna_gain_lin_val_2_0_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0(0) |
00295                                  XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1(0) |
00296                                  XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2(1),
00297 
00298     .lna_gain_lin_val_5_3_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3(3) |
00299                                  XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4(5) |
00300                                  XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5(7),
00301 
00302     .lna_gain_lin_val_8_6_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6(14) |
00303                                  XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7(27) |
00304                                  XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8(50),
00305 
00306     .lna_gain_lin_val_9_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9(91),
00307 
00308     .bba_res_tune_lin_val_3_0_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0(8) |
00309                                      XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1(11) |
00310                                      XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2(16) |
00311                                      XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3(22),
00312 
00313     .bba_res_tune_lin_val_7_4_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4(31) |
00314                                      XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5(44) |
00315                                      XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6(62) |
00316                                      XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7(42), /* Has 2 fractional bits unlike other BBA_RES_TUNE_LIN_VALs */
00317 
00318     .bba_res_tune_lin_val_10_8_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8(128) |
00319                                       XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9(188) |
00320                                       XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10(288),
00321 
00322     .dcoc_bba_step_init = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(939) |
00323                           XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(279),
00324 
00325     .dcoc_tza_step_00_init = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(77) |
00326                              XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(3404),
00327     .dcoc_tza_step_01_init = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(108) |
00328                              XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(2439),
00329     .dcoc_tza_step_02_init = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(155) |
00330                              XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(1691),
00331     .dcoc_tza_step_03_init = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(220) |
00332                              XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(1192),
00333     .dcoc_tza_step_04_init = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(314) |
00334                              XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(835),
00335     .dcoc_tza_step_05_init = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(436) |
00336                              XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(601),
00337     .dcoc_tza_step_06_init = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(614) |
00338                              XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(427),
00339     .dcoc_tza_step_07_init = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(845) |
00340                              XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(310),
00341     .dcoc_tza_step_08_init = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(1256) |
00342                              XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(209),
00343     .dcoc_tza_step_09_init = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(1805) |
00344                              XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(145),
00345     .dcoc_tza_step_10_init = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(2653) |
00346                              XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(99),
00347 #if (RADIO_IS_GEN_2P1)
00348     .dcoc_cal_fail_th_init = XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH(20) |
00349                              XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH(10),
00350     .dcoc_cal_pass_th_init = XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH(16) |
00351                              XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH(2),
00352 #endif /* (RADIO_IS_GEN_2P1) */
00353     /* AGC Configs */    
00354     .agc_gain_tbl_03_00_init = XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(0) |
00355                                XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(0) | 
00356                                XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(1) |
00357                                XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(1) | 
00358                                XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(2) |
00359                                XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(1) | 
00360                                XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(2) |
00361                                XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(2),
00362 
00363     .agc_gain_tbl_07_04_init = XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04(2) |
00364                                XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04(3) |
00365                                XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05(3) |
00366                                XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05(0) |
00367                                XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06(3) |
00368                                XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06(1) |
00369                                XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07(3) |
00370                                XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07(2),
00371 
00372     .agc_gain_tbl_11_08_init = XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08(3) |
00373                                XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08(3) |
00374                                XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09(4) |
00375                                XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09(2) |
00376                                XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10(4) |
00377                                XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10(3) |
00378                                XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11(4) |
00379                                XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11(4),
00380 
00381     .agc_gain_tbl_15_12_init = XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12(5) |
00382                                XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12(4) |
00383                                XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13(5) |
00384                                XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13(5) |
00385                                XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14(6) |
00386                                XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14(4) |
00387                                XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15(6) |
00388                                XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15(5),
00389 
00390     .agc_gain_tbl_19_16_init = XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16(6) |
00391                                XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16(6) |
00392                                XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17(6) |
00393                                XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17(7) |
00394                                XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18(7) |
00395                                XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18(6) |
00396                                XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19(7) |
00397                                XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19(7),
00398 
00399     .agc_gain_tbl_23_20_init = XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20(8) |
00400                                XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20(6) |
00401                                XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21(8) |
00402                                XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21(7) |
00403                                XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22(9) |
00404                                XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22(6) |
00405                                XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23(9) |
00406                                XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23(7),
00407 
00408     .agc_gain_tbl_26_24_init = XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24(9) |
00409                                XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24(8) |
00410                                XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25(9) |
00411                                XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(9) |
00412                                XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(9) |
00413                                XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(10),
00414     
00415     .rssi_ctrl_0_init = XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(1) |
00416                         XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(0) |
00417                         XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(1) |
00418                         XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(0) |
00419 #if !RADIO_IS_GEN_2P1
00420                         XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(1) |
00421 #else
00422                         XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB(1) |
00423 #endif /* !RADIO_IS_GEN_2P1 */
00424                         XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY(4) |
00425                         XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(3) |
00426                         XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE(3) |
00427                         XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(0xE8) ,
00428 
00429     .cca_ed_lqi_ctrl_0_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH(0) |
00430                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH(0) |
00431                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR(0x1A) |
00432                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ(0),
00433 
00434     .cca_ed_lqi_ctrl_1_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY(0) |
00435                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR(0) |
00436                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT(0x4) |
00437                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS(0x7) |
00438                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS(0) |
00439 #if !RADIO_IS_GEN_2P1
00440                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE(0) |
00441 #endif /* !RADIO_IS_GEN_2P1 */
00442                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE(0) |
00443                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS(0) |
00444                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE(0) |
00445                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH(0) |
00446                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT(0x5) |
00447                               XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS(0x2),
00448 
00449     /* XCVR_TSM configs */
00450     .tsm_ctrl = XCVR_TSM_CTRL_PA_RAMP_SEL(PA_RAMP_SEL) |
00451                 XCVR_TSM_CTRL_DATA_PADDING_EN(DATA_PADDING_EN) |
00452                 XCVR_TSM_CTRL_TSM_IRQ0_EN(0) |
00453                 XCVR_TSM_CTRL_TSM_IRQ1_EN(0) |
00454                 XCVR_TSM_CTRL_RAMP_DN_DELAY(0x4) |
00455                 XCVR_TSM_CTRL_TX_ABORT_DIS(0) |
00456                 XCVR_TSM_CTRL_RX_ABORT_DIS(0) |
00457                 XCVR_TSM_CTRL_ABORT_ON_CTUNE(0) |
00458                 XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(0) |
00459                 XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(0) |
00460                 XCVR_TSM_CTRL_BKPT(0xFF) ,
00461 
00462     .tsm_ovrd2_init = XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(0) | XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK,
00463     .end_of_seq_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(END_OF_RX_WU_26MHZ) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU),
00464     .end_of_seq_init_32mhz = B3(END_OF_RX_WD) | B2(END_OF_RX_WU) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU),
00465 
00466 #if !RADIO_IS_GEN_2P1
00467     .lpps_ctrl_init = B3(102) | B2(40) | B1(0) | B0(0),
00468 #endif /* !RADIO_IS_GEN_2P1 */
00469 
00470     .tsm_fast_ctrl2_init_26mhz = B3(102 + ADD_FOR_26MHZ) | B2(40 + ADD_FOR_26MHZ) | B1(66) | B0(8),
00471     .tsm_fast_ctrl2_init_32mhz = B3(102) | B2(40) | B1(66) | B0(8),
00472 
00473     .pa_ramp_tbl_0_init = XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0(PA_RAMP_0) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1(PA_RAMP_1) |
00474                           XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2(PA_RAMP_2) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3(PA_RAMP_3),
00475     .pa_ramp_tbl_1_init = XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4(PA_RAMP_4) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5(PA_RAMP_5) |
00476                           XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(PA_RAMP_6) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(PA_RAMP_7),
00477 
00478     .recycle_count_init_26mhz = B3(0) | B2(0x1C + ADD_FOR_26MHZ) | B1(0x06) | B0(0x66 + ADD_FOR_26MHZ),
00479     .recycle_count_init_26mhz = B3(0) | B2(0x1C) | B1(0x06) | B0(0x66),
00480 
00481     .tsm_timing_00_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_hf_en */
00482     .tsm_timing_01_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_adcdac_en */
00483     .tsm_timing_02_init = B3(END_OF_RX_WD) | B2(0x00) | B1(0xFF) | B0(0xFF), /* bb_ldo_bba_en */
00484     .tsm_timing_03_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_pd_en */
00485     .tsm_timing_04_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_fdbk_en */
00486     .tsm_timing_05_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vcolo_en */
00487     .tsm_timing_06_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vtref_en */
00488     .tsm_timing_07_init = B3(0x05) | B2(0x00) | B1(0x05) | B0(0x00), /* bb_ldo_fdbk_bleed_en */
00489     .tsm_timing_08_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_bleed_en */
00490     .tsm_timing_09_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_fastcharge_en */
00491 
00492     .tsm_timing_10_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_pll_ref_clk_en */
00493     .tsm_timing_11_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_dac_ref_clk_en */
00494     .tsm_timing_12_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_vco_ref_clk_en */
00495     .tsm_timing_13_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_vco_autotune_en */
00496     .tsm_timing_14_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x31+ADD_FOR_26MHZ) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ), /* sy_pd_cycle_slip_ld_ft_en */
00497     .tsm_timing_14_init_32mhz = B3(END_OF_RX_WD) | B2(0x31 + AUX_PLL_DELAY) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ),
00498     .tsm_timing_15_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_vco_en */
00499     .tsm_timing_16_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1C + ADD_FOR_26MHZ) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_buf_en */
00500     .tsm_timing_16_init_32mhz = B3(END_OF_RX_WD) | B2(0x1C + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00501     .tsm_timing_17_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x55), /* sy_lo_tx_buf_en */
00502     .tsm_timing_18_init = B3(END_OF_RX_WD) | B2(0x05 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x05), /* sy_divn_en */
00503     .tsm_timing_19_init = B3(0x18+AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0x4C) | B0(0x03), /* sy_pd_filter_charge_en */
00504 
00505     .tsm_timing_20_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_pd_en */
00506     .tsm_timing_21_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x04), /* sy_lo_divn_en */
00507     .tsm_timing_22_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(0xFF) |           B0(0xFF), /* sy_lo_rx_en */
00508     .tsm_timing_23_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x04), /*sy_lo_tx_en  */
00509     .tsm_timing_24_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_divn_cal_en */
00510     .tsm_timing_25_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_lna_mixer_en */
00511     .tsm_timing_25_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00512     .tsm_timing_26_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x58), /* tx_pa_en */
00513     .tsm_timing_27_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_i_q_en */
00514     .tsm_timing_27_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00515     .tsm_timing_28_init_26mhz = B3(0x21 + ADD_FOR_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_reset_en */
00516     .tsm_timing_28_init_32mhz = B3(0x21 + AUX_PLL_DELAY) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00517     .tsm_timing_29_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1E + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_i_q_en */
00518     .tsm_timing_29_init_32mhz = B3(END_OF_RX_WD) | B2(0x1E + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00519 
00520     .tsm_timing_30_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_pdet_en */
00521     .tsm_timing_30_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00522     .tsm_timing_31_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1F + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_tza_dcoc_en */
00523     .tsm_timing_31_init_32mhz = B3(END_OF_RX_WD) | B2(0x1F + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00524     .tsm_timing_32_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_i_q_en */
00525     .tsm_timing_32_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00526     .tsm_timing_33_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_pdet_en */
00527     .tsm_timing_33_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00528     .tsm_timing_34_init = B3(END_OF_RX_WD) | B2(0x07 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x07), /* pll_dig_en */
00529     .tsm_timing_35_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD), /* tx_dig_en - Byte 0 comes from mode specific settings */
00530     .tsm_timing_36_init_26mhz = B3(END_OF_RX_WD) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_dig_en */
00531     .tsm_timing_36_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00532     .tsm_timing_37_init_26mhz = B3(0x67 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_init */
00533     .tsm_timing_37_init_32mhz = B3(0x67 + AUX_PLL_DELAY) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00534     .tsm_timing_38_init = B3(END_OF_RX_WD) | B2(0x0E + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x42), /* sigma_delta_en */
00535     .tsm_timing_39_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_phy_en */
00536     .tsm_timing_39_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00537 
00538     .tsm_timing_40_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_en */
00539     .tsm_timing_40_init_32mhz = B3(END_OF_RX_WD) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00540     .tsm_timing_41_init_26mhz = B3(0x27 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_init */
00541     .tsm_timing_41_init_32mhz = B3(0x27 + AUX_PLL_DELAY) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00542     .tsm_timing_51_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_bias_en */
00543     .tsm_timing_52_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x06 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_fcal_en */
00544     .tsm_timing_52_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x06 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00545     .tsm_timing_53_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_lf_pd_en */
00546     .tsm_timing_54_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x03 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_pd_lf_filter_charge_en */
00547     .tsm_timing_54_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00548     .tsm_timing_55_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_adc_buf_en */
00549     .tsm_timing_55_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00550     .tsm_timing_56_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_dig_buf_en */
00551     .tsm_timing_56_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF),
00552     .tsm_timing_57_init = B3(0x1A + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /*rxtx_rccal_en  */
00553     .tsm_timing_58_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* tx_hpm_dac_en */
00554 
00555 /* XCVR_TX_DIG configs */
00556 #define radio_dft_mode 0
00557 #define lfsr_length 4
00558 #define lfsr_en 0
00559 #define dft_clk_sel 4
00560 #define tx_dft_en 0
00561 #define soc_test_sel 0
00562 #define tx_capture_pol 0
00563 #define freq_word_adj 0
00564 #define lrm 0
00565 #define data_padding_pat_1 0x55
00566 #define data_padding_pat_0 0xAA
00567 #define gfsk_multiply_table_manual 0
00568 #define gfsk_mi 1
00569 #define gfsk_mld 0
00570 #define gfsk_fld 0
00571 #define gfsk_mod_index_scaling 0
00572 #define tx_image_filter_ovrd_en 0
00573 #define tx_image_filter_0_ovrd 0
00574 #define tx_image_filter_1_ovrd 0
00575 #define tx_image_filter_2_ovrd 0
00576 #define gfsk_filter_coeff_manual2 0xC0630401
00577 #define gfsk_filter_coeff_manual1 0xBB29960D
00578 #define fsk_modulation_scale_0 0x1800
00579 #define fsk_modulation_scale_1 0x0800
00580 #define dft_mod_patternval 0
00581 #define ctune_bist_go 0
00582 #define ctune_bist_thrshld 0
00583 #define pa_am_mod_freq 0
00584 #define pa_am_mod_entries 0
00585 #define pa_am_mod_en 0
00586 #define syn_bist_go 0
00587 #define syn_bist_all_channels 0
00588 #define freq_count_threshold 0
00589 #define hpm_inl_bist_go 0
00590 #define hpm_dnl_bist_go 0
00591 #define dft_max_ram_size 0
00592 
00593     .tx_ctrl = XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(radio_dft_mode) |
00594                XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) |
00595                XCVR_TX_DIG_CTRL_LFSR_EN(lfsr_en) |
00596                XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) |
00597                XCVR_TX_DIG_CTRL_TX_DFT_EN(tx_dft_en) |
00598                XCVR_TX_DIG_CTRL_SOC_TEST_SEL(soc_test_sel) |
00599                XCVR_TX_DIG_CTRL_TX_CAPTURE_POL(tx_capture_pol) |
00600                XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(freq_word_adj),
00601 /*-------------------------------------------------------------------------------------------------*/
00602     .tx_data_padding = XCVR_TX_DIG_DATA_PADDING_LRM(lrm) |
00603                        XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1(data_padding_pat_1) |
00604                        XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0(data_padding_pat_0),
00605 /*-------------------------------------------------------------------------------------------------*/
00606     .tx_dft_pattern = XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN(dft_mod_patternval),
00607 #if !RADIO_IS_GEN_2P1
00608 /*-------------------------------------------------------------------------------------------------*/
00609     .rf_dft_bist_1 = XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO(ctune_bist_go) |
00610                      XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD(ctune_bist_thrshld) |
00611                      XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ(pa_am_mod_freq) |
00612                      XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES(pa_am_mod_entries) |
00613                      XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN(pa_am_mod_en),
00614 /*-------------------------------------------------------------------------------------------------*/
00615     .rf_dft_bist_2 = XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO(syn_bist_go) |
00616                      XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS(syn_bist_all_channels) |
00617                      XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD(freq_count_threshold) |
00618                      XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO(hpm_inl_bist_go) |
00619                      XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO(hpm_dnl_bist_go) |
00620                      XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE(dft_max_ram_size),
00621 #endif /* !RADIO_IS_GEN_2P1 */
00622 };
00623