Igor Stepura
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kw41z-rf-driver
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fsl_xcvr.h
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00001 /* 00002 * Copyright (c) 2015, Freescale Semiconductor, Inc. 00003 * Copyright 2016-2017 NXP. 00004 * 00005 * Redistribution and use in source and binary forms, with or without modification, 00006 * are permitted provided that the following conditions are met: 00007 * 00008 * o Redistributions of source code must retain the above copyright notice, this list 00009 * of conditions and the following disclaimer. 00010 * 00011 * o Redistributions in binary form must reproduce the above copyright notice, this 00012 * list of conditions and the following disclaimer in the documentation and/or 00013 * other materials provided with the distribution. 00014 * 00015 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00016 * contributors may be used to endorse or promote products derived from this 00017 * software without specific prior written permission. 00018 * 00019 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00020 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00021 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00022 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00023 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00024 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00025 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00026 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00027 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00028 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00029 */ 00030 #ifndef _FSL_XCVR_H_ 00031 /* clang-format off */ 00032 #define _FSL_XCVR_H_ 00033 /* clang-format on */ 00034 00035 #include "fsl_device_registers.h" 00036 #include "fsl_xcvr_trim.h " 00037 00038 #if gMWS_UseCoexistence_d 00039 #include "MWS.h" 00040 #endif /* gMWS_UseCoexistence_d */ 00041 /*! 00042 * @addtogroup xcvr 00043 * @{ 00044 */ 00045 00046 /*! @file*/ 00047 00048 /******************************************************************************* 00049 * Definitions 00050 ******************************************************************************/ 00051 /* KW4xZ/KW3xZ/KW2xZ Radio type */ 00052 #define RADIO_IS_GEN_2P0 (1) 00053 00054 /* Default RF OSC definition. Allows for compile time clock frequency definition */ 00055 #ifdef CLOCK_MAIN 00056 00057 #else 00058 #if RF_OSC_26MHZ == 1 00059 #define CLOCK_MAIN (EXT_CLK_26_MHZ) /* See ext_clock_config_t for this value */ 00060 #else 00061 #define CLOCK_MAIN (EXT_CLK_32_MHZ) /* See ext_clock_config_t for this value */ 00062 #endif /* RF_OSC_26MHZ == 1 */ 00063 #endif /* CLOCK_MAIN */ 00064 00065 #define TBD_ZERO (0) 00066 #define FSL_XCVR_DRIVER_VERSION (MAKE_VERSION(0, 1, 0)) 00067 00068 #define B0(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0xFFU) 00069 #define B1(x) (((uint32_t)(((uint32_t)(x)) << 8)) & 0xFF00U) 00070 #define B2(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0xFF0000U) 00071 #define B3(x) (((uint32_t)(((uint32_t)(x)) << 24)) & 0xFF000000U) 00072 00073 #define USE_DEFAULT_PRE_REF (0) 00074 #define TRIM_BBA_DCOC_DAC_AT_INIT (1) 00075 #define PRESLOW_ENA (1) 00076 00077 /* GEN3 TSM defines */ 00078 #if RADIO_IS_GEN_3P0 00079 00080 /* TSM timings initializations for Gen3 radio */ 00081 /* NOTE: These timings are stored in 32MHz or 26MHz "baseline" settings, selected by conditional compile below */ 00082 /* The init structures for 32Mhz and 26MHz are made identical to allow the same code in fsl_xcvr.c to apply the */ 00083 /* settings for all radio generations. The Gen2 radio init value storage had a different structure so this preserves compatibility */ 00084 #if RF_OSC_26MHZ == 1 00085 #define TSM_TIMING00init (0x6d006f00U) /* (bb_ldo_hf_en) */ 00086 #define TSM_TIMING01init (0x6d006f00U) /* (bb_ldo_adcdac_en) */ 00087 #define TSM_TIMING02init (0x6d00ffffU) /* (bb_ldo_bba_en) */ 00088 #define TSM_TIMING03init (0x6d006f00U) /* (bb_ldo_pd_en) */ 00089 #define TSM_TIMING04init (0x6d006f00U) /* (bb_ldo_fdbk_en) */ 00090 #define TSM_TIMING05init (0x6d006f00U) /* (bb_ldo_vcolo_en) */ 00091 #define TSM_TIMING06init (0x6d006f00U) /* (bb_ldo_vtref_en) */ 00092 #define TSM_TIMING07init (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */ 00093 #define TSM_TIMING08init (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */ 00094 #define TSM_TIMING09init (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */ 00095 #define TSM_TIMING10init (0x6d036f03U) /* (bb_xtal_pll_ref_clk_en) */ 00096 #define TSM_TIMING11init (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */ 00097 #define TSM_TIMING12init (0x6d03ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */ 00098 #define TSM_TIMING13init (0x18004c00U) /* (sy_vco_autotune_en) */ 00099 #define TSM_TIMING14init (0x6d356863U) /* (sy_pd_cycle_slip_ld_ft_en) */ 00100 #define TSM_TIMING15init (0x6d036f03U) /* (sy_vco_en) */ 00101 #define TSM_TIMING16init (0x6d20ffffU) /* (sy_lo_rx_buf_en) */ 00102 #define TSM_TIMING17init (0xffff6f58U) /* (sy_lo_tx_buf_en) */ 00103 #define TSM_TIMING18init (0x6d056f05U) /* (sy_divn_en) */ 00104 #define TSM_TIMING19init (0x18034c03U) /* (sy_pd_filter_charge_en) */ 00105 #define TSM_TIMING20init (0x6d036f03U) /* (sy_pd_en) */ 00106 #define TSM_TIMING21init (0x6d046f04U) /* (sy_lo_divn_en) */ 00107 #define TSM_TIMING22init (0x6d04ffffU) /* (sy_lo_rx_en) */ 00108 #define TSM_TIMING23init (0xffff6f04U) /* (sy_lo_tx_en) */ 00109 #define TSM_TIMING24init (0x18004c00U) /* (sy_divn_cal_en) */ 00110 #define TSM_TIMING25init (0x6d21ffffU) /* (rx_lna_mixer_en) */ 00111 #define TSM_TIMING26init (0xffff6e58U) /* (tx_pa_en) */ 00112 #define TSM_TIMING27init (0x6d24ffffU) /* (rx_adc_i_q_en) */ 00113 #define TSM_TIMING28init (0x2524ffffU) /* (rx_adc_reset_en) */ 00114 #define TSM_TIMING29init (0x6d22ffffU) /* (rx_bba_i_q_en) */ 00115 #define TSM_TIMING30init (0x6d24ffffU) /* (rx_bba_pdet_en) */ 00116 #define TSM_TIMING31init (0x6d23ffffU) /* (rx_bba_tza_dcoc_en) */ 00117 #define TSM_TIMING32init (0x6d21ffffU) /* (rx_tza_i_q_en) */ 00118 #define TSM_TIMING33init (0x6d24ffffU) /* (rx_tza_pdet_en) */ 00119 #define TSM_TIMING34init (0x6d076f07U) /* (pll_dig_en) */ 00120 #define TSM_TIMING35init (0xffff6f5fU) /* (tx_dig_en) */ 00121 #define TSM_TIMING36init (0x6d6affffU) /* (rx_dig_en) */ 00122 #define TSM_TIMING37init (0x6b6affffU) /* (rx_init) */ 00123 #define TSM_TIMING38init (0x6d0e6f42U) /* (sigma_delta_en) */ 00124 #define TSM_TIMING39init (0x6d6affffU) /* (rx_phy_en) */ 00125 #define TSM_TIMING40init (0x6d2affffU) /* (dcoc_en) */ 00126 #define TSM_TIMING41init (0x2b2affffU) /* (dcoc_init) */ 00127 #define TSM_TIMING42init (0xffffffffU) /* (sar_adc_trig_en) */ 00128 #define TSM_TIMING43init (0xffffffffU) /* (tsm_spare0_en) */ 00129 #define TSM_TIMING44init (0xffffffffU) /* (tsm_spare1_en) */ 00130 #define TSM_TIMING45init (0xffffffffU) /* (tsm_spare2_en) */ 00131 #define TSM_TIMING46init (0xffffffffU) /* (tsm_spare3_en) */ 00132 #define TSM_TIMING47init (0xffffffffU) /* (gpio0_trig_en) */ 00133 #define TSM_TIMING48init (0xffffffffU) /* (gpio1_trig_en) */ 00134 #define TSM_TIMING49init (0xffffffffU) /* (gpio2_trig_en) */ 00135 #define TSM_TIMING50init (0xffffffffU) /* (gpio3_trig_en) */ 00136 #define TSM_TIMING51init (0x6d03ffffU) /* (rxtx_auxpll_bias_en) */ 00137 #define TSM_TIMING52init (0x1b06ffffU) /* (rxtx_auxpll_fcal_en) */ 00138 #define TSM_TIMING53init (0x6d03ffffU) /* (rxtx_auxpll_lf_pd_en) */ 00139 #define TSM_TIMING54init (0x1b03ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */ 00140 #define TSM_TIMING55init (0x6d24ffffU) /* (rxtx_auxpll_adc_buf_en) */ 00141 #define TSM_TIMING56init (0x6d24ffffU) /* (rxtx_auxpll_dig_buf_en) */ 00142 #define TSM_TIMING57init (0x1a03ffffU) /* (rxtx_rccal_en) */ 00143 #define TSM_TIMING58init (0xffff6f03U) /* (tx_hpm_dac_en) */ 00144 #define END_OF_SEQinit (0x6d6c6f67U) /* */ 00145 #define TX_RX_ON_DELinit (0x00008a86U) /* */ 00146 #define TX_RX_SYNTH_init (0x00002318U) /* */ 00147 #else 00148 #define TSM_TIMING00init (0x69006f00U) /* (bb_ldo_hf_en) */ 00149 #define TSM_TIMING01init (0x69006f00U) /* (bb_ldo_adcdac_en) */ 00150 #define TSM_TIMING02init (0x6900ffffU) /* (bb_ldo_bba_en) */ 00151 #define TSM_TIMING03init (0x69006f00U) /* (bb_ldo_pd_en) */ 00152 #define TSM_TIMING04init (0x69006f00U) /* (bb_ldo_fdbk_en) */ 00153 #define TSM_TIMING05init (0x69006f00U) /* (bb_ldo_vcolo_en) */ 00154 #define TSM_TIMING06init (0x69006f00U) /* (bb_ldo_vtref_en) */ 00155 #define TSM_TIMING07init (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */ 00156 #define TSM_TIMING08init (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */ 00157 #define TSM_TIMING09init (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */ 00158 #define TSM_TIMING10init (0x69036f03U) /* (bb_xtal_pll_ref_clk_en) */ 00159 #define TSM_TIMING11init (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */ 00160 #define TSM_TIMING12init (0x6903ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */ 00161 #define TSM_TIMING13init (0x18004c00U) /* (sy_vco_autotune_en) */ 00162 #define TSM_TIMING14init (0x69316863U) /* (sy_pd_cycle_slip_ld_ft_en) */ 00163 #define TSM_TIMING15init (0x69036f03U) /* (sy_vco_en) */ 00164 #define TSM_TIMING16init (0x691cffffU) /* (sy_lo_rx_buf_en) */ 00165 #define TSM_TIMING17init (0xffff6f58U) /* (sy_lo_tx_buf_en) */ 00166 #define TSM_TIMING18init (0x69056f05U) /* (sy_divn_en) */ 00167 #define TSM_TIMING19init (0x18034c03U) /* (sy_pd_filter_charge_en) */ 00168 #define TSM_TIMING20init (0x69036f03U) /* (sy_pd_en) */ 00169 #define TSM_TIMING21init (0x69046f04U) /* (sy_lo_divn_en) */ 00170 #define TSM_TIMING22init (0x6904ffffU) /* (sy_lo_rx_en) */ 00171 #define TSM_TIMING23init (0xffff6f04U) /* (sy_lo_tx_en) */ 00172 #define TSM_TIMING24init (0x18004c00U) /* (sy_divn_cal_en) */ 00173 #define TSM_TIMING25init (0x691dffffU) /* (rx_lna_mixer_en) */ 00174 #define TSM_TIMING26init (0xffff6e58U) /* (tx_pa_en) */ 00175 #define TSM_TIMING27init (0x6920ffffU) /* (rx_adc_i_q_en) */ 00176 #define TSM_TIMING28init (0x2120ffffU) /* (rx_adc_reset_en) */ 00177 #define TSM_TIMING29init (0x691effffU) /* (rx_bba_i_q_en) */ 00178 #define TSM_TIMING30init (0x6920ffffU) /* (rx_bba_pdet_en) */ 00179 #define TSM_TIMING31init (0x691fffffU) /* (rx_bba_tza_dcoc_en) */ 00180 #define TSM_TIMING32init (0x691dffffU) /* (rx_tza_i_q_en) */ 00181 #define TSM_TIMING33init (0x6920ffffU) /* (rx_tza_pdet_en) */ 00182 #define TSM_TIMING34init (0x69076f07U) /* (pll_dig_en) */ 00183 #define TSM_TIMING35init (0xffff6f5fU) /* (tx_dig_en) */ 00184 #define TSM_TIMING36init (0x6966ffffU) /* (rx_dig_en) */ 00185 #define TSM_TIMING37init (0x6766ffffU) /* (rx_init) */ 00186 #define TSM_TIMING38init (0x690e6f42U) /* (sigma_delta_en) */ 00187 #define TSM_TIMING39init (0x6966ffffU) /* (rx_phy_en) */ 00188 #define TSM_TIMING40init (0x6926ffffU) /* (dcoc_en) */ 00189 #define TSM_TIMING41init (0x2726ffffU) /* (dcoc_init) */ 00190 #define TSM_TIMING42init (0xffffffffU) /* (sar_adc_trig_en) */ 00191 #define TSM_TIMING43init (0xffffffffU) /* (tsm_spare0_en) */ 00192 #define TSM_TIMING44init (0xffffffffU) /* (tsm_spare1_en) */ 00193 #define TSM_TIMING45init (0xffffffffU) /* (tsm_spare2_en) */ 00194 #define TSM_TIMING46init (0xffffffffU) /* (tsm_spare3_en) */ 00195 #define TSM_TIMING47init (0xffffffffU) /* (gpio0_trig_en) */ 00196 #define TSM_TIMING48init (0xffffffffU) /* (gpio1_trig_en) */ 00197 #define TSM_TIMING49init (0xffffffffU) /* (gpio2_trig_en) */ 00198 #define TSM_TIMING50init (0xffffffffU) /* (gpio3_trig_en) */ 00199 #define TSM_TIMING51init (0x6903ffffU) /* (rxtx_auxpll_bias_en) */ 00200 #define TSM_TIMING52init (0x1706ffffU) /* (rxtx_auxpll_fcal_en) */ 00201 #define TSM_TIMING53init (0x6903ffffU) /* (rxtx_auxpll_lf_pd_en) */ 00202 #define TSM_TIMING54init (0x1703ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */ 00203 #define TSM_TIMING55init (0x6920ffffU) /* (rxtx_auxpll_adc_buf_en) */ 00204 #define TSM_TIMING56init (0x6920ffffU) /* (rxtx_auxpll_dig_buf_en) */ 00205 #define TSM_TIMING57init (0x1a03ffffU) /* (rxtx_rccal_en) */ 00206 #define TSM_TIMING58init (0xffff6f03U) /* (tx_hpm_dac_en) */ 00207 #define END_OF_SEQinit (0x69686f67U) /* */ 00208 #define TX_RX_ON_DELinit (0x00008a86U) /* */ 00209 #define TX_RX_SYNTH_init (0x00002318U) /* */ 00210 #endif /* RF_OSC_26MHZ == 1 */ 00211 00212 #define AUX_PLL_DELAY (0) 00213 /* TSM bitfield shift and value definitions */ 00214 #define TX_DIG_EN_ASSERT (95) /* Assertion time for TX_DIG_EN, used in mode specific settings */ 00215 #define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */ 00216 /* EDIT THIS LINE TO CONTROL PA_RAMP! */ 00217 #define PA_RAMP_TIME (2) /* Only allowable values are [0, 1, 2, or 4] in Gen3 */ 00218 #define PA_RAMP_SEL_0US (0) 00219 #define PA_RAMP_SEL_1US (1) 00220 #define PA_RAMP_SEL_2US (2) 00221 #define PA_RAMP_SEL_4US (3) 00222 #if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4)) 00223 #error "Invalid value for PA_RAMP_TIME macro" 00224 #endif /* Error check of PA RAMP TIME */ 00225 00226 #define ADD_FOR_26MHZ (4) 00227 #define END_OF_TX_WU_NORAMP (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ 00228 #define END_OF_TX_WD_NORAMP (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ 00229 /* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */ 00230 /* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */ 00231 #if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2)) 00232 #define END_OF_TX_WU (END_OF_TX_WU_NORAMP) 00233 #define END_OF_TX_WD (END_OF_TX_WD_NORAMP) 00234 #if (PA_RAMP_TIME == 0) 00235 #define PA_RAMP_SEL PA_RAMP_SEL_0US 00236 #define DATA_PADDING_EN (0) 00237 #else 00238 #define DATA_PADDING_EN (1) 00239 #if (PA_RAMP_TIME == 1) 00240 #define PA_RAMP_SEL PA_RAMP_SEL_1US 00241 #else 00242 #define PA_RAMP_SEL PA_RAMP_SEL_2US 00243 #endif /* (PA_RAMP_TIME == 1) */ 00244 #endif /* (PA_RAMP_TIME == 0) */ 00245 #else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2)) */ 00246 #if (PA_RAMP_TIME == 4) 00247 #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 2) 00248 #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 4) 00249 #define PA_RAMP_SEL PA_RAMP_SEL_4US 00250 #define DATA_PADDING_EN (1) 00251 #else /* (PA_RAMP_TIME == 4) */ 00252 #error "Invalid value for PA_RAMP_TIME macro" 00253 #endif /* (PA_RAMP_TIME == 4) */ 00254 #endif/* (PA_RAMP_TIME == 4) */ 00255 00256 #define END_OF_RX_WU (104 + AUX_PLL_DELAY) 00257 00258 #if RF_OSC_26MHZ == 1 00259 #define END_OF_RX_WD (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */ 00260 #else 00261 #define END_OF_RX_WD (END_OF_RX_WU + 1) 00262 #endif /* RF_OSC_26MHZ == 1 */ 00263 00264 #define END_OF_RX_WU_26MHZ (END_OF_RX_WU + ADD_FOR_26MHZ) 00265 #define END_OF_RX_WD_26MHZ (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) 00266 00267 /* PA Bias Table - Gen3 version */ 00268 #define PA_RAMP_0 0x1 00269 #define PA_RAMP_1 0x2 00270 #define PA_RAMP_2 0x4 00271 #define PA_RAMP_3 0x6 00272 #define PA_RAMP_4 0x8 00273 #define PA_RAMP_5 0xc 00274 #define PA_RAMP_6 0x10 00275 #define PA_RAMP_7 0x14 00276 #define PA_RAMP_8 0x18 00277 #define PA_RAMP_9 0x1c 00278 #define PA_RAMP_10 0x22 00279 #define PA_RAMP_11 0x28 00280 #define PA_RAMP_12 0x2c 00281 #define PA_RAMP_13 0x30 00282 #define PA_RAMP_14 0x36 00283 #define PA_RAMP_15 0x3c 00284 00285 #else /* Gen2 TSM definitions */ 00286 /* GEN2 TSM defines */ 00287 #define AUX_PLL_DELAY (0) 00288 /* TSM bitfield shift and value definitions */ 00289 #define TX_DIG_EN_ASSERT (95) 00290 #define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */ 00291 /* EDIT THIS LINE TO CONTROL PA_RAMP! */ 00292 #define PA_RAMP_TIME (2) /* Only allowable values are [0, 2, 4, or 8] for PA RAMP times in Gen2.0 */ 00293 #define PA_RAMP_SEL_0US (0) 00294 #define PA_RAMP_SEL_2US (1) 00295 #define PA_RAMP_SEL_4US (2) 00296 #define PA_RAMP_SEL_8US (3) 00297 00298 #if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4) || (PA_RAMP_TIME == 8)) 00299 #error "Invalid value for PA_RAMP_TIME macro" 00300 #endif /* Error check of PA RAMP TIME */ 00301 #define ADD_FOR_26MHZ (4) 00302 #define END_OF_TX_WU_NORAMP (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ 00303 #define END_OF_TX_WD_NORAMP (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ 00304 /* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */ 00305 /* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */ 00306 #if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) 00307 #define END_OF_TX_WU (END_OF_TX_WU_NORAMP) 00308 #define END_OF_TX_WD (END_OF_TX_WD_NORAMP) 00309 #define TX_SYNTH_DELAY_ADJ (0) 00310 #define PD_CYCLE_SLIP_TX_HI_ADJ (0) 00311 #define PD_CYCLE_SLIP_TX_LO_ADJ (1) 00312 #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-5) /* Only applies to Zigbee mode */ 00313 #if (PA_RAMP_TIME == 0) 00314 #define PA_RAMP_SEL PA_RAMP_SEL_0US 00315 #define DATA_PADDING_EN (0) 00316 #define TX_DIG_EN_TX_HI_ADJ (-2) 00317 #else 00318 #define DATA_PADDING_EN (1) 00319 #define TX_DIG_EN_TX_HI_ADJ (0) 00320 #define PA_RAMP_SEL PA_RAMP_SEL_2US 00321 #endif /* (PA_RAMP_TIME == 0) */ 00322 #else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */ 00323 #if (PA_RAMP_TIME == 4) 00324 #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 2) 00325 #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 4) 00326 #define TX_SYNTH_DELAY_ADJ (2) 00327 #define PD_CYCLE_SLIP_TX_HI_ADJ (2) 00328 #define PD_CYCLE_SLIP_TX_LO_ADJ (1) 00329 #define TX_DIG_EN_TX_HI_ADJ (0) 00330 #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-3) /* Only applies to Zigbee mode */ 00331 #define PA_RAMP_SEL PA_RAMP_SEL_4US 00332 #define DATA_PADDING_EN (1) 00333 #else /* (PA_RAMP_TIME==4) */ 00334 #if ((PA_RAMP_TIME == 8) && (!RADIO_IS_GEN_3P0)) 00335 #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 6) 00336 #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 12) 00337 #define TX_SYNTH_DELAY_ADJ (6) 00338 #define PD_CYCLE_SLIP_TX_HI_ADJ (6) 00339 #define PD_CYCLE_SLIP_TX_LO_ADJ (1) 00340 #define TX_DIG_EN_TX_HI_ADJ (4) 00341 #define ZGBE_TX_DIG_EN_TX_HI_ADJ (1) /* Only applies to Zigbee mode */ 00342 #define PA_RAMP_SEL PA_RAMP_SEL_8US 00343 #define DATA_PADDING_EN (1) 00344 #else /* (PA_RAMP_TIME == 8) */ 00345 #error "Invalid value for PA_RAMP_TIME macro" 00346 #endif /* (PA_RAMP_TIME == 8) */ 00347 #endif/* (PA_RAMP_TIME == 4) */ 00348 #endif /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */ 00349 00350 #define TX_DIG_EN_ASSERT_MSK500 (END_OF_TX_WU - 3) 00351 00352 #define END_OF_RX_WU (104 + AUX_PLL_DELAY) 00353 #if RF_OSC_26MHZ == 1 00354 #define END_OF_RX_WD (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */ 00355 #else 00356 #define END_OF_RX_WD (END_OF_RX_WU + 1) 00357 #endif /* RF_OSC_26MHZ == 1 */ 00358 #define END_OF_RX_WU_26MHZ (END_OF_RX_WU + ADD_FOR_26MHZ) 00359 #define END_OF_RX_WD_26MHZ (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) 00360 00361 /* PA Bias Table */ 00362 #define PA_RAMP_0 0x1 00363 #define PA_RAMP_1 0x2 00364 #define PA_RAMP_2 0x4 00365 #define PA_RAMP_3 0x8 00366 #define PA_RAMP_4 0xe 00367 #define PA_RAMP_5 0x16 00368 #define PA_RAMP_6 0x22 00369 #define PA_RAMP_7 0x2e 00370 00371 /* BLE LL timing definitions */ 00372 #define TX_ON_DELAY (0x85) /* Adjusted TX_ON_DELAY to make turnaround time 150usec */ 00373 #define RX_ON_DELAY (29 + END_OF_RX_WU) 00374 #define RX_ON_DELAY_26MHZ (29 + END_OF_RX_WU_26MHZ) 00375 #define TX_RX_ON_DELAY_VAL (TX_ON_DELAY << 8 | RX_ON_DELAY) 00376 #define TX_RX_ON_DELAY_VAL_26MHZ (TX_ON_DELAY << 8 | RX_ON_DELAY_26MHZ) 00377 #define TX_SYNTH_DELAY (TX_ON_DELAY - END_OF_TX_WU - TX_SYNTH_DELAY_ADJ) /* Adjustment to TX_SYNTH_DELAY due to DATA_PADDING */ 00378 #define RX_SYNTH_DELAY (0x18) 00379 #define TX_RX_SYNTH_DELAY_VAL (TX_SYNTH_DELAY << 8 | RX_SYNTH_DELAY) 00380 00381 /* PHY reference waveform assembly */ 00382 #define RW0PS(loc, val) (((val) & 0x1F) << ((loc) * 5)) /* Ref Word 0 - loc is the phase info symbol number, val is the value of the phase info */ 00383 #define RW1PS(loc, val) (((val) & 0x1F) << (((loc) * 5) - 32)) /* Ref Word 1 - loc is the phase info symbol number, val is the value of the phase info */ 00384 #define RW2PS(loc, val) (((val) & 0x1F) << (((loc) * 5) - 64)) /* Ref Word 2 - loc is the phase info symbol number, val is the value of the phase info */ 00385 #endif /* RADIO_IS_GEN_3P0 */ 00386 00387 /*! @brief Error codes for the XCVR driver. */ 00388 typedef enum _xcvrStatus 00389 { 00390 gXcvrSuccess_c = 0, 00391 gXcvrInvalidParameters_c, 00392 gXcvrUnsupportedOperation_c, 00393 gXcvrTrimFailure_c 00394 } xcvrStatus_t; 00395 00396 /*! @brief Health status returned from PHY upon status check function return. */ 00397 typedef enum _healthStatus 00398 { 00399 NO_ERRORS = 0, 00400 PLL_CTUNE_FAIL = 1, 00401 PLL_CYCLE_SLIP_FAIL = 2, 00402 PLL_FREQ_TARG_FAIL = 4, 00403 PLL_TSM_ABORT_FAIL = 8, 00404 } healthStatus_t; 00405 00406 /*! @brief Health status returned from PHY upon status check function return. */ 00407 typedef enum _ext_clock_config 00408 { 00409 EXT_CLK_32_MHZ = 0, 00410 EXT_CLK_26_MHZ = 1, 00411 } ext_clock_config_t; 00412 00413 /*! @brief Radio operating mode setting types. */ 00414 typedef enum _radio_mode 00415 { 00416 BLE_MODE = 0, 00417 ZIGBEE_MODE = 1, 00418 ANT_MODE = 2, 00419 00420 /* BT=0.5, h=** */ 00421 GFSK_BT_0p5_h_0p5 = 3, /* < BT=0.5, h=0.5 [BLE at 1MBPS data rate; CS4 at 250KBPS data rate] */ 00422 GFSK_BT_0p5_h_0p32 = 4, /* < BT=0.5, h=0.32*/ 00423 GFSK_BT_0p5_h_0p7 = 5, /* < BT=0.5, h=0.7 [ CS1 at 500KBPS data rate] */ 00424 GFSK_BT_0p5_h_1p0 = 6, /* < BT=0.5, h=1.0 [ CS4 at 250KBPS data rate] */ 00425 00426 /* BT=** h=0.5 */ 00427 GFSK_BT_0p3_h_0p5 = 7, /* < BT=0.3, h=0.5 [ CS2 at 1MBPS data rate] */ 00428 GFSK_BT_0p7_h_0p5 = 8, /* < BT=0.7, h=0.5 */ 00429 00430 MSK = 9, 00431 NUM_RADIO_MODES = 10, 00432 } radio_mode_t; 00433 00434 /*! @brief Link layer types. */ 00435 typedef enum _link_layer 00436 { 00437 BLE_LL = 0, /* Must match bit assignment in RADIO1_IRQ_SEL */ 00438 ZIGBEE_LL = 1, /* Must match bit assignment in RADIO1_IRQ_SEL */ 00439 ANT_LL = 2, /* Must match bit assignment in RADIO1_IRQ_SEL */ 00440 GENFSK_LL = 3, /* Must match bit assignment in RADIO1_IRQ_SEL */ 00441 UNASSIGNED_LL = 4, /* Must match bit assignment in RADIO1_IRQ_SEL */ 00442 } link_layer_t; 00443 00444 /*! @brief Data rate selections. */ 00445 typedef enum _data_rate 00446 { 00447 DR_1MBPS = 0, /* Must match bit assignment in BITRATE field */ 00448 DR_500KBPS = 1, /* Must match bit assignment in BITRATE field */ 00449 DR_250KBPS = 2, /* Must match bit assignment in BITRATE field */ 00450 #if RADIO_IS_GEN_3P0 00451 DR_2MBPS = 3, /* Must match bit assignment in BITRATE field */ 00452 #endif /* RADIO_IS_GEN_3P0 */ 00453 DR_UNASSIGNED = 4, /* Must match bit assignment in BITRATE field */ 00454 } data_rate_t; 00455 00456 /*! @brief Control settings for Fast Antenna Diversity */ 00457 typedef enum _FAD_LPPS_CTRL 00458 { 00459 NONE = 0, 00460 FAD_ENABLED = 1, 00461 LPPS_ENABLED = 2 00462 } FAD_LPPS_CTRL_T; 00463 00464 /*! @brief XCVR XCVR Panic codes for indicating panic reason. */ 00465 typedef enum _XCVR_PANIC_ID 00466 { 00467 WRONG_RADIO_ID_DETECTED = 1, 00468 CALIBRATION_INVALID = 2, 00469 } XCVR_PANIC_ID_T; 00470 00471 /*! @brief Initialization or mode change selection for config routine. */ 00472 typedef enum _XCVR_INIT_MODE_CHG 00473 { 00474 XCVR_MODE_CHANGE = 0, 00475 XCVR_FIRST_INIT = 1, 00476 } XCVR_INIT_MODE_CHG_T; 00477 00478 typedef enum _XCVR_COEX_PRIORITY 00479 { 00480 XCVR_COEX_LOW_PRIO = 0, 00481 XCVR_COEX_HIGH_PRIO = 1 00482 } XCVR_COEX_PRIORITY_T; 00483 00484 /*! @brief Current configuration of the radio. */ 00485 typedef struct xcvr_currConfig_tag 00486 { 00487 radio_mode_t radio_mode; 00488 data_rate_t data_rate; 00489 } xcvr_currConfig_t; 00490 00491 /*! 00492 * @brief XCVR RX_DIG channel filter coefficient storage 00493 * Storage of the coefficients varies from 6 bits to 10 bits so all use int16_t for storage. 00494 */ 00495 typedef struct _xcvr_rx_chf_coeffs 00496 { 00497 uint16_t rx_chf_coef_0; /* < 6 bit two's complement stored in a uint16_t */ 00498 uint16_t rx_chf_coef_1; /* < 6 bit two's complement stored in a uint16_t */ 00499 uint16_t rx_chf_coef_2; /* < 7 bit two's complement stored in a uint16_t */ 00500 uint16_t rx_chf_coef_3; /* < 7 bit two's complement stored in a uint16_t */ 00501 uint16_t rx_chf_coef_4; /* < 7 bit two's complement stored in a uint16_t */ 00502 uint16_t rx_chf_coef_5; /* < 7 bit two's complement stored in a uint16_t */ 00503 uint16_t rx_chf_coef_6; /* < 8 bit two's complement stored in a uint16_t */ 00504 uint16_t rx_chf_coef_7; /* < 8 bit two's complement stored in a uint16_t */ 00505 uint16_t rx_chf_coef_8; /* < 9 bit two's complement stored in a uint16_t */ 00506 uint16_t rx_chf_coef_9; /* < 9 bit two's complement stored in a uint16_t */ 00507 uint16_t rx_chf_coef_10; /* < 10 bit two's complement stored in a uint16_t */ 00508 uint16_t rx_chf_coef_11; /* < 10 bit two's complement stored in a uint16_t */ 00509 } xcvr_rx_chf_coeffs_t; 00510 00511 /*! 00512 * @brief XCVR masked init type for 32 bit registers 00513 * Initialization uses the mask to clear selected fields of the register and then OR's in the init value. All init values must be in their proper field position. 00514 */ 00515 typedef struct _xcvr_masked_init_32 00516 { 00517 uint32_t mask; 00518 uint32_t init; 00519 } xcvr_masked_init_32_t; 00520 00521 /*! 00522 * @brief XCVR common configure structure 00523 */ 00524 typedef struct _xcvr_common_config 00525 { 00526 /* XCVR_ANA configs */ 00527 xcvr_masked_init_32_t ana_sy_ctrl1; 00528 00529 /* XCVR_PLL_DIG configs */ 00530 uint32_t pll_hpm_bump; 00531 uint32_t pll_mod_ctrl; 00532 uint32_t pll_chan_map; 00533 uint32_t pll_lock_detect; 00534 uint32_t pll_hpm_ctrl; 00535 #if !RADIO_IS_GEN_2P1 00536 uint32_t pll_hpmcal_ctrl; 00537 #endif /* !RADIO_IS_GEN_2P1 */ 00538 uint32_t pll_hpm_sdm_res; 00539 uint32_t pll_lpm_ctrl; 00540 uint32_t pll_lpm_sdm_ctrl1; 00541 uint32_t pll_delay_match; 00542 uint32_t pll_ctune_ctrl; 00543 00544 /* XCVR_RX_DIG configs */ 00545 uint32_t rx_dig_ctrl_init; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ 00546 uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */ 00547 uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */ 00548 uint32_t dcoc_ctrl_1_init; 00549 uint32_t dcoc_cal_gain_init; 00550 uint32_t dc_resid_ctrl_init; /* NOTE: This will be OR'd with datarate specific init for DCOC_RESID_CTRL to form complete register initialization */ 00551 uint32_t dcoc_cal_rcp_init; 00552 uint32_t lna_gain_val_3_0; 00553 uint32_t lna_gain_val_7_4; 00554 uint32_t lna_gain_val_8; 00555 uint32_t bba_res_tune_val_7_0; 00556 uint32_t bba_res_tune_val_10_8; 00557 uint32_t lna_gain_lin_val_2_0_init; 00558 uint32_t lna_gain_lin_val_5_3_init; 00559 uint32_t lna_gain_lin_val_8_6_init; 00560 uint32_t lna_gain_lin_val_9_init; 00561 uint32_t bba_res_tune_lin_val_3_0_init; 00562 uint32_t bba_res_tune_lin_val_7_4_init; 00563 uint32_t bba_res_tune_lin_val_10_8_init; 00564 uint32_t dcoc_bba_step_init; 00565 uint32_t dcoc_tza_step_00_init; 00566 uint32_t dcoc_tza_step_01_init; 00567 uint32_t dcoc_tza_step_02_init; 00568 uint32_t dcoc_tza_step_03_init; 00569 uint32_t dcoc_tza_step_04_init; 00570 uint32_t dcoc_tza_step_05_init; 00571 uint32_t dcoc_tza_step_06_init; 00572 uint32_t dcoc_tza_step_07_init; 00573 uint32_t dcoc_tza_step_08_init; 00574 uint32_t dcoc_tza_step_09_init; 00575 uint32_t dcoc_tza_step_10_init; 00576 #if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) 00577 uint32_t dcoc_cal_fail_th_init; 00578 uint32_t dcoc_cal_pass_th_init; 00579 #endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ 00580 uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */ 00581 uint32_t agc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */ 00582 uint32_t agc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */ 00583 uint32_t agc_ctrl_3_init; 00584 /* Other agc config inits moved to modeXdatarate config table */ 00585 uint32_t agc_gain_tbl_03_00_init; 00586 uint32_t agc_gain_tbl_07_04_init; 00587 uint32_t agc_gain_tbl_11_08_init; 00588 uint32_t agc_gain_tbl_15_12_init; 00589 uint32_t agc_gain_tbl_19_16_init; 00590 uint32_t agc_gain_tbl_23_20_init; 00591 uint32_t agc_gain_tbl_26_24_init; 00592 uint32_t rssi_ctrl_0_init; 00593 #if RADIO_IS_GEN_3P0 00594 uint32_t rssi_ctrl_1_init; 00595 #endif /* RADIO_IS_GEN_3P0 */ 00596 uint32_t cca_ed_lqi_ctrl_0_init; 00597 uint32_t cca_ed_lqi_ctrl_1_init; 00598 00599 /* XCVR_TSM configs */ 00600 uint32_t tsm_ctrl; 00601 uint32_t tsm_ovrd2_init; 00602 uint32_t end_of_seq_init_26mhz; 00603 uint32_t end_of_seq_init_32mhz; 00604 #if !RADIO_IS_GEN_2P1 00605 uint32_t lpps_ctrl_init; 00606 #endif /* !RADIO_IS_GEN_2P1 */ 00607 uint32_t tsm_fast_ctrl2_init_26mhz; 00608 uint32_t tsm_fast_ctrl2_init_32mhz; 00609 uint32_t recycle_count_init_26mhz; 00610 uint32_t recycle_count_init_32mhz; 00611 uint32_t pa_ramp_tbl_0_init; 00612 uint32_t pa_ramp_tbl_1_init; 00613 #if RADIO_IS_GEN_3P0 00614 uint32_t pa_ramp_tbl_2_init; 00615 uint32_t pa_ramp_tbl_3_init; 00616 #endif /* RADIO_IS_GEN_3P0 */ 00617 uint32_t tsm_timing_00_init; 00618 uint32_t tsm_timing_01_init; 00619 uint32_t tsm_timing_02_init; 00620 uint32_t tsm_timing_03_init; 00621 uint32_t tsm_timing_04_init; 00622 uint32_t tsm_timing_05_init; 00623 uint32_t tsm_timing_06_init; 00624 uint32_t tsm_timing_07_init; 00625 uint32_t tsm_timing_08_init; 00626 uint32_t tsm_timing_09_init; 00627 uint32_t tsm_timing_10_init; 00628 uint32_t tsm_timing_11_init; 00629 uint32_t tsm_timing_12_init; 00630 uint32_t tsm_timing_13_init; 00631 uint32_t tsm_timing_14_init_26mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */ 00632 uint32_t tsm_timing_14_init_32mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */ 00633 uint32_t tsm_timing_15_init; 00634 uint32_t tsm_timing_16_init_26mhz; 00635 uint32_t tsm_timing_16_init_32mhz; 00636 uint32_t tsm_timing_17_init; 00637 uint32_t tsm_timing_18_init; 00638 uint32_t tsm_timing_19_init; 00639 uint32_t tsm_timing_20_init; 00640 uint32_t tsm_timing_21_init; 00641 uint32_t tsm_timing_22_init; 00642 uint32_t tsm_timing_23_init; 00643 uint32_t tsm_timing_24_init; 00644 uint32_t tsm_timing_25_init_26mhz; 00645 uint32_t tsm_timing_25_init_32mhz; 00646 uint32_t tsm_timing_26_init; 00647 uint32_t tsm_timing_27_init_26mhz; 00648 uint32_t tsm_timing_27_init_32mhz; 00649 uint32_t tsm_timing_28_init_26mhz; 00650 uint32_t tsm_timing_28_init_32mhz; 00651 uint32_t tsm_timing_29_init_26mhz; 00652 uint32_t tsm_timing_29_init_32mhz; 00653 uint32_t tsm_timing_30_init_26mhz; 00654 uint32_t tsm_timing_30_init_32mhz; 00655 uint32_t tsm_timing_31_init_26mhz; 00656 uint32_t tsm_timing_31_init_32mhz; 00657 uint32_t tsm_timing_32_init_26mhz; 00658 uint32_t tsm_timing_32_init_32mhz; 00659 uint32_t tsm_timing_33_init_26mhz; 00660 uint32_t tsm_timing_33_init_32mhz; 00661 uint32_t tsm_timing_34_init; 00662 uint32_t tsm_timing_35_init; /* tsm_timing_35 has a mode specific LSbyte*/ 00663 uint32_t tsm_timing_36_init_26mhz; 00664 uint32_t tsm_timing_36_init_32mhz; 00665 uint32_t tsm_timing_37_init_26mhz; 00666 uint32_t tsm_timing_37_init_32mhz; 00667 uint32_t tsm_timing_38_init; 00668 uint32_t tsm_timing_39_init_26mhz; 00669 uint32_t tsm_timing_39_init_32mhz; 00670 uint32_t tsm_timing_40_init_26mhz; 00671 uint32_t tsm_timing_40_init_32mhz; 00672 uint32_t tsm_timing_41_init_26mhz; 00673 uint32_t tsm_timing_41_init_32mhz; 00674 uint32_t tsm_timing_51_init; 00675 uint32_t tsm_timing_52_init_26mhz; 00676 uint32_t tsm_timing_52_init_32mhz; 00677 uint32_t tsm_timing_53_init; 00678 uint32_t tsm_timing_54_init_26mhz; 00679 uint32_t tsm_timing_54_init_32mhz; 00680 uint32_t tsm_timing_55_init_26mhz; 00681 uint32_t tsm_timing_55_init_32mhz; 00682 uint32_t tsm_timing_56_init_26mhz; 00683 uint32_t tsm_timing_56_init_32mhz; 00684 uint32_t tsm_timing_57_init; 00685 uint32_t tsm_timing_58_init; 00686 00687 /* XCVR_TX_DIG configs */ 00688 uint32_t tx_ctrl; 00689 uint32_t tx_data_padding; 00690 uint32_t tx_dft_pattern; 00691 #if !RADIO_IS_GEN_2P1 00692 uint32_t rf_dft_bist_1; 00693 uint32_t rf_dft_bist_2; 00694 #endif /* !RADIO_IS_GEN_2P1 */ 00695 } xcvr_common_config_t; 00696 00697 /*! @brief XCVR mode specific configure structure (varies by radio mode) */ 00698 typedef struct _xcvr_mode_config 00699 { 00700 radio_mode_t radio_mode; 00701 uint32_t scgc5_clock_ena_bits; 00702 00703 /* XCVR_MISC configs */ 00704 xcvr_masked_init_32_t xcvr_ctrl; 00705 00706 /* XCVR_PHY configs */ 00707 #if RADIO_IS_GEN_3P0 00708 uint32_t phy_fsk_pd_cfg0; 00709 uint32_t phy_fsk_pd_cfg1; 00710 uint32_t phy_fsk_cfg; 00711 uint32_t phy_fsk_misc; 00712 uint32_t phy_fad_ctrl; 00713 #else 00714 uint32_t phy_pre_ref0_init; 00715 uint32_t phy_pre_ref1_init; 00716 uint32_t phy_pre_ref2_init; 00717 uint32_t phy_cfg1_init; 00718 uint32_t phy_el_cfg_init; /* Should leave EL_WIN_SIZE and EL_INTERVAL to the data_rate specific configuration */ 00719 #endif /* RADIO_IS_GEN_3P0 */ 00720 00721 /* XCVR_RX_DIG configs */ 00722 uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ 00723 uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ 00724 uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */ 00725 00726 /* XCVR_TSM configs */ 00727 #if (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1) 00728 uint32_t tsm_timing_35_init; /* Only the LSbyte is mode specific */ 00729 #endif /* (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1) */ 00730 00731 /* XCVR_TX_DIG configs */ 00732 uint32_t tx_gfsk_ctrl; 00733 uint32_t tx_gfsk_coeff1_26mhz; 00734 uint32_t tx_gfsk_coeff2_26mhz; 00735 uint32_t tx_gfsk_coeff1_32mhz; 00736 uint32_t tx_gfsk_coeff2_32mhz; 00737 } xcvr_mode_config_t; 00738 00739 /*! 00740 * @brief XCVR modeXdatarate specific configure structure (varies by radio mode AND data rate) 00741 * This structure is used to store all of the XCVR settings which are dependent upon both radio mode and data rate. It is used as an overlay 00742 * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate. 00743 */ 00744 typedef struct _xcvr_mode_datarate_config 00745 { 00746 radio_mode_t radio_mode; 00747 data_rate_t data_rate; 00748 00749 /* XCVR_ANA configs */ 00750 xcvr_masked_init_32_t ana_sy_ctrl2; 00751 xcvr_masked_init_32_t ana_rx_bba; 00752 xcvr_masked_init_32_t ana_rx_tza; 00753 00754 /* XCVR_PHY configs */ 00755 #if RADIO_IS_GEN_3P0 00756 uint32_t phy_fsk_misc_mode_datarate; 00757 #else 00758 uint32_t phy_cfg2_init; 00759 #endif /* RADIO_IS_GEN_3P0 */ 00760 00761 uint32_t agc_ctrl_2_init_26mhz; 00762 uint32_t agc_ctrl_2_init_32mhz; 00763 xcvr_rx_chf_coeffs_t rx_chf_coeffs_26mhz; /* 26MHz ext clk */ 00764 xcvr_rx_chf_coeffs_t rx_chf_coeffs_32mhz; /* 32MHz ext clk */ 00765 uint32_t rx_rccal_ctrl_0; 00766 uint32_t rx_rccal_ctrl_1; 00767 00768 /* XCVR_TX_DIG configs */ 00769 uint32_t tx_fsk_scale_26mhz; /* Only used by MSK mode, but dependent on datarate */ 00770 uint32_t tx_fsk_scale_32mhz; /* Only used by MSK mode, but dependent on datarate */ 00771 } xcvr_mode_datarate_config_t; 00772 00773 /*! 00774 * @brief XCVR datarate specific configure structure (varies by data rate) 00775 * This structure is used to store all of the XCVR settings which are dependent upon data rate. It is used as an overlay 00776 * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate. 00777 */ 00778 typedef struct _xcvr_datarate_config 00779 { 00780 data_rate_t data_rate; 00781 00782 /* XCVR_PHY configs */ 00783 uint32_t phy_el_cfg_init; /* Note: EL_ENABLE is set in xcvr_mode_config_t settings */ 00784 00785 /* XCVR_RX_DIG configs */ 00786 uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ 00787 uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ 00788 uint32_t agc_ctrl_1_init_26mhz; 00789 uint32_t agc_ctrl_1_init_32mhz; 00790 uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */ 00791 uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */ 00792 uint32_t dcoc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */ 00793 uint32_t dcoc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */ 00794 uint32_t dcoc_ctrl_2_init_26mhz; 00795 uint32_t dcoc_ctrl_2_init_32mhz; 00796 uint32_t dcoc_cal_iir_init_26mhz; 00797 uint32_t dcoc_cal_iir_init_32mhz; 00798 uint32_t dc_resid_ctrl_26mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */ 00799 uint32_t dc_resid_ctrl_32mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */ 00800 } xcvr_datarate_config_t; 00801 00802 /*! 00803 * @brief LPUART callback function type 00804 * 00805 * The panic callback function is defined by system if system need to be informed of XCVR fatal errors. 00806 * refer to #XCVR_RegisterPanicCb 00807 */ 00808 typedef void (*panic_fptr)(uint32_t panic_id, uint32_t location, uint32_t extra1, uint32_t extra2); 00809 00810 /* Make available const structures from config files */ 00811 extern const xcvr_common_config_t xcvr_common_config; 00812 extern const xcvr_mode_config_t zgbe_mode_config; 00813 extern const xcvr_mode_config_t ble_mode_config; 00814 extern const xcvr_mode_config_t ant_mode_config; 00815 extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config; 00816 extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config; 00817 extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config; 00818 extern const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config; 00819 extern const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config; 00820 extern const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config; 00821 extern const xcvr_mode_config_t msk_mode_config; 00822 00823 #if RADIO_IS_GEN_3P0 00824 extern const xcvr_datarate_config_t xcvr_2mbps_config; 00825 #endif /* RADIO_IS_GEN_3P0 */ 00826 extern const xcvr_datarate_config_t xcvr_1mbps_config; 00827 extern const xcvr_datarate_config_t xcvr_500kbps_config; 00828 extern const xcvr_datarate_config_t xcvr_250kbps_config; 00829 extern const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config; /* Custom datarate settings for 802.15.4 since it is 2MChips/sec */ 00830 00831 #if RADIO_IS_GEN_3P0 00832 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_2mbps_config; 00833 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_2mbps_config; 00834 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_2mbps_config; 00835 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_2mbps_config; 00836 extern const xcvr_mode_datarate_config_t xcvr_MSK_2mbps_config; 00837 #endif /* RADIO_IS_GEN_3P0 */ 00838 extern const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config; 00839 extern const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config; 00840 extern const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config; 00841 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config; 00842 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config; 00843 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config; 00844 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config; 00845 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config; 00846 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config; 00847 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config; 00848 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config; 00849 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config; 00850 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config; 00851 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config; 00852 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config; 00853 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config; 00854 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config; 00855 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config; 00856 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config; 00857 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config; 00858 extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config; 00859 extern const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config; 00860 extern const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config; 00861 extern const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config; 00862 00863 /******************************************************************************* 00864 * API 00865 ******************************************************************************/ 00866 00867 #if defined(__cplusplus) 00868 extern "C" { 00869 #endif 00870 00871 /*! 00872 * @name XCVR functional Operation 00873 * @{ 00874 */ 00875 00876 /*! 00877 * @brief Initializes an XCVR instance. 00878 * 00879 * This function initializes the XCVR module according to the radio_mode and data_rate settings. This the only function call required to 00880 * start up the XCVR in most situations. 00881 * 00882 * @param radio_mode The radio mode for which the XCVR should be configured. 00883 * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. 00884 * @note This function encompasses the ::XCVRGetDefafultConfig() and ::XCVR_Configure() functions. 00885 */ 00886 xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate); 00887 00888 /*! 00889 * @brief Deinitializes an XCVR instance. 00890 * 00891 * This function gate the XCVR module clock and set all register value to reset value. 00892 * 00893 */ 00894 void XCVR_Deinit(void); 00895 00896 /*! 00897 * @brief Initializes XCVR configure structure. 00898 * 00899 * This function updates pointers to the XCVR configure structures with default values. 00900 * The configurations are divided into a common structure, a set of radio mode specific 00901 * structures (one per radio_mode), a set of mode&datarate specific structures (for each mode at 00902 * each datarate), and a set of data rate specific structures. 00903 * The pointers provided by this routine point to const structures which can be 00904 * copied to variable structures if changes to settings are required. 00905 * 00906 * @param radio_mode [in] The radio mode for which the configuration structures are requested. 00907 * @param data_rate [in] The data rate for which the configuration structures are requested. 00908 * @param com_config [in,out] Pointer to a pointer to the common configuration settings structure. 00909 * @param mode_config [in,out] Pointer to a pointer to the mode specific configuration settings structure. 00910 * @param mode_datarate_config [in,out] Pointer to a pointer to the modeXdata rate specific configuration settings structure. 00911 * @param datarate_config [in,out] Pointer to a pointer to the data rate specific configuration settings structure. 00912 * @return 0 success, others failure 00913 * @see XCVR_Configure 00914 */ 00915 xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, 00916 data_rate_t data_rate, 00917 const xcvr_common_config_t ** com_config, 00918 const xcvr_mode_config_t ** mode_config, 00919 const xcvr_mode_datarate_config_t ** mode_datarate_config, 00920 const xcvr_datarate_config_t ** datarate_config); 00921 00922 /*! 00923 * @brief Initializes an XCVR instance. 00924 * 00925 * This function initializes the XCVR module with user-defined settings. 00926 * 00927 * @param com_config Pointer to the common configuration settings structure. 00928 * @param mode_config Pointer to the mode specific configuration settings structure. 00929 * @param mode_datarate_config Pointer to a pointer to the modeXdata rate specific configuration settings structure. 00930 * @param datarate_config Pointer to a pointer to the data rate specific configuration settings structure. 00931 * @param tempDegC temperature of the die in degrees C. 00932 * @param ext_clk indicates the external clock setting, 32MHz or 26MHz. 00933 * @param first_init indicates whether the call is to initialize (== 1) or the call is to perform a mode change (== 0) 00934 * @return 0 succeed, others failed 00935 */ 00936 xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, 00937 const xcvr_mode_config_t *mode_config, 00938 const xcvr_mode_datarate_config_t *mode_datarate_config, 00939 const xcvr_datarate_config_t *datarate_config, 00940 int16_t tempDegC, 00941 XCVR_INIT_MODE_CHG_T first_init); 00942 00943 /*! 00944 * @brief Set XCVR register to reset value. 00945 * 00946 * This function set XCVR register to the reset value. 00947 * 00948 */ 00949 void XCVR_Reset(void); 00950 00951 /*! 00952 * @brief Change the operating mode of the radio. 00953 * 00954 * This function changes the XCVR to a new radio operating mode. 00955 * 00956 * @param new_radio_mode The radio mode for which the XCVR should be configured. 00957 * @param new_data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. 00958 * @return status of the mode change. 00959 */ 00960 xcvrStatus_t XCVR_ChangeMode(radio_mode_t new_radio_mode, data_rate_t new_data_rate); 00961 00962 /*! 00963 * @brief Enable Narrowband RSSI measurement. 00964 * 00965 * This function enables the narrowband RSSI measurement 00966 * 00967 * @param IIRnbEnable true causes the NB RSSI to be enabled, false disabled. 00968 */ 00969 void XCVR_EnaNBRSSIMeas(uint8_t IIRnbEnable); 00970 00971 /*! 00972 * @brief Set an arbitrary frequency for RX and TX for the radio. 00973 * 00974 * This function sets the radio frequency used for RX and RX.. 00975 * 00976 * @param freq target frequency setting in Hz. 00977 * @param refOsc reference oscillator setting in Hz. 00978 * @return status of the frequency change. 00979 * @details 00980 */ 00981 xcvrStatus_t XCVR_OverrideFrequency(uint32_t freq, uint32_t refOsc); 00982 00983 /*! 00984 * @brief Register a callback from upper layers. 00985 * 00986 * This function registers a callback from the upper layers for the radio to call in case of fatal errors. 00987 * 00988 * @param fptr The function pointer to a panic callback. 00989 */ 00990 void XCVR_RegisterPanicCb(panic_fptr fptr); /* allow upper layers to provide PANIC callback */ 00991 00992 /*! 00993 * @brief Read the health status of the XCVR to detect errors. 00994 * 00995 * This function enables the upper layers to request the current radio health. 00996 * 00997 * @return The health status of the radio.. 00998 */ 00999 healthStatus_t XCVR_HealthCheck(void); /* allow upper layers to poll the radio health */ 01000 01001 /*! 01002 * @brief Control FAD and LPPS features. 01003 * 01004 * This function controls the Fast Antenna Diversity (FAD) and Low Power Preamble Search. 01005 * 01006 * @param fptr control the FAD and LPPS settings. 01007 * 01008 */ 01009 void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control); 01010 01011 /*! 01012 * @brief Change the mapping of the radio IRQs. 01013 * 01014 * This function changes the mapping of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines. 01015 * 01016 * @param irq0_mapping the LL which should be mapped to the INT0 line. 01017 * @param irq1_mapping the LL which should be mapped to the INT1 line. 01018 * @return status of the mapping request. 01019 * @ note The radio_mode_t parameters map to ::link_layer_t selections for the LL which is connected to the INT line. 01020 * @warning 01021 * The same LL must NOT be mapped to both INT lines. 01022 */ 01023 xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping); 01024 01025 #if RADIO_IS_GEN_3P0 01026 /*! 01027 * @brief Sets the network address used by the PHY during BLE Bit Streaming Mode. 01028 * 01029 * This function programs the register in the PHY which contains the network address used during BSM. 01030 * 01031 * @param bsm_ntw_address the address to be used during BSM. 01032 * @ note This routine does NOT enable BSM. 01033 */ 01034 void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address); 01035 01036 /*! 01037 * @brief Reads the currently programmed network address used by the PHY during BLE Bit Streaming Mode. 01038 * 01039 * This function reads the register in the PHY which contains the network address used during BSM. 01040 * 01041 * @return bsm_ntw_address the address to be used during BSM. 01042 * @ note This routine does NOT enable BSM. 01043 */ 01044 uint32_t XCVR_GetBSM_NTW_Address(void); 01045 #endif /* RADIO_IS_GEN_3P0 */ 01046 01047 /*! 01048 * @brief Get the mapping of the one of the radio IRQs. 01049 * 01050 * This function reads the setting for the mapping of one of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines. 01051 * 01052 * @param int_num the number, 0 or 1, of the INT line to fetched. 01053 * @return the mapping setting of the specified line. 01054 * @note Any value passed into this routine other than 0 will be treated as a 1. 01055 */ 01056 link_layer_t XCVR_GetIRQMapping(uint8_t int_num); 01057 01058 /*! 01059 * @brief Get the current configuration of the XCVR. 01060 * 01061 * This function fetches the current configuration (radio mode and radio data rate) of the XCVR to allow LL to properly config data rates, etc 01062 * 01063 * @param curr_config pointer to a structure to be updated with the current mode and data rate. 01064 * @return the status of the request, success or invalid parameter (null pointer). 01065 * @note This API will return meaningless results if called before the radio is initialized... 01066 */ 01067 xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config); 01068 01069 /******************************************************************************* 01070 * Customer level trim functions 01071 ******************************************************************************/ 01072 /*! 01073 * @brief Controls setting the XTAL trim value.. 01074 * 01075 * This function enables the upper layers set a crystal trim compensation facor 01076 * 01077 * @param xtalTrim the trim value to apply to the XTAL trimming register. Only the 7 LSB are valid, setting the 8th bit returns an error. 01078 * @return The health status of the radio.. 01079 */ 01080 xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim); 01081 01082 /*! 01083 * @brief Controls getting the XTAL trim value.. 01084 * 01085 * This function enables the upper layers to read the current XTAL compensation factors. 01086 * The returned value is in the range 0..127 (7 bits). 01087 * 01088 * @return The XTAL trim compensation factors.. 01089 */ 01090 uint8_t XCVR_GetXtalTrim(void); 01091 01092 /*! 01093 * @brief Controls setting the RSSI adjustment.. 01094 * 01095 * This function enables the upper layers to set an RSSI adjustment value. 01096 * 01097 * @param adj the adjustment value to apply to the RSSI adjustment register. The value must be a signed 8-bit value, in 1/4 dBm step. 01098 * @return The health status of the radio.. 01099 */ 01100 xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj); 01101 01102 /*! 01103 * @brief Controls getting the RSSI adjustment.. 01104 * 01105 * This function enables the upper layers to read the current XCVR RSSI adjustment value. 01106 * The returned value is a signed 8-bit value, in 1/4 dBm step. 01107 * 01108 * @return The RSSI adjustment value.. 01109 */ 01110 int8_t XCVR_GetRssiAdjustment(void); 01111 01112 /*! 01113 * @brief Controls setting the PLL to a particular channel. 01114 * 01115 * This function enables setting the radio channel for TX and RX. 01116 * 01117 * @param channel the channel number to set 01118 * @param useMappedChannel when true, channel is assumed to be from the protocol specific channel map. when false, channel is assumed to be from the 128 general channel list.. 01119 * @return The status of the channel over-ride. 01120 */ 01121 xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel); 01122 01123 /*! 01124 * @brief Reads the current frequency for RX and TX for the radio. 01125 * 01126 * This function reads the radio frequency used for RX and RX.. 01127 * 01128 * @return Current radio frequency setting. 01129 */ 01130 uint32_t XCVR_GetFreq(void); 01131 01132 /*! 01133 * @brief Force receiver warmup. 01134 * 01135 * This function forces the initiation of a receiver warmup sequence. 01136 * 01137 */ 01138 void XCVR_ForceRxWu(void); 01139 01140 /*! 01141 * @brief Force receiver warmdown. 01142 * 01143 * This function forces the initiation of a receiver warmdown sequence. 01144 * 01145 */ 01146 void XCVR_ForceRxWd(void); 01147 01148 /*! 01149 * @brief Force transmitter warmup. 01150 * 01151 * This function forces the initiation of a transmit warmup sequence. 01152 * 01153 */ 01154 void XCVR_ForceTxWu(void); 01155 01156 /*! 01157 * @brief Force transmitter warmdown. 01158 * 01159 * This function forces the initiation of a transmit warmdown sequence. 01160 * 01161 */ 01162 void XCVR_ForceTxWd(void); 01163 01164 /*! 01165 * @brief Starts transmit with a TX pattern register data sequence. 01166 * 01167 * This function starts transmitting using the DFT pattern register mode. 01168 * 01169 * @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation. 01170 * @param radio_mode The radio mode for which the XCVR should be configured. 01171 * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. 01172 * @param tx_pattern - the data pattern to transmit on. 01173 * @return The status of the pattern reg transmit. 01174 * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode 01175 * and data rate. 01176 */ 01177 xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern); 01178 01179 /*! 01180 * @brief Starts transmit with a TX LFSR register data sequence. 01181 * 01182 * This function starts transmitting using the DFT LFSR register mode. 01183 * 01184 * @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation. 01185 * @param radio_mode The radio mode for which the XCVR should be configured. 01186 * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. 01187 * @param lfsr_length - the length of the LFSR sequence to use. 01188 * @return The status of the LFSR reg transmit. 01189 * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode 01190 * and data rate. 01191 */ 01192 xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length); 01193 01194 /*! 01195 * @brief Controls clearing all TX DFT settings. 01196 * 01197 * This function reverts all TX DFT settings from the test modes to normal operating mode. 01198 * 01199 */ 01200 void XCVR_DftTxOff(void); 01201 01202 /*! 01203 * @brief Controls setting the PA power level. 01204 * 01205 * This function enables setting the PA power level to a specific setting, overriding any link layer settings. 01206 * 01207 * @param pa_power - the power level to set. Valid values are 0, 1, and even values from 2 to 0x3E, inclusive. 01208 * @return The status of the PA power over-ride. 01209 */ 01210 xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power); 01211 01212 /*! 01213 * @brief Starts CW TX. 01214 * 01215 * This function starts transmitting CW (no modulation). 01216 * 01217 * @param rf_channel_freq - the RF channel to transmit on. Valid values are integer values from 2360 to 2487MHz, inclusive. 01218 * @param protocol - the protocol setting to use, valid settings are 6 (GFSK) and 7 (FSK). 01219 * @return The status of the CW transmit. 01220 */ 01221 xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol); 01222 01223 xcvrStatus_t XCVR_CoexistenceInit(void); 01224 xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority); 01225 xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings); 01226 01227 /* @} */ 01228 01229 #if defined(__cplusplus) 01230 } 01231 #endif 01232 01233 /*! @}*/ 01234 01235 #endif /* _FSL_XCVR_H_ */ 01236
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