fsl_xcvr.c

00001 /*
00002  * Copyright (c) 2015, Freescale Semiconductor, Inc.
00003  * Copyright 2016-2017 NXP
00004  *
00005  * Redistribution and use in source and binary forms, with or without modification,
00006  * are permitted provided that the following conditions are met:
00007  *
00008  * o Redistributions of source code must retain the above copyright notice, this list
00009  *   of conditions and the following disclaimer.
00010  *
00011  * o Redistributions in binary form must reproduce the above copyright notice, this
00012  *   list of conditions and the following disclaimer in the documentation and/or
00013  *   other materials provided with the distribution.
00014  *
00015  * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00016  *   contributors may be used to endorse or promote products derived from this
00017  *   software without specific prior written permission.
00018  *
00019  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00020  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00021  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00022  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00023  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00024  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00025  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00026  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00027  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00028  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00029  */
00030 #include "EmbeddedTypes.h "
00031 #include "fsl_device_registers.h"
00032 #include "fsl_common.h"
00033 #include "fsl_xcvr.h "
00034 #include "fsl_xcvr_trim.h "
00035 #include <math.h>
00036 #include "ifr_radio.h "
00037 
00038 /*******************************************************************************
00039  * Definitions
00040  ******************************************************************************/
00041 #define channelMapTableSize (128U)
00042 #define gPllDenom_c         0x02000000U /* Denominator is a constant value */
00043 #define ABS(x) ((x) > 0 ? (x) : -(x))
00044 
00045 #ifndef TRUE
00046 #define TRUE                        (true)
00047 #endif
00048 
00049 #ifndef FALSE
00050 #define FALSE                       (false)
00051 #endif
00052 #define RF_OSCILLATOR_STAYS_ON     (false) /* Control whether RF_OSC can be left on all the time. */
00053 #define RF_OSCILLATOR_READY        ((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) != 0x0U)
00054 
00055 #ifndef EXTERNAL_CLOCK_GEN
00056 #define EXTERNAL_CLOCK_GEN   0
00057 #endif
00058 
00059 #define ANT_A   1
00060 #define ANT_B   0
00061 
00062 #ifndef XCVR_COEX_RF_ACTIVE_PIN
00063 #define XCVR_COEX_RF_ACTIVE_PIN ANT_B
00064 #endif /* XCVR_COEX_RF_ACTIVE_PIN */
00065 
00066 typedef struct xcvr_pllChannel_tag
00067 {
00068     unsigned int integer;
00069     unsigned int numerator;
00070 } xcvr_pllChannel_t;
00071 
00072 /*******************************************************************************
00073  * Prototypes
00074  ******************************************************************************/
00075 void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address);
00076 void rf_osc_startup(void);
00077 void rf_osc_shutdown(void);
00078 extern double trunc (double);
00079 extern double round (double);
00080 
00081 /*******************************************************************************
00082  * Variables
00083  ******************************************************************************/
00084 static panic_fptr s_PanicFunctionPtr = NULL;
00085 const xcvr_pllChannel_t mapTable [channelMapTableSize] =
00086 {
00087     {0x00000025, 0x07C00000}, /* 0 */
00088     {0x00000025, 0x07C80000}, /* 1 */
00089     {0x00000025, 0x07D00000}, /* 2 */
00090     {0x00000025, 0x07D80000}, /* 3 */
00091     {0x00000025, 0x07E00000}, /* 4 */
00092     {0x00000025, 0x07E80000}, /* 5 */
00093     {0x00000025, 0x07F00000}, /* 6 */
00094     {0x00000025, 0x07F80000}, /* 7 */
00095     {0x00000025, 0x00000000}, /* 8 */
00096     {0x00000025, 0x00080000}, /* 9 */
00097     {0x00000025, 0x00100000}, /* 10 */
00098     {0x00000025, 0x00180000}, /* 11 */
00099     {0x00000025, 0x00200000}, /* 12 */
00100     {0x00000025, 0x00280000}, /* 13 */
00101     {0x00000025, 0x00300000}, /* 14 */
00102     {0x00000025, 0x00380000}, /* 15 */
00103     {0x00000025, 0x00400000}, /* 16 */
00104     {0x00000025, 0x00480000}, /* 17 */
00105     {0x00000025, 0x00500000}, /* 18 */
00106     {0x00000025, 0x00580000}, /* 19 */
00107     {0x00000025, 0x00600000}, /* 20 */
00108     {0x00000025, 0x00680000}, /* 21 */
00109     {0x00000025, 0x00700000}, /* 22 */
00110     {0x00000025, 0x00780000}, /* 23 */
00111     {0x00000025, 0x00800000}, /* 24 */
00112     {0x00000025, 0x00880000}, /* 25 */
00113     {0x00000025, 0x00900000}, /* 26 */
00114     {0x00000025, 0x00980000}, /* 27 */
00115     {0x00000025, 0x00A00000}, /* 28 */
00116     {0x00000025, 0x00A80000}, /* 29 */
00117     {0x00000025, 0x00B00000}, /* 30 */
00118     {0x00000025, 0x00B80000}, /* 31 */
00119     {0x00000025, 0x00C00000}, /* 32 */
00120     {0x00000025, 0x00C80000}, /* 33 */
00121     {0x00000025, 0x00D00000}, /* 34 */
00122     {0x00000025, 0x00D80000}, /* 35 */
00123     {0x00000025, 0x00E00000}, /* 36 */
00124     {0x00000025, 0x00E80000}, /* 37 */
00125     {0x00000025, 0x00F00000}, /* 38 */
00126     {0x00000025, 0x00F80000}, /* 39 */
00127     {0x00000025, 0x01000000}, /* 40 */
00128     {0x00000026, 0x07080000}, /* 41 */
00129     {0x00000026, 0x07100000}, /* 42 */
00130     {0x00000026, 0x07180000}, /* 43 */
00131     {0x00000026, 0x07200000}, /* 44 */
00132     {0x00000026, 0x07280000}, /* 45 */
00133     {0x00000026, 0x07300000}, /* 46 */
00134     {0x00000026, 0x07380000}, /* 47 */
00135     {0x00000026, 0x07400000}, /* 48 */
00136     {0x00000026, 0x07480000}, /* 49 */
00137     {0x00000026, 0x07500000}, /* 50 */
00138     {0x00000026, 0x07580000}, /* 51 */
00139     {0x00000026, 0x07600000}, /* 52 */
00140     {0x00000026, 0x07680000}, /* 53 */
00141     {0x00000026, 0x07700000}, /* 54 */
00142     {0x00000026, 0x07780000}, /* 55 */
00143     {0x00000026, 0x07800000}, /* 56 */
00144     {0x00000026, 0x07880000}, /* 57 */
00145     {0x00000026, 0x07900000}, /* 58 */
00146     {0x00000026, 0x07980000}, /* 59 */
00147     {0x00000026, 0x07A00000}, /* 60 */
00148     {0x00000026, 0x07A80000}, /* 61 */
00149     {0x00000026, 0x07B00000}, /* 62 */
00150     {0x00000026, 0x07B80000}, /* 63 */
00151     {0x00000026, 0x07C00000}, /* 64 */
00152     {0x00000026, 0x07C80000}, /* 65 */
00153     {0x00000026, 0x07D00000}, /* 66 */
00154     {0x00000026, 0x07D80000}, /* 67 */
00155     {0x00000026, 0x07E00000}, /* 68 */
00156     {0x00000026, 0x07E80000}, /* 69 */
00157     {0x00000026, 0x07F00000}, /* 70 */
00158     {0x00000026, 0x07F80000}, /* 71 */
00159     {0x00000026, 0x00000000}, /* 72 */
00160     {0x00000026, 0x00080000}, /* 73 */
00161     {0x00000026, 0x00100000}, /* 74 */
00162     {0x00000026, 0x00180000}, /* 75 */
00163     {0x00000026, 0x00200000}, /* 76 */
00164     {0x00000026, 0x00280000}, /* 77 */
00165     {0x00000026, 0x00300000}, /* 78 */
00166     {0x00000026, 0x00380000}, /* 79 */
00167     {0x00000026, 0x00400000}, /* 80 */
00168     {0x00000026, 0x00480000}, /* 81 */
00169     {0x00000026, 0x00500000}, /* 82 */
00170     {0x00000026, 0x00580000}, /* 83 */
00171     {0x00000026, 0x00600000}, /* 84 */
00172     {0x00000026, 0x00680000}, /* 85 */
00173     {0x00000026, 0x00700000}, /* 86 */
00174     {0x00000026, 0x00780000}, /* 87 */
00175     {0x00000026, 0x00800000}, /* 88 */
00176     {0x00000026, 0x00880000}, /* 89 */
00177     {0x00000026, 0x00900000}, /* 90 */
00178     {0x00000026, 0x00980000}, /* 91 */
00179     {0x00000026, 0x00A00000}, /* 92 */
00180     {0x00000026, 0x00A80000}, /* 93 */
00181     {0x00000026, 0x00B00000}, /* 94 */
00182     {0x00000026, 0x00B80000}, /* 95 */
00183     {0x00000026, 0x00C00000}, /* 96 */
00184     {0x00000026, 0x00C80000}, /* 97 */
00185     {0x00000026, 0x00D00000}, /* 98 */
00186     {0x00000026, 0x00D80000}, /* 99 */
00187     {0x00000026, 0x00E00000}, /* 100 */
00188     {0x00000026, 0x00E80000}, /* 101 */
00189     {0x00000026, 0x00F00000}, /* 102 */
00190     {0x00000026, 0x00F80000}, /* 103 */
00191     {0x00000026, 0x01000000}, /* 104 */
00192     {0x00000027, 0x07080000}, /* 105 */
00193     {0x00000027, 0x07100000}, /* 106 */
00194     {0x00000027, 0x07180000}, /* 107 */
00195     {0x00000027, 0x07200000}, /* 108 */
00196     {0x00000027, 0x07280000}, /* 109 */
00197     {0x00000027, 0x07300000}, /* 110 */
00198     {0x00000027, 0x07380000}, /* 111 */
00199     {0x00000027, 0x07400000}, /* 112 */
00200     {0x00000027, 0x07480000}, /* 113 */
00201     {0x00000027, 0x07500000}, /* 114 */
00202     {0x00000027, 0x07580000}, /* 115 */
00203     {0x00000027, 0x07600000}, /* 116 */
00204     {0x00000027, 0x07680000}, /* 117 */
00205     {0x00000027, 0x07700000}, /* 118 */
00206     {0x00000027, 0x07780000}, /* 119 */
00207     {0x00000027, 0x07800000}, /* 120 */
00208     {0x00000027, 0x07880000}, /* 121 */
00209     {0x00000027, 0x07900000}, /* 122 */
00210     {0x00000027, 0x07980000}, /* 123 */
00211     {0x00000027, 0x07A00000}, /* 124 */
00212     {0x00000027, 0x07A80000}, /* 125 */
00213     {0x00000027, 0x07B00000}, /* 126 */
00214     {0x00000027, 0x07B80000}  /* 127 */
00215 };
00216 
00217 /* Registers for timing of TX & RX */
00218 #if RADIO_IS_GEN_3P0
00219 uint16_t tx_rx_on_delay = TX_RX_ON_DELinit;
00220 uint16_t tx_rx_synth_delay = TX_RX_SYNTH_init;
00221 #else
00222 #if RF_OSC_26MHZ == 1
00223 uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL_26MHZ;
00224 #else
00225 uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL;
00226 #endif /* RF_OSC_26MHZ == 1 */
00227 uint16_t tx_rx_synth_delay = TX_RX_SYNTH_DELAY_VAL;
00228 #endif /* RADIO_IS_GEN_3P0 */
00229 
00230 /* NOTE: These arrays MUST be ordered in the same order as the radio_mode_t enumeration. */
00231 #if RADIO_IS_GEN_3P0
00232 const xcvr_mode_datarate_config_t * mode_configs_dr_2mbps[NUM_RADIO_MODES] =
00233 {
00234     (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
00235     (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
00236     (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
00237     &xcvr_GFSK_BT_0p5_h_0p5_2mbps_config,
00238     &xcvr_GFSK_BT_0p5_h_0p32_2mbps_config,
00239     (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
00240     (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */
00241     &xcvr_GFSK_BT_0p3_h_0p5_2mbps_config,
00242     &xcvr_GFSK_BT_0p7_h_0p5_2mbps_config,
00243     &xcvr_MSK_2mbps_config,
00244 };
00245 #endif /* RADIO_IS_GEN_3P0 */
00246 
00247 const xcvr_mode_datarate_config_t * mode_configs_dr_1mbps[NUM_RADIO_MODES] =
00248 {
00249     &xcvr_BLE_1mbps_config,
00250 #if RADIO_IS_GEN_2P1
00251     NULL,
00252     NULL,
00253 #else
00254     &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */
00255     &xcvr_ANT_1mbps_config,
00256 #endif /* RADIO_IS_GEN_2P1 */
00257     &xcvr_GFSK_BT_0p5_h_0p5_1mbps_config,
00258     &xcvr_GFSK_BT_0p5_h_0p32_1mbps_config,
00259     &xcvr_GFSK_BT_0p5_h_0p7_1mbps_config,
00260     &xcvr_GFSK_BT_0p5_h_1p0_1mbps_config,
00261     &xcvr_GFSK_BT_0p3_h_0p5_1mbps_config,
00262     &xcvr_GFSK_BT_0p7_h_0p5_1mbps_config,
00263     &xcvr_MSK_1mbps_config,
00264 };
00265 
00266 const xcvr_mode_datarate_config_t * mode_configs_dr_500kbps[NUM_RADIO_MODES] =
00267 {
00268     &xcvr_BLE_1mbps_config, /* Invalid option */
00269 #if RADIO_IS_GEN_2P1
00270     NULL,
00271     NULL,
00272 #else
00273     &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 setting */
00274     &xcvr_ANT_1mbps_config, /* Invalid option */
00275 #endif /* RADIO_IS_GEN_2P1 */
00276     &xcvr_GFSK_BT_0p5_h_0p5_500kbps_config,
00277     &xcvr_GFSK_BT_0p5_h_0p32_500kbps_config,
00278     &xcvr_GFSK_BT_0p5_h_0p7_500kbps_config,
00279     &xcvr_GFSK_BT_0p5_h_1p0_500kbps_config,
00280     &xcvr_GFSK_BT_0p3_h_0p5_500kbps_config,
00281     &xcvr_GFSK_BT_0p7_h_0p5_500kbps_config,
00282     &xcvr_MSK_500kbps_config,
00283 };
00284 const xcvr_mode_datarate_config_t * mode_configs_dr_250kbps[NUM_RADIO_MODES] =
00285 {
00286     &xcvr_BLE_1mbps_config, /* Invalid option */
00287 #if RADIO_IS_GEN_2P1
00288     NULL,
00289     NULL,
00290 #else
00291     &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */
00292     &xcvr_ANT_1mbps_config, /* Invalid option */
00293 #endif /* RADIO_IS_GEN_2P1 */
00294     &xcvr_GFSK_BT_0p5_h_0p5_250kbps_config,
00295     &xcvr_GFSK_BT_0p5_h_0p32_250kbps_config,
00296     &xcvr_GFSK_BT_0p5_h_0p7_250kbps_config,
00297     &xcvr_GFSK_BT_0p5_h_1p0_250kbps_config,
00298     &xcvr_GFSK_BT_0p3_h_0p5_250kbps_config,
00299     &xcvr_GFSK_BT_0p7_h_0p5_250kbps_config,
00300     &xcvr_MSK_250kbps_config,
00301 };
00302 
00303 static xcvr_currConfig_t current_xcvr_config;
00304 
00305 void rf_osc_startup(void)
00306 {
00307     if (!RF_OSCILLATOR_READY)
00308     {
00309         RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN_MASK;
00310     }
00311     while (!RF_OSCILLATOR_READY)
00312     {
00313         /* Wait for RF_OSC_READY to be asserted before continuing */
00314     }
00315 }
00316 
00317 void rf_osc_shutdown(void)
00318 {
00319     if (!RF_OSCILLATOR_STAYS_ON)
00320     {
00321         RSIM->CONTROL &= ~RSIM_CONTROL_RF_OSC_EN_MASK;
00322     }
00323 }
00324     
00325 /*******************************************************************************
00326  * Code
00327  ******************************************************************************/
00328 xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate)
00329 {
00330     const xcvr_mode_datarate_config_t * mode_datarate_config;
00331     const xcvr_datarate_config_t * datarate_config ;
00332     const xcvr_mode_config_t * radio_mode_cfg;
00333     const xcvr_common_config_t * radio_common_config;
00334 
00335     xcvrStatus_t status;
00336 
00337     IFR_SW_TRIM_TBL_ENTRY_T sw_trim_tbl[] =
00338     {
00339         {TRIM_STATUS, 0, FALSE}, /*< Fetch the trim status word if available.*/
00340         {TRIM_VERSION, 0, FALSE} /*< Fetch the trim version number if available.*/
00341     };
00342     const uint8_t NUM_TRIM_TBL_ENTRIES = sizeof(sw_trim_tbl)/sizeof(IFR_SW_TRIM_TBL_ENTRY_T);
00343 
00344 #ifndef SIMULATION
00345 
00346 #if (EXTERNAL_CLOCK_GEN)
00347     RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK; /* Only when external clock is being used */
00348 #endif /* EXTERNAL_CLOCK_GEN */
00349 
00350 #if RADIO_IS_GEN_2P0
00351     RSIM->RF_OSC_CTRL &= ~RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK; /* Set EXT_OSC_OVRD value to zero */
00352     RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */   
00353 #endif /* RADIO_IS_GEN_2P0 */
00354 
00355     /* Check that this is the proper radio version */
00356     {
00357         uint8_t radio_id = ((RSIM->MISC & RSIM_MISC_RADIO_VERSION_MASK)>>RSIM_MISC_RADIO_VERSION_SHIFT);
00358 
00359         if (
00360 #if RADIO_IS_GEN_3P0
00361             (radio_id != 0x5) /* KW3 Gen3 */
00362 #elif RADIO_IS_GEN_2P1
00363             (radio_id != 0x5) /* KW35 Gen2.1 */
00364 #else
00365             (radio_id != 0x3) &&  /* KW41/31/21 v1 */
00366             (radio_id != 0xB) /* KW41/31/21 v1.1 */
00367 #endif /* RADIO_IS_GEN_3P0 */
00368             )
00369         {
00370             XcvrPanic(WRONG_RADIO_ID_DETECTED, (uint32_t)&XCVR_Init);
00371         }
00372     }
00373 
00374 #if RADIO_IS_GEN_3P0
00375     /* Assert Radio Run Request and wait for ack from SPM. */
00376     RSIM->POWER |= RSIM_POWER_RSIM_RUN_REQUEST_MASK;
00377     while ((RSIM->POWER & RSIM_POWER_SPM_RUN_ACK_STAT_MASK) == 0)
00378     {
00379     }
00380     RSIM->CONTROL |= RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK; 
00381     rf_osc_startup(); /* Start RF_OSC to allow radio registers access */
00382 #else
00383     SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK;
00384 
00385     /* Load IFR trim values */
00386     handle_ifr(&sw_trim_tbl[0], NUM_TRIM_TBL_ENTRIES);
00387 #endif /* RADIO_IS_GEN_3P0 */
00388 
00389 #endif /* ifndef SIMULATION */
00390 
00391     /* Perform the desired XCVR initialization and configuration */
00392     status = XCVR_GetDefaultConfig(radio_mode, data_rate, 
00393                                    (const xcvr_common_config_t **)&radio_common_config, 
00394                                    (const xcvr_mode_config_t **)&radio_mode_cfg, 
00395                                    (const xcvr_mode_datarate_config_t **)&mode_datarate_config, 
00396                                    (const xcvr_datarate_config_t **)&datarate_config);
00397                                   
00398     if (status == gXcvrSuccess_c)
00399     {
00400         status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, 
00401                                 (const xcvr_mode_config_t *)radio_mode_cfg, 
00402                                 (const xcvr_mode_datarate_config_t *)mode_datarate_config, 
00403                                 (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_FIRST_INIT);
00404         current_xcvr_config.radio_mode = radio_mode;
00405         current_xcvr_config.data_rate = data_rate;
00406     }
00407 
00408     return status;
00409 }
00410 
00411 void XCVR_Deinit(void)
00412 {
00413 #if RADIO_IS_GEN_3P0
00414     rf_osc_shutdown();
00415     RSIM->POWER |= RSIM_POWER_RSIM_STOP_MODE_MASK; /* Set radio stop mode to RVLLS */
00416     RSIM->POWER &= ~RSIM_POWER_RSIM_RUN_REQUEST_MASK; /* Clear RUN request */
00417 #else
00418 
00419 #endif /* RADIO_IS_GEN_3P0 */
00420 }
00421 
00422 xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, 
00423                                    data_rate_t data_rate, 
00424                                    const xcvr_common_config_t ** com_config, 
00425                                    const xcvr_mode_config_t ** mode_config, 
00426                                    const xcvr_mode_datarate_config_t ** mode_datarate_config, 
00427                                    const xcvr_datarate_config_t ** datarate_config)
00428 {
00429     xcvrStatus_t status = gXcvrSuccess_c;
00430     /* Common configuration pointer */
00431     *com_config = (const xcvr_common_config_t *)&xcvr_common_config;
00432 
00433     /* Mode dependent configuration pointer */
00434     switch (radio_mode)
00435     {
00436 #if !RADIO_IS_GEN_2P1
00437         case ZIGBEE_MODE:
00438             *mode_config = ( const xcvr_mode_config_t *)&zgbe_mode_config; /* Zigbee configuration */
00439             break;
00440         case ANT_MODE:
00441             *mode_config = ( const xcvr_mode_config_t *)&ant_mode_config; /* ANT configuration */
00442             break;
00443 #endif /* !RADIO_IS_GEN_2P1 */
00444         case BLE_MODE:
00445             *mode_config = ( const xcvr_mode_config_t *)&ble_mode_config; /* BLE configuration */
00446             break;
00447         case GFSK_BT_0p5_h_0p5:
00448             *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p5_mode_config; /* GFSK_BT_0p5_h_0p5 configuration */
00449             break;
00450         case GFSK_BT_0p5_h_0p32:
00451             *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p32_mode_config; /* GFSK_BT_0p5_h_0p32 configuration */
00452             break;
00453         case GFSK_BT_0p5_h_0p7:
00454             *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p7_mode_config; /* GFSK_BT_0p5_h_0p7 configuration */
00455             break;
00456         case GFSK_BT_0p5_h_1p0:
00457             *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_1p0_mode_config; /* GFSK_BT_0p5_h_1p0 configuration */
00458             break;
00459         case GFSK_BT_0p3_h_0p5:
00460             *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p3_h_0p5_mode_config; /* GFSK_BT_0p3_h_0p5 configuration */
00461             break;
00462         case GFSK_BT_0p7_h_0p5:
00463             *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p7_h_0p5_mode_config; /* GFSK_BT_0p7_h_0p5 configuration */
00464             break;
00465         case MSK:
00466             *mode_config = ( const xcvr_mode_config_t *)&msk_mode_config; /* MSK configuration */
00467             break;
00468         default:    
00469             status = gXcvrInvalidParameters_c;
00470             break;
00471     }
00472 
00473     /* Data rate dependent and modeXdatarate dependent configuration pointers */
00474     if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */
00475     {
00476         switch (data_rate)
00477         {
00478 #if RADIO_IS_GEN_3P0
00479             case DR_2MBPS:
00480                 if ((radio_mode == GFSK_BT_0p5_h_0p7) || (radio_mode == GFSK_BT_0p5_h_1p0) || (radio_mode == ZIGBEE_MODE) || (radio_mode == BLE_MODE) || (radio_mode == ANT_MODE))
00481                 {
00482                     status = gXcvrInvalidParameters_c;
00483                 }
00484                 else
00485                 {
00486                     *datarate_config = (const xcvr_datarate_config_t *)&xcvr_2mbps_config; /* 2Mbps datarate configurations */
00487                     *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_2mbps[radio_mode];
00488                 }
00489                 break;
00490 #endif /* RADIO_IS_GEN_3P0 */
00491             case DR_1MBPS:
00492                 *datarate_config = (const xcvr_datarate_config_t *)&xcvr_1mbps_config; /* 1Mbps datarate configurations */
00493                 *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_1mbps[radio_mode];
00494                 break;
00495             case DR_500KBPS:
00496                 if (radio_mode == ZIGBEE_MODE)
00497                 {
00498                     /* See fsl_xcvr_zgbe_config.c for settings */
00499 #if !RADIO_IS_GEN_2P1
00500                     *datarate_config = (const xcvr_datarate_config_t *)&xcvr_802_15_4_500kbps_config; /* 500Kbps datarate configurations */
00501 #endif /* !RADIO_IS_GEN_2P1 */
00502                 }
00503                 else
00504                 {
00505                     *datarate_config = (const xcvr_datarate_config_t *)&xcvr_500kbps_config; /* 500Kbps datarate configurations */
00506                 }
00507                 *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_500kbps[radio_mode];
00508                 break;
00509             case DR_250KBPS:
00510                 *datarate_config = (const xcvr_datarate_config_t *)&xcvr_250kbps_config; /* 250Kbps datarate configurations */
00511                 *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_250kbps[radio_mode];
00512                 break;
00513             default:
00514                 status = gXcvrInvalidParameters_c;
00515                 break;
00516         }
00517     }
00518 
00519     return status;
00520 }
00521 
00522 xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, 
00523                             const xcvr_mode_config_t *mode_config, 
00524                             const xcvr_mode_datarate_config_t *mode_datarate_config, 
00525                             const xcvr_datarate_config_t *datarate_config, 
00526                             int16_t tempDegC, 
00527                             XCVR_INIT_MODE_CHG_T first_init)
00528 {
00529     xcvrStatus_t config_status = gXcvrSuccess_c;
00530     uint32_t temp; 
00531 
00532     /* Turn on the module clocks before doing anything */
00533 #if RADIO_IS_GEN_3P0
00534     RSIM->CONTROL |= mode_config->scgc5_clock_ena_bits; /* Same bit storage is used but RSIM bit assignments are applied */
00535 #else
00536     SIM->SCGC5 |= mode_config->scgc5_clock_ena_bits;
00537 #endif /* RADIO_IS_GEN_3P0 */
00538 
00539     /*******************************************************************************/
00540     /* XCVR_ANA configs */
00541     /*******************************************************************************/
00542 
00543     /* Configure PLL Loop Filter */
00544     if (first_init)
00545     {
00546         XCVR_ANA->SY_CTRL_1 &= ~com_config->ana_sy_ctrl1.mask;
00547         XCVR_ANA->SY_CTRL_1 |= com_config->ana_sy_ctrl1.init;
00548     }
00549 
00550     /* Configure VCO KVM */
00551     XCVR_ANA->SY_CTRL_2 &= ~mode_datarate_config->ana_sy_ctrl2.mask;
00552     XCVR_ANA->SY_CTRL_2 |= mode_datarate_config->ana_sy_ctrl2.init;
00553 
00554     /* Configure analog filter bandwidth */
00555     XCVR_ANA->RX_BBA &= ~mode_datarate_config->ana_rx_bba.mask;
00556     XCVR_ANA->RX_BBA |= mode_datarate_config->ana_rx_bba.init;
00557     XCVR_ANA->RX_TZA &= ~mode_datarate_config->ana_rx_tza.mask;
00558     XCVR_ANA->RX_TZA |= mode_datarate_config->ana_rx_tza.init;
00559 
00560 #if RADIO_IS_GEN_2P0
00561     if (first_init)
00562     {
00563         temp = XCVR_ANA->TX_DAC_PA;
00564         temp &= ~XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK;
00565         temp |= XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(4);
00566         XCVR_ANA->TX_DAC_PA = temp;
00567 
00568         temp = XCVR_ANA->BB_LDO_2;
00569         temp &= ~XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK;
00570         temp |= XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(0);
00571         XCVR_ANA->BB_LDO_2 = temp;
00572 
00573         temp = XCVR_ANA->RX_LNA;
00574         temp &= ~XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK;
00575         temp |= XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(1);
00576         XCVR_ANA->RX_LNA = temp;
00577 
00578         temp = XCVR_ANA->BB_LDO_1;
00579         temp &= ~XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK;
00580         temp |= XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(1);
00581         XCVR_ANA->BB_LDO_1 = temp;
00582     }
00583 #endif /* RADIO_IS_GEN_2P0 */
00584 
00585     /*******************************************************************************/
00586     /* XCVR_MISC configs */
00587     /*******************************************************************************/
00588     temp = XCVR_MISC->XCVR_CTRL;
00589     temp &= ~(mode_config->xcvr_ctrl.mask | XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK);
00590     temp |= mode_config->xcvr_ctrl.init;
00591     
00592 #if RF_OSC_26MHZ == 1
00593     {
00594         temp |= XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(1);
00595     }
00596 #endif /* RF_OSC_26MHZ == 1 */
00597 
00598     XCVR_MISC->XCVR_CTRL = temp;
00599 
00600 #if RADIO_IS_GEN_2P1
00601     XCVR_MISC->FAD_CTRL &= ~XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK;
00602 #endif /* RADIO_IS_GEN_2P1 */
00603 
00604     /*******************************************************************************/
00605     /* XCVR_PHY configs */
00606     /*******************************************************************************/
00607 #if RADIO_IS_GEN_3P0
00608     XCVR_PHY->PHY_FSK_PD_CFG0 = mode_config->phy_fsk_pd_cfg0;
00609     XCVR_PHY->PHY_FSK_PD_CFG1 = mode_config->phy_fsk_pd_cfg1;
00610     XCVR_PHY->PHY_FSK_CFG = mode_config->phy_fsk_cfg;
00611     XCVR_PHY->PHY_FSK_MISC = mode_config->phy_fsk_misc | mode_datarate_config->phy_fsk_misc_mode_datarate;
00612     XCVR_PHY->FSK_FAD_CTRL = mode_config->phy_fad_ctrl;
00613 #else
00614     XCVR_PHY->PHY_PRE_REF0 = mode_config->phy_pre_ref0_init;
00615     XCVR_PHY->PRE_REF1 = mode_config->phy_pre_ref1_init;
00616     XCVR_PHY->PRE_REF2 = mode_config->phy_pre_ref2_init;
00617     XCVR_PHY->CFG1 = mode_config->phy_cfg1_init;
00618     XCVR_PHY->CFG2 = mode_datarate_config->phy_cfg2_init;
00619     XCVR_PHY->EL_CFG = mode_config->phy_el_cfg_init | datarate_config->phy_el_cfg_init; /* EL_WIN_SIZE and EL_INTERVAL are datarate dependent, */
00620 #endif /* RADIO_IS_GEN_3P0 */
00621 
00622     /*******************************************************************************/
00623     /* XCVR_PLL_DIG configs */
00624     /*******************************************************************************/
00625     if (first_init)
00626     {
00627         XCVR_PLL_DIG->HPM_BUMP = com_config->pll_hpm_bump;
00628         XCVR_PLL_DIG->MOD_CTRL = com_config->pll_mod_ctrl;
00629         XCVR_PLL_DIG->CHAN_MAP = com_config->pll_chan_map;
00630         XCVR_PLL_DIG->LOCK_DETECT = com_config->pll_lock_detect;
00631         XCVR_PLL_DIG->HPM_CTRL = com_config->pll_hpm_ctrl;
00632 #if !RADIO_IS_GEN_2P1
00633         XCVR_PLL_DIG->HPMCAL_CTRL = com_config->pll_hpmcal_ctrl;
00634 #endif /* !RADIO_IS_GEN_2P1 */
00635         XCVR_PLL_DIG->HPM_SDM_RES = com_config->pll_hpm_sdm_res;
00636         XCVR_PLL_DIG->LPM_CTRL = com_config->pll_lpm_ctrl;
00637         XCVR_PLL_DIG->LPM_SDM_CTRL1 = com_config->pll_lpm_sdm_ctrl1;
00638         XCVR_PLL_DIG->DELAY_MATCH = com_config->pll_delay_match;
00639         XCVR_PLL_DIG->CTUNE_CTRL = com_config->pll_ctune_ctrl;
00640     }
00641 
00642     /*******************************************************************************/
00643     /* XCVR_RX_DIG configs */
00644     /*******************************************************************************/
00645 
00646     /* Configure RF Aux PLL for proper operation based on external clock frequency */
00647     if (first_init)
00648     {
00649         temp = XCVR_ANA->RX_AUXPLL;
00650         temp &= ~XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK;
00651 #if RF_OSC_26MHZ == 1
00652         {
00653             temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(4);
00654         }
00655 #else
00656         {
00657             temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(7);
00658         }
00659 #endif /* RF_OSC_26MHZ == 1 */
00660         XCVR_ANA->RX_AUXPLL = temp;
00661     }
00662     
00663     /* Configure RX_DIG_CTRL */
00664 #if RF_OSC_26MHZ == 1
00665     {
00666         temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */
00667                mode_config->rx_dig_ctrl_init_26mhz | /* Mode  specific portion of RX_DIG_CTRL init */
00668                datarate_config->rx_dig_ctrl_init_26mhz | /* Datarate specific portion of RX_DIG_CTRL init */
00669                XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK; /* Always enable the sample rate converter for 26MHz */
00670     }
00671 #else
00672     {
00673         temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */
00674                mode_config->rx_dig_ctrl_init_32mhz | /* Mode specific portion of RX_DIG_CTRL init */
00675                datarate_config->rx_dig_ctrl_init_32mhz | /* Datarate specific portion of RX_DIG_CTRL init */
00676                0; /* Always disable the sample rate converter for 32MHz */
00677     }
00678 #endif /* RF_OSC_26MHZ == 1 */
00679 
00680     temp |= com_config->rx_dig_ctrl_init;  /* Common portion of RX_DIG_CTRL init */
00681     XCVR_RX_DIG->RX_DIG_CTRL = temp;
00682 
00683     /* DCOC_CAL_IIR */
00684 #if RF_OSC_26MHZ == 1
00685     {
00686         XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_26mhz;
00687     }
00688 #else
00689     {
00690         XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_32mhz;
00691     }
00692 #endif /* RF_OSC_26MHZ == 1 */
00693 
00694     /* DC_RESID_CTRL */
00695 #if RF_OSC_26MHZ == 1
00696     {
00697         XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_26mhz;
00698     }
00699 #else
00700     {
00701         XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_32mhz;
00702     }
00703 #endif /* RF_OSC_26MHZ == 1 */
00704 
00705     /* DCOC_CTRL_0  & _1 */
00706 #if RF_OSC_26MHZ == 1
00707     {
00708         XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_26mhz | datarate_config->dcoc_ctrl_0_init_26mhz; /* Combine common and datarate specific settings */
00709         XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */
00710 #if RADIO_IS_GEN_3P0
00711         XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_26mhz;
00712 #endif /* RADIO_IS_GEN_3P0 */
00713 
00714     }
00715 #else
00716     {
00717         XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_32mhz | datarate_config->dcoc_ctrl_0_init_32mhz; /* Combine common and datarate specific settings */
00718         XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */
00719 #if RADIO_IS_GEN_3P0
00720         XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_32mhz;
00721 #endif /* RADIO_IS_GEN_3P0 */
00722     }
00723 #endif /* RF_OSC_26MHZ == 1 */
00724     if (first_init)
00725     {
00726         /* DCOC_CAL_GAIN */
00727         XCVR_RX_DIG->DCOC_CAL_GAIN = com_config->dcoc_cal_gain_init;
00728 
00729         /* DCOC_CAL_RCP */
00730         XCVR_RX_DIG->DCOC_CAL_RCP = com_config->dcoc_cal_rcp_init;
00731         XCVR_RX_DIG->LNA_GAIN_VAL_3_0 = com_config->lna_gain_val_3_0;
00732         XCVR_RX_DIG->LNA_GAIN_VAL_7_4 = com_config->lna_gain_val_7_4;
00733         XCVR_RX_DIG->LNA_GAIN_VAL_8 = com_config->lna_gain_val_8;
00734         XCVR_RX_DIG->BBA_RES_TUNE_VAL_7_0 = com_config->bba_res_tune_val_7_0;
00735         XCVR_RX_DIG->BBA_RES_TUNE_VAL_10_8 = com_config->bba_res_tune_val_10_8;
00736 
00737         /* LNA_GAIN_LIN_VAL */
00738         XCVR_RX_DIG->LNA_GAIN_LIN_VAL_2_0 = com_config->lna_gain_lin_val_2_0_init;
00739         XCVR_RX_DIG->LNA_GAIN_LIN_VAL_5_3 = com_config->lna_gain_lin_val_5_3_init;
00740         XCVR_RX_DIG->LNA_GAIN_LIN_VAL_8_6 = com_config->lna_gain_lin_val_8_6_init;
00741         XCVR_RX_DIG->LNA_GAIN_LIN_VAL_9 = com_config->lna_gain_lin_val_9_init;
00742 
00743         /* BBA_RES_TUNE_LIN_VAL */
00744         XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_3_0 = com_config->bba_res_tune_lin_val_3_0_init;
00745         XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_7_4 = com_config->bba_res_tune_lin_val_7_4_init;
00746         XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_10_8 = com_config->bba_res_tune_lin_val_10_8_init;
00747 
00748         /* BBA_STEP */
00749         XCVR_RX_DIG->DCOC_BBA_STEP = com_config->dcoc_bba_step_init;
00750 
00751         /* DCOC_TZA_STEP */
00752         XCVR_RX_DIG->DCOC_TZA_STEP_0 = com_config->dcoc_tza_step_00_init;
00753         XCVR_RX_DIG->DCOC_TZA_STEP_1 = com_config->dcoc_tza_step_01_init;
00754         XCVR_RX_DIG->DCOC_TZA_STEP_2 = com_config->dcoc_tza_step_02_init;
00755         XCVR_RX_DIG->DCOC_TZA_STEP_3 = com_config->dcoc_tza_step_03_init;
00756         XCVR_RX_DIG->DCOC_TZA_STEP_4 = com_config->dcoc_tza_step_04_init;
00757         XCVR_RX_DIG->DCOC_TZA_STEP_5 = com_config->dcoc_tza_step_05_init;
00758         XCVR_RX_DIG->DCOC_TZA_STEP_6 = com_config->dcoc_tza_step_06_init;
00759         XCVR_RX_DIG->DCOC_TZA_STEP_7 = com_config->dcoc_tza_step_07_init;
00760         XCVR_RX_DIG->DCOC_TZA_STEP_8 = com_config->dcoc_tza_step_08_init;
00761         XCVR_RX_DIG->DCOC_TZA_STEP_9 = com_config->dcoc_tza_step_09_init;
00762         XCVR_RX_DIG->DCOC_TZA_STEP_10 = com_config->dcoc_tza_step_10_init;
00763 
00764 #if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1)
00765         /* DCOC_CAL_FAIL and DCOC_CAL_PASS */
00766         XCVR_RX_DIG->DCOC_CAL_FAIL_TH = com_config->dcoc_cal_fail_th_init;
00767         XCVR_RX_DIG->DCOC_CAL_PASS_TH = com_config->dcoc_cal_pass_th_init;
00768 #endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */
00769     }
00770 
00771     /* AGC_CTRL_0 .. _3 */
00772     XCVR_RX_DIG->AGC_CTRL_0 = com_config->agc_ctrl_0_init | mode_config->agc_ctrl_0_init;
00773 
00774 #if RF_OSC_26MHZ == 1
00775     {
00776         XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_26mhz | datarate_config->agc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */
00777         XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_26mhz;
00778     }
00779 #else
00780     {
00781         XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_32mhz | datarate_config->agc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */
00782         XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_32mhz;
00783     }
00784 #endif /* RF_OSC_26MHZ == 1 */
00785 
00786     if (first_init)
00787     {
00788         XCVR_RX_DIG->AGC_CTRL_3 = com_config->agc_ctrl_3_init;
00789 
00790         /* AGC_GAIN_TBL_** */
00791         XCVR_RX_DIG->AGC_GAIN_TBL_03_00 = com_config->agc_gain_tbl_03_00_init;
00792         XCVR_RX_DIG->AGC_GAIN_TBL_07_04 = com_config->agc_gain_tbl_07_04_init;
00793         XCVR_RX_DIG->AGC_GAIN_TBL_11_08 = com_config->agc_gain_tbl_11_08_init;
00794         XCVR_RX_DIG->AGC_GAIN_TBL_15_12 = com_config->agc_gain_tbl_15_12_init;
00795         XCVR_RX_DIG->AGC_GAIN_TBL_19_16 = com_config->agc_gain_tbl_19_16_init;
00796         XCVR_RX_DIG->AGC_GAIN_TBL_23_20 = com_config->agc_gain_tbl_23_20_init;
00797         XCVR_RX_DIG->AGC_GAIN_TBL_26_24 = com_config->agc_gain_tbl_26_24_init;
00798 
00799         /* RSSI_CTRL_0 */
00800         XCVR_RX_DIG->RSSI_CTRL_0 = com_config->rssi_ctrl_0_init;
00801 
00802 #if RADIO_IS_GEN_3P0
00803         XCVR_RX_DIG->RSSI_CTRL_1 = com_config->rssi_ctrl_1_init;
00804 #endif /* RADIO_IS_GEN_3P0 */
00805 
00806         /* CCA_ED_LQI_0 and _1 */
00807         XCVR_RX_DIG->CCA_ED_LQI_CTRL_0 = com_config->cca_ed_lqi_ctrl_0_init;
00808         XCVR_RX_DIG->CCA_ED_LQI_CTRL_1 = com_config->cca_ed_lqi_ctrl_1_init;
00809     }
00810 
00811     /* Channel filter coefficients */
00812 #if RF_OSC_26MHZ == 1
00813     {
00814         XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_0;
00815         XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_1;
00816         XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_2;
00817         XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_3;
00818         XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_4;
00819         XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_5;
00820         XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_6;
00821         XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_7;
00822         XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_8;
00823         XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_9;
00824         XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_10;
00825         XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_11;
00826     }
00827 #else
00828     {
00829         XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_0;
00830         XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_1;
00831         XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_2;
00832         XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_3;
00833         XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_4;
00834         XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_5;
00835         XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_6;
00836         XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_7;
00837         XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_8;
00838         XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_9;
00839         XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_10;
00840         XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_11;
00841     }
00842 #endif /* RF_OSC_26MHZ == 1 */
00843 
00844     XCVR_RX_DIG->RX_RCCAL_CTRL0 = mode_datarate_config->rx_rccal_ctrl_0;
00845     XCVR_RX_DIG->RX_RCCAL_CTRL1 = mode_datarate_config->rx_rccal_ctrl_1;
00846 
00847     /*******************************************************************************/
00848     /* XCVR_TSM configs */
00849     /*******************************************************************************/
00850     XCVR_TSM->CTRL = com_config->tsm_ctrl;
00851 
00852 #if RADIO_IS_GEN_2P0
00853     if ((mode_config->radio_mode != ZIGBEE_MODE) && (mode_config->radio_mode != BLE_MODE))
00854     {
00855         XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_DATA_PADDING_EN_MASK;
00856     }
00857 #endif /* RADIO_IS_GEN_2P0 */
00858 
00859     if (first_init)
00860     {
00861 #if !RADIO_IS_GEN_2P1
00862         XCVR_MISC->LPPS_CTRL = com_config->lpps_ctrl_init; /* Register is in XCVR_MISC but grouped with TSM for intialization */
00863 #endif /* !RADIO_IS_GEN_2P1 */
00864 
00865         XCVR_TSM->OVRD2 = com_config->tsm_ovrd2_init;
00866         /* TSM registers and timings - dependent upon clock frequency */
00867 #if RF_OSC_26MHZ == 1
00868         {
00869             XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_26mhz;
00870             XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_26mhz;
00871             XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_26mhz;
00872             XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_26mhz;
00873             XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_26mhz;
00874             XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_26mhz;
00875             XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_26mhz;
00876             XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_26mhz;
00877             XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_26mhz;
00878             XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_26mhz;
00879             XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_26mhz;
00880             XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_26mhz;
00881             XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_26mhz;
00882             XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_26mhz;
00883             XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_26mhz;
00884             XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_26mhz;
00885             XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_26mhz;
00886             XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_26mhz;
00887             XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_26mhz;
00888             XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_26mhz;
00889             XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_26mhz;
00890             XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_26mhz;
00891         }
00892 #else
00893         {
00894             XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_32mhz;
00895             XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_32mhz;
00896             XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_32mhz;
00897             XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_32mhz;
00898             XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_32mhz;
00899             XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_32mhz;
00900             XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_32mhz;
00901             XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_32mhz;
00902             XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_32mhz;
00903             XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_32mhz;
00904             XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_32mhz;
00905             XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_32mhz;
00906             XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_32mhz;
00907             XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_32mhz;
00908             XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_32mhz;
00909             XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_32mhz;
00910             XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_32mhz;
00911             XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_32mhz;
00912             XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_32mhz;
00913             XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_32mhz;
00914             XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_32mhz;
00915             XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_32mhz;
00916         }
00917 #endif /* RF_OSC_26MHZ == 1 */
00918 
00919         /* TSM timings independent of clock frequency */
00920         XCVR_TSM->TIMING00 = com_config->tsm_timing_00_init;
00921         XCVR_TSM->TIMING01 = com_config->tsm_timing_01_init;
00922         XCVR_TSM->TIMING02 = com_config->tsm_timing_02_init;
00923         XCVR_TSM->TIMING03 = com_config->tsm_timing_03_init;
00924         XCVR_TSM->TIMING04 = com_config->tsm_timing_04_init;
00925         XCVR_TSM->TIMING05 = com_config->tsm_timing_05_init;
00926         XCVR_TSM->TIMING06 = com_config->tsm_timing_06_init;
00927         XCVR_TSM->TIMING07 = com_config->tsm_timing_07_init;
00928         XCVR_TSM->TIMING08 = com_config->tsm_timing_08_init;
00929         XCVR_TSM->TIMING09 = com_config->tsm_timing_09_init;
00930         XCVR_TSM->TIMING10 = com_config->tsm_timing_10_init;
00931         XCVR_TSM->TIMING11 = com_config->tsm_timing_11_init;
00932         XCVR_TSM->TIMING12 = com_config->tsm_timing_12_init;
00933         XCVR_TSM->TIMING13 = com_config->tsm_timing_13_init;
00934         XCVR_TSM->TIMING15 = com_config->tsm_timing_15_init;
00935         XCVR_TSM->TIMING17 = com_config->tsm_timing_17_init;
00936         XCVR_TSM->TIMING18 = com_config->tsm_timing_18_init;
00937         XCVR_TSM->TIMING19 = com_config->tsm_timing_19_init;
00938         XCVR_TSM->TIMING20 = com_config->tsm_timing_20_init;
00939         XCVR_TSM->TIMING21 = com_config->tsm_timing_21_init;
00940         XCVR_TSM->TIMING22 = com_config->tsm_timing_22_init;
00941         XCVR_TSM->TIMING23 = com_config->tsm_timing_23_init;
00942         XCVR_TSM->TIMING24 = com_config->tsm_timing_24_init;
00943         XCVR_TSM->TIMING26 = com_config->tsm_timing_26_init;
00944         XCVR_TSM->TIMING34 = com_config->tsm_timing_34_init;
00945         XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init;
00946         XCVR_TSM->TIMING38 = com_config->tsm_timing_38_init;
00947         XCVR_TSM->TIMING51 = com_config->tsm_timing_51_init;
00948         XCVR_TSM->TIMING53 = com_config->tsm_timing_53_init;
00949         XCVR_TSM->TIMING57 = com_config->tsm_timing_57_init;
00950         XCVR_TSM->TIMING58 = com_config->tsm_timing_58_init;
00951         
00952 #if RF_OSC_26MHZ == 1
00953         {
00954             XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) |
00955                                    XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) |
00956                                    XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU_26MHZ) |
00957                                    XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD_26MHZ);
00958         }
00959 #else
00960         {
00961             XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) |
00962                                    XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) |
00963                                    XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU) |
00964                                    XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD);
00965         }
00966 #endif /* RF_OSC_26MHZ == 1 */
00967 
00968         XCVR_TSM->PA_RAMP_TBL0 = com_config->pa_ramp_tbl_0_init;
00969         XCVR_TSM->PA_RAMP_TBL1 = com_config->pa_ramp_tbl_1_init;
00970         
00971 #if RADIO_IS_GEN_3P0
00972         XCVR_TSM->PA_RAMP_TBL2 = com_config->pa_ramp_tbl_2_init;
00973         XCVR_TSM->PA_RAMP_TBL3 = com_config->pa_ramp_tbl_3_init;
00974 
00975         /* Apply PA_RAMP_TIME == 4usec adjustments to TX_WD signals */
00976 #if (PA_RAMP_TIME == 4)
00977         XCVR_TSM->TIMING00 += B1(2); /* (bb_ldo_hf_en) */
00978         XCVR_TSM->TIMING01 += B1(2); /* (bb_ldo_adcdac_en) */
00979         XCVR_TSM->TIMING03 += B1(2); /* (bb_ldo_pd_en) */
00980         XCVR_TSM->TIMING04 += B1(2); /* (bb_ldo_fdbk_en) */
00981         XCVR_TSM->TIMING05 += B1(2); /* (bb_ldo_vcolo_en) */
00982         XCVR_TSM->TIMING06 += B1(2); /* (bb_ldo_vtref_en) */
00983         XCVR_TSM->TIMING10 += B1(2); /* (bb_xtal_pll_ref_clk_en) */
00984         XCVR_TSM->TIMING11 += B1(2); /* (bb_xtal_dac_ref_clk_en) */
00985         XCVR_TSM->TIMING15 += B1(2); /* (sy_vco_en) */
00986         XCVR_TSM->TIMING17 += B1(2); /* (sy_lo_tx_buf_en) */
00987         XCVR_TSM->TIMING18 += B1(2); /* (sy_divn_en) */
00988         XCVR_TSM->TIMING20 += B1(2); /*  (sy_pd_en) */
00989         XCVR_TSM->TIMING21 += B1(2); /* (sy_lo_divn_en) */
00990         XCVR_TSM->TIMING23 += B1(2); /* (sy_lo_tx_en) */
00991         XCVR_TSM->TIMING26 += B1(2); /* (tx_pa_en) */ 
00992         XCVR_TSM->TIMING34 += B1(2); /* (pll_dig_en) */
00993         XCVR_TSM->TIMING35 += B1(2); /* (tx_dig_en) */
00994         XCVR_TSM->TIMING38 += B1(2); /* (sigma_delta_en) */
00995         XCVR_TSM->TIMING58 += B1(2)  /* (tx_hpm_dac_en) */
00996         temp = XCVR_TSM->TIMING14;
00997         temp &= 0xFFFF0000; 
00998         temp |= B0(END_OF_TX_WU - 4) | B1(END_OF_TX_WU + 1); /* (sy_pd_cycle_slip_ld_ft_en) */
00999         XCVR_TSM->TIMING14 = temp;
01000 #endif /* (PA_RAMP_TIME == 4) */
01001 #endif /* RADIO_IS_GEN_3P0 */
01002     }
01003     
01004 #if RADIO_IS_GEN_3P0
01005     if (mode_config->radio_mode == ZIGBEE_MODE)
01006     {
01007         temp = XCVR_TSM->TIMING35;
01008         temp &= ~(B0(0xFF));
01009         if (DATA_PADDING_EN == 1)
01010         {
01011             temp |= B0(END_OF_TX_WU - 2 - 8); /* Adjust for data padding time */
01012         }
01013         else
01014         {
01015             temp |= B0(END_OF_TX_WU - 2); /* No data padding adjustment */
01016         }
01017         XCVR_TSM->TIMING35 = temp;
01018     }
01019 #else
01020 
01021     if ((mode_datarate_config->radio_mode == MSK) && ((mode_datarate_config->data_rate == DR_500KBPS) || (mode_datarate_config->data_rate == DR_250KBPS)))
01022     {
01023         /* Apply a specific value of TX_DIG_EN which assumes no DATA PADDING */
01024         XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | B0(TX_DIG_EN_ASSERT_MSK500); /* LSbyte is mode specific */
01025     }
01026     else
01027     {
01028         XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | mode_config->tsm_timing_35_init; /* LSbyte is mode specific, other bytes are common */
01029     }
01030 #endif /* RADIO_IS_GEN_3P0 */
01031     
01032     /*******************************************************************************/
01033     /* XCVR_TX_DIG configs */
01034     /*******************************************************************************/
01035 #if RF_OSC_26MHZ == 1
01036     {
01037         XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_26mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */
01038         XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_26mhz;
01039         XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_26mhz;
01040     }
01041 #else
01042     {
01043         XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_32mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */
01044         XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_32mhz;
01045         XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_32mhz;
01046     }
01047 #endif /* RF_OSC_26MHZ == 1 */
01048 
01049     if (first_init)
01050     {
01051         XCVR_TX_DIG->CTRL = com_config->tx_ctrl;
01052         XCVR_TX_DIG->DATA_PADDING = com_config->tx_data_padding;
01053         XCVR_TX_DIG->DFT_PATTERN = com_config->tx_dft_pattern;
01054         
01055 #if !RADIO_IS_GEN_2P1
01056         XCVR_TX_DIG->RF_DFT_BIST_1 = com_config->rf_dft_bist_1;
01057         XCVR_TX_DIG->RF_DFT_BIST_2 = com_config->rf_dft_bist_2;
01058 #endif /* !RADIO_IS_GEN_2P1 */
01059     }
01060 
01061     XCVR_TX_DIG->GFSK_CTRL = mode_config->tx_gfsk_ctrl;
01062 
01063 #ifndef SIMULATION
01064 #if (TRIM_BBA_DCOC_DAC_AT_INIT)
01065     if (first_init)
01066     {
01067         uint32_t end_of_rx_wu = 0;
01068         XCVR_ForceRxWu();
01069         /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */
01070         temp = XCVR_TSM->END_OF_SEQ;
01071         end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
01072         while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {};
01073 
01074 //        if (!rx_bba_dcoc_dac_trim_shortIQ())
01075         if (!rx_bba_dcoc_dac_trim_DCest())
01076         {
01077             config_status = gXcvrTrimFailure_c;
01078         }
01079 
01080         XCVR_ForceRxWd();
01081         DCOC_DAC_INIT_Cal (1);
01082     }
01083 #endif /* TRIM_BBA_DCOC_DAC_AT_INIT */
01084 #endif /* ifndef SIMULATION */
01085     return config_status;
01086 }
01087 
01088 void XCVR_Reset(void)
01089 {
01090 #if RADIO_IS_GEN_3P0
01091 #else
01092     RSIM->CONTROL |= RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* Assert radio software reset */
01093     RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset */
01094     RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset a second time per RADIO_RESET bit description */
01095 #endif /* RADIO_IS_GEN_3P0 */
01096 }
01097 
01098 xcvrStatus_t XCVR_ChangeMode (radio_mode_t new_radio_mode, data_rate_t new_data_rate) /* Change from one radio mode to another */
01099 {
01100     xcvrStatus_t status;
01101     const xcvr_mode_datarate_config_t * mode_datarate_config;
01102     const xcvr_datarate_config_t * datarate_config ;
01103     const xcvr_mode_config_t * radio_mode_cfg;
01104     const xcvr_common_config_t * radio_common_config;
01105 
01106     status = XCVR_GetDefaultConfig(new_radio_mode, new_data_rate, (void *)&radio_common_config, (void *)&radio_mode_cfg, (void *)&mode_datarate_config, (void *)&datarate_config );
01107     
01108     if (status == gXcvrSuccess_c)
01109     {
01110         status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, 
01111                                 (const xcvr_mode_config_t *)radio_mode_cfg, 
01112                                 (const xcvr_mode_datarate_config_t *)mode_datarate_config, 
01113                                 (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_MODE_CHANGE);
01114         current_xcvr_config.radio_mode = new_radio_mode;
01115         current_xcvr_config.data_rate = new_data_rate;
01116     }
01117 
01118     return status;
01119 }
01120 
01121 void XCVR_EnaNBRSSIMeas( uint8_t IIRnbEnable )
01122 {
01123     if (IIRnbEnable)
01124     {
01125         XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK;
01126     }
01127     else
01128     {
01129         XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK;
01130     }
01131 }
01132 
01133 xcvrStatus_t XCVR_OverrideFrequency ( uint32_t freq, uint32_t refOsc )
01134 {
01135     double integer_used_in_Hz, 
01136            integer_used_in_LSB, 
01137            numerator_fraction, 
01138            numerator_in_Hz, 
01139            numerator_in_LSB, 
01140            numerator_unrounded,
01141            real_int_and_fraction, 
01142            real_fraction, 
01143            requested_freq_in_LSB,
01144            sdm_lsb;
01145     uint32_t temp;
01146     static uint32_t integer_truncated,
01147                     integer_to_use;
01148     static int32_t numerator_rounded;
01149 
01150     /* Configure for Coarse Tune */
01151     uint32_t coarse_tune_target = freq / 1000000;
01152 
01153     temp = XCVR_PLL_DIG->CTUNE_CTRL;
01154     temp &= ~XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK;
01155     temp |= XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(coarse_tune_target);
01156     XCVR_PLL_DIG->CTUNE_CTRL = temp;
01157 
01158     /* Calculate the Low Port values */
01159     sdm_lsb = refOsc / 131072.0;
01160 
01161     real_int_and_fraction = freq / (refOsc * 2.0);
01162 
01163     integer_truncated = (uint32_t) trunc(real_int_and_fraction);
01164 
01165     real_fraction = real_int_and_fraction - integer_truncated;
01166 
01167     if (real_fraction > 0.5) 
01168     {
01169         integer_to_use = integer_truncated + 1;
01170     } 
01171     else                     
01172     {
01173         integer_to_use = integer_truncated;
01174     }
01175 
01176     numerator_fraction = real_int_and_fraction - integer_to_use;
01177 
01178     integer_used_in_Hz  = integer_to_use * refOsc * 2;
01179     integer_used_in_LSB = integer_used_in_Hz / sdm_lsb;
01180 
01181     numerator_in_Hz  = numerator_fraction * refOsc * 2;
01182     numerator_in_LSB = numerator_in_Hz    / sdm_lsb;
01183 
01184     requested_freq_in_LSB = integer_used_in_LSB + numerator_in_LSB;
01185 
01186     numerator_unrounded = (requested_freq_in_LSB - integer_used_in_LSB) * 256;
01187 
01188     numerator_rounded = (int32_t)round(numerator_unrounded);
01189 
01190     /* Write the Low Port Integer and Numerator */
01191     temp = XCVR_PLL_DIG->LPM_SDM_CTRL1;
01192     temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK;
01193     temp |= (XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(integer_to_use) | 
01194              XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK);
01195     XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp;
01196 
01197     XCVR_PLL_DIG->LPM_SDM_CTRL2 = numerator_rounded;
01198 
01199     return gXcvrSuccess_c;
01200 }
01201 
01202 void XCVR_RegisterPanicCb ( panic_fptr fptr ) /* Allow upper layers to provide PANIC callback */
01203 {
01204     s_PanicFunctionPtr = fptr;
01205 }
01206 
01207 void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address)
01208 {
01209     if ( s_PanicFunctionPtr != NULL)
01210     {
01211         s_PanicFunctionPtr(panic_id, panic_address, 0, 0);
01212     }
01213     else
01214     {
01215         uint8_t dummy;
01216 
01217         while(1)
01218         {
01219             dummy = dummy;
01220         }
01221     }
01222 }
01223 
01224 healthStatus_t XCVR_HealthCheck ( void ) /* Allow upper layers to poll the radio health */
01225 {
01226     return (healthStatus_t)NO_ERRORS;
01227 }
01228 
01229 void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control)
01230 {
01231 
01232 }
01233 
01234 /* Helper function to map radio mode to LL usage */
01235 link_layer_t map_mode_to_ll(radio_mode_t mode)
01236 {
01237     link_layer_t llret;
01238     switch (mode)
01239     {
01240         case BLE_MODE:
01241             llret = BLE_LL;
01242             break;
01243         case ZIGBEE_MODE:
01244             llret = ZIGBEE_LL;
01245             break;
01246         case ANT_MODE:
01247             llret = ANT_LL;
01248             break;
01249         case GFSK_BT_0p5_h_0p5:
01250         case GFSK_BT_0p5_h_0p32:
01251         case GFSK_BT_0p5_h_0p7:
01252         case GFSK_BT_0p5_h_1p0:
01253         case GFSK_BT_0p3_h_0p5:
01254         case GFSK_BT_0p7_h_0p5:
01255         case MSK: 
01256             llret = GENFSK_LL;
01257             break;
01258         default:
01259             llret = UNASSIGNED_LL;
01260             break;
01261     }
01262     return llret;
01263 }
01264 
01265 #if RADIO_IS_GEN_3P0
01266 void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address)
01267 {
01268     XCVR_PHY->NTW_ADR_BSM = bsm_ntw_address;
01269 }
01270 
01271 uint32_t XCVR_GetBSM_NTW_Address(void)
01272 {
01273     return XCVR_PHY->NTW_ADR_BSM;
01274 }
01275 #endif /* RADIO_IS_GEN_3P0 */
01276 
01277 /* Setup IRQ mapping to LL interrupt outputs in XCVR_CTRL */
01278 xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping)
01279 {
01280     link_layer_t int0 = map_mode_to_ll(irq0_mapping);
01281     link_layer_t int1 = map_mode_to_ll(irq1_mapping);
01282     xcvrStatus_t statusret;
01283     /* Make sure the two LL's requested aren't the same */
01284     if (int0 == int1)
01285     {
01286         statusret = gXcvrInvalidParameters_c;
01287     }
01288     else
01289     {
01290         uint32_t temp;
01291         temp = XCVR_MISC->XCVR_CTRL;
01292         temp &= ~(XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK);
01293         temp |= (XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL(int0) | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL(int1));
01294         XCVR_MISC->XCVR_CTRL = temp;
01295         statusret = gXcvrSuccess_c;
01296     }
01297     return statusret;
01298 }
01299 
01300 /* Get current state of IRQ mapping for either  radio INT0 or INT1 */
01301 link_layer_t XCVR_GetIRQMapping(uint8_t int_num)
01302 {
01303     if (int_num == 0)
01304     {
01305         return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT);
01306     }
01307     else
01308     {
01309         return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT);
01310     }
01311 }
01312 
01313 /* Get current state of radio mode and data rate */
01314 xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config)
01315 {
01316     xcvrStatus_t status = gXcvrInvalidParameters_c;
01317     if (curr_config != NULL)
01318     {
01319         curr_config->radio_mode = current_xcvr_config.radio_mode;
01320         curr_config->data_rate = current_xcvr_config.data_rate;
01321         status = gXcvrSuccess_c;
01322     }
01323     return status;
01324 }
01325 
01326 /* Customer level trim functions */
01327 xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim)
01328 {
01329     xcvrStatus_t status = gXcvrInvalidParameters_c;
01330 
01331     if ((xtalTrim & 0x80) == 0)
01332     {
01333         uint32_t temp;
01334         temp = RSIM->ANA_TRIM;
01335         temp &= ~RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK;
01336         RSIM->ANA_TRIM = temp | RSIM_ANA_TRIM_BB_XTAL_TRIM(xtalTrim);
01337         status = gXcvrSuccess_c;
01338     }
01339     return status;
01340 }
01341 
01342 uint8_t  XCVR_GetXtalTrim(void)
01343 {
01344     uint8_t temp_xtal;
01345     temp_xtal = ((RSIM->ANA_TRIM & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK)>>RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT);
01346     return temp_xtal;
01347 }
01348 
01349 /* RSSI adjustment */
01350 xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj)
01351 {
01352     XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK;
01353     XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(adj);
01354     return gXcvrSuccess_c;
01355 }
01356 
01357 int8_t  XCVR_GetRssiAdjustment(void)
01358 {
01359     int8_t adj;
01360     adj = (XCVR_RX_DIG->RSSI_CTRL_0 & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK) >> XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT;
01361     return adj;
01362 }
01363 
01364 /* Radio debug functions */
01365 xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel)
01366 {
01367     uint32_t temp;
01368 
01369     if (channel == 0xFF)
01370     {
01371         /* Clear all of the overrides and restore to LL channel control */
01372         temp = XCVR_PLL_DIG->CHAN_MAP;
01373         temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK 
01374 #if !RADIO_IS_GEN_2P1
01375                  | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK
01376 #endif /* !RADIO_IS_GEN_2P1 */
01377 #if RADIO_IS_GEN_3P0
01378                  | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK
01379 #endif /* RADIO_IS_GEN_3P0 */
01380                  );
01381 
01382       XCVR_PLL_DIG->CHAN_MAP = temp; 
01383 
01384       /* Stop using the manual frequency setting */
01385       XCVR_PLL_DIG->LPM_SDM_CTRL1 &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK;
01386 
01387       return gXcvrSuccess_c;
01388     }
01389 
01390     if (channel >= 128)
01391     {
01392         return gXcvrInvalidParameters_c;
01393     }
01394 
01395     if (useMappedChannel)
01396     {
01397         temp = (XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK)>>XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT; /* Extract PROTOCOL bitfield */
01398 
01399         switch (temp)
01400         {
01401 #if !RADIO_IS_GEN_2P1
01402             case 0x3: /* ANT protocol */
01403                 ANT->CHANNEL_NUM = channel;
01404                 break;
01405 #endif /* !RADIO_IS_GEN_2P1 */
01406             case 0x8: /* GENFSK protocol */
01407             case 0x9: /* MSK protocol */
01408                 GENFSK->CHANNEL_NUM = channel;
01409                 break;
01410             default: /* All other protocols */
01411                 temp = XCVR_PLL_DIG->CHAN_MAP;
01412                 temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK
01413 #if RADIO_IS_GEN_3P0
01414                          | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK
01415 #endif /* RADIO_IS_GEN_3P0 */
01416                          );
01417                 temp |= (XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel) | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK
01418 #if !RADIO_IS_GEN_2P1
01419                         | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK
01420 #endif /* !RADIO_IS_GEN_2P1 */
01421                         );
01422                 XCVR_PLL_DIG->CHAN_MAP = temp; 
01423                 break;
01424         }
01425     }
01426     else
01427     {
01428         XCVR_PLL_DIG->CHAN_MAP |= (XCVR_PLL_DIG_CHAN_MAP_BOC_MASK
01429 #if !RADIO_IS_GEN_2P1
01430                                   | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK
01431 #endif /* !RADIO_IS_GEN_2P1 */
01432                                   ); 
01433 
01434         XCVR_PLL_DIG->LPM_SDM_CTRL3 = XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(gPllDenom_c);
01435         XCVR_PLL_DIG->LPM_SDM_CTRL2 = XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(mapTable[channel].numerator);
01436 
01437         temp = XCVR_PLL_DIG->LPM_SDM_CTRL1;
01438         temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK;
01439         temp |= XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(mapTable[channel].integer);
01440         XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp;
01441 
01442         /* Stop using the LL channel map and use the manual frequency setting */
01443         XCVR_PLL_DIG->LPM_SDM_CTRL1 |= XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK;
01444     }
01445 
01446     return gXcvrSuccess_c;
01447 }
01448 
01449 uint32_t XCVR_GetFreq ( void )
01450 {
01451     uint32_t pll_int;
01452     uint32_t pll_num_unsigned;
01453     int32_t pll_num;
01454     uint32_t pll_denom;
01455     float freq_float;
01456 
01457     if (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK) /* Not using mapped channels */
01458     {
01459         pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK) >>
01460                    XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT;
01461 
01462         pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_CTRL2;
01463         pll_denom = XCVR_PLL_DIG->LPM_SDM_CTRL3;
01464     }
01465     else
01466     {
01467         /* Using mapped channels so need to read from the _SELECTED fields to get the values being used */
01468         pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK) >>
01469                    XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT;
01470 
01471         pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_RES1;
01472         pll_denom = XCVR_PLL_DIG->LPM_SDM_RES2;
01473     }
01474 
01475     uint32_t freq = 0;
01476 
01477 #if RF_OSC_26MHZ == 1
01478     uint32_t ref_clk = 26U;
01479 #else
01480     uint32_t ref_clk = 32U;
01481 #endif /* RF_OSC_26MHZ == 1 */
01482 
01483     /* Check if sign bit is asserted */
01484     if (pll_num_unsigned & 0x04000000U)
01485     {
01486         /* Sign extend the numerator */
01487         pll_num = (~pll_num_unsigned + 1) & 0x03FFFFFFU; 
01488 
01489         /* Calculate the frequency in MHz */
01490         freq_float = (ref_clk * 2 * (pll_int - ((float)pll_num / pll_denom))); 
01491     }
01492     else
01493     {
01494         /* Calculate the frequency in MHz */
01495         pll_num = pll_num_unsigned;
01496         freq_float = (ref_clk * 2 * (pll_int + ((float)pll_num / (float)pll_denom))); 
01497     }
01498 
01499     freq = (uint32_t)freq_float;
01500 
01501     return freq;
01502 }
01503 
01504 void XCVR_ForceRxWu(void)
01505 {
01506     XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_RX_EN_MASK;
01507 }
01508 
01509 void XCVR_ForceRxWd(void)
01510 {
01511     XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_RX_EN_MASK;
01512 }
01513 
01514 void XCVR_ForceTxWu(void)
01515 {
01516     XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK;
01517 }
01518 
01519 void XCVR_ForceTxWd(void)
01520 {
01521     XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK;
01522 }
01523 
01524 xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol)
01525 {
01526     uint32_t temp;
01527     if ((protocol != 6) && (protocol != 7))
01528     {
01529         return gXcvrInvalidParameters_c; /* Failure */
01530     }
01531 
01532     if ((rf_channel_freq < 2360) || (rf_channel_freq >2487))
01533     {
01534         return gXcvrInvalidParameters_c; /* failure */
01535     }
01536 
01537     /* Set the DFT Mode */
01538     temp  = XCVR_TX_DIG->CTRL;
01539     temp &= ~XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK;
01540     temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(1);
01541     XCVR_TX_DIG->CTRL = temp;
01542 
01543     /* Choose Protocol 6 or 7 if using the Channel Number register */
01544     temp  = XCVR_MISC->XCVR_CTRL;
01545     temp &= ~XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK;
01546     temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(protocol);
01547     XCVR_MISC->XCVR_CTRL = temp;
01548 
01549     /* Select the RF Channel, using the Channel Number register */
01550     XCVR_OverrideChannel(rf_channel_freq-2360,1);
01551 
01552     /* Warm-up the Radio */
01553     XCVR_ForceTxWu();
01554 
01555     return gXcvrSuccess_c; /* Success */
01556 }
01557 
01558 xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern)
01559 {
01560     uint32_t temp;
01561     uint8_t dft_mode = 0;
01562     uint8_t dft_clk_sel = 0;
01563     xcvrStatus_t status = gXcvrSuccess_c;
01564     
01565     XCVR_ChangeMode(radio_mode, data_rate);
01566     
01567     /* Select the RF Channel, using the Channel Number register */
01568     XCVR_OverrideChannel(channel_num, 1);
01569 
01570     switch (radio_mode)
01571     {
01572         case ZIGBEE_MODE:
01573             dft_mode = 6; /* OQPSK configuration */
01574             break;
01575         case ANT_MODE:
01576         case BLE_MODE:
01577         case GFSK_BT_0p5_h_0p5:
01578         case GFSK_BT_0p5_h_0p32:
01579         case GFSK_BT_0p5_h_0p7:
01580         case GFSK_BT_0p5_h_1p0:
01581         case GFSK_BT_0p3_h_0p5:
01582         case GFSK_BT_0p7_h_0p5:
01583             dft_mode = 2; /* GFSK configuration */
01584             break;
01585         case MSK:
01586             dft_mode = 4; /* MSK configuration */
01587             break;
01588         default:
01589             status = gXcvrInvalidParameters_c;
01590             break;
01591     }
01592 
01593     if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */
01594     {
01595         switch (data_rate)
01596         {
01597             case DR_1MBPS:
01598                 dft_clk_sel = 4;
01599                 break;
01600             case DR_500KBPS:
01601                 dft_clk_sel = 3;
01602                 break;
01603             case DR_250KBPS:
01604                 dft_clk_sel = 2;
01605                 break;
01606             default:
01607                 status = gXcvrInvalidParameters_c;
01608                 break;
01609         }
01610     }
01611 
01612     temp = XCVR_TX_DIG->CTRL;
01613     temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | XCVR_TX_DIG_CTRL_LFSR_EN_MASK);
01614     temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) |
01615             XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) |
01616             XCVR_TX_DIG_CTRL_TX_DFT_EN(1) |
01617             XCVR_TX_DIG_CTRL_LFSR_EN(0);
01618     XCVR_TX_DIG->CTRL = temp;
01619 
01620     XCVR_TX_DIG->DFT_PATTERN = tx_pattern;
01621 
01622     if (status == gXcvrSuccess_c)
01623     {
01624         /* Warm-up the Radio */
01625         XCVR_ForceTxWu();
01626     }
01627 
01628     return status;
01629 }
01630 
01631 xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length)
01632 {
01633     uint32_t temp;
01634     uint8_t dft_mode = 0;
01635     uint8_t dft_clk_sel = 0;
01636     xcvrStatus_t status = gXcvrSuccess_c;
01637     uint8_t bitrate_setting = 0xFF;
01638 
01639     if (lfsr_length > 5)
01640     {
01641         return gXcvrInvalidParameters_c;
01642     }
01643     
01644     XCVR_ChangeMode(radio_mode, data_rate);
01645     
01646     /* Select the RF Channel, using the Channel Number register */
01647     XCVR_OverrideChannel(channel_num, 1);
01648 
01649     switch (radio_mode)
01650     {
01651         case ZIGBEE_MODE:
01652             dft_mode = 7; /* OQPSK configuration */
01653             break;
01654         case ANT_MODE:
01655         case BLE_MODE:
01656         case GFSK_BT_0p5_h_0p5:
01657         case GFSK_BT_0p5_h_0p32:
01658         case GFSK_BT_0p5_h_0p7:
01659         case GFSK_BT_0p5_h_1p0:
01660         case GFSK_BT_0p3_h_0p5:
01661         case GFSK_BT_0p7_h_0p5:
01662             dft_mode = 3; /* GFSK configuration */
01663             bitrate_setting = data_rate;
01664             break;
01665         case MSK:
01666             dft_mode = 5; /* MSK configuration */
01667             break;
01668 
01669         default:
01670             status = gXcvrInvalidParameters_c;
01671             break;
01672     }
01673 
01674     if (status == gXcvrSuccess_c)
01675     {
01676         switch (data_rate)
01677         {
01678             case DR_1MBPS:
01679                 dft_clk_sel = 4;
01680                 break;
01681             case DR_500KBPS:
01682                 dft_clk_sel = 3;
01683                 break;
01684             case DR_250KBPS:
01685                 dft_clk_sel = 2;
01686                 break;
01687             default:
01688                 status = gXcvrInvalidParameters_c;
01689                 break;
01690         }
01691     }
01692 
01693     if (bitrate_setting < 4)
01694     {
01695         GENFSK->BITRATE = bitrate_setting;
01696     }
01697 
01698     temp = XCVR_TX_DIG->CTRL;
01699     temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK |
01700               XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK |
01701               XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK |
01702               XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK |
01703               XCVR_TX_DIG_CTRL_LFSR_EN_MASK);
01704     temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) |
01705             XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) |
01706             XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) |
01707             XCVR_TX_DIG_CTRL_TX_DFT_EN(0) |
01708             XCVR_TX_DIG_CTRL_LFSR_EN(1);
01709     XCVR_TX_DIG->CTRL = temp;
01710 
01711     if (status == gXcvrSuccess_c)
01712     {
01713         /* Warm-up the Radio */
01714         XCVR_ForceTxWu();
01715     }
01716 
01717     return status;
01718 }
01719 
01720 void XCVR_DftTxOff(void)
01721 {
01722     XCVR_ForceTxWd();
01723     XCVR_MISC->XCVR_CTRL |= XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in LL registers */
01724     /* Clear the RF Channel over-ride */
01725     XCVR_OverrideChannel(0xFF,1);
01726     XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | /* Clear DFT_MODE */
01727                            XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | /* Clear DFT_CLK_SEL */
01728                            XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | /* Clear DFT_EN */
01729                            XCVR_TX_DIG_CTRL_LFSR_EN_MASK);/* Clear LFSR_EN */
01730 }
01731 
01732 xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power)
01733 {
01734     if (pa_power > 0x3F)
01735     {
01736         return gXcvrInvalidParameters_c; /* Failure */
01737     }
01738     
01739     if (pa_power != 1)
01740     {
01741         pa_power = pa_power & 0xFEU; /* Ensure LSbit is cleared */
01742     }
01743     
01744     XCVR_MISC->XCVR_CTRL &= ~XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in TSM registers */
01745     XCVR_TSM->PA_POWER = pa_power;
01746 
01747     return gXcvrSuccess_c; /* Success */
01748 }
01749 
01750 xcvrStatus_t XCVR_CoexistenceInit(void)
01751 {
01752 #if gMWS_UseCoexistence_d  
01753     uint32_t temp = 0x00U;
01754     uint32_t end_of_tx_wu = 0x00U;
01755     uint32_t end_of_rx_wu = 0x00U;
01756     
01757 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
01758 #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
01759     uint32_t tsm_timing47 = 0x00U;
01760 #else /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_B) */
01761     uint32_t tsm_timing48 = 0x00U;
01762 #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
01763     uint32_t tsm_timing50 = 0x00U;    
01764 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
01765     
01766 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
01767     // RF_ACTIVE = ANT_B (PTC1, gpio1_trig_en)
01768     uint32_t tsm_timing48 = 0x00U;
01769     // RF_PRIORITY = ANT_A (PTC4, gpio0_trig_en)
01770     uint32_t tsm_timing47 = 0x00U;    
01771 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
01772     
01773     uint16_t tsm_timing43_rx = 0x00;
01774     uint16_t tsm_timing43_tx = 0x00;    
01775 
01776     /* Select GPIO mode for FAD pins */
01777     temp = XCVR_MISC->FAD_CTRL;
01778     temp &= ~(XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK);
01779     XCVR_MISC->FAD_CTRL = temp;
01780 
01781     /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */
01782     end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >>
01783                     XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT;
01784     end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >>
01785                     XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;
01786     
01787 /*****************
01788  *  TX SEQUENCE  *
01789  *****************/    
01790 
01791     if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d)
01792     {
01793         temp = end_of_tx_wu;
01794     }
01795     else
01796     {
01797         temp = gMWS_CoexRfActiveAssertTime_d;
01798     }
01799     
01800     /* Save the TX RF_ACTIVE start time. */
01801     tsm_timing43_tx = end_of_tx_wu - temp; 
01802 
01803 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)    
01804     /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */
01805 #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
01806     tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & 
01807                                                         XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK);
01808 #else
01809     tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & 
01810                                                         XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK);    
01811 #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
01812 
01813     /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */
01814     tsm_timing50 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & 
01815                                                         XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK);
01816 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
01817 
01818 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
01819     /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */
01820     tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & 
01821                                                         XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK);
01822 
01823     /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */
01824     tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & 
01825                                                         XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK);        
01826 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */  
01827     
01828 /*****************
01829  *  RX SEQUENCE  *
01830  *****************/
01831 
01832     if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d)
01833     {
01834         temp = end_of_rx_wu;
01835     }
01836     else
01837     {
01838         temp = gMWS_CoexRfActiveAssertTime_d;
01839     }
01840 
01841     /* Save the RX RF_ACTIVE start time. */
01842     tsm_timing43_rx = end_of_rx_wu - temp; 
01843 
01844 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)    
01845     /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */
01846 #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
01847     tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & 
01848                                                          XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
01849 #else
01850     tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & 
01851                                                          XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK);
01852 #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
01853 
01854     /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */
01855     tsm_timing50 |= ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & 
01856                                                           XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) |
01857                      (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & 
01858                                                                              XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK));
01859 
01860 #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
01861     temp = XCVR_TSM->TIMING47;
01862     temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
01863     temp |= tsm_timing47;
01864     XCVR_TSM->TIMING47 = temp;
01865 #else
01866     temp = XCVR_TSM->TIMING48;
01867     temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK);
01868     temp |= tsm_timing48;
01869     XCVR_TSM->TIMING48 = temp;    
01870 #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
01871 
01872     temp = XCVR_TSM->TIMING50;
01873     temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK | 
01874               XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK |
01875               XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK);
01876     temp |= tsm_timing50;
01877     XCVR_TSM->TIMING50 = temp;
01878 
01879 #if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A)
01880     GPIOC->PDDR |= 0x18;
01881     PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
01882     PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
01883 #else
01884     GPIOC->PDDR |= 0x0A;
01885     PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
01886     PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
01887 #endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */
01888 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
01889     
01890 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)    
01891     /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */
01892     tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & 
01893                                                          XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK);
01894     
01895     /* Set PRIORITY pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */
01896     tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & 
01897                                                           XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
01898     
01899     /* RF_ACTIVE */
01900     temp = XCVR_TSM->TIMING48;
01901     temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK);
01902     temp |= tsm_timing48;
01903     XCVR_TSM->TIMING48 = temp;
01904     
01905     /* RF_PRIORITY */
01906     temp = XCVR_TSM->TIMING47;
01907     temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);
01908     temp |= tsm_timing47;
01909     XCVR_TSM->TIMING47 = temp;
01910     
01911     /* Overwrite pins settings */
01912     GPIOC->PDDR |= 0x12;
01913     PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);
01914     PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2);    
01915 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
01916 
01917     tsm_timing43_tx += gMWS_CoexConfirmWaitTime_d;
01918 
01919     if (tsm_timing43_tx > end_of_tx_wu - 1)
01920     {
01921         tsm_timing43_tx = end_of_tx_wu - 1;
01922     }
01923 
01924     tsm_timing43_rx += gMWS_CoexConfirmWaitTime_d;
01925     
01926     if (tsm_timing43_rx > end_of_rx_wu - 1)
01927     {
01928         tsm_timing43_rx = end_of_rx_wu - 1;
01929     }
01930 
01931     XCVR_TSM->TIMING43 = ((((uint32_t)(tsm_timing43_tx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK) |
01932                           (((uint32_t)(tsm_timing43_tx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK) | 
01933                           (((uint32_t)(tsm_timing43_rx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK) |
01934                           (((uint32_t)(tsm_timing43_rx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK));
01935 
01936     BTLE_RF->MISC_CTRL = 0x02;
01937 
01938     XCVR_TSM->CTRL |= XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK;
01939 
01940     /* Save the updated registers values. */
01941     XCVR_CoexistenceSaveRestoreTimings(1);    
01942 #endif /* gMWS_UseCoexistence_d */ 
01943 
01944     return gXcvrSuccess_c;
01945 }
01946 
01947 xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority)
01948 {
01949 #if gMWS_UseCoexistence_d
01950     uint32_t temp = 0x00U;
01951     uint32_t end_of_tx_wu = 0x00U;
01952     uint32_t end_of_rx_wu = 0x00U;
01953 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
01954     uint32_t tsm_timing50 = 0x00U;
01955 #endif    
01956 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
01957     uint32_t tsm_timing47 = 0x00U;
01958 #endif    
01959 
01960     /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */
01961     end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >>
01962                     XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT;
01963     end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >>
01964                     XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT;    
01965 
01966 /*****************
01967  *      RX       *
01968  *****************/
01969     
01970     if (XCVR_COEX_HIGH_PRIO == rxPriority)
01971     {
01972         if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d)
01973         {
01974             temp = end_of_rx_wu;
01975         }
01976         else
01977         {
01978             temp = gMWS_CoexRfActiveAssertTime_d;
01979         }
01980 
01981 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
01982         /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start for high priority RX. */
01983         tsm_timing50 = ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & 
01984                                                              XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) |
01985                         (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & 
01986                                                                                   XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK));
01987 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
01988 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
01989      /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence */
01990         tsm_timing47 = (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & 
01991                                                             XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK);   
01992 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
01993     }
01994     else
01995     {
01996         /* Low priority RX */
01997 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
01998         tsm_timing50 = (((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & 
01999                                    XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) |
02000                         ((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & 
02001                                    XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK));
02002 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
02003 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)        
02004         tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & 
02005                                    XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK) |
02006                         ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT) & 
02007                                    XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK));
02008 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
02009     }
02010 
02011 /*****************
02012  *      TX       *
02013  *****************/
02014     if (XCVR_COEX_HIGH_PRIO == txPriority)
02015     {
02016         if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d)
02017         {
02018             temp = end_of_tx_wu;
02019         }
02020         else
02021         {
02022             temp = gMWS_CoexRfActiveAssertTime_d;
02023         }
02024 
02025         /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence for HIGH priority TX. */
02026 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
02027         tsm_timing50 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & 
02028                                                              XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK);
02029 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
02030 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)        
02031         tsm_timing47 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & 
02032                                                              XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK);
02033 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */                
02034     }
02035     else
02036     {        
02037 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
02038         /* Set STATUS pin HIGH at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */
02039         tsm_timing50 |= (((uint32_t)(end_of_tx_wu) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & 
02040                                                       XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK);
02041 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
02042 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
02043         /* Set STATUS pin LOW at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */                
02044         tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & 
02045                                    XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK) |
02046                         ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT) & 
02047                                    XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK));
02048 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
02049     }
02050 
02051 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)
02052     temp = XCVR_TSM->TIMING50;
02053     temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK |
02054               XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK |
02055               XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK);
02056     temp |= tsm_timing50;
02057     XCVR_TSM->TIMING50 = temp;
02058 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */
02059 #if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d)
02060     temp = XCVR_TSM->TIMING47;
02061     temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK |
02062               XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK |
02063               XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK |
02064               XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK);
02065     temp |= tsm_timing47;
02066     XCVR_TSM->TIMING47 = temp;    
02067 #endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */
02068     
02069     /* Save the updated registers values. */
02070     XCVR_CoexistenceSaveRestoreTimings(1);
02071 #endif /* gMWS_UseCoexistence_d */
02072 
02073     return gXcvrSuccess_c;
02074 }
02075 
02076 xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings)
02077 {
02078 #if gMWS_UseCoexistence_d
02079     static uint32_t tsm_ovrd0_saved = 0x00;
02080     static uint32_t tsm_ovrd1_saved = 0x00;
02081     static uint32_t tsm_ovrd2_saved = 0x00;
02082     static uint32_t tsm_ovrd3_saved = 0x00;
02083     static uint32_t tsm_timing47_saved = 0x00;
02084     static uint32_t tsm_timing48_saved = 0x00;
02085 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)    
02086     static uint32_t tsm_timing49_saved = 0x00;
02087     static uint32_t tsm_timing50_saved = 0x00;
02088 #endif    
02089 
02090     if (saveTimings == 0)
02091     {
02092         /* Restore registers values. */
02093         XCVR_TSM->OVRD0 = tsm_ovrd0_saved; 
02094         XCVR_TSM->OVRD1 = tsm_ovrd1_saved;
02095         XCVR_TSM->OVRD2 = tsm_ovrd2_saved;
02096         XCVR_TSM->OVRD3 = tsm_ovrd3_saved;
02097 
02098         XCVR_TSM->TIMING47 = tsm_timing47_saved;
02099         XCVR_TSM->TIMING48 = tsm_timing48_saved;
02100 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)        
02101         XCVR_TSM->TIMING49 = tsm_timing49_saved;
02102         XCVR_TSM->TIMING50 = tsm_timing50_saved;
02103 #endif        
02104     }
02105     else
02106     {
02107         /* Save registers values. */
02108         tsm_ovrd0_saved = XCVR_TSM->OVRD0;
02109         tsm_ovrd1_saved = XCVR_TSM->OVRD1;
02110         tsm_ovrd2_saved = XCVR_TSM->OVRD2;
02111         tsm_ovrd3_saved = XCVR_TSM->OVRD3;
02112         tsm_timing47_saved = XCVR_TSM->TIMING47;
02113         tsm_timing48_saved = XCVR_TSM->TIMING48;
02114 #if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d)        
02115         tsm_timing49_saved = XCVR_TSM->TIMING49;
02116         tsm_timing50_saved = XCVR_TSM->TIMING50;
02117 #endif        
02118     }
02119 #endif /* gMWS_UseCoexistence_d */
02120 
02121     return gXcvrSuccess_c;
02122 }
02123