Lukasz Uszko
SX1278 RA-01, RA-02 LoRa library
- This code is deprecated. Use this: https://github.com/luk6xff/DevLibs/tree/master/LORA instead.
Revision 0:4e8ef5758455, committed 2019-11-16
- Comitter:
- igbt6
- Date:
- Sat Nov 16 16:34:57 2019 +0000
- Commit message:
- SX1278 - RA-01 Lora library
Changed in this revision
diff -r 000000000000 -r 4e8ef5758455 LICENSE.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/LICENSE.txt Sat Nov 16 16:34:57 2019 +0000 @@ -0,0 +1,27 @@ +--- Revised BSD License --- +Copyright (c) 2017, SEMTECH S.A. +All rights reserved. +Copyright (c) 2019, LUK6XFF [luszko@op.pl] +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the Semtech corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL SEMTECH S.A. BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff -r 000000000000 -r 4e8ef5758455 README.md
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/README.md Sat Nov 16 16:34:57 2019 +0000
@@ -0,0 +1,298 @@
+# SX1278 LORA module library
+
+
+## Description
+The library was tested with [MBED](https://www.mbed.com) platform on RA-01 and RA-02 boards from AI-Thinker. It should work for all LORA SX127x chips from SEMTECH.
+
+## Usage
+Simple snippet how to quickly use the library for LORA communication on mbed platform:
+* CLIENT
+```cpp
+
+#include "SX1278/platform/sx1278-mbed.h"
+
+// PINOUT FOR MBED_NUCLEO_L053R8 BOARD
+#define SX1278_MOSI PB_15
+#define SX1278_MISO PB_14
+#define SX1278_SCLK PB_13
+#define SX1278_NSS PB_12
+#define SX1278_RST PB_1
+#define SX1278_DIO0 PA_9
+#define SX1278_DIO1 PA_8
+#define SX1278_DIO2 PB_10
+#define SX1278_DIO3 PB_4
+#define SX1278_DIO4 PB_5
+#define SX1278_DIO5 PB_3
+
+// Defines
+#define DEBUG_ON 1
+
+// Radio LORA settings
+#define RF_FREQUENCY RF_FREQUENCY_434_0
+#define TX_OUTPUT_POWER 14 // dBm
+#define LORA_BANDWIDTH LORA_BANDWIDTH_125kHz
+#define LORA_SPREADING_FACTOR LORA_SF8
+#define LORA_CODINGRATE LORA_ERROR_CODING_RATE_4_5
+#define LORA_PREAMBLE_LENGTH 8 // Same for Tx and Rx
+#define LORA_SYMBOL_TIMEOUT 5 // Symbols
+#define LORA_FIX_LENGTH_PAYLOAD_ON false
+#define LORA_FHSS_ENABLED false
+#define LORA_NB_SYMB_HOP 4
+#define LORA_IQ_INVERSION_ON false
+#define LORA_CRC_ENABLED true
+#define RX_TIMEOUT_VALUE 8000 // in ms
+
+
+// Radio events function pointer
+static RadioEvents_t RadioEvents;
+
+// Function to be executed on Radio Tx Done event
+void OnTxDone(void);
+
+// Function to be executed on Radio Rx Done event
+void OnRxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr);
+
+// Function executed on Radio Tx Timeout event
+void OnTxTimeout(void);
+
+// Function executed on Radio Rx Timeout event
+void OnRxTimeout(void);
+
+// Function executed on Radio Rx Error event
+void OnRxError(void);
+
+const char GatewayMsg[] = "Hello FROM LORA GATEWAY!";
+const char ClientMsg[] = "Hello FROM LORA CLIENT!";
+
+//-----------------------------------------------------------------------------
+
+// Main
+int main()
+{
+ // Radio initialization
+ RadioEvents.TxDone = OnTxDone;
+ RadioEvents.RxDone = OnRxDone;
+ RadioEvents.TxTimeout = OnTxTimeout;
+ RadioEvents.RxTimeout = OnRxTimeout;
+ RadioEvents.RxError = OnRxError;
+ SX1278MbedInit(&RadioEvents,SX1278_MOSI, SX1278_MISO, SX1278_SCLK, SX1278_NSS, SX1278_RST, \
+ SX1278_DIO0, SX1278_DIO1, SX1278_DIO2, SX1278_DIO3, NC, NC);
+ SX1278SetChannel(RF_FREQUENCY);
+
+ // Verify if SX1278 connected to the the board
+ while(SX1278Read(REG_VERSION) == 0x00)
+ {
+ debug("Radio could not be detected!\n\r");
+ wait(1);
+ }
+
+ SX1278SetMaxPayloadLength(MODEM_LORA, MAX_PAYLOAD_LENGTH);
+ SX1278SetTxConfig(MODEM_LORA, TX_OUTPUT_POWER, 0, LORA_BANDWIDTH,
+ LORA_SPREADING_FACTOR, LORA_CODINGRATE,
+ LORA_PREAMBLE_LENGTH, LORA_FIX_LENGTH_PAYLOAD_ON,
+ LORA_CRC_ENABLED, LORA_FHSS_ENABLED, LORA_NB_SYMB_HOP,
+ LORA_IQ_INVERSION_ON, 4000);
+
+ SX1278SetRxConfig(MODEM_LORA, LORA_BANDWIDTH, LORA_SPREADING_FACTOR,
+ LORA_CODINGRATE, 0, LORA_PREAMBLE_LENGTH,
+ LORA_SYMBOL_TIMEOUT, LORA_FIX_LENGTH_PAYLOAD_ON, 0,
+ LORA_CRC_ENABLED, LORA_FHSS_ENABLED, LORA_NB_SYMB_HOP,
+ LORA_IQ_INVERSION_ON, true);
+
+ while(true)
+ {
+ SX1278Send((uint8_t*)ClientMsg, sizeof(ClientMsg));
+ SX1278SetRx(RX_TIMEOUT_VALUE);
+ SX1278DelayMs(RX_TIMEOUT_VALUE);
+ debug_if(DEBUG_ON, "> Data sent to the client\n\r");
+ }
+}
+
+//-----------------------------------------------------------------------------
+void OnTxDone(void)
+{
+ SX1278SetSleep();
+ debug_if(DEBUG_ON, "> OnTxDone\n\r");
+}
+
+//-----------------------------------------------------------------------------
+void OnRxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr)
+{
+ SX1278SetSleep();
+ debug_if(DEBUG_ON, "> RssiValue: %d\n\r", rssi);
+ debug_if(DEBUG_ON, "> SnrValue: %d\n\r", snr);
+ debug_if(DEBUG_ON, "> PAYLOAD: %s\n\r", payload);
+ debug_if(DEBUG_ON, "> OnRxDone\n\r");
+}
+
+//-----------------------------------------------------------------------------
+void OnTxTimeout(void)
+{
+ SX1278SetSleep();
+ debug_if(DEBUG_ON, "> OnTxTimeout\n\r");
+}
+
+//-----------------------------------------------------------------------------
+void OnRxTimeout(void)
+{
+ SX1278SetSleep();
+ debug_if(DEBUG_ON, "> OnRxTimeout\n\r");
+}
+
+//-----------------------------------------------------------------------------
+void OnRxError(void)
+{
+ SX1278SetSleep();
+ debug_if(DEBUG_ON, "> OnRxError\n\r");
+}
+
+//-----------------------------------------------------------------------------
+
+```
+
+* GATEWAY
+```cpp
+
+#include "SX1278/platform/sx1278-mbed.h"
+
+// PINOUT FOR MBED_NUCLEO_L053R8 BOARD
+#define SX1278_MOSI PB_15
+#define SX1278_MISO PB_14
+#define SX1278_SCLK PB_13
+#define SX1278_NSS PB_12
+#define SX1278_RST PB_1
+#define SX1278_DIO0 PA_9
+#define SX1278_DIO1 PA_8
+#define SX1278_DIO2 PB_10
+#define SX1278_DIO3 PB_4
+#define SX1278_DIO4 PB_5
+#define SX1278_DIO5 PB_3
+
+// Defines
+#define DEBUG_ON 1
+
+// Radio LORA settings
+#define RF_FREQUENCY RF_FREQUENCY_434_0
+#define TX_OUTPUT_POWER 14 // dBm
+#define LORA_BANDWIDTH LORA_BANDWIDTH_125kHz
+#define LORA_SPREADING_FACTOR LORA_SF8
+#define LORA_CODINGRATE LORA_ERROR_CODING_RATE_4_5
+#define LORA_PREAMBLE_LENGTH 8 // Same for Tx and Rx
+#define LORA_SYMBOL_TIMEOUT 5 // Symbols
+#define LORA_FIX_LENGTH_PAYLOAD_ON false
+#define LORA_FHSS_ENABLED false
+#define LORA_NB_SYMB_HOP 4
+#define LORA_IQ_INVERSION_ON false
+#define LORA_CRC_ENABLED true
+#define RX_TIMEOUT_VALUE 8000 // in ms
+
+
+// Radio events function pointer
+static RadioEvents_t RadioEvents;
+
+// Function to be executed on Radio Tx Done event
+void OnTxDone(void);
+
+// Function to be executed on Radio Rx Done event
+void OnRxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr);
+
+// Function executed on Radio Tx Timeout event
+void OnTxTimeout(void);
+
+// Function executed on Radio Rx Timeout event
+void OnRxTimeout(void);
+
+// Function executed on Radio Rx Error event
+void OnRxError(void);
+
+const char GatewayMsg[] = "Hello FROM LORA GATEWAY!";
+const char ClientMsg[] = "Hello FROM LORA CLIENT!";
+
+//-----------------------------------------------------------------------------
+
+// Main
+int main()
+{
+ // Radio initialization
+ RadioEvents.TxDone = OnTxDone;
+ RadioEvents.RxDone = OnRxDone;
+ RadioEvents.TxTimeout = OnTxTimeout;
+ RadioEvents.RxTimeout = OnRxTimeout;
+ RadioEvents.RxError = OnRxError;
+ SX1278MbedInit(&RadioEvents,SX1278_MOSI, SX1278_MISO, SX1278_SCLK, SX1278_NSS, SX1278_RST, \
+ SX1278_DIO0, SX1278_DIO1, SX1278_DIO2, SX1278_DIO3, NC, NC);
+ SX1278SetChannel(RF_FREQUENCY);
+
+ // Verify if SX1278 connected to the the board
+ while(SX1278Read(REG_VERSION) == 0x00)
+ {
+ debug("Radio could not be detected!\n\r");
+ wait(1);
+ }
+
+ SX1278SetMaxPayloadLength(MODEM_LORA, MAX_PAYLOAD_LENGTH);
+ SX1278SetTxConfig(MODEM_LORA, TX_OUTPUT_POWER, 0, LORA_BANDWIDTH,
+ LORA_SPREADING_FACTOR, LORA_CODINGRATE,
+ LORA_PREAMBLE_LENGTH, LORA_FIX_LENGTH_PAYLOAD_ON,
+ LORA_CRC_ENABLED, LORA_FHSS_ENABLED, LORA_NB_SYMB_HOP,
+ LORA_IQ_INVERSION_ON, 4000);
+
+ SX1278SetRxConfig(MODEM_LORA, LORA_BANDWIDTH, LORA_SPREADING_FACTOR,
+ LORA_CODINGRATE, 0, LORA_PREAMBLE_LENGTH,
+ LORA_SYMBOL_TIMEOUT, LORA_FIX_LENGTH_PAYLOAD_ON, 0,
+ LORA_CRC_ENABLED, LORA_FHSS_ENABLED, LORA_NB_SYMB_HOP,
+ LORA_IQ_INVERSION_ON, true);
+
+ while(true)
+ {
+ SX1278SetRx(RX_TIMEOUT_VALUE);
+ }
+}
+
+//-----------------------------------------------------------------------------
+void OnTxDone(void)
+{
+ SX1278SetSleep();
+ debug_if(DEBUG_ON, "> OnTxDone\n\r");
+}
+
+//-----------------------------------------------------------------------------
+void OnRxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr)
+{
+ SX1278Send((uint8_t*)GatewayMsg, sizeof(GatewayMsg));
+ SX1278SetSleep();
+ debug_if(DEBUG_ON, "> RssiValue: %d\n\r", rssi);
+ debug_if(DEBUG_ON, "> SnrValue: %d\n\r", snr);
+ debug_if(DEBUG_ON, "> PAYLOAD: %s\n\r", payload);
+ debug_if(DEBUG_ON, "> OnRxDone\n\r");
+}
+
+//-----------------------------------------------------------------------------
+void OnTxTimeout(void)
+{
+ SX1278SetSleep();
+ debug_if(DEBUG_ON, "> OnTxTimeout\n\r");
+}
+
+//-----------------------------------------------------------------------------
+void OnRxTimeout(void)
+{
+ SX1278SetSleep();
+ debug_if(DEBUG_ON, "> OnRxTimeout\n\r");
+}
+
+//-----------------------------------------------------------------------------
+void OnRxError(void)
+{
+ SX1278SetSleep();
+ debug_if(DEBUG_ON, "> OnRxError\n\r");
+}
+```
+
+
+## Porting to other platform
+If you want to port this library on other platform, the only thing you have to do is define HW/Platform dependent functions as it is done in `platform/sx1278-mbed.cpp` file.
+
+
+## Author
+* Lukasz Uszko aka `luk6xff` [luszko@op.pl]
diff -r 000000000000 -r 4e8ef5758455 platform/sx1278-mbed.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/sx1278-mbed.cpp Sat Nov 16 16:34:57 2019 +0000
@@ -0,0 +1,197 @@
+/**
+ * @brief: Implementation of a SX1278 platform dependent [MBED] radio functions
+ * @author: luk6xff
+ * @email: luszko@op.pl
+ * @date: 2019-11-15
+ */
+
+#include "sx1278-mbed.h"
+
+
+/**
+ * SPI Interface
+ */
+SPI* spi; // mosimiso, sclk
+DigitalOut* nss;
+
+/**
+ * SX1278 Reset pin
+ */
+DigitalInOut* reset;
+
+/**
+ * SX1278 DIO pins
+ */
+InterruptIn* dio0;
+InterruptIn* dio1;
+InterruptIn* dio2;
+InterruptIn* dio3;
+InterruptIn* dio4;
+DigitalIn* dio5;
+
+/**
+ * Tx and Rx timers
+ */
+Timeout txTimeoutTimer;
+Timeout rxTimeoutTimer;
+Timeout rxTimeoutSyncWord;
+
+
+//-----------------------------------------------------------------------------
+void SX1278MbedInit(RadioEvents_t *events,
+ PinName _mosi, PinName _miso, PinName _sclk, PinName _nss,
+ PinName _reset,
+ PinName _dio0, PinName _dio1, PinName _dio2, PinName _dio3, PinName _dio4, PinName _dio5)
+
+{
+ spi = new SPI(_mosi, _miso, _sclk);
+ nss = new DigitalOut(_nss);
+ reset = new DigitalInOut(_reset);
+ dio0 = new InterruptIn(_dio0);
+ dio1 = new InterruptIn(_dio1);
+ dio2 = new InterruptIn(_dio2);
+ dio3 = new InterruptIn(_dio3);
+ dio4 = new InterruptIn(_dio4);
+ dio5 = new DigitalIn(_dio5);
+
+ SX1278Init(events);
+}
+
+//-----------------------------------------------------------------------------
+void SX1278MbedDeInit()
+{
+ // IO
+ SX1278IoDeInit();
+ // Timers
+ txTimeoutTimer.detach();
+ rxTimeoutTimer.detach();
+ rxTimeoutSyncWord.detach();
+}
+
+//-----------------------------------------------------------------------------
+void SX1278IoInit(void)
+{
+ // Init SPI
+ *nss = 1;
+ spi->format(8,0);
+ uint32_t frequencyToSet = 8000000;
+ spi->frequency(frequencyToSet);
+ SX1278DelayMs(100);
+}
+
+//-----------------------------------------------------------------------------
+void SX1278IoDeInit(void)
+{
+ delete(spi);
+ delete(nss);
+ delete(reset);
+ delete(dio0);
+ delete(dio1);
+ delete(dio2);
+ delete(dio3);
+ delete(dio4);
+ delete(dio5);
+}
+
+
+//-----------------------------------------------------------------------------
+void SX1278IoIrqInit(DioIrqHandler *irqHandlers)
+{
+ dio0->rise(mbed::callback(irqHandlers[0]));
+ dio1->rise(mbed::callback(irqHandlers[1]));
+ dio2->rise(mbed::callback(irqHandlers[2]));
+ dio3->rise(mbed::callback(irqHandlers[3]));
+ dio4->rise(mbed::callback(irqHandlers[4]));
+}
+
+//-----------------------------------------------------------------------------
+void SX1278Reset(void)
+{
+ reset->output();
+ *reset = 0;
+ SX1278DelayMs(1);
+ reset->input();
+ SX1278DelayMs(6);
+}
+
+//-----------------------------------------------------------------------------
+void SX1278WriteBuffer(uint8_t addr, uint8_t *buffer, uint8_t size)
+{
+ uint8_t i;
+
+ *nss = 0;
+ spi->write(addr | 0x80);
+ for(i = 0; i < size; i++)
+ {
+ spi->write(buffer[i]);
+ }
+ *nss = 1;
+}
+
+//-----------------------------------------------------------------------------
+void SX1278ReadBuffer(uint8_t addr, uint8_t *buffer, uint8_t size)
+{
+ uint8_t i;
+
+ *nss = 0;
+ spi->write(addr & 0x7F);
+ for(i = 0; i < size; i++)
+ {
+ buffer[i] = spi->write(0);
+ }
+ *nss = 1;
+}
+
+
+
+//-----------------------------------------------------------------------------
+void SX1278SetTimeout(TimeoutTimer_t timer, timeoutFuncPtr func, int timeout_ms)
+{
+ switch(timer)
+ {
+ case RXTimeoutTimer:
+ {
+ if (func)
+ {
+ rxTimeoutTimer.attach_us(mbed::callback(func), timeout_ms*1000);
+ }
+ else
+ {
+ rxTimeoutTimer.detach();
+ }
+ break;
+ }
+ case TXTimeoutTimer:
+ {
+ if (func)
+ {
+ txTimeoutTimer.attach_us(mbed::callback(func), timeout_ms*1000);
+ }
+ else
+ {
+ txTimeoutTimer.detach();
+ }
+ break;
+ }
+ case RXTimeoutSyncWordTimer:
+ {
+ if (func)
+ {
+ rxTimeoutSyncWord.attach_us(mbed::callback(func), timeout_ms*1000);
+ }
+ else
+ {
+ rxTimeoutSyncWord.detach();
+ }
+ break;
+ }
+ }
+}
+
+//-----------------------------------------------------------------------------
+void SX1278DelayMs(int ms)
+{
+ wait_us(ms*1000);
+}
+
+//-----------------------------------------------------------------------------
diff -r 000000000000 -r 4e8ef5758455 platform/sx1278-mbed.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/platform/sx1278-mbed.h Sat Nov 16 16:34:57 2019 +0000 @@ -0,0 +1,23 @@ + +/** + * @brief: Implementation of a SX1278 platform dependent [MBED] radio functions + * @author: luk6xff + * @email: luszko@op.pl + * @date: 2019-11-15 + */ + + +#ifndef __SX1278_MBED_H__ +#define __SX1278_MBED_H__ + +#include "mbed.h" +#include "../sx1278.h" + +void SX1278MbedInit(RadioEvents_t *events, + PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset, + PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5); + +void SX1278MbedDeInit(); + +#endif // __SX1278_MBED_H__ +
diff -r 000000000000 -r 4e8ef5758455 registers.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/registers.h Sat Nov 16 16:34:57 2019 +0000 @@ -0,0 +1,1686 @@ +/** + * @brief: SX1278 LoRa and FSK modem registers and bits definitions + * @author: SEMTECH, modified by luk6xff + * @email: luszko@op.pl + * @date: 2019-11-15 + */ + +#ifndef __REGISTERS_H__ +#define __REGISTERS_H__ + +/*! + * ============================================================================ + * SX1278 LoRa Internal registers Address + * ============================================================================ + */ +#define REG_LR_FIFO 0x00 +// Common settings +#define REG_LR_OPMODE 0x01 +#define REG_LR_FRFMSB 0x06 +#define REG_LR_FRFMID 0x07 +#define REG_LR_FRFLSB 0x08 +// Tx settings +#define REG_LR_PACONFIG 0x09 +#define REG_LR_PARAMP 0x0A +#define REG_LR_OCP 0x0B +// Rx settings +#define REG_LR_LNA 0x0C +// LoRa registers +#define REG_LR_FIFOADDRPTR 0x0D +#define REG_LR_FIFOTXBASEADDR 0x0E +#define REG_LR_FIFORXBASEADDR 0x0F +#define REG_LR_FIFORXCURRENTADDR 0x10 +#define REG_LR_IRQFLAGSMASK 0x11 +#define REG_LR_IRQFLAGS 0x12 +#define REG_LR_RXNBBYTES 0x13 +#define REG_LR_RXHEADERCNTVALUEMSB 0x14 +#define REG_LR_RXHEADERCNTVALUELSB 0x15 +#define REG_LR_RXPACKETCNTVALUEMSB 0x16 +#define REG_LR_RXPACKETCNTVALUELSB 0x17 +#define REG_LR_MODEMSTAT 0x18 +#define REG_LR_PKTSNRVALUE 0x19 +#define REG_LR_PKTRSSIVALUE 0x1A +#define REG_LR_RSSIVALUE 0x1B +#define REG_LR_HOPCHANNEL 0x1C +#define REG_LR_MODEMCONFIG1 0x1D +#define REG_LR_MODEMCONFIG2 0x1E +#define REG_LR_SYMBTIMEOUTLSB 0x1F +#define REG_LR_PREAMBLEMSB 0x20 +#define REG_LR_PREAMBLELSB 0x21 +#define REG_LR_PAYLOADLENGTH 0x22 +#define REG_LR_PAYLOADMAXLENGTH 0x23 +#define REG_LR_HOPPERIOD 0x24 +#define REG_LR_FIFORXBYTEADDR 0x25 +#define REG_LR_MODEMCONFIG3 0x26 +#define REG_LR_FEIMSB 0x28 +#define REG_LR_FEIMID 0x29 +#define REG_LR_FEILSB 0x2A +#define REG_LR_RSSIWIDEBAND 0x2C +#define REG_LR_IFFREQ1 0x2F +#define REG_LR_IFFREQ2 0x30 +#define REG_LR_DETECTOPTIMIZE 0x31 +#define REG_LR_INVERTIQ 0x33 +#define REG_LR_HIGHBWOPTIMIZE1 0x36 +#define REG_LR_DETECTIONTHRESHOLD 0x37 +#define REG_LR_SYNCWORD 0x39 +#define REG_LR_HIGHBWOPTIMIZE2 0x3A +#define REG_LR_INVERTIQ2 0x3B + +// end of documented register in datasheet +// I/O settings +#define REG_LR_DIOMAPPING1 0x40 +#define REG_LR_DIOMAPPING2 0x41 +// Version +#define REG_LR_VERSION 0x42 +// Additional settings +#define REG_LR_PLLHOP 0x44 +#define REG_LR_TCXO 0x4B +#define REG_LR_PADAC 0x4D +#define REG_LR_FORMERTEMP 0x5B +#define REG_LR_BITRATEFRAC 0x5D +#define REG_LR_AGCREF 0x61 +#define REG_LR_AGCTHRESH1 0x62 +#define REG_LR_AGCTHRESH2 0x63 +#define REG_LR_AGCTHRESH3 0x64 +#define REG_LR_PLL 0x70 + +/*! + * ============================================================================ + * SX1276 LoRa bits control definition + * ============================================================================ + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default +#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF +#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 +#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default + +#define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7 +#define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default +#define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00 + +#define RFLR_OPMODE_MASK 0xF8 +#define RFLR_OPMODE_SLEEP 0x00 +#define RFLR_OPMODE_STANDBY 0x01 // Default +#define RFLR_OPMODE_SYNTHESIZER_TX 0x02 +#define RFLR_OPMODE_TRANSMITTER 0x03 +#define RFLR_OPMODE_SYNTHESIZER_RX 0x04 +#define RFLR_OPMODE_RECEIVER 0x05 +// LoRa specific modes +#define RFLR_OPMODE_RECEIVER_SINGLE 0x06 +#define RFLR_OPMODE_CAD 0x07 + +/*! + * RegFrf (MHz) + */ +#define RFLR_FRFMSB_434_MHZ 0x6C // Default +#define RFLR_FRFMID_434_MHZ 0x80 // Default +#define RFLR_FRFLSB_434_MHZ 0x00 // Default + +/*! + * RegPaConfig + */ +#define RFLR_PACONFIG_PASELECT_MASK 0x7F +#define RFLR_PACONFIG_PASELECT_PABOOST 0x80 +#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RFLR_PACONFIG_MAX_POWER_MASK 0x8F + +#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF +#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 +#define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default + +#define RFLR_PARAMP_MASK 0xF0 +#define RFLR_PARAMP_3400_US 0x00 +#define RFLR_PARAMP_2000_US 0x01 +#define RFLR_PARAMP_1000_US 0x02 +#define RFLR_PARAMP_0500_US 0x03 +#define RFLR_PARAMP_0250_US 0x04 +#define RFLR_PARAMP_0125_US 0x05 +#define RFLR_PARAMP_0100_US 0x06 +#define RFLR_PARAMP_0062_US 0x07 +#define RFLR_PARAMP_0050_US 0x08 +#define RFLR_PARAMP_0040_US 0x09 // Default +#define RFLR_PARAMP_0031_US 0x0A +#define RFLR_PARAMP_0025_US 0x0B +#define RFLR_PARAMP_0020_US 0x0C +#define RFLR_PARAMP_0015_US 0x0D +#define RFLR_PARAMP_0012_US 0x0E +#define RFLR_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RFLR_OCP_MASK 0xDF +#define RFLR_OCP_ON 0x20 // Default +#define RFLR_OCP_OFF 0x00 + +#define RFLR_OCP_TRIM_MASK 0xE0 +#define RFLR_OCP_TRIM_045_MA 0x00 +#define RFLR_OCP_TRIM_050_MA 0x01 +#define RFLR_OCP_TRIM_055_MA 0x02 +#define RFLR_OCP_TRIM_060_MA 0x03 +#define RFLR_OCP_TRIM_065_MA 0x04 +#define RFLR_OCP_TRIM_070_MA 0x05 +#define RFLR_OCP_TRIM_075_MA 0x06 +#define RFLR_OCP_TRIM_080_MA 0x07 +#define RFLR_OCP_TRIM_085_MA 0x08 +#define RFLR_OCP_TRIM_090_MA 0x09 +#define RFLR_OCP_TRIM_095_MA 0x0A +#define RFLR_OCP_TRIM_100_MA 0x0B // Default +#define RFLR_OCP_TRIM_105_MA 0x0C +#define RFLR_OCP_TRIM_110_MA 0x0D +#define RFLR_OCP_TRIM_115_MA 0x0E +#define RFLR_OCP_TRIM_120_MA 0x0F +#define RFLR_OCP_TRIM_130_MA 0x10 +#define RFLR_OCP_TRIM_140_MA 0x11 +#define RFLR_OCP_TRIM_150_MA 0x12 +#define RFLR_OCP_TRIM_160_MA 0x13 +#define RFLR_OCP_TRIM_170_MA 0x14 +#define RFLR_OCP_TRIM_180_MA 0x15 +#define RFLR_OCP_TRIM_190_MA 0x16 +#define RFLR_OCP_TRIM_200_MA 0x17 +#define RFLR_OCP_TRIM_210_MA 0x18 +#define RFLR_OCP_TRIM_220_MA 0x19 +#define RFLR_OCP_TRIM_230_MA 0x1A +#define RFLR_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RFLR_LNA_GAIN_MASK 0x1F +#define RFLR_LNA_GAIN_G1 0x20 // Default +#define RFLR_LNA_GAIN_G2 0x40 +#define RFLR_LNA_GAIN_G3 0x60 +#define RFLR_LNA_GAIN_G4 0x80 +#define RFLR_LNA_GAIN_G5 0xA0 +#define RFLR_LNA_GAIN_G6 0xC0 + +#define RFLR_LNA_BOOST_LF_MASK 0xE7 +#define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default + +#define RFLR_LNA_BOOST_HF_MASK 0xFC +#define RFLR_LNA_BOOST_HF_OFF 0x00 // Default +#define RFLR_LNA_BOOST_HF_ON 0x03 + +/*! + * RegFifoAddrPtr + */ +#define RFLR_FIFOADDRPTR 0x00 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFOTXBASEADDR 0x80 // Default + +/*! + * RegFifoTxBaseAddr + */ +#define RFLR_FIFORXBASEADDR 0x00 // Default + +/*! + * RegFifoRxCurrentAddr (Read Only) + */ + +/*! + * RegIrqFlagsMask + */ +#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 +#define RFLR_IRQFLAGS_RXDONE_MASK 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 +#define RFLR_IRQFLAGS_TXDONE_MASK 0x08 +#define RFLR_IRQFLAGS_CADDONE_MASK 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 +#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 + +/*! + * RegIrqFlags + */ +#define RFLR_IRQFLAGS_RXTIMEOUT 0x80 +#define RFLR_IRQFLAGS_RXDONE 0x40 +#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 +#define RFLR_IRQFLAGS_VALIDHEADER 0x10 +#define RFLR_IRQFLAGS_TXDONE 0x08 +#define RFLR_IRQFLAGS_CADDONE 0x04 +#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 +#define RFLR_IRQFLAGS_CADDETECTED 0x01 + +/*! + * RegFifoRxNbBytes (Read Only) + */ + +/*! + * RegRxHeaderCntValueMsb (Read Only) + */ + +/*! + * RegRxHeaderCntValueLsb (Read Only) + */ + +/*! + * RegRxPacketCntValueMsb (Read Only) + */ + +/*! + * RegRxPacketCntValueLsb (Read Only) + */ + +/*! + * RegModemStat (Read Only) + */ +#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F +#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 + +/*! + * RegPktSnrValue (Read Only) + */ + +/*! + * RegPktRssiValue (Read Only) + */ + +/*! + * RegRssiValue (Read Only) + */ + +/*! + * RegHopChannel (Read Only) + */ +#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F +#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 +#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default + +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40 +#define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default + +#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F + +/*! + * RegModemConfig1 + */ +#define RFLR_MODEMCONFIG1_BW_MASK 0x0F +#define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 +#define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 +#define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 +#define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 +#define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 +#define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 +#define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 +#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default +#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 +#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 + +#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default +#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 +#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 + +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01 +#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default + +/*! + * RegModemConfig2 + */ +#define RFLR_MODEMCONFIG2_SF_MASK 0x0F +#define RFLR_MODEMCONFIG2_SF_6 0x60 +#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default +#define RFLR_MODEMCONFIG2_SF_8 0x80 +#define RFLR_MODEMCONFIG2_SF_9 0x90 +#define RFLR_MODEMCONFIG2_SF_10 0xA0 +#define RFLR_MODEMCONFIG2_SF_11 0xB0 +#define RFLR_MODEMCONFIG2_SF_12 0xC0 + +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 +#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 + +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 +#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC +#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default + +/*! + * RegSymbTimeoutLsb + */ +#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default + +/*! + * RegPreambleLengthMsb + */ +#define RFLR_PREAMBLELENGTHMSB 0x00 // Default + +/*! + * RegPreambleLengthLsb + */ +#define RFLR_PREAMBLELENGTHLSB 0x08 // Default + +/*! + * RegPayloadLength + */ +#define RFLR_PAYLOADLENGTH 0x0E // Default + +/*! + * RegPayloadMaxLength + */ +#define RFLR_PAYLOADMAXLENGTH 0xFF // Default + +/*! + * RegHopPeriod + */ +#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default + +/*! + * RegFifoRxByteAddr (Read Only) + */ + +/*! + * RegModemConfig3 + */ +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 +#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default + +#define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB +#define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default +#define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 + +/*! + * RegFeiMsb (Read Only) + */ + +/*! + * RegFeiMid (Read Only) + */ + +/*! + * RegFeiLsb (Read Only) + */ + +/*! + * RegRssiWideband (Read Only) + */ + +/*! + * RegDetectOptimize + */ +#define RFLR_DETECTIONOPTIMIZE_MASK 0xF8 +#define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default +#define RFLR_DETECTIONOPTIMIZE_SF6 0x05 + +/*! + * RegInvertIQ + */ +#define RFLR_INVERTIQ_RX_MASK 0xBF +#define RFLR_INVERTIQ_RX_OFF 0x00 +#define RFLR_INVERTIQ_RX_ON 0x40 +#define RFLR_INVERTIQ_TX_MASK 0xFE +#define RFLR_INVERTIQ_TX_OFF 0x01 +#define RFLR_INVERTIQ_TX_ON 0x00 + +/*! + * RegDetectionThreshold + */ +#define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default +#define RFLR_DETECTIONTHRESH_SF6 0x0C + +/*! + * RegInvertIQ2 + */ +#define RFLR_INVERTIQ2_ON 0x19 +#define RFLR_INVERTIQ2_OFF 0x1D + +/*! + * RegDioMapping1 + */ +#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F +#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO0_01 0x40 +#define RFLR_DIOMAPPING1_DIO0_10 0x80 +#define RFLR_DIOMAPPING1_DIO0_11 0xC0 + +#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF +#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO1_01 0x10 +#define RFLR_DIOMAPPING1_DIO1_10 0x20 +#define RFLR_DIOMAPPING1_DIO1_11 0x30 + +#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 +#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO2_01 0x04 +#define RFLR_DIOMAPPING1_DIO2_10 0x08 +#define RFLR_DIOMAPPING1_DIO2_11 0x0C + +#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC +#define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default +#define RFLR_DIOMAPPING1_DIO3_01 0x01 +#define RFLR_DIOMAPPING1_DIO3_10 0x02 +#define RFLR_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RFLR_DIOMAPPING2_DIO4_MASK 0x3F +#define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO4_01 0x40 +#define RFLR_DIOMAPPING2_DIO4_10 0x80 +#define RFLR_DIOMAPPING2_DIO4_11 0xC0 + +#define RFLR_DIOMAPPING2_DIO5_MASK 0xCF +#define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default +#define RFLR_DIOMAPPING2_DIO5_01 0x10 +#define RFLR_DIOMAPPING2_DIO5_10 0x20 +#define RFLR_DIOMAPPING2_DIO5_11 0x30 + +#define RFLR_DIOMAPPING2_MAP_MASK 0xFE +#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegPllHop + */ +#define RFLR_PLLHOP_FASTHOP_MASK 0x7F +#define RFLR_PLLHOP_FASTHOP_ON 0x80 +#define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RFLR_TCXO_TCXOINPUT_MASK 0xEF +#define RFLR_TCXO_TCXOINPUT_ON 0x10 +#define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RFLR_PADAC_20DBM_MASK 0xF8 +#define RFLR_PADAC_20DBM_ON 0x07 +#define RFLR_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegFormerTemp + */ + +/*! + * RegBitrateFrac + */ +#define RF_BITRATEFRAC_MASK 0xF0 + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegPll + */ +#define RF_PLL_BANDWIDTH_MASK 0x3F +#define RF_PLL_BANDWIDTH_75 0x00 +#define RF_PLL_BANDWIDTH_150 0x40 +#define RF_PLL_BANDWIDTH_225 0x80 +#define RF_PLL_BANDWIDTH_300 0xC0 // Default + + + +/*! + * ============================================================================ + * SX1278 FSK Internal registers Address + * ============================================================================ + */ +#define REG_FIFO 0x00 +// Common settings +#define REG_OPMODE 0x01 +#define REG_BITRATEMSB 0x02 +#define REG_BITRATELSB 0x03 +#define REG_FDEVMSB 0x04 +#define REG_FDEVLSB 0x05 +#define REG_FRFMSB 0x06 +#define REG_FRFMID 0x07 +#define REG_FRFLSB 0x08 +// Tx settings +#define REG_PACONFIG 0x09 +#define REG_PARAMP 0x0A +#define REG_OCP 0x0B +// Rx settings +#define REG_LNA 0x0C +#define REG_RXCONFIG 0x0D +#define REG_RSSICONFIG 0x0E +#define REG_RSSICOLLISION 0x0F +#define REG_RSSITHRESH 0x10 +#define REG_RSSIVALUE 0x11 +#define REG_RXBW 0x12 +#define REG_AFCBW 0x13 +#define REG_OOKPEAK 0x14 +#define REG_OOKFIX 0x15 +#define REG_OOKAVG 0x16 +#define REG_RES17 0x17 +#define REG_RES18 0x18 +#define REG_RES19 0x19 +#define REG_AFCFEI 0x1A +#define REG_AFCMSB 0x1B +#define REG_AFCLSB 0x1C +#define REG_FEIMSB 0x1D +#define REG_FEILSB 0x1E +#define REG_PREAMBLEDETECT 0x1F +#define REG_RXTIMEOUT1 0x20 +#define REG_RXTIMEOUT2 0x21 +#define REG_RXTIMEOUT3 0x22 +#define REG_RXDELAY 0x23 +// Oscillator settings +#define REG_OSC 0x24 +// Packet handler settings +#define REG_PREAMBLEMSB 0x25 +#define REG_PREAMBLELSB 0x26 +#define REG_SYNCCONFIG 0x27 +#define REG_SYNCVALUE1 0x28 +#define REG_SYNCVALUE2 0x29 +#define REG_SYNCVALUE3 0x2A +#define REG_SYNCVALUE4 0x2B +#define REG_SYNCVALUE5 0x2C +#define REG_SYNCVALUE6 0x2D +#define REG_SYNCVALUE7 0x2E +#define REG_SYNCVALUE8 0x2F +#define REG_PACKETCONFIG1 0x30 +#define REG_PACKETCONFIG2 0x31 +#define REG_PAYLOADLENGTH 0x32 +#define REG_NODEADRS 0x33 +#define REG_BROADCASTADRS 0x34 +#define REG_FIFOTHRESH 0x35 +// SM settings +#define REG_SEQCONFIG1 0x36 +#define REG_SEQCONFIG2 0x37 +#define REG_TIMERRESOL 0x38 +#define REG_TIMER1COEF 0x39 +#define REG_TIMER2COEF 0x3A +// Service settings +#define REG_IMAGECAL 0x3B +#define REG_TEMP 0x3C +#define REG_LOWBAT 0x3D +// Status +#define REG_IRQFLAGS1 0x3E +#define REG_IRQFLAGS2 0x3F +// I/O settings +#define REG_DIOMAPPING1 0x40 +#define REG_DIOMAPPING2 0x41 +// Version +#define REG_VERSION 0x42 +// Additional settings +#define REG_PLLHOP 0x44 +#define REG_TCXO 0x4B +#define REG_PADAC 0x4D +#define REG_FORMERTEMP 0x5B +#define REG_BITRATEFRAC 0x5D +#define REG_AGCREF 0x61 +#define REG_AGCTHRESH1 0x62 +#define REG_AGCTHRESH2 0x63 +#define REG_AGCTHRESH3 0x64 +#define REG_PLL 0x70 + +/*! + * ============================================================================ + * SX1276 FSK bits control definition + * ============================================================================ + */ + +/*! + * RegFifo + */ + +/*! + * RegOpMode + */ +#define RF_OPMODE_LONGRANGEMODE_MASK 0x7F +#define RF_OPMODE_LONGRANGEMODE_OFF 0x00 +#define RF_OPMODE_LONGRANGEMODE_ON 0x80 + +#define RF_OPMODE_MODULATIONTYPE_MASK 0x9F +#define RF_OPMODE_MODULATIONTYPE_FSK 0x00 // Default +#define RF_OPMODE_MODULATIONTYPE_OOK 0x20 + +#define RF_OPMODE_MODULATIONSHAPING_MASK 0xE7 +#define RF_OPMODE_MODULATIONSHAPING_00 0x00 // Default +#define RF_OPMODE_MODULATIONSHAPING_01 0x08 +#define RF_OPMODE_MODULATIONSHAPING_10 0x10 +#define RF_OPMODE_MODULATIONSHAPING_11 0x18 + +#define RF_OPMODE_MASK 0xF8 +#define RF_OPMODE_SLEEP 0x00 +#define RF_OPMODE_STANDBY 0x01 // Default +#define RF_OPMODE_SYNTHESIZER_TX 0x02 +#define RF_OPMODE_TRANSMITTER 0x03 +#define RF_OPMODE_SYNTHESIZER_RX 0x04 +#define RF_OPMODE_RECEIVER 0x05 + +/*! + * RegBitRate (bits/sec) + */ +#define RF_BITRATEMSB_1200_BPS 0x68 +#define RF_BITRATELSB_1200_BPS 0x2B +#define RF_BITRATEMSB_2400_BPS 0x34 +#define RF_BITRATELSB_2400_BPS 0x15 +#define RF_BITRATEMSB_4800_BPS 0x1A // Default +#define RF_BITRATELSB_4800_BPS 0x0B // Default +#define RF_BITRATEMSB_9600_BPS 0x0D +#define RF_BITRATELSB_9600_BPS 0x05 +#define RF_BITRATEMSB_15000_BPS 0x08 +#define RF_BITRATELSB_15000_BPS 0x55 +#define RF_BITRATEMSB_19200_BPS 0x06 +#define RF_BITRATELSB_19200_BPS 0x83 +#define RF_BITRATEMSB_38400_BPS 0x03 +#define RF_BITRATELSB_38400_BPS 0x41 +#define RF_BITRATEMSB_76800_BPS 0x01 +#define RF_BITRATELSB_76800_BPS 0xA1 +#define RF_BITRATEMSB_153600_BPS 0x00 +#define RF_BITRATELSB_153600_BPS 0xD0 +#define RF_BITRATEMSB_57600_BPS 0x02 +#define RF_BITRATELSB_57600_BPS 0x2C +#define RF_BITRATEMSB_115200_BPS 0x01 +#define RF_BITRATELSB_115200_BPS 0x16 +#define RF_BITRATEMSB_12500_BPS 0x0A +#define RF_BITRATELSB_12500_BPS 0x00 +#define RF_BITRATEMSB_25000_BPS 0x05 +#define RF_BITRATELSB_25000_BPS 0x00 +#define RF_BITRATEMSB_50000_BPS 0x02 +#define RF_BITRATELSB_50000_BPS 0x80 +#define RF_BITRATEMSB_100000_BPS 0x01 +#define RF_BITRATELSB_100000_BPS 0x40 +#define RF_BITRATEMSB_150000_BPS 0x00 +#define RF_BITRATELSB_150000_BPS 0xD5 +#define RF_BITRATEMSB_200000_BPS 0x00 +#define RF_BITRATELSB_200000_BPS 0xA0 +#define RF_BITRATEMSB_250000_BPS 0x00 +#define RF_BITRATELSB_250000_BPS 0x80 +#define RF_BITRATEMSB_32768_BPS 0x03 +#define RF_BITRATELSB_32768_BPS 0xD1 + +/*! + * RegFdev (Hz) + */ +#define RF_FDEVMSB_2000_HZ 0x00 +#define RF_FDEVLSB_2000_HZ 0x21 +#define RF_FDEVMSB_5000_HZ 0x00 // Default +#define RF_FDEVLSB_5000_HZ 0x52 // Default +#define RF_FDEVMSB_10000_HZ 0x00 +#define RF_FDEVLSB_10000_HZ 0xA4 +#define RF_FDEVMSB_15000_HZ 0x00 +#define RF_FDEVLSB_15000_HZ 0xF6 +#define RF_FDEVMSB_20000_HZ 0x01 +#define RF_FDEVLSB_20000_HZ 0x48 +#define RF_FDEVMSB_25000_HZ 0x01 +#define RF_FDEVLSB_25000_HZ 0x9A +#define RF_FDEVMSB_30000_HZ 0x01 +#define RF_FDEVLSB_30000_HZ 0xEC +#define RF_FDEVMSB_35000_HZ 0x02 +#define RF_FDEVLSB_35000_HZ 0x3D +#define RF_FDEVMSB_40000_HZ 0x02 +#define RF_FDEVLSB_40000_HZ 0x8F +#define RF_FDEVMSB_45000_HZ 0x02 +#define RF_FDEVLSB_45000_HZ 0xE1 +#define RF_FDEVMSB_50000_HZ 0x03 +#define RF_FDEVLSB_50000_HZ 0x33 +#define RF_FDEVMSB_55000_HZ 0x03 +#define RF_FDEVLSB_55000_HZ 0x85 +#define RF_FDEVMSB_60000_HZ 0x03 +#define RF_FDEVLSB_60000_HZ 0xD7 +#define RF_FDEVMSB_65000_HZ 0x04 +#define RF_FDEVLSB_65000_HZ 0x29 +#define RF_FDEVMSB_70000_HZ 0x04 +#define RF_FDEVLSB_70000_HZ 0x7B +#define RF_FDEVMSB_75000_HZ 0x04 +#define RF_FDEVLSB_75000_HZ 0xCD +#define RF_FDEVMSB_80000_HZ 0x05 +#define RF_FDEVLSB_80000_HZ 0x1F +#define RF_FDEVMSB_85000_HZ 0x05 +#define RF_FDEVLSB_85000_HZ 0x71 +#define RF_FDEVMSB_90000_HZ 0x05 +#define RF_FDEVLSB_90000_HZ 0xC3 +#define RF_FDEVMSB_95000_HZ 0x06 +#define RF_FDEVLSB_95000_HZ 0x14 +#define RF_FDEVMSB_100000_HZ 0x06 +#define RF_FDEVLSB_100000_HZ 0x66 +#define RF_FDEVMSB_110000_HZ 0x07 +#define RF_FDEVLSB_110000_HZ 0x0A +#define RF_FDEVMSB_120000_HZ 0x07 +#define RF_FDEVLSB_120000_HZ 0xAE +#define RF_FDEVMSB_130000_HZ 0x08 +#define RF_FDEVLSB_130000_HZ 0x52 +#define RF_FDEVMSB_140000_HZ 0x08 +#define RF_FDEVLSB_140000_HZ 0xF6 +#define RF_FDEVMSB_150000_HZ 0x09 +#define RF_FDEVLSB_150000_HZ 0x9A +#define RF_FDEVMSB_160000_HZ 0x0A +#define RF_FDEVLSB_160000_HZ 0x3D +#define RF_FDEVMSB_170000_HZ 0x0A +#define RF_FDEVLSB_170000_HZ 0xE1 +#define RF_FDEVMSB_180000_HZ 0x0B +#define RF_FDEVLSB_180000_HZ 0x85 +#define RF_FDEVMSB_190000_HZ 0x0C +#define RF_FDEVLSB_190000_HZ 0x29 +#define RF_FDEVMSB_200000_HZ 0x0C +#define RF_FDEVLSB_200000_HZ 0xCD + +/*! + * RegFrf (MHz) + */ +#define RF_FRFMSB_863_MHZ 0xD7 +#define RF_FRFMID_863_MHZ 0xC0 +#define RF_FRFLSB_863_MHZ 0x00 +#define RF_FRFMSB_864_MHZ 0xD8 +#define RF_FRFMID_864_MHZ 0x00 +#define RF_FRFLSB_864_MHZ 0x00 +#define RF_FRFMSB_865_MHZ 0xD8 +#define RF_FRFMID_865_MHZ 0x40 +#define RF_FRFLSB_865_MHZ 0x00 +#define RF_FRFMSB_866_MHZ 0xD8 +#define RF_FRFMID_866_MHZ 0x80 +#define RF_FRFLSB_866_MHZ 0x00 +#define RF_FRFMSB_867_MHZ 0xD8 +#define RF_FRFMID_867_MHZ 0xC0 +#define RF_FRFLSB_867_MHZ 0x00 +#define RF_FRFMSB_868_MHZ 0xD9 +#define RF_FRFMID_868_MHZ 0x00 +#define RF_FRFLSB_868_MHZ 0x00 +#define RF_FRFMSB_869_MHZ 0xD9 +#define RF_FRFMID_869_MHZ 0x40 +#define RF_FRFLSB_869_MHZ 0x00 +#define RF_FRFMSB_870_MHZ 0xD9 +#define RF_FRFMID_870_MHZ 0x80 +#define RF_FRFLSB_870_MHZ 0x00 + +#define RF_FRFMSB_902_MHZ 0xE1 +#define RF_FRFMID_902_MHZ 0x80 +#define RF_FRFLSB_902_MHZ 0x00 +#define RF_FRFMSB_903_MHZ 0xE1 +#define RF_FRFMID_903_MHZ 0xC0 +#define RF_FRFLSB_903_MHZ 0x00 +#define RF_FRFMSB_904_MHZ 0xE2 +#define RF_FRFMID_904_MHZ 0x00 +#define RF_FRFLSB_904_MHZ 0x00 +#define RF_FRFMSB_905_MHZ 0xE2 +#define RF_FRFMID_905_MHZ 0x40 +#define RF_FRFLSB_905_MHZ 0x00 +#define RF_FRFMSB_906_MHZ 0xE2 +#define RF_FRFMID_906_MHZ 0x80 +#define RF_FRFLSB_906_MHZ 0x00 +#define RF_FRFMSB_907_MHZ 0xE2 +#define RF_FRFMID_907_MHZ 0xC0 +#define RF_FRFLSB_907_MHZ 0x00 +#define RF_FRFMSB_908_MHZ 0xE3 +#define RF_FRFMID_908_MHZ 0x00 +#define RF_FRFLSB_908_MHZ 0x00 +#define RF_FRFMSB_909_MHZ 0xE3 +#define RF_FRFMID_909_MHZ 0x40 +#define RF_FRFLSB_909_MHZ 0x00 +#define RF_FRFMSB_910_MHZ 0xE3 +#define RF_FRFMID_910_MHZ 0x80 +#define RF_FRFLSB_910_MHZ 0x00 +#define RF_FRFMSB_911_MHZ 0xE3 +#define RF_FRFMID_911_MHZ 0xC0 +#define RF_FRFLSB_911_MHZ 0x00 +#define RF_FRFMSB_912_MHZ 0xE4 +#define RF_FRFMID_912_MHZ 0x00 +#define RF_FRFLSB_912_MHZ 0x00 +#define RF_FRFMSB_913_MHZ 0xE4 +#define RF_FRFMID_913_MHZ 0x40 +#define RF_FRFLSB_913_MHZ 0x00 +#define RF_FRFMSB_914_MHZ 0xE4 +#define RF_FRFMID_914_MHZ 0x80 +#define RF_FRFLSB_914_MHZ 0x00 +#define RF_FRFMSB_915_MHZ 0xE4 // Default +#define RF_FRFMID_915_MHZ 0xC0 // Default +#define RF_FRFLSB_915_MHZ 0x00 // Default +#define RF_FRFMSB_916_MHZ 0xE5 +#define RF_FRFMID_916_MHZ 0x00 +#define RF_FRFLSB_916_MHZ 0x00 +#define RF_FRFMSB_917_MHZ 0xE5 +#define RF_FRFMID_917_MHZ 0x40 +#define RF_FRFLSB_917_MHZ 0x00 +#define RF_FRFMSB_918_MHZ 0xE5 +#define RF_FRFMID_918_MHZ 0x80 +#define RF_FRFLSB_918_MHZ 0x00 +#define RF_FRFMSB_919_MHZ 0xE5 +#define RF_FRFMID_919_MHZ 0xC0 +#define RF_FRFLSB_919_MHZ 0x00 +#define RF_FRFMSB_920_MHZ 0xE6 +#define RF_FRFMID_920_MHZ 0x00 +#define RF_FRFLSB_920_MHZ 0x00 +#define RF_FRFMSB_921_MHZ 0xE6 +#define RF_FRFMID_921_MHZ 0x40 +#define RF_FRFLSB_921_MHZ 0x00 +#define RF_FRFMSB_922_MHZ 0xE6 +#define RF_FRFMID_922_MHZ 0x80 +#define RF_FRFLSB_922_MHZ 0x00 +#define RF_FRFMSB_923_MHZ 0xE6 +#define RF_FRFMID_923_MHZ 0xC0 +#define RF_FRFLSB_923_MHZ 0x00 +#define RF_FRFMSB_924_MHZ 0xE7 +#define RF_FRFMID_924_MHZ 0x00 +#define RF_FRFLSB_924_MHZ 0x00 +#define RF_FRFMSB_925_MHZ 0xE7 +#define RF_FRFMID_925_MHZ 0x40 +#define RF_FRFLSB_925_MHZ 0x00 +#define RF_FRFMSB_926_MHZ 0xE7 +#define RF_FRFMID_926_MHZ 0x80 +#define RF_FRFLSB_926_MHZ 0x00 +#define RF_FRFMSB_927_MHZ 0xE7 +#define RF_FRFMID_927_MHZ 0xC0 +#define RF_FRFLSB_927_MHZ 0x00 +#define RF_FRFMSB_928_MHZ 0xE8 +#define RF_FRFMID_928_MHZ 0x00 +#define RF_FRFLSB_928_MHZ 0x00 + +/*! + * RegPaConfig + */ +#define RF_PACONFIG_PASELECT_MASK 0x7F +#define RF_PACONFIG_PASELECT_PABOOST 0x80 +#define RF_PACONFIG_PASELECT_RFO 0x00 // Default + +#define RF_PACONFIG_MAX_POWER_MASK 0x8F + +#define RF_PACONFIG_OUTPUTPOWER_MASK 0xF0 + +/*! + * RegPaRamp + */ +#define RF_PARAMP_MODULATIONSHAPING_MASK 0x9F +#define RF_PARAMP_MODULATIONSHAPING_00 0x00 // Default +#define RF_PARAMP_MODULATIONSHAPING_01 0x20 +#define RF_PARAMP_MODULATIONSHAPING_10 0x40 +#define RF_PARAMP_MODULATIONSHAPING_11 0x60 + +#define RF_PARAMP_LOWPNTXPLL_MASK 0xEF +#define RF_PARAMP_LOWPNTXPLL_OFF 0x10 +#define RF_PARAMP_LOWPNTXPLL_ON 0x00 // Default + +#define RF_PARAMP_MASK 0xF0 +#define RF_PARAMP_3400_US 0x00 +#define RF_PARAMP_2000_US 0x01 +#define RF_PARAMP_1000_US 0x02 +#define RF_PARAMP_0500_US 0x03 +#define RF_PARAMP_0250_US 0x04 +#define RF_PARAMP_0125_US 0x05 +#define RF_PARAMP_0100_US 0x06 +#define RF_PARAMP_0062_US 0x07 +#define RF_PARAMP_0050_US 0x08 +#define RF_PARAMP_0040_US 0x09 // Default +#define RF_PARAMP_0031_US 0x0A +#define RF_PARAMP_0025_US 0x0B +#define RF_PARAMP_0020_US 0x0C +#define RF_PARAMP_0015_US 0x0D +#define RF_PARAMP_0012_US 0x0E +#define RF_PARAMP_0010_US 0x0F + +/*! + * RegOcp + */ +#define RF_OCP_MASK 0xDF +#define RF_OCP_ON 0x20 // Default +#define RF_OCP_OFF 0x00 + +#define RF_OCP_TRIM_MASK 0xE0 +#define RF_OCP_TRIM_045_MA 0x00 +#define RF_OCP_TRIM_050_MA 0x01 +#define RF_OCP_TRIM_055_MA 0x02 +#define RF_OCP_TRIM_060_MA 0x03 +#define RF_OCP_TRIM_065_MA 0x04 +#define RF_OCP_TRIM_070_MA 0x05 +#define RF_OCP_TRIM_075_MA 0x06 +#define RF_OCP_TRIM_080_MA 0x07 +#define RF_OCP_TRIM_085_MA 0x08 +#define RF_OCP_TRIM_090_MA 0x09 +#define RF_OCP_TRIM_095_MA 0x0A +#define RF_OCP_TRIM_100_MA 0x0B // Default +#define RF_OCP_TRIM_105_MA 0x0C +#define RF_OCP_TRIM_110_MA 0x0D +#define RF_OCP_TRIM_115_MA 0x0E +#define RF_OCP_TRIM_120_MA 0x0F +#define RF_OCP_TRIM_130_MA 0x10 +#define RF_OCP_TRIM_140_MA 0x11 +#define RF_OCP_TRIM_150_MA 0x12 +#define RF_OCP_TRIM_160_MA 0x13 +#define RF_OCP_TRIM_170_MA 0x14 +#define RF_OCP_TRIM_180_MA 0x15 +#define RF_OCP_TRIM_190_MA 0x16 +#define RF_OCP_TRIM_200_MA 0x17 +#define RF_OCP_TRIM_210_MA 0x18 +#define RF_OCP_TRIM_220_MA 0x19 +#define RF_OCP_TRIM_230_MA 0x1A +#define RF_OCP_TRIM_240_MA 0x1B + +/*! + * RegLna + */ +#define RF_LNA_GAIN_MASK 0x1F +#define RF_LNA_GAIN_G1 0x20 // Default +#define RF_LNA_GAIN_G2 0x40 +#define RF_LNA_GAIN_G3 0x60 +#define RF_LNA_GAIN_G4 0x80 +#define RF_LNA_GAIN_G5 0xA0 +#define RF_LNA_GAIN_G6 0xC0 + +#define RF_LNA_BOOST_MASK 0xFC +#define RF_LNA_BOOST_OFF 0x00 // Default +#define RF_LNA_BOOST_ON 0x03 + +/*! + * RegRxConfig + */ +#define RF_RXCONFIG_RESTARTRXONCOLLISION_MASK 0x7F +#define RF_RXCONFIG_RESTARTRXONCOLLISION_ON 0x80 +#define RF_RXCONFIG_RESTARTRXONCOLLISION_OFF 0x00 // Default + +#define RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK 0x40 // Write only + +#define RF_RXCONFIG_RESTARTRXWITHPLLLOCK 0x20 // Write only + +#define RF_RXCONFIG_AFCAUTO_MASK 0xEF +#define RF_RXCONFIG_AFCAUTO_ON 0x10 +#define RF_RXCONFIG_AFCAUTO_OFF 0x00 // Default + +#define RF_RXCONFIG_AGCAUTO_MASK 0xF7 +#define RF_RXCONFIG_AGCAUTO_ON 0x08 // Default +#define RF_RXCONFIG_AGCAUTO_OFF 0x00 + +#define RF_RXCONFIG_RXTRIGER_MASK 0xF8 +#define RF_RXCONFIG_RXTRIGER_OFF 0x00 +#define RF_RXCONFIG_RXTRIGER_RSSI 0x01 +#define RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT 0x06 // Default +#define RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT 0x07 + +/*! + * RegRssiConfig + */ +#define RF_RSSICONFIG_OFFSET_MASK 0x07 +#define RF_RSSICONFIG_OFFSET_P_00_DB 0x00 // Default +#define RF_RSSICONFIG_OFFSET_P_01_DB 0x08 +#define RF_RSSICONFIG_OFFSET_P_02_DB 0x10 +#define RF_RSSICONFIG_OFFSET_P_03_DB 0x18 +#define RF_RSSICONFIG_OFFSET_P_04_DB 0x20 +#define RF_RSSICONFIG_OFFSET_P_05_DB 0x28 +#define RF_RSSICONFIG_OFFSET_P_06_DB 0x30 +#define RF_RSSICONFIG_OFFSET_P_07_DB 0x38 +#define RF_RSSICONFIG_OFFSET_P_08_DB 0x40 +#define RF_RSSICONFIG_OFFSET_P_09_DB 0x48 +#define RF_RSSICONFIG_OFFSET_P_10_DB 0x50 +#define RF_RSSICONFIG_OFFSET_P_11_DB 0x58 +#define RF_RSSICONFIG_OFFSET_P_12_DB 0x60 +#define RF_RSSICONFIG_OFFSET_P_13_DB 0x68 +#define RF_RSSICONFIG_OFFSET_P_14_DB 0x70 +#define RF_RSSICONFIG_OFFSET_P_15_DB 0x78 +#define RF_RSSICONFIG_OFFSET_M_16_DB 0x80 +#define RF_RSSICONFIG_OFFSET_M_15_DB 0x88 +#define RF_RSSICONFIG_OFFSET_M_14_DB 0x90 +#define RF_RSSICONFIG_OFFSET_M_13_DB 0x98 +#define RF_RSSICONFIG_OFFSET_M_12_DB 0xA0 +#define RF_RSSICONFIG_OFFSET_M_11_DB 0xA8 +#define RF_RSSICONFIG_OFFSET_M_10_DB 0xB0 +#define RF_RSSICONFIG_OFFSET_M_09_DB 0xB8 +#define RF_RSSICONFIG_OFFSET_M_08_DB 0xC0 +#define RF_RSSICONFIG_OFFSET_M_07_DB 0xC8 +#define RF_RSSICONFIG_OFFSET_M_06_DB 0xD0 +#define RF_RSSICONFIG_OFFSET_M_05_DB 0xD8 +#define RF_RSSICONFIG_OFFSET_M_04_DB 0xE0 +#define RF_RSSICONFIG_OFFSET_M_03_DB 0xE8 +#define RF_RSSICONFIG_OFFSET_M_02_DB 0xF0 +#define RF_RSSICONFIG_OFFSET_M_01_DB 0xF8 + +#define RF_RSSICONFIG_SMOOTHING_MASK 0xF8 +#define RF_RSSICONFIG_SMOOTHING_2 0x00 +#define RF_RSSICONFIG_SMOOTHING_4 0x01 +#define RF_RSSICONFIG_SMOOTHING_8 0x02 // Default +#define RF_RSSICONFIG_SMOOTHING_16 0x03 +#define RF_RSSICONFIG_SMOOTHING_32 0x04 +#define RF_RSSICONFIG_SMOOTHING_64 0x05 +#define RF_RSSICONFIG_SMOOTHING_128 0x06 +#define RF_RSSICONFIG_SMOOTHING_256 0x07 + +/*! + * RegRssiCollision + */ +#define RF_RSSICOLISION_THRESHOLD 0x0A // Default + +/*! + * RegRssiThresh + */ +#define RF_RSSITHRESH_THRESHOLD 0xFF // Default + +/*! + * RegRssiValue (Read Only) + */ + +/*! + * RegRxBw + */ +#define RF_RXBW_MANT_MASK 0xE7 +#define RF_RXBW_MANT_16 0x00 +#define RF_RXBW_MANT_20 0x08 +#define RF_RXBW_MANT_24 0x10 // Default + +#define RF_RXBW_EXP_MASK 0xF8 +#define RF_RXBW_EXP_0 0x00 +#define RF_RXBW_EXP_1 0x01 +#define RF_RXBW_EXP_2 0x02 +#define RF_RXBW_EXP_3 0x03 +#define RF_RXBW_EXP_4 0x04 +#define RF_RXBW_EXP_5 0x05 // Default +#define RF_RXBW_EXP_6 0x06 +#define RF_RXBW_EXP_7 0x07 + +/*! + * RegAfcBw + */ +#define RF_AFCBW_MANTAFC_MASK 0xE7 +#define RF_AFCBW_MANTAFC_16 0x00 +#define RF_AFCBW_MANTAFC_20 0x08 // Default +#define RF_AFCBW_MANTAFC_24 0x10 + +#define RF_AFCBW_EXPAFC_MASK 0xF8 +#define RF_AFCBW_EXPAFC_0 0x00 +#define RF_AFCBW_EXPAFC_1 0x01 +#define RF_AFCBW_EXPAFC_2 0x02 +#define RF_AFCBW_EXPAFC_3 0x03 // Default +#define RF_AFCBW_EXPAFC_4 0x04 +#define RF_AFCBW_EXPAFC_5 0x05 +#define RF_AFCBW_EXPAFC_6 0x06 +#define RF_AFCBW_EXPAFC_7 0x07 + +/*! + * RegOokPeak + */ +#define RF_OOKPEAK_BITSYNC_MASK 0xDF // Default +#define RF_OOKPEAK_BITSYNC_ON 0x20 // Default +#define RF_OOKPEAK_BITSYNC_OFF 0x00 + +#define RF_OOKPEAK_OOKTHRESHTYPE_MASK 0xE7 +#define RF_OOKPEAK_OOKTHRESHTYPE_FIXED 0x00 +#define RF_OOKPEAK_OOKTHRESHTYPE_PEAK 0x08 // Default +#define RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE 0x10 + +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK 0xF8 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB 0x00 // Default +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB 0x01 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB 0x02 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB 0x03 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB 0x04 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB 0x05 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB 0x06 +#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB 0x07 + +/*! + * RegOokFix + */ +#define RF_OOKFIX_OOKFIXEDTHRESHOLD 0x0C // Default + +/*! + * RegOokAvg + */ +#define RF_OOKAVG_OOKPEAKTHRESHDEC_MASK 0x1F +#define RF_OOKAVG_OOKPEAKTHRESHDEC_000 0x00 // Default +#define RF_OOKAVG_OOKPEAKTHRESHDEC_001 0x20 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_010 0x40 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_011 0x60 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_100 0x80 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_101 0xA0 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_110 0xC0 +#define RF_OOKAVG_OOKPEAKTHRESHDEC_111 0xE0 + +#define RF_OOKAVG_AVERAGEOFFSET_MASK 0xF3 +#define RF_OOKAVG_AVERAGEOFFSET_0_DB 0x00 // Default +#define RF_OOKAVG_AVERAGEOFFSET_2_DB 0x04 +#define RF_OOKAVG_AVERAGEOFFSET_4_DB 0x08 +#define RF_OOKAVG_AVERAGEOFFSET_6_DB 0x0C + +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK 0xFC +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_00 0x00 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_01 0x01 +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_10 0x02 // Default +#define RF_OOKAVG_OOKAVERAGETHRESHFILT_11 0x03 + +/*! + * RegAfcFei + */ +#define RF_AFCFEI_AGCSTART 0x10 + +#define RF_AFCFEI_AFCCLEAR 0x02 + +#define RF_AFCFEI_AFCAUTOCLEAR_MASK 0xFE +#define RF_AFCFEI_AFCAUTOCLEAR_ON 0x01 +#define RF_AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default + +/*! + * RegAfcMsb (Read Only) + */ + +/*! + * RegAfcLsb (Read Only) + */ + +/*! + * RegFeiMsb (Read Only) + */ + +/*! + * RegFeiLsb (Read Only) + */ + +/*! + * RegPreambleDetect + */ +#define RF_PREAMBLEDETECT_DETECTOR_MASK 0x7F +#define RF_PREAMBLEDETECT_DETECTOR_ON 0x80 // Default +#define RF_PREAMBLEDETECT_DETECTOR_OFF 0x00 + +#define RF_PREAMBLEDETECT_DETECTORSIZE_MASK 0x9F +#define RF_PREAMBLEDETECT_DETECTORSIZE_1 0x00 +#define RF_PREAMBLEDETECT_DETECTORSIZE_2 0x20 // Default +#define RF_PREAMBLEDETECT_DETECTORSIZE_3 0x40 +#define RF_PREAMBLEDETECT_DETECTORSIZE_4 0x60 + +#define RF_PREAMBLEDETECT_DETECTORTOL_MASK 0xE0 +#define RF_PREAMBLEDETECT_DETECTORTOL_0 0x00 +#define RF_PREAMBLEDETECT_DETECTORTOL_1 0x01 +#define RF_PREAMBLEDETECT_DETECTORTOL_2 0x02 +#define RF_PREAMBLEDETECT_DETECTORTOL_3 0x03 +#define RF_PREAMBLEDETECT_DETECTORTOL_4 0x04 +#define RF_PREAMBLEDETECT_DETECTORTOL_5 0x05 +#define RF_PREAMBLEDETECT_DETECTORTOL_6 0x06 +#define RF_PREAMBLEDETECT_DETECTORTOL_7 0x07 +#define RF_PREAMBLEDETECT_DETECTORTOL_8 0x08 +#define RF_PREAMBLEDETECT_DETECTORTOL_9 0x09 +#define RF_PREAMBLEDETECT_DETECTORTOL_10 0x0A // Default +#define RF_PREAMBLEDETECT_DETECTORTOL_11 0x0B +#define RF_PREAMBLEDETECT_DETECTORTOL_12 0x0C +#define RF_PREAMBLEDETECT_DETECTORTOL_13 0x0D +#define RF_PREAMBLEDETECT_DETECTORTOL_14 0x0E +#define RF_PREAMBLEDETECT_DETECTORTOL_15 0x0F +#define RF_PREAMBLEDETECT_DETECTORTOL_16 0x10 +#define RF_PREAMBLEDETECT_DETECTORTOL_17 0x11 +#define RF_PREAMBLEDETECT_DETECTORTOL_18 0x12 +#define RF_PREAMBLEDETECT_DETECTORTOL_19 0x13 +#define RF_PREAMBLEDETECT_DETECTORTOL_20 0x14 +#define RF_PREAMBLEDETECT_DETECTORTOL_21 0x15 +#define RF_PREAMBLEDETECT_DETECTORTOL_22 0x16 +#define RF_PREAMBLEDETECT_DETECTORTOL_23 0x17 +#define RF_PREAMBLEDETECT_DETECTORTOL_24 0x18 +#define RF_PREAMBLEDETECT_DETECTORTOL_25 0x19 +#define RF_PREAMBLEDETECT_DETECTORTOL_26 0x1A +#define RF_PREAMBLEDETECT_DETECTORTOL_27 0x1B +#define RF_PREAMBLEDETECT_DETECTORTOL_28 0x1C +#define RF_PREAMBLEDETECT_DETECTORTOL_29 0x1D +#define RF_PREAMBLEDETECT_DETECTORTOL_30 0x1E +#define RF_PREAMBLEDETECT_DETECTORTOL_31 0x1F + +/*! + * RegRxTimeout1 + */ +#define RF_RXTIMEOUT1_TIMEOUTRXRSSI 0x00 // Default + +/*! + * RegRxTimeout2 + */ +#define RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE 0x00 // Default + +/*! + * RegRxTimeout3 + */ +#define RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC 0x00 // Default + +/*! + * RegRxDelay + */ +#define RF_RXDELAY_INTERPACKETRXDELAY 0x00 // Default + +/*! + * RegOsc + */ +#define RF_OSC_RCCALSTART 0x08 + +#define RF_OSC_CLKOUT_MASK 0xF8 +#define RF_OSC_CLKOUT_32_MHZ 0x00 +#define RF_OSC_CLKOUT_16_MHZ 0x01 +#define RF_OSC_CLKOUT_8_MHZ 0x02 +#define RF_OSC_CLKOUT_4_MHZ 0x03 +#define RF_OSC_CLKOUT_2_MHZ 0x04 +#define RF_OSC_CLKOUT_1_MHZ 0x05 // Default +#define RF_OSC_CLKOUT_RC 0x06 +#define RF_OSC_CLKOUT_OFF 0x07 + +/*! + * RegPreambleMsb/RegPreambleLsb + */ +#define RF_PREAMBLEMSB_SIZE 0x00 // Default +#define RF_PREAMBLELSB_SIZE 0x03 // Default + +/*! + * RegSyncConfig + */ +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK 0x3F +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON 0x80 // Default +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF 0x40 +#define RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF 0x00 + + +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK 0xDF +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_55 0x20 +#define RF_SYNCCONFIG_PREAMBLEPOLARITY_AA 0x00 // Default + +#define RF_SYNCCONFIG_SYNC_MASK 0xEF +#define RF_SYNCCONFIG_SYNC_ON 0x10 // Default +#define RF_SYNCCONFIG_SYNC_OFF 0x00 + + +#define RF_SYNCCONFIG_SYNCSIZE_MASK 0xF8 +#define RF_SYNCCONFIG_SYNCSIZE_1 0x00 +#define RF_SYNCCONFIG_SYNCSIZE_2 0x01 +#define RF_SYNCCONFIG_SYNCSIZE_3 0x02 +#define RF_SYNCCONFIG_SYNCSIZE_4 0x03 // Default +#define RF_SYNCCONFIG_SYNCSIZE_5 0x04 +#define RF_SYNCCONFIG_SYNCSIZE_6 0x05 +#define RF_SYNCCONFIG_SYNCSIZE_7 0x06 +#define RF_SYNCCONFIG_SYNCSIZE_8 0x07 + +/*! + * RegSyncValue1-8 + */ +#define RF_SYNCVALUE1_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE2_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE3_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE4_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE5_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE6_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE7_SYNCVALUE 0x01 // Default +#define RF_SYNCVALUE8_SYNCVALUE 0x01 // Default + +/*! + * RegPacketConfig1 + */ +#define RF_PACKETCONFIG1_PACKETFORMAT_MASK 0x7F +#define RF_PACKETCONFIG1_PACKETFORMAT_FIXED 0x00 +#define RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE 0x80 // Default + +#define RF_PACKETCONFIG1_DCFREE_MASK 0x9F +#define RF_PACKETCONFIG1_DCFREE_OFF 0x00 // Default +#define RF_PACKETCONFIG1_DCFREE_MANCHESTER 0x20 +#define RF_PACKETCONFIG1_DCFREE_WHITENING 0x40 + +#define RF_PACKETCONFIG1_CRC_MASK 0xEF +#define RF_PACKETCONFIG1_CRC_ON 0x10 // Default +#define RF_PACKETCONFIG1_CRC_OFF 0x00 + +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK 0xF7 +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_ON 0x00 // Default +#define RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 + +#define RF_PACKETCONFIG1_ADDRSFILTERING_MASK 0xF9 +#define RF_PACKETCONFIG1_ADDRSFILTERING_OFF 0x00 // Default +#define RF_PACKETCONFIG1_ADDRSFILTERING_NODE 0x02 +#define RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST 0x04 + +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK 0xFE +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT 0x00 // Default +#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM 0x01 + +/*! + * RegPacketConfig2 + */ + +#define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE_MASK 0x7F +#define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE 0x80 +#define RF_PACKETCONFIG2_WMBUS_CRC_DISABLE 0x00 // Default + +#define RF_PACKETCONFIG2_DATAMODE_MASK 0xBF +#define RF_PACKETCONFIG2_DATAMODE_CONTINUOUS 0x00 +#define RF_PACKETCONFIG2_DATAMODE_PACKET 0x40 // Default + +#define RF_PACKETCONFIG2_IOHOME_MASK 0xDF +#define RF_PACKETCONFIG2_IOHOME_ON 0x20 +#define RF_PACKETCONFIG2_IOHOME_OFF 0x00 // Default + +#define RF_PACKETCONFIG2_BEACON_MASK 0xF7 +#define RF_PACKETCONFIG2_BEACON_ON 0x08 +#define RF_PACKETCONFIG2_BEACON_OFF 0x00 // Default + +#define RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK 0xF8 + +/*! + * RegPayloadLength + */ +#define RF_PAYLOADLENGTH_LENGTH 0x40 // Default + +/*! + * RegNodeAdrs + */ +#define RF_NODEADDRESS_ADDRESS 0x00 + +/*! + * RegBroadcastAdrs + */ +#define RF_BROADCASTADDRESS_ADDRESS 0x00 + +/*! + * RegFifoThresh + */ +#define RF_FIFOTHRESH_TXSTARTCONDITION_MASK 0x7F +#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH 0x00 // Default +#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY 0x80 + +#define RF_FIFOTHRESH_FIFOTHRESHOLD_MASK 0xC0 +#define RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD 0x0F // Default + +/*! + * RegSeqConfig1 + */ +#define RF_SEQCONFIG1_SEQUENCER_START 0x80 + +#define RF_SEQCONFIG1_SEQUENCER_STOP 0x40 + +#define RF_SEQCONFIG1_IDLEMODE_MASK 0xDF +#define RF_SEQCONFIG1_IDLEMODE_SLEEP 0x20 +#define RF_SEQCONFIG1_IDLEMODE_STANDBY 0x00 // Default + +#define RF_SEQCONFIG1_FROMSTART_MASK 0xE7 +#define RF_SEQCONFIG1_FROMSTART_TOLPS 0x00 // Default +#define RF_SEQCONFIG1_FROMSTART_TORX 0x08 +#define RF_SEQCONFIG1_FROMSTART_TOTX 0x10 +#define RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL 0x18 + +#define RF_SEQCONFIG1_LPS_MASK 0xFB +#define RF_SEQCONFIG1_LPS_SEQUENCER_OFF 0x00 // Default +#define RF_SEQCONFIG1_LPS_IDLE 0x04 + +#define RF_SEQCONFIG1_FROMIDLE_MASK 0xFD +#define RF_SEQCONFIG1_FROMIDLE_TOTX 0x00 // Default +#define RF_SEQCONFIG1_FROMIDLE_TORX 0x02 + +#define RF_SEQCONFIG1_FROMTX_MASK 0xFE +#define RF_SEQCONFIG1_FROMTX_TOLPS 0x00 // Default +#define RF_SEQCONFIG1_FROMTX_TORX 0x01 + +/*! + * RegSeqConfig2 + */ +#define RF_SEQCONFIG2_FROMRX_MASK 0x1F +#define RF_SEQCONFIG2_FROMRX_TOUNUSED_000 0x00 // Default +#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY 0x20 +#define RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY 0x40 +#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK 0x60 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI 0x80 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC 0xA0 +#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE 0xC0 +#define RF_SEQCONFIG2_FROMRX_TOUNUSED_111 0xE0 + +#define RF_SEQCONFIG2_FROMRXTIMEOUT_MASK 0xE7 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART 0x00 // Default +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX 0x08 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS 0x10 +#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF 0x18 + +#define RF_SEQCONFIG2_FROMRXPKT_MASK 0xF8 +#define RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF 0x00 // Default +#define RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY 0x01 +#define RF_SEQCONFIG2_FROMRXPKT_TOLPS 0x02 +#define RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX 0x03 +#define RF_SEQCONFIG2_FROMRXPKT_TORX 0x04 + +/*! + * RegTimerResol + */ +#define RF_TIMERRESOL_TIMER1RESOL_MASK 0xF3 +#define RF_TIMERRESOL_TIMER1RESOL_OFF 0x00 // Default +#define RF_TIMERRESOL_TIMER1RESOL_000064_US 0x04 +#define RF_TIMERRESOL_TIMER1RESOL_004100_US 0x08 +#define RF_TIMERRESOL_TIMER1RESOL_262000_US 0x0C + +#define RF_TIMERRESOL_TIMER2RESOL_MASK 0xFC +#define RF_TIMERRESOL_TIMER2RESOL_OFF 0x00 // Default +#define RF_TIMERRESOL_TIMER2RESOL_000064_US 0x01 +#define RF_TIMERRESOL_TIMER2RESOL_004100_US 0x02 +#define RF_TIMERRESOL_TIMER2RESOL_262000_US 0x03 + +/*! + * RegTimer1Coef + */ +#define RF_TIMER1COEF_TIMER1COEFFICIENT 0xF5 // Default + +/*! + * RegTimer2Coef + */ +#define RF_TIMER2COEF_TIMER2COEFFICIENT 0x20 // Default + +/*! + * RegImageCal + */ +#define RF_IMAGECAL_AUTOIMAGECAL_MASK 0x7F +#define RF_IMAGECAL_AUTOIMAGECAL_ON 0x80 +#define RF_IMAGECAL_AUTOIMAGECAL_OFF 0x00 // Default + +#define RF_IMAGECAL_IMAGECAL_MASK 0xBF +#define RF_IMAGECAL_IMAGECAL_START 0x40 + +#define RF_IMAGECAL_IMAGECAL_RUNNING 0x20 +#define RF_IMAGECAL_IMAGECAL_DONE 0x00 // Default + +#define RF_IMAGECAL_TEMPCHANGE_HIGHER 0x08 +#define RF_IMAGECAL_TEMPCHANGE_LOWER 0x00 + +#define RF_IMAGECAL_TEMPTHRESHOLD_MASK 0xF9 +#define RF_IMAGECAL_TEMPTHRESHOLD_05 0x00 +#define RF_IMAGECAL_TEMPTHRESHOLD_10 0x02 // Default +#define RF_IMAGECAL_TEMPTHRESHOLD_15 0x04 +#define RF_IMAGECAL_TEMPTHRESHOLD_20 0x06 + +#define RF_IMAGECAL_TEMPMONITOR_MASK 0xFE +#define RF_IMAGECAL_TEMPMONITOR_ON 0x00 // Default +#define RF_IMAGECAL_TEMPMONITOR_OFF 0x01 + +/*! + * RegTemp (Read Only) + */ + +/*! + * RegLowBat + */ +#define RF_LOWBAT_MASK 0xF7 +#define RF_LOWBAT_ON 0x08 +#define RF_LOWBAT_OFF 0x00 // Default + +#define RF_LOWBAT_TRIM_MASK 0xF8 +#define RF_LOWBAT_TRIM_1695 0x00 +#define RF_LOWBAT_TRIM_1764 0x01 +#define RF_LOWBAT_TRIM_1835 0x02 // Default +#define RF_LOWBAT_TRIM_1905 0x03 +#define RF_LOWBAT_TRIM_1976 0x04 +#define RF_LOWBAT_TRIM_2045 0x05 +#define RF_LOWBAT_TRIM_2116 0x06 +#define RF_LOWBAT_TRIM_2185 0x07 + +/*! + * RegIrqFlags1 + */ +#define RF_IRQFLAGS1_MODEREADY 0x80 + +#define RF_IRQFLAGS1_RXREADY 0x40 + +#define RF_IRQFLAGS1_TXREADY 0x20 + +#define RF_IRQFLAGS1_PLLLOCK 0x10 + +#define RF_IRQFLAGS1_RSSI 0x08 + +#define RF_IRQFLAGS1_TIMEOUT 0x04 + +#define RF_IRQFLAGS1_PREAMBLEDETECT 0x02 + +#define RF_IRQFLAGS1_SYNCADDRESSMATCH 0x01 + +/*! + * RegIrqFlags2 + */ +#define RF_IRQFLAGS2_FIFOFULL 0x80 + +#define RF_IRQFLAGS2_FIFOEMPTY 0x40 + +#define RF_IRQFLAGS2_FIFOLEVEL 0x20 + +#define RF_IRQFLAGS2_FIFOOVERRUN 0x10 + +#define RF_IRQFLAGS2_PACKETSENT 0x08 + +#define RF_IRQFLAGS2_PAYLOADREADY 0x04 + +#define RF_IRQFLAGS2_CRCOK 0x02 + +#define RF_IRQFLAGS2_LOWBAT 0x01 + +/*! + * RegDioMapping1 + */ +#define RF_DIOMAPPING1_DIO0_MASK 0x3F +#define RF_DIOMAPPING1_DIO0_00 0x00 // Default +#define RF_DIOMAPPING1_DIO0_01 0x40 +#define RF_DIOMAPPING1_DIO0_10 0x80 +#define RF_DIOMAPPING1_DIO0_11 0xC0 + +#define RF_DIOMAPPING1_DIO1_MASK 0xCF +#define RF_DIOMAPPING1_DIO1_00 0x00 // Default +#define RF_DIOMAPPING1_DIO1_01 0x10 +#define RF_DIOMAPPING1_DIO1_10 0x20 +#define RF_DIOMAPPING1_DIO1_11 0x30 + +#define RF_DIOMAPPING1_DIO2_MASK 0xF3 +#define RF_DIOMAPPING1_DIO2_00 0x00 // Default +#define RF_DIOMAPPING1_DIO2_01 0x04 +#define RF_DIOMAPPING1_DIO2_10 0x08 +#define RF_DIOMAPPING1_DIO2_11 0x0C + +#define RF_DIOMAPPING1_DIO3_MASK 0xFC +#define RF_DIOMAPPING1_DIO3_00 0x00 // Default +#define RF_DIOMAPPING1_DIO3_01 0x01 +#define RF_DIOMAPPING1_DIO3_10 0x02 +#define RF_DIOMAPPING1_DIO3_11 0x03 + +/*! + * RegDioMapping2 + */ +#define RF_DIOMAPPING2_DIO4_MASK 0x3F +#define RF_DIOMAPPING2_DIO4_00 0x00 // Default +#define RF_DIOMAPPING2_DIO4_01 0x40 +#define RF_DIOMAPPING2_DIO4_10 0x80 +#define RF_DIOMAPPING2_DIO4_11 0xC0 + +#define RF_DIOMAPPING2_DIO5_MASK 0xCF +#define RF_DIOMAPPING2_DIO5_00 0x00 // Default +#define RF_DIOMAPPING2_DIO5_01 0x10 +#define RF_DIOMAPPING2_DIO5_10 0x20 +#define RF_DIOMAPPING2_DIO5_11 0x30 + +#define RF_DIOMAPPING2_MAP_MASK 0xFE +#define RF_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 +#define RF_DIOMAPPING2_MAP_RSSI 0x00 // Default + +/*! + * RegVersion (Read Only) + */ + +/*! + * RegPllHop + */ +#define RF_PLLHOP_FASTHOP_MASK 0x7F +#define RF_PLLHOP_FASTHOP_ON 0x80 +#define RF_PLLHOP_FASTHOP_OFF 0x00 // Default + +/*! + * RegTcxo + */ +#define RF_TCXO_TCXOINPUT_MASK 0xEF +#define RF_TCXO_TCXOINPUT_ON 0x10 +#define RF_TCXO_TCXOINPUT_OFF 0x00 // Default + +/*! + * RegPaDac + */ +#define RF_PADAC_20DBM_MASK 0xF8 +#define RF_PADAC_20DBM_ON 0x07 +#define RF_PADAC_20DBM_OFF 0x04 // Default + +/*! + * RegFormerTemp + */ + +/*! + * RegBitrateFrac + */ +#define RF_BITRATEFRAC_MASK 0xF0 + +/*! + * RegAgcRef + */ + +/*! + * RegAgcThresh1 + */ + +/*! + * RegAgcThresh2 + */ + +/*! + * RegAgcThresh3 + */ + +/*! + * RegPll + */ +#define RF_PLL_BANDWIDTH_MASK 0x3F +#define RF_PLL_BANDWIDTH_75 0x00 +#define RF_PLL_BANDWIDTH_150 0x40 +#define RF_PLL_BANDWIDTH_225 0x80 +#define RF_PLL_BANDWIDTH_300 0xC0 // Default + + + + + + + + + + + +#endif // __REGISTERS_H__
diff -r 000000000000 -r 4e8ef5758455 sx1278.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sx1278.c Sat Nov 16 16:34:57 2019 +0000
@@ -0,0 +1,1895 @@
+/**
+ * @brief: Implementation of a SX1278 radio functions
+ * @author: luk6xff based on SEMTCH code: https://github.com/Lora-net/LoRaMac-node
+ * @email: luszko@op.pl
+ * @date: 2019-11-15
+ */
+#include "registers.h"
+#include "sx1278.h"
+
+#include <math.h>
+#include <string.h>
+
+/**
+ * ============================================================================
+ * @brief Private global constants
+ * ============================================================================
+ */
+//-----------------------------------------------------------------------------
+/**
+ * Precomputed FSK bandwidth registers values
+ */
+static const BandwidthMap_t SX1278FskBandwidths[] =
+{
+ { 2600 , 0x17 },
+ { 3100 , 0x0F },
+ { 3900 , 0x07 },
+ { 5200 , 0x16 },
+ { 6300 , 0x0E },
+ { 7800 , 0x06 },
+ { 10400 , 0x15 },
+ { 12500 , 0x0D },
+ { 15600 , 0x05 },
+ { 20800 , 0x14 },
+ { 25000 , 0x0C },
+ { 31300 , 0x04 },
+ { 41700 , 0x13 },
+ { 50000 , 0x0B },
+ { 62500 , 0x03 },
+ { 83333 , 0x12 },
+ { 100000, 0x0A },
+ { 125000, 0x02 },
+ { 166700, 0x11 },
+ { 200000, 0x09 },
+ { 250000, 0x01 },
+ { 300000, 0x00 }, // Invalid Bandwidth
+};
+
+//-----------------------------------------------------------------------------
+/**
+ * @brief Precomputed LORA bandwidth registers values
+ */
+static const BandwidthMap_t SX1278LoRaBandwidths[] =
+{
+ { 7800, 0 }, // 7.8 kHz requires TCXO
+ { 10400, 1 }, // 10.4 kHz requires TCXO
+ { 15600, 2 }, // 15.6 kHz requires TCXO
+ { 20800, 3 }, // 20.8 kHz requires TCXO
+ { 31250, 4 }, // 31.25 kHz requires TCXO
+ { 41700, 5 }, // 41.7 kHz requires TCXO
+ { 62500, 6 }, // 62.5 kHz requires TCXO
+ { 125000, 7 }, // 125 kHz the LoRa protocol default
+ { 250000, 8 }, // 250 kHz
+ { 500000, 9 }, // 500 kHz
+ { 600000, 10 },// Invalid Bandwidth, reserved
+ };
+
+//-----------------------------------------------------------------------------
+/**
+ * @brief Radio hardware registers initialization definition
+ */
+static const RadioRegisters_t SX1278RadioRegsInit[] =
+{ \
+ { MODEM_FSK , REG_LNA , 0x23 },\
+ { MODEM_FSK , REG_RXCONFIG , 0x1E },\
+ { MODEM_FSK , REG_RSSICONFIG , 0xD2 },\
+ { MODEM_FSK , REG_AFCFEI , 0x01 },\
+ { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },\
+ { MODEM_FSK , REG_OSC , 0x07 },\
+ { MODEM_FSK , REG_SYNCCONFIG , 0x12 },\
+ { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },\
+ { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },\
+ { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },\
+ { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },\
+ { MODEM_FSK , REG_FIFOTHRESH , 0x8F },\
+ { MODEM_FSK , REG_IMAGECAL , 0x02 },\
+ { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },\
+ { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },\
+ { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },\
+};
+
+
+/**
+ * ============================================================================
+ * @brief Private functions prototypes
+ * ============================================================================
+ */
+
+/**
+ * @brief Performs the Rx chain calibration for LF and HF bands
+ * @note Must be called just after the reset so all registers are at their
+ * default values
+ */
+static void RxChainCalibration(void);
+
+/**
+ * Returns the known FSK bandwidth registers value
+ *
+ * @param [IN] bandwidth Bandwidth value in Hz
+ * @retval regValue Bandwidth register value.
+ */
+static uint8_t GetFskBandwidthRegValue(uint32_t bandwidth);
+
+/**
+ * Returns the known LORA bandwidth registers value
+ *
+ * @param [IN] bandwidth Bandwidth value in Hz
+ * @retval regValue Bandwidth register value.
+ */
+static uint8_t GetLoRaBandwidthRegValue(uint32_t bandwidth);
+
+
+/**
+ * @brief DIO 0 IRQ callback
+ */
+static void OnDio0Irq();
+
+/**
+ * @brief DIO 1 IRQ callback
+ */
+static void OnDio1Irq();
+
+/**
+ * @brief DIO 2 IRQ callback
+ */
+static void OnDio2Irq();
+
+/**
+ * @brief DIO 3 IRQ callback
+ */
+static void OnDio3Irq();
+
+/**
+ * @brief DIO 4 IRQ callback
+ */
+static void OnDio4Irq();
+
+/**
+ * @brief DIO 5 IRQ callback
+ */
+static void OnDio5Irq();
+
+/**
+ * @brief Tx & Rx timeout timer callback
+ */
+static void OnTimeoutIrq();
+
+
+
+/**
+ * ============================================================================
+ * @brief Private global variables
+ * ============================================================================
+ */
+
+/**
+ * Radio callbacks variable
+ */
+static RadioEvents_t* RadioEvents;
+
+/**
+ * Reception buffer
+ */
+static uint8_t RxTxBuffer[RX_BUFFER_SIZE];
+
+/**
+ * Hardware DIO IRQ functions
+ */
+DioIrqHandler dioIrq[] = { OnDio0Irq, OnDio1Irq,
+ OnDio2Irq, OnDio3Irq,
+ OnDio4Irq, NULL };
+
+/**
+ * Radio settings
+ */
+RadioSettings_t settings;
+
+
+
+/**
+ * ============================================================================
+ * @brief Public functions definitions
+ * ============================================================================
+ */
+//-----------------------------------------------------------------------------
+bool SX1278Init(RadioEvents_t *events)
+{
+ RadioEvents = events;
+
+ if (SX1278Read(REG_VERSION) == 0x00)
+ {
+ return false;
+ }
+
+ SX1278Reset();
+ RxChainCalibration();
+ SX1278SetOpMode(RF_OPMODE_SLEEP);
+
+ SX1278IoIrqInit(dioIrq);
+ SX1278RadioRegistersInit();
+ SX1278SetModem(MODEM_FSK);
+ settings.State = RF_IDLE;
+ return true;
+}
+
+//-----------------------------------------------------------------------------
+void SX1278RadioRegistersInit()
+{
+ uint8_t i = 0;
+ for(i = 0; i < sizeof(SX1278RadioRegsInit) / sizeof(RadioRegisters_t); i++)
+ {
+ SX1278SetModem(SX1278RadioRegsInit[i].Modem);
+ SX1278Write(SX1278RadioRegsInit[i].Addr, SX1278RadioRegsInit[i].Value);
+ }
+}
+
+//-----------------------------------------------------------------------------
+RadioState_t SX1278GetStatus(void)
+{
+ return settings.State;
+}
+
+//-----------------------------------------------------------------------------
+void SX1278SetChannel(uint32_t freq)
+{
+ settings.Channel = freq;
+ freq = (uint32_t)((double)freq / (double)FREQ_STEP);
+ SX1278Write(REG_FRFMSB, (uint8_t)((freq >> 16) & 0xFF));
+ SX1278Write(REG_FRFMID, (uint8_t)((freq >> 8) & 0xFF));
+ SX1278Write(REG_FRFLSB, (uint8_t)(freq & 0xFF));
+}
+
+//-----------------------------------------------------------------------------
+bool SX1278IsChannelFree(RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarrierSenseTime)
+{
+ // TODO handle carrierSenseTime
+ int16_t rssi = 0;
+
+ SX1278SetModem(modem);
+
+ SX1278SetChannel(freq);
+
+ SX1278SetOpMode(RF_OPMODE_RECEIVER);
+
+ SX1278DelayMs(1);
+
+ rssi = SX1278GetRssi(modem);
+
+ SX1278SetSleep();
+ if (rssi > rssiThresh)
+ {
+ return false;
+ }
+ return true;
+}
+
+//-----------------------------------------------------------------------------
+uint32_t SX1278Random(void)
+{
+ uint8_t i;
+ uint32_t rnd = 0;
+
+ /*
+ * Radio setup for random number generation
+ */
+ // Set LoRa modem ON
+ SX1278SetModem(MODEM_LORA);
+
+ // Disable LoRa modem interrupts
+ SX1278Write(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED);
+
+ // Set radio in continuous reception
+ SX1278SetOpMode(RF_OPMODE_RECEIVER);
+
+ for(i = 0; i < 32; i++)
+ {
+ SX1278DelayMs(1);
+ // Unfiltered RSSI value SX1278Reading. Only takes the LSB value
+ rnd |= ((uint32_t)SX1278Read(REG_LR_RSSIWIDEBAND) & 0x01) << i;
+ }
+
+ SX1278SetSleep();
+
+ return rnd;
+}
+
+//-----------------------------------------------------------------------------
+void SX1278SetRxConfig(RadioModems_t modem, uint32_t bandwidth,
+ uint32_t datarate, uint8_t coderate,
+ uint32_t bandwidthAfc, uint16_t preambleLen,
+ uint16_t symbTimeout, bool fixLen,
+ uint8_t payloadLen,
+ bool crcOn, bool freqHopOn, uint8_t hopPeriod,
+ bool iqInverted, bool rxContinuous)
+{
+ SX1278SetModem(modem);
+
+ switch (modem)
+ {
+ case MODEM_FSK:
+ {
+ settings.Fsk.Bandwidth = bandwidth;
+ settings.Fsk.Datarate = datarate;
+ settings.Fsk.BandwidthAfc = bandwidthAfc;
+ settings.Fsk.FixLen = fixLen;
+ settings.Fsk.PayloadLen = payloadLen;
+ settings.Fsk.CrcOn = crcOn;
+ settings.Fsk.IqInverted = iqInverted;
+ settings.Fsk.RxContinuous = rxContinuous;
+ settings.Fsk.PreambleLen = preambleLen;
+ settings.Fsk.RxSingleTimeout = symbTimeout * ((1.0 / (double)datarate) * 8.0) * 1000;
+
+ datarate = (uint16_t)((double)XTAL_FREQ / (double)datarate);
+ SX1278Write(REG_BITRATEMSB, (uint8_t)(datarate >> 8));
+ SX1278Write(REG_BITRATELSB, (uint8_t)(datarate & 0xFF));
+
+ SX1278Write(REG_RXBW, GetFskBandwidthRegValue(bandwidth));
+ SX1278Write(REG_AFCBW, GetFskBandwidthRegValue(bandwidthAfc));
+
+ SX1278Write(REG_PREAMBLEMSB, (uint8_t)((preambleLen >> 8) & 0xFF));
+ SX1278Write(REG_PREAMBLELSB, (uint8_t)(preambleLen & 0xFF));
+
+ if (fixLen == 1)
+ {
+ SX1278Write(REG_PAYLOADLENGTH, payloadLen);
+ }
+ else
+ {
+ SX1278Write(REG_PAYLOADLENGTH, 0xFF); // Set payload length to the maximum
+ }
+
+ SX1278Write(REG_PACKETCONFIG1,
+ (SX1278Read(REG_PACKETCONFIG1) &
+ RF_PACKETCONFIG1_CRC_MASK &
+ RF_PACKETCONFIG1_PACKETFORMAT_MASK) |
+ ((fixLen == 1) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE) |
+ (crcOn << 4));
+ SX1278Write(REG_PACKETCONFIG2, (SX1278Read(REG_PACKETCONFIG2) | RF_PACKETCONFIG2_DATAMODE_PACKET));
+ }
+ break;
+ case MODEM_LORA:
+ {
+ if (bandwidth > 11) // specified in Hz, needs mapping
+ {
+ bandwidth = GetLoRaBandwidthRegValue(bandwidth);
+ }
+ if (bandwidth > LORA_BANDWIDTH_500kHz)
+ {
+ // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
+ while(1);
+ }
+ settings.LoRa.Bandwidth = bandwidth;
+ settings.LoRa.Datarate = datarate;
+ settings.LoRa.Coderate = coderate;
+ settings.LoRa.PreambleLen = preambleLen;
+ settings.LoRa.FixLen = fixLen;
+ settings.LoRa.PayloadLen = payloadLen;
+ settings.LoRa.CrcOn = crcOn;
+ settings.LoRa.FreqHopOn = freqHopOn;
+ settings.LoRa.HopPeriod = hopPeriod;
+ settings.LoRa.IqInverted = iqInverted;
+ settings.LoRa.RxContinuous = rxContinuous;
+
+ if (datarate > LORA_SF12)
+ {
+ datarate = LORA_SF12;
+ }
+ else if (datarate < LORA_SF6)
+ {
+ datarate = LORA_SF6;
+ }
+
+ if (((bandwidth == LORA_BANDWIDTH_125kHz) && ((datarate == LORA_SF11) || (datarate == LORA_SF12))) ||
+ ((bandwidth == LORA_BANDWIDTH_250kHz) && (datarate == LORA_SF12)))
+ {
+ settings.LoRa.LowDatarateOptimize = 0x01;
+ }
+ else
+ {
+ settings.LoRa.LowDatarateOptimize = 0x00;
+ }
+
+ SX1278Write(REG_LR_MODEMCONFIG1,
+ (SX1278Read(REG_LR_MODEMCONFIG1) &
+ RFLR_MODEMCONFIG1_BW_MASK &
+ RFLR_MODEMCONFIG1_CODINGRATE_MASK &
+ RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK) |
+ (bandwidth << 4) | (coderate << 1) |
+ fixLen);
+
+ SX1278Write(REG_LR_MODEMCONFIG2,
+ (SX1278Read(REG_LR_MODEMCONFIG2) &
+ RFLR_MODEMCONFIG2_SF_MASK &
+ RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
+ RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK) |
+ (datarate << 4) | (crcOn << 2) |
+ ((symbTimeout >> 8) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK));
+
+ SX1278Write(REG_LR_MODEMCONFIG3,
+ (SX1278Read(REG_LR_MODEMCONFIG3) &
+ RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK) |
+ (settings.LoRa.LowDatarateOptimize << 3));
+
+ SX1278Write(REG_LR_SYMBTIMEOUTLSB, (uint8_t)(symbTimeout & 0xFF));
+
+ SX1278Write(REG_LR_PREAMBLEMSB, (uint8_t)((preambleLen >> 8) & 0xFF));
+ SX1278Write(REG_LR_PREAMBLELSB, (uint8_t)(preambleLen & 0xFF));
+
+ if (fixLen == 1)
+ {
+ SX1278Write(REG_LR_PAYLOADLENGTH, payloadLen);
+ }
+
+ if (settings.LoRa.FreqHopOn == true)
+ {
+ SX1278Write(REG_LR_PLLHOP, (SX1278Read(REG_LR_PLLHOP) & RFLR_PLLHOP_FASTHOP_MASK) | RFLR_PLLHOP_FASTHOP_ON);
+ SX1278Write(REG_LR_HOPPERIOD, settings.LoRa.HopPeriod);
+ }
+
+ if ((bandwidth == LORA_BANDWIDTH_500kHz) && (settings.Channel > RF_MID_BAND_THRESH))
+ {
+ // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
+ SX1278Write(REG_LR_HIGHBWOPTIMIZE1, 0x02);
+ SX1278Write(REG_LR_HIGHBWOPTIMIZE2, 0x64);
+ }
+ else if (bandwidth == LORA_BANDWIDTH_500kHz)
+ {
+ // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
+ SX1278Write(REG_LR_HIGHBWOPTIMIZE1, 0x02);
+ SX1278Write(REG_LR_HIGHBWOPTIMIZE2, 0x7F);
+ }
+ else
+ {
+ // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
+ SX1278Write(REG_LR_HIGHBWOPTIMIZE1, 0x03);
+ }
+
+ if (datarate == LORA_SF6)
+ {
+ SX1278Write(REG_LR_DETECTOPTIMIZE,
+ (SX1278Read(REG_LR_DETECTOPTIMIZE) &
+ RFLR_DETECTIONOPTIMIZE_MASK) |
+ RFLR_DETECTIONOPTIMIZE_SF6);
+ SX1278Write(REG_LR_DETECTIONTHRESHOLD,
+ RFLR_DETECTIONTHRESH_SF6);
+ }
+ else
+ {
+ SX1278Write(REG_LR_DETECTOPTIMIZE,
+ (SX1278Read(REG_LR_DETECTOPTIMIZE) &
+ RFLR_DETECTIONOPTIMIZE_MASK) |
+ RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12);
+ SX1278Write(REG_LR_DETECTIONTHRESHOLD,
+ RFLR_DETECTIONTHRESH_SF7_TO_SF12);
+ }
+ }
+ break;
+ }
+}
+
+//-----------------------------------------------------------------------------
+void SX1278SetTxConfig(RadioModems_t modem, int8_t power, uint32_t fdev,
+ uint32_t bandwidth, uint32_t datarate,
+ uint8_t coderate, uint16_t preambleLen,
+ bool fixLen, bool crcOn, bool freqHopOn,
+ uint8_t hopPeriod, bool iqInverted, uint32_t timeout)
+{
+ SX1278SetModem(modem);
+ SX1278SetRfTxPower(power);
+
+ switch (modem)
+ {
+ case MODEM_FSK:
+ {
+ settings.Fsk.Power = power;
+ settings.Fsk.Fdev = fdev;
+ settings.Fsk.Bandwidth = bandwidth;
+ settings.Fsk.Datarate = datarate;
+ settings.Fsk.PreambleLen = preambleLen;
+ settings.Fsk.FixLen = fixLen;
+ settings.Fsk.CrcOn = crcOn;
+ settings.Fsk.IqInverted = iqInverted;
+ settings.Fsk.TxTimeout = timeout;
+
+ fdev = (uint16_t)((double)fdev / (double)FREQ_STEP);
+ SX1278Write(REG_FDEVMSB, (uint8_t)(fdev >> 8));
+ SX1278Write(REG_FDEVLSB, (uint8_t)(fdev & 0xFF));
+
+ datarate = (uint16_t)((double)XTAL_FREQ / (double)datarate);
+ SX1278Write(REG_BITRATEMSB, (uint8_t)(datarate >> 8));
+ SX1278Write(REG_BITRATELSB, (uint8_t)(datarate & 0xFF));
+
+ SX1278Write(REG_PREAMBLEMSB, (preambleLen >> 8) & 0x00FF);
+ SX1278Write(REG_PREAMBLELSB, preambleLen & 0xFF);
+
+ SX1278Write(REG_PACKETCONFIG1,
+ (SX1278Read(REG_PACKETCONFIG1) &
+ RF_PACKETCONFIG1_CRC_MASK &
+ RF_PACKETCONFIG1_PACKETFORMAT_MASK) |
+ ((fixLen == 1) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE) |
+ (crcOn << 4));
+ SX1278Write(REG_PACKETCONFIG2, (SX1278Read(REG_PACKETCONFIG2) | RF_PACKETCONFIG2_DATAMODE_PACKET));
+ }
+ break;
+ case MODEM_LORA:
+ {
+ settings.LoRa.Power = power;
+ if (bandwidth > LORA_BANDWIDTH_500kHz)
+ {
+ // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
+ while(1);
+ }
+
+ settings.LoRa.Bandwidth = bandwidth;
+ settings.LoRa.Datarate = datarate;
+ settings.LoRa.Coderate = coderate;
+ settings.LoRa.PreambleLen = preambleLen;
+ settings.LoRa.FixLen = fixLen;
+ settings.LoRa.FreqHopOn = freqHopOn;
+ settings.LoRa.HopPeriod = hopPeriod;
+ settings.LoRa.CrcOn = crcOn;
+ settings.LoRa.IqInverted = iqInverted;
+ settings.LoRa.TxTimeout = timeout;
+
+ if (datarate > LORA_SF12)
+ {
+ datarate = LORA_SF12;
+ }
+ else if (datarate < LORA_SF6)
+ {
+ datarate = LORA_SF6;
+ }
+ if (((bandwidth == LORA_BANDWIDTH_125kHz) && ((datarate == LORA_SF11) || (datarate == LORA_SF12))) ||
+ ((bandwidth == LORA_BANDWIDTH_250kHz) && (datarate == LORA_SF12)))
+ {
+ settings.LoRa.LowDatarateOptimize = 0x01;
+ }
+ else
+ {
+ settings.LoRa.LowDatarateOptimize = 0x00;
+ }
+
+ if (settings.LoRa.FreqHopOn == true)
+ {
+ SX1278Write(REG_LR_PLLHOP, (SX1278Read(REG_LR_PLLHOP) & RFLR_PLLHOP_FASTHOP_MASK) | RFLR_PLLHOP_FASTHOP_ON);
+ SX1278Write(REG_LR_HOPPERIOD, settings.LoRa.HopPeriod);
+ }
+
+ SX1278Write(REG_LR_MODEMCONFIG1,
+ (SX1278Read(REG_LR_MODEMCONFIG1) &
+ RFLR_MODEMCONFIG1_BW_MASK &
+ RFLR_MODEMCONFIG1_CODINGRATE_MASK &
+ RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK) |
+ (bandwidth << 4) | (coderate << 1) |
+ fixLen);
+
+ SX1278Write(REG_LR_MODEMCONFIG2,
+ (SX1278Read(REG_LR_MODEMCONFIG2) &
+ RFLR_MODEMCONFIG2_SF_MASK &
+ RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK) |
+ (datarate << 4) | (crcOn << 2));
+
+ SX1278Write(REG_LR_MODEMCONFIG3,
+ (SX1278Read(REG_LR_MODEMCONFIG3) &
+ RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK) |
+ (settings.LoRa.LowDatarateOptimize << 3));
+
+ SX1278Write(REG_LR_PREAMBLEMSB, (preambleLen >> 8) & 0x00FF);
+ SX1278Write(REG_LR_PREAMBLELSB, preambleLen & 0xFF);
+
+ if (datarate == LORA_SF6)
+ {
+ SX1278Write(REG_LR_DETECTOPTIMIZE,
+ (SX1278Read(REG_LR_DETECTOPTIMIZE) &
+ RFLR_DETECTIONOPTIMIZE_MASK) |
+ RFLR_DETECTIONOPTIMIZE_SF6);
+ SX1278Write(REG_LR_DETECTIONTHRESHOLD,
+ RFLR_DETECTIONTHRESH_SF6);
+ }
+ else
+ {
+ SX1278Write(REG_LR_DETECTOPTIMIZE,
+ (SX1278Read(REG_LR_DETECTOPTIMIZE) &
+ RFLR_DETECTIONOPTIMIZE_MASK) |
+ RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12);
+ SX1278Write(REG_LR_DETECTIONTHRESHOLD,
+ RFLR_DETECTIONTHRESH_SF7_TO_SF12);
+ }
+ }
+ break;
+ }
+}
+
+//-----------------------------------------------------------------------------
+uint32_t SX1278TimeOnAir(RadioModems_t modem, uint8_t pktLen)
+{
+ uint32_t airTime = 0;
+
+ switch (modem)
+ {
+ case MODEM_FSK:
+ {
+ airTime = rint((8 * (settings.Fsk.PreambleLen +
+ ((SX1278Read(REG_SYNCCONFIG) & ~RF_SYNCCONFIG_SYNCSIZE_MASK) + 1) +
+ ((settings.Fsk.FixLen == 0x01) ? 0.0 : 1.0) +
+ (((SX1278Read(REG_PACKETCONFIG1) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK) != 0x00) ? 1.0 : 0) +
+ pktLen +
+ ((settings.Fsk.CrcOn == 0x01) ? 2.0 : 0)) /
+ settings.Fsk.Datarate) * 1000);
+ }
+ break;
+ case MODEM_LORA:
+ {
+ double bw = 0.0;
+ // NOTE: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
+ switch (settings.LoRa.Bandwidth)
+ {
+ case LORA_BANDWIDTH_7kHz: // 7.8 kHz
+ bw = 78e2;
+ break;
+ case LORA_BANDWIDTH_10kHz: // 10.4 kHz
+ bw = 104e2;
+ break;
+ case LORA_BANDWIDTH_15kHz: // 15.6 kHz
+ bw = 156e2;
+ break;
+ case LORA_BANDWIDTH_20kHz: // 20.8 kHz
+ bw = 208e2;
+ break;
+ case LORA_BANDWIDTH_31kHz: // 31.25 kHz
+ bw = 312e2;
+ break;
+ case LORA_BANDWIDTH_41kHz: // 41.7 kHz
+ bw = 414e2;
+ break;
+ case LORA_BANDWIDTH_62kHz: // 62.5 kHz
+ bw = 625e2;
+ break;
+ case LORA_BANDWIDTH_125kHz: // 125 kHz
+ bw = 125e3;
+ break;
+ case LORA_BANDWIDTH_250kHz: // 250 kHz
+ bw = 250e3;
+ break;
+ case LORA_BANDWIDTH_500kHz: // 500 kHz
+ bw = 500e3;
+ break;
+ }
+
+ // Symbol rate : time for one symbol (secs)
+ double rs = bw / (1 << settings.LoRa.Datarate);
+ double ts = 1 / rs;
+ // time of preamble
+ double tPreamble = (settings.LoRa.PreambleLen + 4.25) * ts;
+ // Symbol length of payload and time
+ double tmp = ceil((8 * pktLen - 4 * settings.LoRa.Datarate +
+ 28 + 16 * settings.LoRa.CrcOn -
+ (settings.LoRa.FixLen ? 20 : 0)) /
+ (double)(4 * (settings.LoRa.Datarate -
+ ((settings.LoRa.LowDatarateOptimize > 0) ? 2 : 0)))) *
+ (settings.LoRa.Coderate + 4);
+ double nPayload = 8 + ((tmp > 0) ? tmp : 0);
+ double tPayload = nPayload * ts;
+ // Time on air
+ double tOnAir = tPreamble + tPayload;
+ // return ms secs
+ airTime = floor(tOnAir * 1000 + 0.999);
+ }
+ break;
+ }
+ return airTime;
+}
+
+//-----------------------------------------------------------------------------
+void SX1278Send(uint8_t *buffer, uint8_t size)
+{
+ uint32_t txTimeout = 0;
+
+ switch (settings.Modem)
+ {
+ case MODEM_FSK:
+ {
+ settings.FskPacketHandler.NbBytes = 0;
+ settings.FskPacketHandler.Size = size;
+
+ if (settings.Fsk.FixLen == false)
+ {
+ SX1278WriteFifo((uint8_t*)&size, 1);
+ }
+ else
+ {
+ SX1278Write(REG_PAYLOADLENGTH, size);
+ }
+
+ if ((size > 0) && (size <= 64))
+ {
+ settings.FskPacketHandler.ChunkSize = size;
+ }
+ else
+ {
+ memcpy(RxTxBuffer, buffer, size);
+ settings.FskPacketHandler.ChunkSize = 32;
+ }
+
+ // Write payload buffer
+ SX1278WriteFifo(buffer, settings.FskPacketHandler.ChunkSize);
+ settings.FskPacketHandler.NbBytes += settings.FskPacketHandler.ChunkSize;
+ txTimeout = settings.Fsk.TxTimeout;
+ }
+ break;
+ case MODEM_LORA:
+ {
+ if (settings.LoRa.IqInverted == true)
+ {
+ SX1278Write(REG_LR_INVERTIQ, ((SX1278Read(REG_LR_INVERTIQ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON));
+ SX1278Write(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON);
+ }
+ else
+ {
+ SX1278Write(REG_LR_INVERTIQ, ((SX1278Read(REG_LR_INVERTIQ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF));
+ SX1278Write(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF);
+ }
+
+ settings.LoRaPacketHandler.Size = size;
+
+ // Initializes the payload size
+ SX1278Write(REG_LR_PAYLOADLENGTH, size);
+
+ // Full buffer used for Tx
+ SX1278Write(REG_LR_FIFOTXBASEADDR, 0);
+ SX1278Write(REG_LR_FIFOADDRPTR, 0);
+
+ // FIFO operations can not take place in SX1278SetSleep mode
+ if ((SX1278Read(REG_OPMODE) & ~RF_OPMODE_MASK) == RF_OPMODE_SLEEP)
+ {
+ SX1278SetStandby();
+ SX1278DelayMs(1);
+ }
+ // SX1278Write payload buffer
+ SX1278WriteFifo(buffer, size);
+ txTimeout = settings.LoRa.TxTimeout;
+ }
+ break;
+ }
+
+ SX1278SetTx(txTimeout);
+}
+
+//-----------------------------------------------------------------------------
+void SX1278SetSleep(void)
+{
+ SX1278SetTimeout(TXTimeoutTimer, NULL, 0);
+ SX1278SetTimeout(RXTimeoutTimer, NULL, 0);
+
+ SX1278SetOpMode(RF_OPMODE_SLEEP);
+ //TODO Disable TCXO radio is in SLEEP mode if available
+ settings.State = RF_IDLE;
+}
+
+//-----------------------------------------------------------------------------
+void SX1278SetStandby(void)
+{
+ SX1278SetTimeout(TXTimeoutTimer, NULL, 0);
+ SX1278SetTimeout(RXTimeoutTimer, NULL, 0);
+ SX1278SetTimeout(RXTimeoutSyncWordTimer, NULL, 0);
+
+ SX1278SetOpMode(RF_OPMODE_STANDBY);
+ settings.State = RF_IDLE;
+}
+
+//-----------------------------------------------------------------------------
+void SX1278SetRx(uint32_t timeout)
+{
+ bool rxContinuous = false;
+
+ switch (settings.Modem)
+ {
+ case MODEM_FSK:
+ {
+ rxContinuous = settings.Fsk.RxContinuous;
+
+ // DIO0=PayloadSX1278Ready
+ // DIO1=FifoLevel
+ // DIO2=SyncAddr
+ // DIO3=FifoEmpty
+ // DIO4=Preamble
+ // DIO5=ModeSX1278Ready
+ SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1) & RF_DIOMAPPING1_DIO0_MASK &
+ RF_DIOMAPPING1_DIO1_MASK &
+ RF_DIOMAPPING1_DIO2_MASK) |
+ RF_DIOMAPPING1_DIO0_00 |
+ RF_DIOMAPPING1_DIO1_00 |
+ RF_DIOMAPPING1_DIO2_11);
+
+ SX1278Write(REG_DIOMAPPING2, (SX1278Read(REG_DIOMAPPING2) & RF_DIOMAPPING2_DIO4_MASK &
+ RF_DIOMAPPING2_MAP_MASK) |
+ RF_DIOMAPPING2_DIO4_11 |
+ RF_DIOMAPPING2_MAP_PREAMBLEDETECT);
+
+ settings.FskPacketHandler.FifoThresh = SX1278Read(REG_FIFOTHRESH) & 0x3F;
+
+ SX1278Write(REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT);
+
+ settings.FskPacketHandler.PreambleDetected = false;
+ settings.FskPacketHandler.SyncWordDetected = false;
+ settings.FskPacketHandler.NbBytes = 0;
+ settings.FskPacketHandler.Size = 0;
+ }
+ break;
+ case MODEM_LORA:
+ {
+ if (settings.LoRa.IqInverted == true)
+ {
+ SX1278Write(REG_LR_INVERTIQ, ((SX1278Read(REG_LR_INVERTIQ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF));
+ SX1278Write(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON);
+ }
+ else
+ {
+ SX1278Write(REG_LR_INVERTIQ, ((SX1278Read(REG_LR_INVERTIQ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF));
+ SX1278Write(REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF);
+ }
+
+ // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
+ if (settings.LoRa.Bandwidth < LORA_BANDWIDTH_500kHz)
+ {
+ SX1278Write(REG_LR_DETECTOPTIMIZE, SX1278Read(REG_LR_DETECTOPTIMIZE) & 0x7F);
+ SX1278Write(REG_LR_IFFREQ2, 0x00);
+ switch (settings.LoRa.Bandwidth)
+ {
+ case LORA_BANDWIDTH_7kHz: // 7.8 kHz
+ SX1278Write(REG_LR_IFFREQ1, 0x48 );
+ SX1278SetChannel(settings.Channel + 7810);
+ break;
+ case LORA_BANDWIDTH_10kHz: // 10.4 kHz
+ SX1278Write(REG_LR_IFFREQ1, 0x44 );
+ SX1278SetChannel(settings.Channel + 10420);
+ break;
+ case LORA_BANDWIDTH_15kHz: // 15.6 kHz
+ SX1278Write(REG_LR_IFFREQ1, 0x44 );
+ SX1278SetChannel(settings.Channel + 15620);
+ break;
+ case LORA_BANDWIDTH_20kHz: // 20.8 kHz
+ SX1278Write(REG_LR_IFFREQ1, 0x44 );
+ SX1278SetChannel(settings.Channel + 20830);
+ break;
+ case LORA_BANDWIDTH_31kHz: // 31.25 kHz
+ SX1278Write(REG_LR_IFFREQ1, 0x44 );
+ SX1278SetChannel(settings.Channel + 31250);
+ break;
+ case LORA_BANDWIDTH_41kHz: // 41.4 kHz
+ SX1278Write(REG_LR_IFFREQ1, 0x44 );
+ SX1278SetChannel(settings.Channel + 41670);
+ break;
+ case LORA_BANDWIDTH_62kHz: // 62.5 kHz
+ SX1278Write(REG_LR_IFFREQ1, 0x40 );
+ break;
+ case LORA_BANDWIDTH_125kHz: // 125 kHz
+ SX1278Write(REG_LR_IFFREQ1, 0x40 );
+ break;
+ case LORA_BANDWIDTH_250kHz: // 250 kHz
+ SX1278Write(REG_LR_IFFREQ1, 0x40 );
+ break;
+ }
+ }
+ else
+ {
+ SX1278Write(REG_LR_DETECTOPTIMIZE, SX1278Read(REG_LR_DETECTOPTIMIZE) | 0x80);
+ }
+
+ rxContinuous = settings.LoRa.RxContinuous;
+
+ if (settings.LoRa.FreqHopOn == true)
+ {
+ SX1278Write(REG_LR_IRQFLAGSMASK,//RFLR_IRQFLAGS_RXTIMEOUT |
+ //RFLR_IRQFLAGS_RXDONE |
+ //RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_CADDONE |
+ //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED);
+
+ // DIO0=RxDone, DIO2=FhssChangeChannel
+ SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00);
+ }
+ else
+ {
+ SX1278Write(REG_LR_IRQFLAGSMASK,//RFLR_IRQFLAGS_RXTIMEOUT |
+ //RFLR_IRQFLAGS_RXDONE |
+ //RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED);
+
+ // DIO0=RxDone
+ SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1) & RFLR_DIOMAPPING1_DIO0_MASK) | RFLR_DIOMAPPING1_DIO0_00);
+ }
+ SX1278Write(REG_LR_FIFORXBASEADDR, 0);
+ SX1278Write(REG_LR_FIFOADDRPTR, 0);
+ }
+ break;
+ }
+
+ memset(RxTxBuffer, 0, (size_t)RX_BUFFER_SIZE);
+
+ settings.State = RF_RX_RUNNING;
+ if (timeout != 0)
+ {
+ SX1278SetTimeout(RXTimeoutTimer, &OnTimeoutIrq, timeout);
+ }
+
+ if (settings.Modem == MODEM_FSK)
+ {
+ SX1278SetOpMode(RF_OPMODE_RECEIVER);
+
+ if (rxContinuous == false)
+ {
+ SX1278SetTimeout(RXTimeoutSyncWordTimer, &OnTimeoutIrq, settings.Fsk.RxSingleTimeout);
+ }
+ }
+ else // MODEM_LORA
+ {
+ if (rxContinuous == true)
+ {
+ SX1278SetOpMode(RFLR_OPMODE_RECEIVER);
+ }
+ else
+ {
+ SX1278SetOpMode(RFLR_OPMODE_RECEIVER_SINGLE);
+ }
+ }
+}
+
+//-----------------------------------------------------------------------------
+void SX1278SetTx(uint32_t timeout)
+{
+
+ switch (settings.Modem)
+ {
+ case MODEM_FSK:
+ {
+ // DIO0=PacketSent
+ // DIO1=FifoEmpty
+ // DIO2=FifoFull
+ // DIO3=FifoEmpty
+ // DIO4=LowBat
+ // DIO5=ModeSX1278Ready
+ SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1) & RF_DIOMAPPING1_DIO0_MASK &
+ RF_DIOMAPPING1_DIO1_MASK &
+ RF_DIOMAPPING1_DIO2_MASK) |
+ RF_DIOMAPPING1_DIO1_01);
+
+ SX1278Write(REG_DIOMAPPING2, (SX1278Read(REG_DIOMAPPING2) & RF_DIOMAPPING2_DIO4_MASK &
+ RF_DIOMAPPING2_MAP_MASK));
+ settings.FskPacketHandler.FifoThresh = SX1278Read(REG_FIFOTHRESH) & 0x3F;
+ }
+ break;
+ case MODEM_LORA:
+ {
+ if (settings.LoRa.FreqHopOn == true)
+ {
+ SX1278Write(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ //RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_CADDONE |
+ //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED);
+
+ // DIO0=TxDone, DIO2=FhssChangeChannel
+ SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00);
+ }
+ else
+ {
+ SX1278Write(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ //RFLR_IRQFLAGS_TXDONE |
+ RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+ RFLR_IRQFLAGS_CADDETECTED);
+
+ // DIO0=TxDone
+ SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1) & RFLR_DIOMAPPING1_DIO0_MASK) | RFLR_DIOMAPPING1_DIO0_01);
+ }
+ }
+ break;
+ }
+
+ settings.State = RF_TX_RUNNING;
+ SX1278SetTimeout(TXTimeoutTimer, &OnTimeoutIrq, timeout);
+ SX1278SetOpMode(RF_OPMODE_TRANSMITTER);
+}
+
+//-----------------------------------------------------------------------------
+void SX1278StartCad(void)
+{
+ switch (settings.Modem)
+ {
+ case MODEM_FSK:
+ {
+
+ }
+ break;
+ case MODEM_LORA:
+ {
+ SX1278Write(REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
+ RFLR_IRQFLAGS_RXDONE |
+ RFLR_IRQFLAGS_PAYLOADCRCERROR |
+ RFLR_IRQFLAGS_VALIDHEADER |
+ RFLR_IRQFLAGS_TXDONE |
+ //RFLR_IRQFLAGS_CADDONE |
+ RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
+ //RFLR_IRQFLAGS_CADDETECTED
+ );
+
+ if (dioIrq[3])
+ {
+ // DIO3=CADDone
+ SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 );
+ }
+ else
+ {
+ // DIO0=CADDone
+ SX1278Write(REG_DIOMAPPING1, (SX1278Read(REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_10 );
+ }
+
+ settings.State = RF_CAD;
+ SX1278SetOpMode(RFLR_OPMODE_CAD);
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+//-----------------------------------------------------------------------------
+void SX1278SetTxContinuousWave(uint32_t freq, int8_t power, uint16_t time)
+{
+ uint32_t timeout = (uint32_t)(time);
+
+ SX1278SetChannel(freq);
+
+ SX1278SetTxConfig(MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout);
+
+ SX1278Write(REG_PACKETCONFIG2, (SX1278Read(REG_PACKETCONFIG2) & RF_PACKETCONFIG2_DATAMODE_MASK));
+ // Disable radio interrupts
+ SX1278Write(REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11);
+ SX1278Write(REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10);
+
+ settings.State = RF_TX_RUNNING;
+ SX1278SetTimeout(TXTimeoutTimer, &OnTimeoutIrq, timeout);
+ SX1278SetOpMode(RF_OPMODE_TRANSMITTER);
+}
+
+//-----------------------------------------------------------------------------
+int16_t SX1278GetRssi(RadioModems_t modem)
+{
+ int16_t rssi = 0;
+
+ switch (modem)
+ {
+ case MODEM_FSK:
+ rssi = -(SX1278Read(REG_RSSIVALUE) >> 1);
+ break;
+ case MODEM_LORA:
+ if (settings.Channel > RF_MID_BAND_THRESH)
+ {
+ rssi = RSSI_OFFSET_HF + SX1278Read(REG_LR_RSSIVALUE);
+ }
+ else
+ {
+ rssi = RSSI_OFFSET_LF + SX1278Read(REG_LR_RSSIVALUE);
+ }
+ break;
+ default:
+ rssi = -1;
+ break;
+ }
+ return rssi;
+}
+
+//-----------------------------------------------------------------------------
+int32_t SX1278GetFrequencyError(RadioModems_t modem )
+{
+ int32_t val = 0;
+
+ if (modem != MODEM_LORA)
+ return 0;
+
+ val = (SX1278Read(REG_LR_FEIMSB) & 0b1111) << 16; // high word, 4 valid bits only
+ val |= ((SX1278Read(REG_LR_FEIMID) << 8) | SX1278Read(REG_LR_FEILSB)); // high byte, low byte
+ if (val & 0x80000) //convert sign bit
+ val |= 0xfff00000;
+
+ int32_t bandwidth = 0;
+ for (int i = 0; i < (int)(sizeof(SX1278LoRaBandwidths) / sizeof(BandwidthMap_t)) -1; i++ ) {
+ if (SX1278LoRaBandwidths[i].RegValue == settings.LoRa.Bandwidth) {
+ bandwidth = SX1278LoRaBandwidths[i].bandwidth;
+ break;
+ }
+ }
+ if (!bandwidth)
+ return 0;
+
+ float bandWidthkHz = (float)bandwidth/1000;
+
+ int32_t hz = (((float)val * (float)(1<<24)) / ((float)XTAL_FREQ)) * (bandWidthkHz / 500.0);
+
+ return hz;
+}
+
+//-----------------------------------------------------------------------------
+void SX1278SetOpMode(uint8_t opMode)
+{
+ // if(opMode == RF_OPMODE_SLEEP ) // TODO NOT USED on RA-01
+ // {
+ // SX1278SetAntSwLowPower( true );
+ // }
+ // else
+ // {
+ // // Enable TCXO if operating mode different from SLEEP.
+ // SX1278SetBoardTcxo( true );
+ // SX1278SetAntSwLowPower( false );
+ // SX1278SetAntSw( opMode );
+ // }
+ SX1278Write(REG_OPMODE, (SX1278Read(REG_OPMODE) & RF_OPMODE_MASK) | opMode);
+}
+
+//-----------------------------------------------------------------------------
+void SX1278SetModem(RadioModems_t modem)
+{
+ if ((SX1278Read(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_ON) != 0)
+ {
+ settings.Modem = MODEM_LORA;
+ }
+ else
+ {
+ settings.Modem = MODEM_FSK;
+ }
+
+ if (settings.Modem == modem)
+ {
+ return;
+ }
+
+ settings.Modem = modem;
+ switch (settings.Modem)
+ {
+ default:
+ case MODEM_FSK:
+ SX1278SetSleep();
+ SX1278Write(REG_OPMODE, (SX1278Read(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK) | RFLR_OPMODE_LONGRANGEMODE_OFF);
+
+ SX1278Write(REG_DIOMAPPING1, 0x00);
+ SX1278Write(REG_DIOMAPPING2, 0x30); // DIO5=ModeSX1278Ready
+ break;
+ case MODEM_LORA:
+ SX1278SetSleep();
+ SX1278Write(REG_OPMODE, (SX1278Read(REG_OPMODE) & RFLR_OPMODE_LONGRANGEMODE_MASK) | RFLR_OPMODE_LONGRANGEMODE_ON);
+
+ SX1278Write(REG_DIOMAPPING1, 0x00);
+ SX1278Write(REG_DIOMAPPING2, 0x00);
+ break;
+ }
+}
+
+//-----------------------------------------------------------------------------
+void SX1278SetMaxPayloadLength(RadioModems_t modem, uint8_t max)
+{
+ SX1278SetModem(modem);
+
+ switch (modem)
+ {
+ case MODEM_FSK:
+ if (settings.Fsk.FixLen == false)
+ {
+ SX1278Write(REG_PAYLOADLENGTH, max);
+ }
+ break;
+ case MODEM_LORA:
+ SX1278Write(REG_LR_PAYLOADMAXLENGTH, max);
+ break;
+ }
+}
+
+//-----------------------------------------------------------------------------
+void SX1278SetPublicNetwork(bool enable)
+{
+ SX1278SetModem(MODEM_LORA);
+ settings.LoRa.PublicNetwork = enable;
+ if (enable == true)
+ {
+ // Change LoRa modem SyncWord
+ SX1278Write(REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD);
+ }
+ else
+ {
+ // Change LoRa modem SyncWord
+ SX1278Write(REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD);
+ }
+}
+
+//-----------------------------------------------------------------------------
+void OnTimeoutIrq()
+{
+ switch (settings.State)
+ {
+ case RF_RX_RUNNING:
+ if (settings.Modem == MODEM_FSK)
+ {
+ settings.FskPacketHandler.PreambleDetected = false;
+ settings.FskPacketHandler.SyncWordDetected = false;
+ settings.FskPacketHandler.NbBytes = 0;
+ settings.FskPacketHandler.Size = 0;
+
+ // Clear Irqs
+ SX1278Write(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
+ RF_IRQFLAGS1_PREAMBLEDETECT |
+ RF_IRQFLAGS1_SYNCADDRESSMATCH);
+ SX1278Write(REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN);
+
+ if (settings.Fsk.RxContinuous == true)
+ {
+ // Continuous mode restart Rx chain
+ SX1278Write(REG_RXCONFIG, SX1278Read(REG_RXCONFIG) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK);
+ SX1278SetTimeout(RXTimeoutSyncWordTimer, &OnTimeoutIrq, settings.Fsk.RxSingleTimeout);
+ }
+ else
+ {
+ settings.State = RF_IDLE;
+ SX1278SetTimeout(RXTimeoutSyncWordTimer, NULL, 0);
+ }
+ }
+ if ((RadioEvents != NULL) && (RadioEvents->RxTimeout != NULL))
+ {
+ RadioEvents->RxTimeout();
+ }
+ break;
+ case RF_TX_RUNNING:
+ // Tx timeout shouldn't happen.
+ // But it has been observed that when it happens it is a result of a corrupted SPI transfer
+ // it depends on the platform design.
+ //
+ // The workaround is to put the radio in a known state. Thus, we re-initialize it.
+
+ // BEGIN WORKAROUND
+
+ // Reset the radio
+ SX1278Reset();
+
+ // Calibrate Rx chain
+ RxChainCalibration();
+
+ // Initialize radio default values
+ SX1278SetOpMode(RF_OPMODE_SLEEP);
+ SX1278RadioRegistersInit();
+
+ SX1278SetModem(MODEM_FSK);
+
+ // Restore previous network type setting.
+ SX1278SetPublicNetwork(settings.LoRa.PublicNetwork);
+ // END WORKAROUND
+
+ settings.State = RF_IDLE;
+ if ((RadioEvents != NULL) && (RadioEvents->TxTimeout != NULL))
+ {
+ RadioEvents->TxTimeout();
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+//-----------------------------------------------------------------------------
+void SX1278SetRfTxPower(int8_t power)
+{
+ uint8_t paConfig = 0;
+ uint8_t paDac = 0;
+
+ paConfig = SX1278Read(REG_PACONFIG);
+ paDac = SX1278Read(REG_PADAC);
+
+ paConfig = (paConfig & RF_PACONFIG_PASELECT_MASK) | SX1278GetPaSelect(settings.Channel);
+ paConfig = (paConfig & RF_PACONFIG_MAX_POWER_MASK) | 0x70;
+
+ if((paConfig & RF_PACONFIG_PASELECT_PABOOST) == RF_PACONFIG_PASELECT_PABOOST)
+ {
+ if(power > 17)
+ {
+ paDac = (paDac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_ON;
+ }
+ else
+ {
+ paDac = (paDac & RF_PADAC_20DBM_MASK) | RF_PADAC_20DBM_OFF;
+ }
+ if((paDac & RF_PADAC_20DBM_ON) == RF_PADAC_20DBM_ON)
+ {
+ if(power < 5)
+ {
+ power = 5;
+ }
+ if(power > 20)
+ {
+ power = 20;
+ }
+ paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK) | (uint8_t)((uint16_t)(power - 5) & 0x0F);
+ }
+ else
+ {
+ if(power < 2)
+ {
+ power = 2;
+ }
+ if(power > 17)
+ {
+ power = 17;
+ }
+ paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK) | (uint8_t)((uint16_t)(power - 2) & 0x0F);
+ }
+ }
+ else
+ {
+ if(power < -1)
+ {
+ power = -1;
+ }
+ if(power > 14)
+ {
+ power = 14;
+ }
+ paConfig = (paConfig & RF_PACONFIG_OUTPUTPOWER_MASK) | (uint8_t)((uint16_t)(power + 1) & 0x0F);
+ }
+ SX1278Write(REG_PACONFIG, paConfig);
+ SX1278Write(REG_PADAC, paDac);
+}
+
+//-----------------------------------------------------------------------------
+uint8_t SX1278GetPaSelect(uint32_t channel)
+{
+ if(channel > RF_MID_BAND_THRESH)
+ {
+ return RF_PACONFIG_PASELECT_PABOOST;
+ }
+ else
+ {
+ return RF_PACONFIG_PASELECT_RFO;
+ }
+}
+
+//-----------------------------------------------------------------------------
+bool SX1278CheckRfFrequency(uint32_t frequency)
+{
+ // Implement check. Currently all frequencies are supported
+ return true;
+}
+
+//-----------------------------------------------------------------------------
+void SX1278Write(uint8_t addr, uint8_t data)
+{
+ SX1278WriteBuffer(addr, &data, 1);
+}
+
+//-----------------------------------------------------------------------------
+uint8_t SX1278Read(uint8_t addr)
+{
+ uint8_t data;
+ SX1278ReadBuffer(addr, &data, 1);
+ return data;
+}
+
+//-----------------------------------------------------------------------------
+void SX1278WriteFifo(uint8_t *buffer, uint8_t size)
+{
+ SX1278WriteBuffer(0, buffer, size);
+}
+
+//-----------------------------------------------------------------------------
+void SX1278ReadFifo(uint8_t *buffer, uint8_t size)
+{
+ SX1278ReadBuffer(0, buffer, size);
+}
+
+
+//-----------------------------------------------------------------------------
+
+
+
+/**
+ * ============================================================================
+ * @brief Private functions definitions
+ * ============================================================================
+ */
+//-----------------------------------------------------------------------------
+void RxChainCalibration(void)
+{
+ uint8_t regPaConfigInitVal;
+ uint32_t initialFreq;
+
+ // Save context
+ regPaConfigInitVal = SX1278Read(REG_PACONFIG);
+ initialFreq = (double)(((uint32_t)SX1278Read(REG_FRFMSB) << 16) |
+ ((uint32_t)SX1278Read(REG_FRFMID) << 8) |
+ ((uint32_t)SX1278Read(REG_FRFLSB))) * (double)FREQ_STEP;
+
+ // Cut the PA just in case, RFO output, power = -1 dBm
+ SX1278Write(REG_PACONFIG, 0x00);
+
+ // Launch Rx chain calibration for LF band
+ SX1278Write (REG_IMAGECAL, (SX1278Read(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_MASK) | RF_IMAGECAL_IMAGECAL_START);
+ while((SX1278Read(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_RUNNING) == RF_IMAGECAL_IMAGECAL_RUNNING)
+ {
+ }
+
+ // Sets a Frequency in HF band
+ SX1278SetChannel(868000000);
+
+ // Launch Rx chain calibration for HF band
+ SX1278Write(REG_IMAGECAL, (SX1278Read(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_MASK) | RF_IMAGECAL_IMAGECAL_START);
+ while((SX1278Read(REG_IMAGECAL) & RF_IMAGECAL_IMAGECAL_RUNNING) == RF_IMAGECAL_IMAGECAL_RUNNING)
+ {
+ }
+
+ // Restore context
+ SX1278Write(REG_PACONFIG, regPaConfigInitVal);
+ SX1278SetChannel(initialFreq);
+}
+
+//-----------------------------------------------------------------------------
+uint8_t GetFskBandwidthRegValue(uint32_t bandwidth)
+{
+ uint8_t i;
+
+ for (i = 0; i < (sizeof(SX1278FskBandwidths) / sizeof(BandwidthMap_t)) - 1; i++)
+ {
+ if ((bandwidth >= SX1278FskBandwidths[i].bandwidth) && (bandwidth < SX1278FskBandwidths[i + 1].bandwidth))
+ {
+ return SX1278FskBandwidths[i].RegValue;
+ }
+ }
+ // ERROR: Value not found
+ while(1);
+}
+
+//-----------------------------------------------------------------------------
+uint8_t GetLoRaBandwidthRegValue(uint32_t bandwidth)
+{
+ uint8_t i;
+
+ for (i = 0; i < (sizeof(SX1278LoRaBandwidths) / sizeof(BandwidthMap_t)) - 1; i++)
+ {
+ if ((bandwidth >= SX1278LoRaBandwidths[i].bandwidth) && (bandwidth < SX1278LoRaBandwidths[i + 1].bandwidth))
+ {
+ return SX1278LoRaBandwidths[i].RegValue;
+ }
+ }
+ // ERROR: Value not found
+ while(1);
+}
+
+//-----------------------------------------------------------------------------
+void OnDio0Irq()
+{
+ volatile uint8_t irqFlags = 0;
+
+ switch (settings.State)
+ {
+ case RF_RX_RUNNING:
+ //TimerStop(&RxTimeoutTimer);
+ // RxDone interrupt
+ switch (settings.Modem)
+ {
+ case MODEM_FSK:
+ if (settings.Fsk.CrcOn == true)
+ {
+ irqFlags = SX1278Read(REG_IRQFLAGS2);
+ if ((irqFlags & RF_IRQFLAGS2_CRCOK) != RF_IRQFLAGS2_CRCOK)
+ {
+ // Clear Irqs
+ SX1278Write(REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
+ RF_IRQFLAGS1_PREAMBLEDETECT |
+ RF_IRQFLAGS1_SYNCADDRESSMATCH);
+ SX1278Write(REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN);
+
+ SX1278SetTimeout(RXTimeoutTimer, NULL, 0);
+
+ if (settings.Fsk.RxContinuous == false)
+ {
+ SX1278SetTimeout(RXTimeoutSyncWordTimer, NULL, 0);
+ settings.State = RF_IDLE;
+ }
+ else
+ {
+ // Continuous mode restart Rx chain
+ SX1278Write(REG_RXCONFIG, SX1278Read(REG_RXCONFIG) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK);
+ SX1278SetTimeout(RXTimeoutSyncWordTimer, &OnTimeoutIrq, settings.Fsk.RxSingleTimeout);
+ }
+
+ if ((RadioEvents != NULL) && (RadioEvents->RxError != NULL))
+ {
+ RadioEvents->RxError();
+ }
+ settings.FskPacketHandler.PreambleDetected = false;
+ settings.FskPacketHandler.SyncWordDetected = false;
+ settings.FskPacketHandler.NbBytes = 0;
+ settings.FskPacketHandler.Size = 0;
+ break;
+ }
+ }
+
+ // SX1278Read received packet size
+ if ((settings.FskPacketHandler.Size == 0) && (settings.FskPacketHandler.NbBytes == 0))
+ {
+ if (settings.Fsk.FixLen == false)
+ {
+ SX1278ReadFifo((uint8_t*)&settings.FskPacketHandler.Size, 1);
+ }
+ else
+ {
+ settings.FskPacketHandler.Size = SX1278Read(REG_PAYLOADLENGTH);
+ }
+ SX1278ReadFifo(RxTxBuffer + settings.FskPacketHandler.NbBytes, settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes);
+ settings.FskPacketHandler.NbBytes += (settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes);
+ }
+ else
+ {
+ SX1278ReadFifo(RxTxBuffer + settings.FskPacketHandler.NbBytes, settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes);
+ settings.FskPacketHandler.NbBytes += (settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes);
+ }
+
+ SX1278SetTimeout(RXTimeoutTimer, NULL, 0);
+
+ if (settings.Fsk.RxContinuous == false)
+ {
+ settings.State = RF_IDLE;
+ SX1278SetTimeout(RXTimeoutSyncWordTimer, NULL, 0);
+ }
+ else
+ {
+ // Continuous mode restart Rx chain
+ SX1278Write(REG_RXCONFIG, SX1278Read(REG_RXCONFIG) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK);
+ SX1278SetTimeout(RXTimeoutSyncWordTimer, &OnTimeoutIrq, settings.Fsk.RxSingleTimeout);
+ }
+
+ if ((RadioEvents != NULL) && (RadioEvents->RxDone != NULL))
+ {
+ RadioEvents->RxDone(RxTxBuffer, settings.FskPacketHandler.Size, settings.FskPacketHandler.RssiValue, 0);
+ }
+ settings.FskPacketHandler.PreambleDetected = false;
+ settings.FskPacketHandler.SyncWordDetected = false;
+ settings.FskPacketHandler.NbBytes = 0;
+ settings.FskPacketHandler.Size = 0;
+ break;
+ case MODEM_LORA:
+ {
+ // Clear Irq
+ SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE);
+
+ irqFlags = SX1278Read(REG_LR_IRQFLAGS);
+ if ((irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK) == RFLR_IRQFLAGS_PAYLOADCRCERROR)
+ {
+ // Clear Irq
+ SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR);
+
+ if (settings.LoRa.RxContinuous == false)
+ {
+ settings.State = RF_IDLE;
+ }
+ SX1278SetTimeout(RXTimeoutTimer, NULL, 0);
+
+ if ((RadioEvents != NULL) && (RadioEvents->RxError != NULL))
+ {
+ RadioEvents->RxError();
+ }
+ break;
+ }
+ // Returns SNR value [dB] rounded to the nearest integer value
+ settings.LoRaPacketHandler.SnrValue = (((int8_t)SX1278Read(REG_LR_PKTSNRVALUE)) + 2) >> 2;
+ int16_t rssi = SX1278Read(REG_LR_PKTRSSIVALUE);
+ if (settings.LoRaPacketHandler.SnrValue < 0)
+ {
+ if (settings.Channel > RF_MID_BAND_THRESH)
+ {
+ settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
+ settings.LoRaPacketHandler.SnrValue;
+ }
+ else
+ {
+ settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
+ settings.LoRaPacketHandler.SnrValue;
+ }
+ }
+ else
+ {
+ if(settings.Channel > RF_MID_BAND_THRESH)
+ {
+ settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
+ }
+ else
+ {
+ settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
+ }
+ }
+
+ settings.LoRaPacketHandler.Size = SX1278Read( REG_LR_RXNBBYTES);
+ SX1278Write( REG_LR_FIFOADDRPTR, SX1278Read( REG_LR_FIFORXCURRENTADDR));
+ SX1278ReadFifo( RxTxBuffer, settings.LoRaPacketHandler.Size);
+
+ if(settings.LoRa.RxContinuous == false)
+ {
+ settings.State = RF_IDLE;
+ }
+
+ SX1278SetTimeout(RXTimeoutTimer, NULL, 0);
+
+ if ((RadioEvents != NULL) && (RadioEvents->RxDone != NULL))
+ {
+ RadioEvents->RxDone(RxTxBuffer, settings.LoRaPacketHandler.Size, settings.LoRaPacketHandler.RssiValue, settings.LoRaPacketHandler.SnrValue);
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case RF_TX_RUNNING:
+ SX1278SetTimeout(TXTimeoutTimer, NULL, 0);
+ // TxDone interrupt
+ switch (settings.Modem)
+ {
+ case MODEM_LORA:
+ // Clear Irq
+ SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE);
+ // Intentional fall through
+ case MODEM_FSK:
+ default:
+ settings.State = RF_IDLE;
+ if ((RadioEvents != NULL) && (RadioEvents->TxDone != NULL))
+ {
+ RadioEvents->TxDone();
+ }
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+//-----------------------------------------------------------------------------
+void OnDio1Irq()
+{
+ switch (settings.State)
+ {
+ case RF_RX_RUNNING:
+ switch (settings.Modem)
+ {
+ case MODEM_FSK:
+ // Stop Timer
+ SX1278SetTimeout(RXTimeoutSyncWordTimer, NULL, 0);
+
+ // FifoLevel interrupt
+ // SX1278Read received packet size
+ if ((settings.FskPacketHandler.Size == 0) && (settings.FskPacketHandler.NbBytes == 0))
+ {
+ if (settings.Fsk.FixLen == false)
+ {
+ SX1278ReadFifo((uint8_t*)&settings.FskPacketHandler.Size, 1);
+ }
+ else
+ {
+ settings.FskPacketHandler.Size = SX1278Read(REG_PAYLOADLENGTH);
+ }
+ }
+ // ERRATA 3.1 - PayloadReady Set for 31.25ns if FIFO is Empty
+ //
+ // When FifoLevel interrupt is used to offload the
+ // FIFO, the microcontroller should monitor both
+ // PayloadReady and FifoLevel interrupts, and
+ // read only (FifoThreshold-1) bytes off the FIFO
+ // when FifoLevel fires
+ if ((settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes) > settings.FskPacketHandler.FifoThresh)
+ {
+ SX1278ReadFifo((RxTxBuffer + settings.FskPacketHandler.NbBytes), settings.FskPacketHandler.FifoThresh);
+ settings.FskPacketHandler.NbBytes += settings.FskPacketHandler.FifoThresh;
+ }
+ else
+ {
+ SX1278ReadFifo((RxTxBuffer + settings.FskPacketHandler.NbBytes), settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes);
+ settings.FskPacketHandler.NbBytes += (settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes);
+ }
+ break;
+ case MODEM_LORA:
+ // Sync time out
+ SX1278SetTimeout(RXTimeoutTimer, NULL, 0);
+ // Clear Irq
+ SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT);
+
+ settings.State = RF_IDLE;
+ if ((RadioEvents != NULL) && (RadioEvents->RxTimeout != NULL))
+ {
+ RadioEvents->RxTimeout();
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case RF_TX_RUNNING:
+ switch (settings.Modem)
+ {
+ case MODEM_FSK:
+ // FifoEmpty interrupt
+ if ((settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes) > settings.FskPacketHandler.ChunkSize)
+ {
+ SX1278WriteFifo((RxTxBuffer + settings.FskPacketHandler.NbBytes), settings.FskPacketHandler.ChunkSize);
+ settings.FskPacketHandler.NbBytes += settings.FskPacketHandler.ChunkSize;
+ }
+ else
+ {
+ // SX1278Write the last chunk of data
+ SX1278WriteFifo(RxTxBuffer + settings.FskPacketHandler.NbBytes, settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes);
+ settings.FskPacketHandler.NbBytes += settings.FskPacketHandler.Size - settings.FskPacketHandler.NbBytes;
+ }
+ break;
+ case MODEM_LORA:
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+//-----------------------------------------------------------------------------
+void OnDio2Irq()
+{
+ switch (settings.State)
+ {
+ case RF_RX_RUNNING:
+ switch (settings.Modem)
+ {
+ case MODEM_FSK:
+ // Checks if DIO4 is connected. If it is not PreambleDtected is set to true.
+ if (dioIrq[4] == NULL)
+ {
+ settings.FskPacketHandler.PreambleDetected = true;
+ }
+
+ if ((settings.FskPacketHandler.PreambleDetected == true) && (settings.FskPacketHandler.SyncWordDetected == false))
+ {
+ SX1278SetTimeout(RXTimeoutSyncWordTimer, NULL, 0);
+
+ settings.FskPacketHandler.SyncWordDetected = true;
+
+ settings.FskPacketHandler.RssiValue = -(SX1278Read(REG_RSSIVALUE) >> 1);
+
+ settings.FskPacketHandler.AfcValue = (int32_t)(double)(((uint16_t)SX1278Read(REG_AFCMSB) << 8) |
+ (uint16_t)SX1278Read(REG_AFCLSB)) *
+ (double)FREQ_STEP;
+ settings.FskPacketHandler.RxGain = (SX1278Read(REG_LNA) >> 5) & 0x07;
+ }
+ break;
+ case MODEM_LORA:
+ if (settings.LoRa.FreqHopOn == true)
+ {
+ // Clear Irq
+ SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL);
+
+ if ((RadioEvents != NULL) && (RadioEvents->FhssChangeChannel != NULL))
+ {
+ RadioEvents->FhssChangeChannel((SX1278Read(REG_LR_HOPCHANNEL) & RFLR_HOPCHANNEL_CHANNEL_MASK));
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case RF_TX_RUNNING:
+ switch (settings.Modem)
+ {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ if (settings.LoRa.FreqHopOn == true)
+ {
+ // Clear Irq
+ SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL);
+
+ if ((RadioEvents != NULL) && (RadioEvents->FhssChangeChannel != NULL))
+ {
+ RadioEvents->FhssChangeChannel((SX1278Read(REG_LR_HOPCHANNEL) & RFLR_HOPCHANNEL_CHANNEL_MASK));
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+//-----------------------------------------------------------------------------
+void OnDio3Irq()
+{
+ switch (settings.Modem)
+ {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ if ((SX1278Read(REG_LR_IRQFLAGS) & RFLR_IRQFLAGS_CADDETECTED) == RFLR_IRQFLAGS_CADDETECTED)
+ {
+ // Clear Irq
+ SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE);
+ if ((RadioEvents != NULL) && (RadioEvents->CadDone != NULL))
+ {
+ RadioEvents->CadDone(true);
+ }
+ }
+ else
+ {
+ // Clear Irq
+ SX1278Write(REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE);
+ if ((RadioEvents != NULL) && (RadioEvents->CadDone != NULL))
+ {
+ RadioEvents->CadDone(false);
+ }
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+//-----------------------------------------------------------------------------
+void OnDio4Irq()
+{
+ switch (settings.Modem)
+ {
+ case MODEM_FSK:
+ {
+ if (settings.FskPacketHandler.PreambleDetected == false)
+ {
+ settings.FskPacketHandler.PreambleDetected = true;
+ }
+ }
+ break;
+ case MODEM_LORA:
+ break;
+ default:
+ break;
+ }
+}
+
+//-----------------------------------------------------------------------------
+void OnDio5Irq()
+{
+ switch (settings.Modem)
+ {
+ case MODEM_FSK:
+ break;
+ case MODEM_LORA:
+ break;
+ default:
+ break;
+ }
+}
+
+//-----------------------------------------------------------------------------
diff -r 000000000000 -r 4e8ef5758455 sx1278.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sx1278.h Sat Nov 16 16:34:57 2019 +0000
@@ -0,0 +1,931 @@
+/**
+ * @brief: Implementation of a SX1278 radio functions
+ * @author: luk6xff based on SEMTCH code: https://github.com/Lora-net/LoRaMac-node
+ * @email: luszko@op.pl
+ * @date: 2019-11-15
+ */
+
+#ifndef __SX1278_H__
+#define __SX1278_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "registers.h"
+
+/**
+ * ============================================================================
+ * @brief Public defines
+ * ============================================================================
+ */
+
+/**
+ * @brief Radio wake-up time from sleep
+ */
+#define RADIO_WAKEUP_TIME 1 // [ms]
+
+/**
+ * @brief Sync word for Private LoRa networks
+ */
+#define LORA_MAC_PRIVATE_SYNCWORD 0x12
+
+/**
+ * @brief Sync word for Public LoRa networks
+ */
+#define LORA_MAC_PUBLIC_SYNCWORD 0x34
+
+
+/**
+ * @brief SX1278 definitions
+ */
+#define XTAL_FREQ 32000000
+#define FREQ_STEP 61.03515625
+
+#define RX_BUFFER_SIZE 256
+
+/**
+ * @brief Constant values need to compute the RSSI value
+ */
+#define RSSI_OFFSET_LF -164.0
+#define RSSI_OFFSET_HF -157.0
+
+#define RF_MID_BAND_THRESH 525000000
+
+
+
+/**
+ * ============================================================================
+ * @brief Public datatypes declarations
+ * ============================================================================
+ */
+
+/**
+ * Timeout timer type
+ */
+typedef enum
+{
+ RXTimeoutTimer,
+ TXTimeoutTimer,
+ RXTimeoutSyncWordTimer
+} TimeoutTimer_t;
+
+
+/**
+ * Type of the supported board. [RA-01]
+ */
+typedef enum
+{
+ BOARD_RA01 = 0,
+ BOARD_UNKNOWN
+} BoardType_t;
+
+ typedef enum
+ {
+ LORA_SF6 = 6, // 64 chips/symbol, SF6 requires an TCXO!
+ LORA_SF7 = 7, // 128 chips/symbol
+ LORA_SF8 = 8, // 256 chips/symbol
+ LORA_SF9 = 9, // 512 chips/symbol
+ LORA_SF10 = 10, // 1024 chips/symbol
+ LORA_SF11 = 11, // 2048 chips/symbol
+ LORA_SF12 = 12, // 4096 chips/symbol
+} LoraSpreadingFactor_t;
+
+/**
+ * Type of the supported lora bandwidths
+ */
+typedef enum
+{
+ LORA_BANDWIDTH_7kHz = 0, // 7.8 kHz requires TCXO
+ LORA_BANDWIDTH_10kHz = 1, // 10.4 kHz requires TCXO
+ LORA_BANDWIDTH_15kHz = 2, // 15.6 kHz requires TCXO
+ LORA_BANDWIDTH_20kHz = 3, // 20.8 kHz requires TCXO
+ LORA_BANDWIDTH_31kHz = 4, // 31.2 kHz requires TCXO
+ LORA_BANDWIDTH_41kHz = 5, // 41.4 kHz requires TCXO
+ LORA_BANDWIDTH_62kHz = 6, // 62.5 kHz requires TCXO
+ LORA_BANDWIDTH_125kHz = 7,
+ LORA_BANDWIDTH_250kHz = 8,
+ LORA_BANDWIDTH_500kHz = 9,
+ LORA_BANDWIDTH_RESERVED = 10,
+} LoraBandwidth_t;
+
+
+typedef enum
+{ // cyclic error coding to perform forward error detection and correction
+ LORA_ERROR_CODING_RATE_4_5 = 1, // 1.25x overhead
+ LORA_ERROR_CODING_RATE_4_6 = 2, // 1.50x overhead
+ LORA_ERROR_CODING_RATE_4_7 = 3, // 1.75x overhead
+ LORA_ERROR_CODING_RATE_4_8 = 4, // 2.00x overhead
+} LoraCodingRate_t;
+
+
+typedef enum
+{
+ RF_FREQUENCY_434_0 = 434000000, // Hz
+ RF_FREQUENCY_868_0 = 868000000, // Hz
+ RF_FREQUENCY_868_1 = 868100000, // Hz
+ RF_FREQUENCY_868_3 = 868300000, // Hz
+ RF_FREQUENCY_868_5 = 868500000, // Hz
+} RfFrequency_t;
+
+
+/**
+ * @brief Radio driver callback functions.
+ * Reporting functions for upper layers.
+ * The radio driver reports various vital events to the upper controlling layers
+ * using callback functions provided by the upper layers at the initialization
+ * phase.
+ */
+typedef struct
+{
+ /**
+ * @brief Callback when Transmission is done.
+ */
+ void (*TxDone)(void);
+
+ /**
+ * @brief Callback when Transmission is timed out.
+ */
+ void (*TxTimeout)(void);
+
+ /**
+ * @brief Rx Done callback prototype.
+ *
+ * @param [IN] payload Received buffer pointer
+ * @param [IN] size Received buffer size
+ * @param [IN] rssi RSSI value computed while receiving the frame [dBm]
+ * @param [IN] snr Raw SNR value given by the radio hardware
+ * FSK : N/A (set to 0)
+ * LoRa: SNR value in dB
+ */
+ void (*RxDone)(uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr);
+
+ /**
+ * @brief Callback when Reception is timed out.
+ */
+ void (*RxTimeout)(void);
+
+ /**
+ * @brief Callback when Reception ends up in error.
+ */
+ void (*RxError)(void);
+
+ /**
+ * @brief FHSS Change Channel callback prototype.
+ *
+ * @param [IN] currentChannel Index number of the current channel
+ */
+ void (*FhssChangeChannel)(uint8_t currentChannel);
+
+ /**
+ * @brief CAD Done callback prototype.
+ *
+ * @param [IN] channelDetected True, if Channel activity detected.
+ */
+ void (*CadDone) (bool channelActivityDetected);
+} RadioEvents_t;
+
+
+
+/**
+ * @brief Radio driver internal state machine states definition
+ * Helps identify current state of the transceiver.
+ */
+typedef enum
+{
+ /** @brief IDLE state.
+ * Radio is in idle state.
+ */
+ RF_IDLE = 0,
+
+ /** @brief RX state.
+ * Radio is receiving.
+ */
+ RF_RX_RUNNING,
+
+ /** @brief TX state.
+ * Radio is transmitting.
+ */
+ RF_TX_RUNNING,
+
+ /** @brief CAD state.
+ * Radio is detecting channel activity.
+ */
+ RF_CAD,
+} RadioState_t;
+
+/**
+ * @brief Type of modem [LORA/FSK]
+ */
+typedef enum
+{
+ /**
+ * @brief FSK operation mode.
+ * Radio is using FSK modulation.
+ */
+ MODEM_FSK = 0,
+
+ /**
+ * @brief LoRa operation mode.
+ * Radio is using LoRa modulation.
+ */
+ MODEM_LORA
+} RadioModems_t;
+
+/**
+ * @brief Radio FSK modem parameters
+ * Parameters encompassing FSK modulation.
+ */
+typedef struct
+{
+ /**
+ * @brief Transmit power.
+ */
+ int8_t Power;
+
+ /**
+ * @brief Frequency deviation.
+ */
+ uint32_t Fdev;
+
+ /**
+ * @brief Modulation bandwidth.
+ */
+ uint32_t Bandwidth;
+
+ /**
+ * @brief Automated frequency correction bandwidth.
+ */
+ uint32_t BandwidthAfc;
+
+ /**
+ * @brief Data rate (SF).
+ */
+ uint32_t Datarate;
+
+ /**
+ * @brief Expected preamble length.
+ */
+ uint16_t PreambleLen;
+
+ /**
+ * @brief This flag turns on if the TX data size is fixed.
+ */
+ bool FixLen;
+
+ /**
+ * @brief Size of outgoing data.
+ */
+ uint8_t PayloadLen;
+
+ /**
+ * @brief Turn CRC on/off.
+ */
+ bool CrcOn;
+
+ /** @deprecated
+ * @brief Does not apply to FSK. Will be removed.
+ */
+ bool IqInverted;
+
+ /**
+ * @brief Turn continuous reception mode (such as Class C mode) on/off.
+ */
+ bool RxContinuous;
+
+ /**
+ * @brief Timeout value in milliseconds (ms) after which the radio driver reports
+ * a timeout if the radio was unable to transmit.
+ */
+ uint32_t TxTimeout;
+
+ /**
+ * @brief Timeout value in symbols (symb) after which the radio driver reports a timeout
+ * if the radio did not receive a Preamble.
+ */
+ uint32_t RxSingleTimeout;
+} RadioFskSettings_t;
+
+/**
+ * @brief Radio FSK packet handler state
+ * Contains information about an FSK packet and various metadata.
+ */
+typedef struct
+{
+ /**
+ * @brief Set to true (1) when a Preamble is detected, otherwise false (0).
+ */
+ uint8_t PreambleDetected;
+
+ /**
+ * @brief Set to true (1) when a SyncWord is detected, otherwise false (0).
+ */
+ uint8_t SyncWordDetected;
+
+ /**
+ * @brief Storage for RSSI value of the received signal.
+ */
+ int8_t RssiValue;
+
+ /**
+ * @brief Automated frequency correction value.
+ */
+ int32_t AfcValue;
+
+ /**
+ * @brief LNA gain value (dbm).
+ */
+ uint8_t RxGain;
+
+ /**
+ * @brief Size of the received data in bytes.
+ */
+ uint16_t Size;
+
+ /**
+ * @brief Keeps track of number of bytes already read from the RX FIFO.
+ */
+ uint16_t NbBytes;
+
+ /**
+ * @brief Stores the FIFO threshold value.
+ */
+ uint8_t FifoThresh;
+
+ /**
+ * @brief Defines the size of a chunk of outgoing buffer written to
+ * the FIFO at a unit time. For example, if the size of the data exceeds the FIFO
+ * limit, a certain sized chunk is written to the FIFO. Later, a FIFO-level
+ * interrupt enables writing of the remaining data to the FIFO chunk by chunk until
+ * transmission is complete.
+ */
+ uint8_t ChunkSize;
+} RadioFskPacketHandler_t;
+
+/**
+ * @brief Radio LoRa modem parameters
+ * Parameters encompassing LoRa modulation.
+ */
+typedef struct
+{
+ /**
+ * @brief Transmit power.
+ */
+ int8_t Power;
+
+ /**
+ * @brief Modulation bandwidth.
+ */
+ uint32_t Bandwidth;
+
+ /**
+ * @brief Data rate (SF).
+ */
+ uint32_t Datarate;
+
+ /**
+ * @brief Turn low data rate optimization on/off.
+ */
+ bool LowDatarateOptimize;
+
+ /**
+ * @brief Error correction code rate.
+ */
+ uint8_t Coderate;
+
+ /**
+ * @brief Preamble length in symbols.
+ */
+ uint16_t PreambleLen;
+
+ /**
+ * @brief Set to true if the outgoing payload length is fixed.
+ */
+ bool FixLen;
+
+ /**
+ * @brief Size of outgoing payload.
+ */
+ uint8_t PayloadLen;
+
+ /**
+ * @brief Turn CRC on/off.
+ */
+ bool CrcOn;
+
+ /**
+ * @brief Turn frequency hopping on/off.
+ */
+ bool FreqHopOn;
+
+ /**
+ * @brief Number of symbols between two frequency hops.
+ */
+ uint8_t HopPeriod;
+
+ /**
+ * @brief Turn IQ inversion on/off. Usually, the end device sends an IQ inverted
+ * signal, and the base stations do not invert. We recommended sending an
+ * IQ inverted signal from the device side, so any transmissions from the
+ * base stations do not interfere with end device transmission.
+ */
+ bool IqInverted;
+
+ /**
+ * @brief Turn continuous reception mode (such as in Class C) on/off.
+ */
+ bool RxContinuous;
+
+ /**
+ * @brief Timeout in milliseconds (ms) after which the radio driver reports an error
+ * if the radio was unable to transmit.
+ */
+ uint32_t TxTimeout;
+
+ /**
+ * @brief Change the network mode to Public or Private.
+ */
+ bool PublicNetwork;
+} RadioLoRaSettings_t;
+
+/**
+ * Radio LoRa packet handler state
+ */
+typedef struct
+{
+ /**
+ * @brief Signal-to-noise ratio of a received packet.
+ */
+ int8_t SnrValue;
+
+ /**
+ * @brief RSSI value in dBm for the received packet.
+ */
+ int8_t RssiValue;
+
+ /**
+ * @brief Size of the transmitted or received packet.
+ */
+ uint8_t Size;
+} RadioLoRaPacketHandler_t;
+
+
+/**
+ * @brief Global radio settings.
+ * Contains settings for the overall transceiver operation.
+ */
+typedef struct
+{
+ /**
+ * @brief Current state of the radio, such as RF_IDLE.
+ */
+ RadioState_t State;
+
+ /**
+ * @brief Current modem operation, such as LORA or FSK.
+ */
+ RadioModems_t Modem;
+
+ /**
+ * @brief Current channel of operation.
+ */
+ uint32_t Channel;
+
+ /**
+ * @brief Settings for FSK modem part.
+ */
+ RadioFskSettings_t Fsk;
+
+ /**
+ * @brief FSK packet and meta data.
+ */
+ RadioFskPacketHandler_t FskPacketHandler;
+
+ /**
+ * @brief Settings for LoRa modem part.
+ */
+ RadioLoRaSettings_t LoRa;
+
+ /**
+ * @brief LoRa packet and metadata.
+ */
+ RadioLoRaPacketHandler_t LoRaPacketHandler;
+} RadioSettings_t;
+
+
+/**
+ * @brief FSK and LORA bandwidth definition
+ */
+typedef struct
+{
+ uint32_t bandwidth;
+ uint8_t RegValue;
+} BandwidthMap_t;
+
+/**
+ * @brief Radio registers definition
+ */
+typedef struct
+{
+ RadioModems_t Modem;
+ uint8_t Addr;
+ uint8_t Value;
+} RadioRegisters_t;
+
+
+
+/**
+ * @brief Hardware IO IRQ callback function definition
+ */
+typedef void (*DioIrqHandler)(void);
+
+/**
+ * @brief Timeout timer callback function definition
+ */
+typedef void (*timeoutFuncPtr)(void);
+
+/**
+ * ============================================================================
+ * @brief Public functions prototypes
+ * ============================================================================
+ */
+
+/**
+ * @brief Actual implementation of a SX1278 radio
+ */
+
+//-------------------------------------------------------------------------
+// Radio functions
+//-------------------------------------------------------------------------
+/**
+ * @brief Initializes the radio
+ *
+ * @param [IN] events Structure containing the driver callback functions
+ */
+bool SX1278Init(RadioEvents_t *events);
+
+/**
+ * @brief Initializes the radio registers
+ */
+void SX1278RadioRegistersInit();
+
+
+/**
+ * Return current radio status
+ *
+ * @param status Radio status. [RF_IDLE, RX_RUNNING, TX_RUNNING]
+ */
+RadioState_t SX1278GetStatus(void);
+
+/**
+ * @brief Configures the SX1278 with the given modem
+ *
+ * @param [IN] modem Modem to be used [0: FSK, 1: LoRa]
+ */
+void SX1278SetModem(RadioModems_t modem);
+
+/**
+ * @brief Sets the channel frequency
+ *
+ * @param [IN] freq Channel RF frequency
+ */
+void SX1278SetChannel(uint32_t freq);
+
+/**
+ * @brief Sets the channels configuration
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] freq Channel RF frequency
+ * @param [IN] rssiThresh RSSI threshold
+ * @param [IN] maxCarrierSenseTime Max time while the RSSI is measured
+ *
+ * @retval isFree [true: Channel is free, false: Channel is not free]
+ */
+bool SX1278IsChannelFree(RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarrierSenseTime);
+
+/**
+ * @brief Generates a 32 bits random value based on the RSSI readings
+ *
+ * @note This function sets the radio in LoRa modem mode and disables
+ * all interrupts.
+ * After calling this function either SX1278SetRxConfig or
+ * SX1278SetTxConfig functions must be called.
+ *
+ * @retval randomValue 32 bits random value
+ */
+uint32_t SX1278Random(void);
+
+/**
+ * @brief Sets the reception parameters
+ *
+ * @note When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] bandwidth Sets the bandwidth
+ * FSK : >= 2600 and <= 250000 Hz
+ * LoRa: [0: 125 kHz, 1: 250 kHz,
+ * 2: 500 kHz, 3: Reserved]
+ * @param [IN] datarate Sets the Datarate
+ * FSK : 600..300000 bits/s
+ * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ * 10: 1024, 11: 2048, 12: 4096 chips]
+ * @param [IN] coderate Sets the coding rate (LoRa only)
+ * FSK : N/A (set to 0)
+ * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * @param [IN] bandwidthAfc Sets the AFC Bandwidth (FSK only)
+ * FSK : >= 2600 and <= 250000 Hz
+ * LoRa: N/A (set to 0)
+ * @param [IN] preambleLen Sets the Preamble length (LoRa only)
+ * FSK : N/A (set to 0)
+ * LoRa: Length in symbols (the hardware adds 4 more symbols)
+ * @param [IN] symbTimeout Sets the RxSingle timeout value
+ * FSK : timeout number of bytes
+ * LoRa: timeout in symbols
+ * @param [IN] fixLen Fixed length packets [0: variable, 1: fixed]
+ * @param [IN] payloadLen Sets payload length when fixed lenght is used
+ * @param [IN] crcOn Enables/Disables the CRC [0: OFF, 1: ON]
+ * @param [IN] freqHopOn Enables disables the intra-packet frequency hopping
+ * FSK : N/A ( set to 0 )
+ * LoRa: [0: OFF, 1: ON]
+ * @param [IN] hopPeriod Number of symbols between each hop
+ * FSK : N/A ( set to 0 )
+ * LoRa: Number of symbols
+ * @param [IN] iqInverted Inverts IQ signals (LoRa only)
+ * FSK : N/A ( set to 0 )
+ * LoRa: [0: not inverted, 1: inverted]
+ * @param [IN] rxContinuous Sets the reception in continuous mode
+ * [false: single mode, true: continuous mode]
+ */
+void SX1278SetRxConfig (RadioModems_t modem, uint32_t bandwidth,
+ uint32_t datarate, uint8_t coderate,
+ uint32_t bandwidthAfc, uint16_t preambleLen,
+ uint16_t symbTimeout, bool fixLen,
+ uint8_t payloadLen,
+ bool crcOn, bool freqHopOn, uint8_t hopPeriod,
+ bool iqInverted, bool rxContinuous);
+/**
+ * @brief Sets the transmission parameters
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] power Sets the output power [dBm]
+ * @param [IN] fdev Sets the frequency deviation (FSK only)
+ * FSK : [Hz]
+ * LoRa: 0
+ * @param [IN] bandwidth Sets the bandwidth (LoRa only)
+ * FSK : 0
+ * LoRa: [0: 125 kHz, 1: 250 kHz,
+ * 2: 500 kHz, 3: Reserved]
+ * @param [IN] datarate Sets the Datarate
+ * FSK : 600..300000 bits/s
+ * LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ * 10: 1024, 11: 2048, 12: 4096 chips]
+ * @param [IN] coderate Sets the coding rate (LoRa only)
+ * FSK : N/A (set to 0)
+ * LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * @param [IN] preambleLen Sets the preamble length
+ * @param [IN] fixLen Fixed length packets [0: variable, 1: fixed]
+ * @param [IN] crcOn Enables disables the CRC [0: OFF, 1: ON]
+ * @param [IN] freqHopOn Enables disables the intra-packet frequency hopping [0: OFF, 1: ON] (LoRa only)
+ * @param [IN] hopPeriod Number of symbols bewteen each hop (LoRa only)
+ * @param [IN] iqInverted Inverts IQ signals (LoRa only)
+ * FSK : N/A (set to 0)
+ * LoRa: [0: not inverted, 1: inverted]
+ * @param [IN] timeout Transmission timeout [ms]
+ */
+void SX1278SetTxConfig(RadioModems_t modem, int8_t power, uint32_t fdev,
+ uint32_t bandwidth, uint32_t datarate,
+ uint8_t coderate, uint16_t preambleLen,
+ bool fixLen, bool crcOn, bool freqHopOn,
+ uint8_t hopPeriod, bool iqInverted, uint32_t timeout);
+
+/**
+ * @brief Computes the packet time on air for the given payload
+ *
+ * @note Can only be called once SetRxConfig or SetTxConfig have been called
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] pktLen Packet payload length
+ *
+ * @retval airTime Computed airTime (ms) for the given packet payload length
+ */
+uint32_t SX1278GetTimeOnAir(RadioModems_t modem, uint8_t pktLen);
+
+/**
+ * @brief Sends the buffer of size. Prepares the packet to be sent and sets
+ * the radio in transmission
+ *
+ * @param [IN]: buffer Buffer pointer
+ * @param [IN]: size Buffer size
+ */
+void SX1278Send(uint8_t *buffer, uint8_t size);
+
+/**
+ * @brief Sets the radio in sleep mode
+ */
+void SX1278SetSleep(void);
+
+/**
+ * @brief Sets the radio in standby mode
+ */
+void SX1278SetStandby(void);
+
+/**
+ * @brief Sets the radio in CAD mode (starts a Channel Activity Detection)
+ */
+void SX1278StartCad(void);
+
+/**
+ * @brief Sets the radio in reception mode for the given time
+ * @param [IN] timeout Reception timeout [ms]
+ * [0: continuous, others timeout]
+ */
+void SX1278SetRx(uint32_t timeout);
+
+/**
+ * @brief Sets the radio in transmission mode for the given time
+ * @param [IN] timeout Transmission timeout [ms]
+ * [0: continuous, others timeout]
+ */
+void SX1278SetTx(uint32_t timeout);
+
+/**
+ * @brief Sets the radio in continuous wave transmission mode
+ *
+ * @param [IN]: freq Channel RF frequency
+ * @param [IN]: power Sets the output power [dBm]
+ * @param [IN]: time Transmission mode timeout [s]
+ */
+void SX1278SetTxContinuousWave(uint32_t freq, int8_t power, uint16_t time);
+
+/**
+ * @brief Reads the current RSSI value
+ *
+ * @retval rssiValue Current RSSI value in [dBm]
+ */
+int16_t SX1278GetRssi(RadioModems_t modem);
+
+/**
+ * @brief Reads the current frequency error
+ *
+ * @retval frequency error value in [Hz]
+ */
+int32_t SX1278GetFrequencyError(RadioModems_t modem);
+
+/**
+ * @brief Sets the maximum payload length.
+ *
+ * @param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
+ * @param [IN] max Maximum payload length in bytes
+ */
+void SX1278SetMaxPayloadLength(RadioModems_t modem, uint8_t max);
+
+/**
+ * @brief Sets the network to public or private. Updates the sync byte.
+ *
+ * @note Applies to LoRa modem only
+ *
+ * @param [IN] enable if true, it enables a public network
+ */
+void SX1278SetPublicNetwork(bool enable);
+
+/**
+ * @brief Gets the time required for the board plus radio to get out of sleep.[ms]
+ *
+ * @retval Time Radio plus board wakeup time in ms.
+ */
+uint32_t SX1278GetWakeupTime(void);
+
+/**
+ * @brief Sets the SX1278 operating mode
+ *
+ * @param [IN] opMode New operating mode
+ */
+void SX1278SetOpMode(uint8_t opMode);
+
+/**
+ * @brief Sets the radio output power.
+ *
+ * @param [IN] power Sets the RF output power
+ */
+void SX1278SetRfTxPower(int8_t power);
+
+/**
+ * @brief Gets the PA selection configuration
+ *
+ * @param [IN] channel Channel frequency in Hz
+ * @retval PaSelect RegPaConfig PaSelect value
+ */
+uint8_t SX1278GetPaSelect(uint32_t channel);
+
+/**
+ * @brief Checks if the given RF frequency is supported by the hardware
+ *
+ * @param [IN] frequency RF frequency to be checked
+ * @retval isSupported [true: supported, false: unsupported]
+ */
+bool SX1278CheckRfFrequency(uint32_t frequency);
+
+/**
+ * @brief Writes the radio register at the specified address
+ *
+ * @param [IN]: addr Register address
+ * @param [IN]: data New register value
+ */
+void SX1278Write (uint8_t addr, uint8_t data);
+
+/**
+ * @brief Reads the radio register at the specified address
+ *
+ * @param [IN]: addr Register address
+ * @retval data Register value
+ */
+uint8_t SX1278Read(uint8_t addr);
+
+/**
+ * @brief Writes the buffer contents to the SX1278 FIFO
+ *
+ * @param [IN] buffer Buffer containing data to be put on the FIFO.
+ * @param [IN] size Number of bytes to be written to the FIFO
+ */
+void SX1278WriteFifo(uint8_t *buffer, uint8_t size);
+
+/**
+ * @brief Reads the contents of the SX1278 FIFO
+ *
+ * @param [OUT] buffer Buffer where to copy the FIFO read data.
+ * @param [IN] size Number of bytes to be read from the FIFO
+ */
+void SX1278ReadFifo(uint8_t *buffer, uint8_t size);
+
+
+
+//-------------------------------------------------------------------------
+// Board/Platform relative (HW dependent) functions,
+// Must be implemented in folder platform.
+//-------------------------------------------------------------------------
+
+/**
+ * @brief Initializes the radio I/Os pins interface
+ */
+extern void SX1278IoInit(void);
+
+/**
+ * @brief De-initializes the radio I/Os pins interface.
+ *
+ * @note Useful when going in MCU lowpower modes
+ */
+extern void SX1278IoDeInit(void);
+
+/**
+ * @brief Initializes DIO IRQ handlers
+ *
+ * @param [IN] irqHandlers Array containing the IRQ callback functions
+ */
+extern void SX1278IoIrqInit(DioIrqHandler *irqHandlers);
+
+/**
+ * @brief Resets the SX1278
+ */
+extern void SX1278Reset(void);
+
+/**
+ * @brief Writes multiple radio registers starting at address
+ *
+ * @param [IN] addr First Radio register address
+ * @param [IN] buffer Buffer containing the new register's values
+ * @param [IN] size Number of registers to be written
+ */
+extern void SX1278WriteBuffer(uint8_t addr, uint8_t *buffer, uint8_t size);
+
+/**
+ * @brief Reads multiple radio registers starting at address
+ *
+ * @param [IN] addr First Radio register address
+ * @param [OUT] buffer Buffer where to copy the registers data
+ * @param [IN] size Number of registers to be read
+ */
+extern void SX1278ReadBuffer(uint8_t addr, uint8_t *buffer, uint8_t size);
+
+/*
+ * @brief The the Timeout for a given Timer.
+ */
+extern void SX1278SetTimeout(TimeoutTimer_t timer, timeoutFuncPtr, int timeout_ms);
+
+/*
+ * @brief A simple ms sleep
+ */
+extern void SX1278DelayMs(int ms);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // __SX1278_H__
+