Iftikhar Aziz / mbed-dev

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Dependents:   LSS_Rev_1

Fork of mbed-dev by Umar Naeem

targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_i2s.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/StdDriver/nuc472_i2s.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /******************************************************************************
<> 144:ef7eb2e8f9f7 2 * @file i2s.h
<> 144:ef7eb2e8f9f7 3 * @version V0.10
<> 144:ef7eb2e8f9f7 4 * $Revision: 10 $
<> 144:ef7eb2e8f9f7 5 * $Date: 14/09/30 1:12p $
<> 144:ef7eb2e8f9f7 6 * @brief NUC472/NUC442 I2S driver header file
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * @note
<> 144:ef7eb2e8f9f7 9 * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
<> 144:ef7eb2e8f9f7 10 *****************************************************************************/
<> 144:ef7eb2e8f9f7 11 #ifndef __I2S_H__
<> 144:ef7eb2e8f9f7 12 #define __I2S_H__
<> 144:ef7eb2e8f9f7 13
<> 144:ef7eb2e8f9f7 14 #include "NUC472_442.h"
<> 144:ef7eb2e8f9f7 15
<> 144:ef7eb2e8f9f7 16 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 17 extern "C"
<> 144:ef7eb2e8f9f7 18 {
<> 144:ef7eb2e8f9f7 19 #endif
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
<> 144:ef7eb2e8f9f7 22 @{
<> 144:ef7eb2e8f9f7 23 */
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 /** @addtogroup NUC472_442_I2S_Driver I2S Driver
<> 144:ef7eb2e8f9f7 26 @{
<> 144:ef7eb2e8f9f7 27 */
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 /** @addtogroup NUC472_442_I2S_EXPORTED_CONSTANTS I2S Exported Constants
<> 144:ef7eb2e8f9f7 30 @{
<> 144:ef7eb2e8f9f7 31 */
<> 144:ef7eb2e8f9f7 32 #define I2S_DATABIT_8 (0 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
<> 144:ef7eb2e8f9f7 33 #define I2S_DATABIT_16 (1 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
<> 144:ef7eb2e8f9f7 34 #define I2S_DATABIT_24 (2 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
<> 144:ef7eb2e8f9f7 35 #define I2S_DATABIT_32 (3 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /* Audio Format */
<> 144:ef7eb2e8f9f7 38 #define I2S_MONO I2S_CTL_MONO_Msk /*!< Mono channel \hideinitializer */
<> 144:ef7eb2e8f9f7 39 #define I2S_STEREO 0 /*!< Stereo channel \hideinitializer */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /* I2S Data Format */
<> 144:ef7eb2e8f9f7 42 #define I2S_FORMAT_MSB I2S_CTL_FORMAT_Msk /*!< MSB data format \hideinitializer */
<> 144:ef7eb2e8f9f7 43 #define I2S_FORMAT_I2S 0 /*!< I2S data format \hideinitializer */
<> 144:ef7eb2e8f9f7 44 #define I2S_FORMAT_PCMB I2S_CTL_FORMAT_Msk /*!< PCMB data format \hideinitializer */
<> 144:ef7eb2e8f9f7 45 #define I2S_FORMAT_PCMA 0 /*!< PCMA data format \hideinitializer */
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /* I2S Interface */
<> 144:ef7eb2e8f9f7 48 #define I2S_PCM I2S_CTL_PCMEN_Msk /*!< PCM interface is selected \hideinitializer */
<> 144:ef7eb2e8f9f7 49 #define I2S_I2S 0 /*!< I2S interface is selected \hideinitializer */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /* I2S Operation mode */
<> 144:ef7eb2e8f9f7 52 #define I2S_MODE_SLAVE I2S_CTL_SLAVE_Msk /*!< As slave mode \hideinitializer */
<> 144:ef7eb2e8f9f7 53 #define I2S_MODE_MASTER 0 /*!< As master mode \hideinitializer */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* I2S FIFO Threshold */
<> 144:ef7eb2e8f9f7 56 #define I2S_FIFO_TX_LEVEL_WORD_0 0 /*!< TX threshold is 0 word \hideinitializer */
<> 144:ef7eb2e8f9f7 57 #define I2S_FIFO_TX_LEVEL_WORD_1 (1 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */
<> 144:ef7eb2e8f9f7 58 #define I2S_FIFO_TX_LEVEL_WORD_2 (2 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */
<> 144:ef7eb2e8f9f7 59 #define I2S_FIFO_TX_LEVEL_WORD_3 (3 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */
<> 144:ef7eb2e8f9f7 60 #define I2S_FIFO_TX_LEVEL_WORD_4 (4 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */
<> 144:ef7eb2e8f9f7 61 #define I2S_FIFO_TX_LEVEL_WORD_5 (5 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */
<> 144:ef7eb2e8f9f7 62 #define I2S_FIFO_TX_LEVEL_WORD_6 (6 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */
<> 144:ef7eb2e8f9f7 63 #define I2S_FIFO_TX_LEVEL_WORD_7 (7 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 #define I2S_FIFO_RX_LEVEL_WORD_1 0 /*!< RX threshold is 1 word \hideinitializer */
<> 144:ef7eb2e8f9f7 66 #define I2S_FIFO_RX_LEVEL_WORD_2 (1 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */
<> 144:ef7eb2e8f9f7 67 #define I2S_FIFO_RX_LEVEL_WORD_3 (2 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */
<> 144:ef7eb2e8f9f7 68 #define I2S_FIFO_RX_LEVEL_WORD_4 (3 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */
<> 144:ef7eb2e8f9f7 69 #define I2S_FIFO_RX_LEVEL_WORD_5 (4 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */
<> 144:ef7eb2e8f9f7 70 #define I2S_FIFO_RX_LEVEL_WORD_6 (5 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */
<> 144:ef7eb2e8f9f7 71 #define I2S_FIFO_RX_LEVEL_WORD_7 (6 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */
<> 144:ef7eb2e8f9f7 72 #define I2S_FIFO_RX_LEVEL_WORD_8 (7 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* I2S Record Channel */
<> 144:ef7eb2e8f9f7 75 #define I2S_MONO_RIGHT 0 /*!< Record mono right channel \hideinitializer */
<> 144:ef7eb2e8f9f7 76 #define I2S_MONO_LEFT I2S_CTL_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /* I2S Channel */
<> 144:ef7eb2e8f9f7 79 #define I2S_RIGHT 0 /*!< Select right channel \hideinitializer */
<> 144:ef7eb2e8f9f7 80 #define I2S_LEFT 1 /*!< Select left channel \hideinitializer */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /*@}*/ /* end of group NUC472_442_I2S_EXPORTED_CONSTANTS */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /** @addtogroup NUC472_442_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
<> 144:ef7eb2e8f9f7 85 @{
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 88 /* inline functions */
<> 144:ef7eb2e8f9f7 89 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 90 /**
<> 144:ef7eb2e8f9f7 91 * @brief Enable zero cross detect function.
<> 144:ef7eb2e8f9f7 92 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 93 * @param[in] u32ChMask is the mask for left or right channel. Valid values are:
<> 144:ef7eb2e8f9f7 94 * - \ref I2S_RIGHT
<> 144:ef7eb2e8f9f7 95 * - \ref I2S_LEFT
<> 144:ef7eb2e8f9f7 96 * @return none
<> 144:ef7eb2e8f9f7 97 * \hideinitializer
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 static __INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
<> 144:ef7eb2e8f9f7 100 {
<> 144:ef7eb2e8f9f7 101 if(u32ChMask == I2S_RIGHT)
<> 144:ef7eb2e8f9f7 102 i2s->CTL |= I2S_CTL_RZCEN_Msk;
<> 144:ef7eb2e8f9f7 103 else
<> 144:ef7eb2e8f9f7 104 i2s->CTL |= I2S_CTL_LZCEN_Msk;
<> 144:ef7eb2e8f9f7 105 }
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /**
<> 144:ef7eb2e8f9f7 108 * @brief Disable zero cross detect function.
<> 144:ef7eb2e8f9f7 109 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 110 * @param[in] u32ChMask is the mask for left or right channel. Valid values are:
<> 144:ef7eb2e8f9f7 111 * - \ref I2S_RIGHT
<> 144:ef7eb2e8f9f7 112 * - \ref I2S_LEFT
<> 144:ef7eb2e8f9f7 113 * @return none
<> 144:ef7eb2e8f9f7 114 * \hideinitializer
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116 static __INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
<> 144:ef7eb2e8f9f7 117 {
<> 144:ef7eb2e8f9f7 118 if(u32ChMask == I2S_RIGHT)
<> 144:ef7eb2e8f9f7 119 i2s->CTL &= ~I2S_CTL_RZCEN_Msk;
<> 144:ef7eb2e8f9f7 120 else
<> 144:ef7eb2e8f9f7 121 i2s->CTL &= ~I2S_CTL_LZCEN_Msk;
<> 144:ef7eb2e8f9f7 122 }
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
<> 144:ef7eb2e8f9f7 126 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 127 * @return none
<> 144:ef7eb2e8f9f7 128 * \hideinitializer
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 #define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL |= I2S_CTL_TXPDMAEN_Msk )
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /**
<> 144:ef7eb2e8f9f7 133 * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
<> 144:ef7eb2e8f9f7 134 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 135 * @return none
<> 144:ef7eb2e8f9f7 136 * \hideinitializer
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138 #define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL &= ~I2S_CTL_TXPDMAEN_Msk )
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /**
<> 144:ef7eb2e8f9f7 141 * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
<> 144:ef7eb2e8f9f7 142 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 143 * @return none
<> 144:ef7eb2e8f9f7 144 * \hideinitializer
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146 #define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL |= I2S_CTL_RXPDMAEN_Msk )
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /**
<> 144:ef7eb2e8f9f7 149 * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
<> 144:ef7eb2e8f9f7 150 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 151 * @return none
<> 144:ef7eb2e8f9f7 152 * \hideinitializer
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 #define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL &= ~I2S_CTL_RXPDMAEN_Msk )
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @brief Enable I2S Tx function .
<> 144:ef7eb2e8f9f7 158 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 159 * @return none
<> 144:ef7eb2e8f9f7 160 * \hideinitializer
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162 #define I2S_ENABLE_TX(i2s) ( (i2s)->CTL |= I2S_CTL_TXEN_Msk )
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /**
<> 144:ef7eb2e8f9f7 165 * @brief Disable I2S Tx function .
<> 144:ef7eb2e8f9f7 166 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 167 * @return none
<> 144:ef7eb2e8f9f7 168 * \hideinitializer
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170 #define I2S_DISABLE_TX(i2s) ( (i2s)->CTL &= ~I2S_CTL_TXEN_Msk )
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @brief Enable I2S Rx function .
<> 144:ef7eb2e8f9f7 174 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 175 * @return none
<> 144:ef7eb2e8f9f7 176 * \hideinitializer
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178 #define I2S_ENABLE_RX(i2s) ( (i2s)->CTL |= I2S_CTL_RXEN_Msk )
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /**
<> 144:ef7eb2e8f9f7 181 * @brief Disable I2S Rx function .
<> 144:ef7eb2e8f9f7 182 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 183 * @return none
<> 144:ef7eb2e8f9f7 184 * \hideinitializer
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186 #define I2S_DISABLE_RX(i2s) ( (i2s)->CTL &= ~I2S_CTL_RXEN_Msk )
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /**
<> 144:ef7eb2e8f9f7 189 * @brief Enable Tx Mute function .
<> 144:ef7eb2e8f9f7 190 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 191 * @return none
<> 144:ef7eb2e8f9f7 192 * \hideinitializer
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194 #define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL |= I2S_CTL_MUTE_Msk )
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /**
<> 144:ef7eb2e8f9f7 197 * @brief Disable Tx Mute function .
<> 144:ef7eb2e8f9f7 198 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 199 * @return none
<> 144:ef7eb2e8f9f7 200 * \hideinitializer
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 #define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL &= ~I2S_CTL_MUTE_Msk )
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /**
<> 144:ef7eb2e8f9f7 205 * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point.
<> 144:ef7eb2e8f9f7 206 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 207 * @return none
<> 144:ef7eb2e8f9f7 208 * \hideinitializer
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210 #define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL |= I2S_CTL_TXCLR_Msk )
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point.
<> 144:ef7eb2e8f9f7 214 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 215 * @return none
<> 144:ef7eb2e8f9f7 216 * \hideinitializer
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218 #define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL |= I2S_CTL_RXCLR_Msk )
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /**
<> 144:ef7eb2e8f9f7 221 * @brief This function sets the recording source channel when mono mode is used.
<> 144:ef7eb2e8f9f7 222 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 223 * @param[in] u32Ch left or right channel. Valid values are:
<> 144:ef7eb2e8f9f7 224 * - \ref I2S_MONO_LEFT
<> 144:ef7eb2e8f9f7 225 * - \ref I2S_MONO_RIGHT
<> 144:ef7eb2e8f9f7 226 * @return none
<> 144:ef7eb2e8f9f7 227 * \hideinitializer
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229 static __INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
<> 144:ef7eb2e8f9f7 230 {
<> 144:ef7eb2e8f9f7 231 u32Ch == I2S_MONO_LEFT ?
<> 144:ef7eb2e8f9f7 232 (i2s->CTL |= I2S_CTL_RXLCH_Msk) :
<> 144:ef7eb2e8f9f7 233 (i2s->CTL &= ~I2S_CTL_RXLCH_Msk);
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @brief Write data to I2S Tx FIFO.
<> 144:ef7eb2e8f9f7 238 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 239 * @param[in] u32Data: The data written to FIFO.
<> 144:ef7eb2e8f9f7 240 * @return none
<> 144:ef7eb2e8f9f7 241 * \hideinitializer
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 #define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = u32Data )
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @brief Read Rx FIFO.
<> 144:ef7eb2e8f9f7 247 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 248 * @return Data in Rx FIFO.
<> 144:ef7eb2e8f9f7 249 * \hideinitializer
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 #define I2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /**
<> 144:ef7eb2e8f9f7 254 * @brief This function gets the interrupt flag according to the mask parameter.
<> 144:ef7eb2e8f9f7 255 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 256 * @param[in] u32Mask is the mask for the all interrupt flags.
<> 144:ef7eb2e8f9f7 257 * @return The masked bit value of interrupt flag.
<> 144:ef7eb2e8f9f7 258 * \hideinitializer
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 #define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS & u32Mask )
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @brief This function clears the interrupt flag according to the mask parameter.
<> 144:ef7eb2e8f9f7 264 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 265 * @param[in] u32Mask is the mask for the all interrupt flags.
<> 144:ef7eb2e8f9f7 266 * @return none
<> 144:ef7eb2e8f9f7 267 * \hideinitializer
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269 #define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS |= u32Mask )
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /**
<> 144:ef7eb2e8f9f7 272 * @brief Get transmit FIFO level
<> 144:ef7eb2e8f9f7 273 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 274 * @return FIFO level
<> 144:ef7eb2e8f9f7 275 * \hideinitializer
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 #define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS & I2S_STATUS_TXCNT_Msk) >> I2S_STATUS_TXCNT_Pos) & 0xF )
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @brief Get receive FIFO level
<> 144:ef7eb2e8f9f7 281 * @param[in] i2s is the base address of I2S module.
<> 144:ef7eb2e8f9f7 282 * @return FIFO level
<> 144:ef7eb2e8f9f7 283 * \hideinitializer
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 #define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS & I2S_STATUS_RXCNT_Msk) >> I2S_STATUS_RXCNT_Pos) & 0xF )
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat, uint32_t u32AudioInterface);
<> 144:ef7eb2e8f9f7 288 void I2S_Close(I2S_T *i2s);
<> 144:ef7eb2e8f9f7 289 void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
<> 144:ef7eb2e8f9f7 290 void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
<> 144:ef7eb2e8f9f7 291 uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
<> 144:ef7eb2e8f9f7 292 void I2S_DisableMCLK(I2S_T *i2s);
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /*@}*/ /* end of group NUC472_442_I2S_EXPORTED_FUNCTIONS */
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /*@}*/ /* end of group NUC472_442_I2S_Driver */
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /*@}*/ /* end of group NUC472_442_Device_Driver */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 302 }
<> 144:ef7eb2e8f9f7 303 #endif
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 #endif
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
<> 144:ef7eb2e8f9f7 308