Iftikhar Aziz / mbed-dev

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Dependents:   LSS_Rev_1

Fork of mbed-dev by Umar Naeem

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c@19:112740acecfa, 2015-11-10 (annotated)

Committer:
mbed_official
Date:
Tue Nov 10 09:30:11 2015 +0000
Revision:
19:112740acecfa
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision 7218418919aeaf775fb8d386ea7ee0dfc0c80ff9



Full URL: https://github.com/mbedmicro/mbed/commit/7218418919aeaf775fb8d386ea7ee0dfc0c80ff9/



DISCO_F469NI - add disco F469NI support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx_hal_i2s_ex.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 19:112740acecfa 5 * @version V1.4.1
mbed_official 19:112740acecfa 6 * @date 09-October-2015
bogdanm 0:9b334a45a8ff 7 * @brief I2S HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities of I2S extension peripheral:
bogdanm 0:9b334a45a8ff 10 * + Extension features Functions
bogdanm 0:9b334a45a8ff 11 *
bogdanm 0:9b334a45a8ff 12 @verbatim
bogdanm 0:9b334a45a8ff 13 ==============================================================================
bogdanm 0:9b334a45a8ff 14 ##### I2S Extension features #####
bogdanm 0:9b334a45a8ff 15 ==============================================================================
bogdanm 0:9b334a45a8ff 16 [..]
bogdanm 0:9b334a45a8ff 17 (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
bogdanm 0:9b334a45a8ff 18 data simultaneously using two data lines. Each SPI peripheral has an extended block
bogdanm 0:9b334a45a8ff 19 called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
bogdanm 0:9b334a45a8ff 20 (#) The extension block is not a full SPI IP, it is used only as I2S slave to
bogdanm 0:9b334a45a8ff 21 implement full duplex mode. The extension block uses the same clock sources
bogdanm 0:9b334a45a8ff 22 as its master.
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 [..]
bogdanm 0:9b334a45a8ff 27 (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
bogdanm 0:9b334a45a8ff 28 I2Sx can be I2S2 or I2S3.
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 31 ===============================================================================
bogdanm 0:9b334a45a8ff 32 [..]
bogdanm 0:9b334a45a8ff 33 Three operation modes are available within this driver :
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 *** Polling mode IO operation ***
bogdanm 0:9b334a45a8ff 36 =================================
bogdanm 0:9b334a45a8ff 37 [..]
bogdanm 0:9b334a45a8ff 38 (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 *** Interrupt mode IO operation ***
bogdanm 0:9b334a45a8ff 41 ===================================
bogdanm 0:9b334a45a8ff 42 [..]
bogdanm 0:9b334a45a8ff 43 (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
bogdanm 0:9b334a45a8ff 44 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 45 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm 0:9b334a45a8ff 46 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 47 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm 0:9b334a45a8ff 48 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 49 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm 0:9b334a45a8ff 50 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 51 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm 0:9b334a45a8ff 52 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm 0:9b334a45a8ff 53 add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 *** DMA mode IO operation ***
bogdanm 0:9b334a45a8ff 56 ==============================
bogdanm 0:9b334a45a8ff 57 [..]
bogdanm 0:9b334a45a8ff 58 (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
bogdanm 0:9b334a45a8ff 59 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 60 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm 0:9b334a45a8ff 61 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 62 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm 0:9b334a45a8ff 63 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 64 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm 0:9b334a45a8ff 65 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm 0:9b334a45a8ff 66 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm 0:9b334a45a8ff 67 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm 0:9b334a45a8ff 68 add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm 0:9b334a45a8ff 69 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
bogdanm 0:9b334a45a8ff 70 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
bogdanm 0:9b334a45a8ff 71 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 @endverbatim
bogdanm 0:9b334a45a8ff 74 ******************************************************************************
bogdanm 0:9b334a45a8ff 75 * @attention
bogdanm 0:9b334a45a8ff 76 *
bogdanm 0:9b334a45a8ff 77 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 78 *
bogdanm 0:9b334a45a8ff 79 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 80 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 81 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 82 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 83 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 84 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 85 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 86 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 87 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 88 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 89 *
bogdanm 0:9b334a45a8ff 90 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 91 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 92 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 93 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 94 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 95 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 96 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 97 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 98 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 99 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 100 *
bogdanm 0:9b334a45a8ff 101 ******************************************************************************
bogdanm 0:9b334a45a8ff 102 */
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 105 #include "stm32f4xx_hal.h"
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 108 * @{
bogdanm 0:9b334a45a8ff 109 */
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 /** @defgroup I2SEx I2SEx
bogdanm 0:9b334a45a8ff 112 * @brief I2S HAL module driver
bogdanm 0:9b334a45a8ff 113 * @{
bogdanm 0:9b334a45a8ff 114 */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 #ifdef HAL_I2S_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 117 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 118 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 119 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 120 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 121 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 122 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 123 /** @addtogroup I2SEx_Private_Functions
bogdanm 0:9b334a45a8ff 124 * @{
bogdanm 0:9b334a45a8ff 125 */
bogdanm 0:9b334a45a8ff 126 /**
bogdanm 0:9b334a45a8ff 127 * @}
bogdanm 0:9b334a45a8ff 128 */
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 131 /** @defgroup I2SEx_Exported_Functions I2S Exported Functions
bogdanm 0:9b334a45a8ff 132 * @{
bogdanm 0:9b334a45a8ff 133 */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /** @defgroup I2SEx_Group1 Extension features functions
bogdanm 0:9b334a45a8ff 136 * @brief Extension features functions
bogdanm 0:9b334a45a8ff 137 *
bogdanm 0:9b334a45a8ff 138 @verbatim
bogdanm 0:9b334a45a8ff 139 ===============================================================================
bogdanm 0:9b334a45a8ff 140 ##### Extension features Functions #####
bogdanm 0:9b334a45a8ff 141 ===============================================================================
bogdanm 0:9b334a45a8ff 142 [..]
bogdanm 0:9b334a45a8ff 143 This subsection provides a set of functions allowing to manage the I2S data
bogdanm 0:9b334a45a8ff 144 transfers.
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 (#) There are two modes of transfer:
bogdanm 0:9b334a45a8ff 147 (++) Blocking mode : The communication is performed in the polling mode.
bogdanm 0:9b334a45a8ff 148 The status of all data processing is returned by the same function
bogdanm 0:9b334a45a8ff 149 after finishing transfer.
bogdanm 0:9b334a45a8ff 150 (++) No-Blocking mode : The communication is performed using Interrupts
bogdanm 0:9b334a45a8ff 151 or DMA. These functions return the status of the transfer startup.
bogdanm 0:9b334a45a8ff 152 The end of the data processing will be indicated through the
bogdanm 0:9b334a45a8ff 153 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
bogdanm 0:9b334a45a8ff 154 using DMA mode.
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 (#) Blocking mode functions are :
bogdanm 0:9b334a45a8ff 157 (++) HAL_I2S_TransmitReceive()
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 (#) No-Blocking mode functions with Interrupt are :
bogdanm 0:9b334a45a8ff 160 (++) HAL_I2S_TransmitReceive_IT()
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 (#) No-Blocking mode functions with DMA are :
bogdanm 0:9b334a45a8ff 163 (++) HAL_I2S_TransmitReceive_DMA()
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
bogdanm 0:9b334a45a8ff 166 (++) HAL_I2S_TxCpltCallback()
bogdanm 0:9b334a45a8ff 167 (++) HAL_I2S_RxCpltCallback()
bogdanm 0:9b334a45a8ff 168 (++) HAL_I2S_ErrorCallback()
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 @endverbatim
bogdanm 0:9b334a45a8ff 171 * @{
bogdanm 0:9b334a45a8ff 172 */
mbed_official 19:112740acecfa 173 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
mbed_official 19:112740acecfa 174 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
mbed_official 19:112740acecfa 175 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
mbed_official 19:112740acecfa 176 defined(STM32F479xx)
bogdanm 0:9b334a45a8ff 177 /**
bogdanm 0:9b334a45a8ff 178 * @brief Initializes the I2S according to the specified parameters
bogdanm 0:9b334a45a8ff 179 * in the I2S_InitTypeDef and create the associated handle.
bogdanm 0:9b334a45a8ff 180 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 181 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 182 * @retval HAL status
bogdanm 0:9b334a45a8ff 183 */
bogdanm 0:9b334a45a8ff 184 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 185 {
bogdanm 0:9b334a45a8ff 186 uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
bogdanm 0:9b334a45a8ff 187 uint32_t tmp = 0, i2sclk = 0;
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 /* Check the I2S handle allocation */
bogdanm 0:9b334a45a8ff 190 if(hi2s == NULL)
bogdanm 0:9b334a45a8ff 191 {
bogdanm 0:9b334a45a8ff 192 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 193 }
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 /* Check the I2S parameters */
bogdanm 0:9b334a45a8ff 196 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
bogdanm 0:9b334a45a8ff 197 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
bogdanm 0:9b334a45a8ff 198 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
bogdanm 0:9b334a45a8ff 199 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
bogdanm 0:9b334a45a8ff 200 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
bogdanm 0:9b334a45a8ff 201 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
bogdanm 0:9b334a45a8ff 202 assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 if(hi2s->State == HAL_I2S_STATE_RESET)
bogdanm 0:9b334a45a8ff 205 {
bogdanm 0:9b334a45a8ff 206 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 207 hi2s->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 208 /* Init the low level hardware : GPIO, CLOCK, CORTEX */
bogdanm 0:9b334a45a8ff 209 HAL_I2S_MspInit(hi2s);
bogdanm 0:9b334a45a8ff 210 }
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 hi2s->State = HAL_I2S_STATE_BUSY;
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
bogdanm 0:9b334a45a8ff 215 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
bogdanm 0:9b334a45a8ff 216 hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
bogdanm 0:9b334a45a8ff 217 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
bogdanm 0:9b334a45a8ff 218 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
bogdanm 0:9b334a45a8ff 219 hi2s->Instance->I2SPR = 0x0002;
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 /* Get the I2SCFGR register value */
bogdanm 0:9b334a45a8ff 222 tmpreg = hi2s->Instance->I2SCFGR;
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
bogdanm 0:9b334a45a8ff 225 /* If the requested audio frequency is not the default, compute the prescaler */
bogdanm 0:9b334a45a8ff 226 if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
bogdanm 0:9b334a45a8ff 227 {
bogdanm 0:9b334a45a8ff 228 /* Check the frame length (For the Prescaler computing) *******************/
bogdanm 0:9b334a45a8ff 229 if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
bogdanm 0:9b334a45a8ff 230 {
bogdanm 0:9b334a45a8ff 231 /* Packet length is 32 bits */
bogdanm 0:9b334a45a8ff 232 packetlength = 2;
bogdanm 0:9b334a45a8ff 233 }
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 /* Get I2S source Clock frequency ****************************************/
bogdanm 0:9b334a45a8ff 236 i2sclk = I2S_GetInputClock(hi2s);
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 /* Compute the Real divider depending on the MCLK output state, with a floating point */
bogdanm 0:9b334a45a8ff 239 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
bogdanm 0:9b334a45a8ff 240 {
bogdanm 0:9b334a45a8ff 241 /* MCLK output is enabled */
bogdanm 0:9b334a45a8ff 242 tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
bogdanm 0:9b334a45a8ff 243 }
bogdanm 0:9b334a45a8ff 244 else
bogdanm 0:9b334a45a8ff 245 {
bogdanm 0:9b334a45a8ff 246 /* MCLK output is disabled */
bogdanm 0:9b334a45a8ff 247 tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
bogdanm 0:9b334a45a8ff 248 }
bogdanm 0:9b334a45a8ff 249
bogdanm 0:9b334a45a8ff 250 /* Remove the flatting point */
bogdanm 0:9b334a45a8ff 251 tmp = tmp / 10;
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 /* Check the parity of the divider */
bogdanm 0:9b334a45a8ff 254 i2sodd = (uint32_t)(tmp & (uint32_t)1);
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 /* Compute the i2sdiv prescaler */
bogdanm 0:9b334a45a8ff 257 i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
bogdanm 0:9b334a45a8ff 260 i2sodd = (uint32_t) (i2sodd << 8);
bogdanm 0:9b334a45a8ff 261 }
bogdanm 0:9b334a45a8ff 262
bogdanm 0:9b334a45a8ff 263 /* Test if the divider is 1 or 0 or greater than 0xFF */
bogdanm 0:9b334a45a8ff 264 if((i2sdiv < 2) || (i2sdiv > 0xFF))
bogdanm 0:9b334a45a8ff 265 {
bogdanm 0:9b334a45a8ff 266 /* Set the default values */
bogdanm 0:9b334a45a8ff 267 i2sdiv = 2;
bogdanm 0:9b334a45a8ff 268 i2sodd = 0;
bogdanm 0:9b334a45a8ff 269 }
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /* Write to SPIx I2SPR register the computed value */
bogdanm 0:9b334a45a8ff 272 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /* Configure the I2S with the I2S_InitStruct values */
bogdanm 0:9b334a45a8ff 275 tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 #if defined(SPI_I2SCFGR_ASTRTEN)
bogdanm 0:9b334a45a8ff 278 if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT)
bogdanm 0:9b334a45a8ff 279 {
bogdanm 0:9b334a45a8ff 280 /* Write to SPIx I2SCFGR */
bogdanm 0:9b334a45a8ff 281 hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
bogdanm 0:9b334a45a8ff 282 }
bogdanm 0:9b334a45a8ff 283 else
bogdanm 0:9b334a45a8ff 284 {
bogdanm 0:9b334a45a8ff 285 /* Write to SPIx I2SCFGR */
bogdanm 0:9b334a45a8ff 286 hi2s->Instance->I2SCFGR = tmpreg;
bogdanm 0:9b334a45a8ff 287 }
bogdanm 0:9b334a45a8ff 288 #else
bogdanm 0:9b334a45a8ff 289 /* Write to SPIx I2SCFGR */
bogdanm 0:9b334a45a8ff 290 hi2s->Instance->I2SCFGR = tmpreg;
bogdanm 0:9b334a45a8ff 291 #endif
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 /* Configure the I2S extended if the full duplex mode is enabled */
bogdanm 0:9b334a45a8ff 294 assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
bogdanm 0:9b334a45a8ff 295 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
bogdanm 0:9b334a45a8ff 296 {
bogdanm 0:9b334a45a8ff 297 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
bogdanm 0:9b334a45a8ff 298 I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
bogdanm 0:9b334a45a8ff 299 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
bogdanm 0:9b334a45a8ff 300 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
bogdanm 0:9b334a45a8ff 301 I2SxEXT(hi2s->Instance)->I2SPR = 2;
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303 /* Get the I2SCFGR register value */
bogdanm 0:9b334a45a8ff 304 tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
bogdanm 0:9b334a45a8ff 305
bogdanm 0:9b334a45a8ff 306 /* Get the mode to be configured for the extended I2S */
bogdanm 0:9b334a45a8ff 307 if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
bogdanm 0:9b334a45a8ff 308 {
bogdanm 0:9b334a45a8ff 309 tmp = I2S_MODE_SLAVE_RX;
bogdanm 0:9b334a45a8ff 310 }
bogdanm 0:9b334a45a8ff 311 else
bogdanm 0:9b334a45a8ff 312 {
bogdanm 0:9b334a45a8ff 313 if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
bogdanm 0:9b334a45a8ff 314 {
bogdanm 0:9b334a45a8ff 315 tmp = I2S_MODE_SLAVE_TX;
bogdanm 0:9b334a45a8ff 316 }
bogdanm 0:9b334a45a8ff 317 }
bogdanm 0:9b334a45a8ff 318
bogdanm 0:9b334a45a8ff 319 /* Configure the I2S Slave with the I2S Master parameter values */
bogdanm 0:9b334a45a8ff 320 tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 /* Write to SPIx I2SCFGR */
bogdanm 0:9b334a45a8ff 323 I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
bogdanm 0:9b334a45a8ff 324 }
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 327 hi2s->State= HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 return HAL_OK;
bogdanm 0:9b334a45a8ff 330 }
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 /**
bogdanm 0:9b334a45a8ff 333 * @brief Full-Duplex Transmit/Receive data in blocking mode.
bogdanm 0:9b334a45a8ff 334 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 335 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 336 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
bogdanm 0:9b334a45a8ff 337 * @param pRxData: a 16-bit pointer to the Receive data buffer.
bogdanm 0:9b334a45a8ff 338 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 339 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 340 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 341 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 342 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 343 * @param Timeout: Timeout duration
bogdanm 0:9b334a45a8ff 344 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 345 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 346 * @retval HAL status
bogdanm 0:9b334a45a8ff 347 */
bogdanm 0:9b334a45a8ff 348 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 349 {
bogdanm 0:9b334a45a8ff 350 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 351 uint32_t tmp1 = 0, tmp2 = 0;
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
bogdanm 0:9b334a45a8ff 354 {
bogdanm 0:9b334a45a8ff 355 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 356 }
bogdanm 0:9b334a45a8ff 357
bogdanm 0:9b334a45a8ff 358 /* Check the I2S State */
bogdanm 0:9b334a45a8ff 359 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 360 {
bogdanm 0:9b334a45a8ff 361 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
bogdanm 0:9b334a45a8ff 362 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
bogdanm 0:9b334a45a8ff 363 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
bogdanm 0:9b334a45a8ff 364 is selected during the I2S configuration phase, the Size parameter means the number
bogdanm 0:9b334a45a8ff 365 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
bogdanm 0:9b334a45a8ff 366 frame is selected the Size parameter means the number of 16-bit data length. */
bogdanm 0:9b334a45a8ff 367 if((tmp1 == I2S_DATAFORMAT_24B)|| \
bogdanm 0:9b334a45a8ff 368 (tmp2 == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 369 {
bogdanm 0:9b334a45a8ff 370 hi2s->TxXferSize = Size*2;
bogdanm 0:9b334a45a8ff 371 hi2s->TxXferCount = Size*2;
bogdanm 0:9b334a45a8ff 372 hi2s->RxXferSize = Size*2;
bogdanm 0:9b334a45a8ff 373 hi2s->RxXferCount = Size*2;
bogdanm 0:9b334a45a8ff 374 }
bogdanm 0:9b334a45a8ff 375 else
bogdanm 0:9b334a45a8ff 376 {
bogdanm 0:9b334a45a8ff 377 hi2s->TxXferSize = Size;
bogdanm 0:9b334a45a8ff 378 hi2s->TxXferCount = Size;
bogdanm 0:9b334a45a8ff 379 hi2s->RxXferSize = Size;
bogdanm 0:9b334a45a8ff 380 hi2s->RxXferCount = Size;
bogdanm 0:9b334a45a8ff 381 }
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 /* Process Locked */
bogdanm 0:9b334a45a8ff 384 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /* Set the I2S State busy TX/RX */
bogdanm 0:9b334a45a8ff 387 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 390 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 391 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
bogdanm 0:9b334a45a8ff 392 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
bogdanm 0:9b334a45a8ff 393 {
bogdanm 0:9b334a45a8ff 394 /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
bogdanm 0:9b334a45a8ff 395 to avoid the clock de-synchronization between Master and Slave. */
bogdanm 0:9b334a45a8ff 396 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 397 {
bogdanm 0:9b334a45a8ff 398 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
bogdanm 0:9b334a45a8ff 399 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 /* Enable I2Sx peripheral */
bogdanm 0:9b334a45a8ff 402 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 403 }
bogdanm 0:9b334a45a8ff 404
bogdanm 0:9b334a45a8ff 405 while(hi2s->TxXferCount > 0)
bogdanm 0:9b334a45a8ff 406 {
bogdanm 0:9b334a45a8ff 407 /* Wait until TXE flag is set */
bogdanm 0:9b334a45a8ff 408 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 409 {
bogdanm 0:9b334a45a8ff 410 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 411 }
bogdanm 0:9b334a45a8ff 412 hi2s->Instance->DR = (*pTxData++);
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /* Get tick */
bogdanm 0:9b334a45a8ff 415 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /* Wait until RXNE flag is set */
bogdanm 0:9b334a45a8ff 418 while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE)
bogdanm 0:9b334a45a8ff 419 {
bogdanm 0:9b334a45a8ff 420 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 421 {
bogdanm 0:9b334a45a8ff 422 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 423 {
bogdanm 0:9b334a45a8ff 424 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 425 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 428 }
bogdanm 0:9b334a45a8ff 429 }
bogdanm 0:9b334a45a8ff 430 }
bogdanm 0:9b334a45a8ff 431 (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
bogdanm 0:9b334a45a8ff 432
bogdanm 0:9b334a45a8ff 433 hi2s->TxXferCount--;
bogdanm 0:9b334a45a8ff 434 hi2s->RxXferCount--;
bogdanm 0:9b334a45a8ff 435 }
bogdanm 0:9b334a45a8ff 436 }
bogdanm 0:9b334a45a8ff 437 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
bogdanm 0:9b334a45a8ff 438 else
bogdanm 0:9b334a45a8ff 439 {
bogdanm 0:9b334a45a8ff 440 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 441 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 442 {
bogdanm 0:9b334a45a8ff 443 /* Enable I2S peripheral before the I2Sext*/
bogdanm 0:9b334a45a8ff 444 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
bogdanm 0:9b334a45a8ff 447 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
bogdanm 0:9b334a45a8ff 448 }
bogdanm 0:9b334a45a8ff 449 else
bogdanm 0:9b334a45a8ff 450 {
bogdanm 0:9b334a45a8ff 451 /* Check if Master Receiver mode is selected */
bogdanm 0:9b334a45a8ff 452 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm 0:9b334a45a8ff 453 {
bogdanm 0:9b334a45a8ff 454 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
bogdanm 0:9b334a45a8ff 455 access to the SPI_SR register. */
bogdanm 0:9b334a45a8ff 456 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm 0:9b334a45a8ff 457 }
bogdanm 0:9b334a45a8ff 458 }
bogdanm 0:9b334a45a8ff 459 while(hi2s->TxXferCount > 0)
bogdanm 0:9b334a45a8ff 460 {
bogdanm 0:9b334a45a8ff 461 /* Get tick */
bogdanm 0:9b334a45a8ff 462 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 /* Wait until TXE flag is set */
bogdanm 0:9b334a45a8ff 465 while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE)
bogdanm 0:9b334a45a8ff 466 {
bogdanm 0:9b334a45a8ff 467 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 468 {
bogdanm 0:9b334a45a8ff 469 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 470 {
bogdanm 0:9b334a45a8ff 471 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 472 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 475 }
bogdanm 0:9b334a45a8ff 476 }
bogdanm 0:9b334a45a8ff 477 }
bogdanm 0:9b334a45a8ff 478 I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 /* Wait until RXNE flag is set */
bogdanm 0:9b334a45a8ff 481 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm 0:9b334a45a8ff 482 {
bogdanm 0:9b334a45a8ff 483 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 484 }
bogdanm 0:9b334a45a8ff 485 (*pRxData++) = hi2s->Instance->DR;
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 hi2s->TxXferCount--;
bogdanm 0:9b334a45a8ff 488 hi2s->RxXferCount--;
bogdanm 0:9b334a45a8ff 489 }
bogdanm 0:9b334a45a8ff 490 }
bogdanm 0:9b334a45a8ff 491
bogdanm 0:9b334a45a8ff 492 /* Set the I2S State ready */
bogdanm 0:9b334a45a8ff 493 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 496 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 return HAL_OK;
bogdanm 0:9b334a45a8ff 499 }
bogdanm 0:9b334a45a8ff 500 else
bogdanm 0:9b334a45a8ff 501 {
bogdanm 0:9b334a45a8ff 502 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 503 }
bogdanm 0:9b334a45a8ff 504 }
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 /**
bogdanm 0:9b334a45a8ff 507 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
bogdanm 0:9b334a45a8ff 508 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 509 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 510 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
bogdanm 0:9b334a45a8ff 511 * @param pRxData: a 16-bit pointer to the Receive data buffer.
bogdanm 0:9b334a45a8ff 512 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 513 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 514 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 515 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 516 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 517 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 518 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 519 * @retval HAL status
bogdanm 0:9b334a45a8ff 520 */
bogdanm 0:9b334a45a8ff 521 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
bogdanm 0:9b334a45a8ff 522 {
bogdanm 0:9b334a45a8ff 523 uint32_t tmp1 = 0, tmp2 = 0;
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 526 {
bogdanm 0:9b334a45a8ff 527 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
bogdanm 0:9b334a45a8ff 528 {
bogdanm 0:9b334a45a8ff 529 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 530 }
bogdanm 0:9b334a45a8ff 531
bogdanm 0:9b334a45a8ff 532 hi2s->pTxBuffPtr = pTxData;
bogdanm 0:9b334a45a8ff 533 hi2s->pRxBuffPtr = pRxData;
bogdanm 0:9b334a45a8ff 534
bogdanm 0:9b334a45a8ff 535 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
bogdanm 0:9b334a45a8ff 536 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
bogdanm 0:9b334a45a8ff 537 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
bogdanm 0:9b334a45a8ff 538 is selected during the I2S configuration phase, the Size parameter means the number
bogdanm 0:9b334a45a8ff 539 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
bogdanm 0:9b334a45a8ff 540 frame is selected the Size parameter means the number of 16-bit data length. */
bogdanm 0:9b334a45a8ff 541 if((tmp1 == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 542 (tmp2 == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 543 {
bogdanm 0:9b334a45a8ff 544 hi2s->TxXferSize = Size*2;
bogdanm 0:9b334a45a8ff 545 hi2s->TxXferCount = Size*2;
bogdanm 0:9b334a45a8ff 546 hi2s->RxXferSize = Size*2;
bogdanm 0:9b334a45a8ff 547 hi2s->RxXferCount = Size*2;
bogdanm 0:9b334a45a8ff 548 }
bogdanm 0:9b334a45a8ff 549 else
bogdanm 0:9b334a45a8ff 550 {
bogdanm 0:9b334a45a8ff 551 hi2s->TxXferSize = Size;
bogdanm 0:9b334a45a8ff 552 hi2s->TxXferCount = Size;
bogdanm 0:9b334a45a8ff 553 hi2s->RxXferSize = Size;
bogdanm 0:9b334a45a8ff 554 hi2s->RxXferCount = Size;
bogdanm 0:9b334a45a8ff 555 }
bogdanm 0:9b334a45a8ff 556
bogdanm 0:9b334a45a8ff 557 /* Process Locked */
bogdanm 0:9b334a45a8ff 558 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
bogdanm 0:9b334a45a8ff 561 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 564 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 565 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
bogdanm 0:9b334a45a8ff 566 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
bogdanm 0:9b334a45a8ff 567 {
bogdanm 0:9b334a45a8ff 568 /* Enable I2Sext RXNE and ERR interrupts */
bogdanm 0:9b334a45a8ff 569 I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_RXNE | I2S_IT_ERR);
bogdanm 0:9b334a45a8ff 570
bogdanm 0:9b334a45a8ff 571 /* Enable I2Sx TXE and ERR interrupts */
bogdanm 0:9b334a45a8ff 572 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 573
bogdanm 0:9b334a45a8ff 574 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 575 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 576 {
bogdanm 0:9b334a45a8ff 577 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
bogdanm 0:9b334a45a8ff 578 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
bogdanm 0:9b334a45a8ff 579
bogdanm 0:9b334a45a8ff 580 /* Enable I2Sx peripheral */
bogdanm 0:9b334a45a8ff 581 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 582 }
bogdanm 0:9b334a45a8ff 583 }
bogdanm 0:9b334a45a8ff 584 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
bogdanm 0:9b334a45a8ff 585 else
bogdanm 0:9b334a45a8ff 586 {
bogdanm 0:9b334a45a8ff 587 /* Enable I2Sext TXE and ERR interrupts */
bogdanm 0:9b334a45a8ff 588 I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_TXE |I2S_IT_ERR);
bogdanm 0:9b334a45a8ff 589
bogdanm 0:9b334a45a8ff 590 /* Enable I2Sext RXNE and ERR interrupts */
bogdanm 0:9b334a45a8ff 591 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
bogdanm 0:9b334a45a8ff 592
bogdanm 0:9b334a45a8ff 593 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 594 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 595 {
bogdanm 0:9b334a45a8ff 596 /* Check if the I2S_MODE_MASTER_RX is selected */
bogdanm 0:9b334a45a8ff 597 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm 0:9b334a45a8ff 598 {
bogdanm 0:9b334a45a8ff 599 /* Prepare the First Data before enabling the I2S */
bogdanm 0:9b334a45a8ff 600 if(hi2s->TxXferCount != 0)
bogdanm 0:9b334a45a8ff 601 {
bogdanm 0:9b334a45a8ff 602 /* Transmit First data */
bogdanm 0:9b334a45a8ff 603 I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
bogdanm 0:9b334a45a8ff 604 hi2s->TxXferCount--;
bogdanm 0:9b334a45a8ff 605
bogdanm 0:9b334a45a8ff 606 if(hi2s->TxXferCount == 0)
bogdanm 0:9b334a45a8ff 607 {
bogdanm 0:9b334a45a8ff 608 /* Disable I2Sext TXE interrupt */
bogdanm 0:9b334a45a8ff 609 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
bogdanm 0:9b334a45a8ff 610 }
bogdanm 0:9b334a45a8ff 611 }
bogdanm 0:9b334a45a8ff 612 }
bogdanm 0:9b334a45a8ff 613 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 614 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
bogdanm 0:9b334a45a8ff 617 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
bogdanm 0:9b334a45a8ff 618 }
bogdanm 0:9b334a45a8ff 619 }
bogdanm 0:9b334a45a8ff 620 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 621 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 return HAL_OK;
bogdanm 0:9b334a45a8ff 624 }
bogdanm 0:9b334a45a8ff 625 else
bogdanm 0:9b334a45a8ff 626 {
bogdanm 0:9b334a45a8ff 627 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 628 }
bogdanm 0:9b334a45a8ff 629 }
bogdanm 0:9b334a45a8ff 630
bogdanm 0:9b334a45a8ff 631 /**
bogdanm 0:9b334a45a8ff 632 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
bogdanm 0:9b334a45a8ff 633 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 634 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 635 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
bogdanm 0:9b334a45a8ff 636 * @param pRxData: a 16-bit pointer to the Receive data buffer.
bogdanm 0:9b334a45a8ff 637 * @param Size: number of data sample to be sent:
bogdanm 0:9b334a45a8ff 638 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm 0:9b334a45a8ff 639 * configuration phase, the Size parameter means the number of 16-bit data length
bogdanm 0:9b334a45a8ff 640 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm 0:9b334a45a8ff 641 * the Size parameter means the number of 16-bit data length.
bogdanm 0:9b334a45a8ff 642 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm 0:9b334a45a8ff 643 * between Master and Slave(example: audio streaming).
bogdanm 0:9b334a45a8ff 644 * @retval HAL status
bogdanm 0:9b334a45a8ff 645 */
bogdanm 0:9b334a45a8ff 646 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
bogdanm 0:9b334a45a8ff 647 {
bogdanm 0:9b334a45a8ff 648 uint32_t *tmp;
bogdanm 0:9b334a45a8ff 649 uint32_t tmp1 = 0, tmp2 = 0;
bogdanm 0:9b334a45a8ff 650
bogdanm 0:9b334a45a8ff 651 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
bogdanm 0:9b334a45a8ff 652 {
bogdanm 0:9b334a45a8ff 653 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 654 }
bogdanm 0:9b334a45a8ff 655
bogdanm 0:9b334a45a8ff 656 if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm 0:9b334a45a8ff 657 {
bogdanm 0:9b334a45a8ff 658 hi2s->pTxBuffPtr = pTxData;
bogdanm 0:9b334a45a8ff 659 hi2s->pRxBuffPtr = pRxData;
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
bogdanm 0:9b334a45a8ff 662 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
bogdanm 0:9b334a45a8ff 663 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
bogdanm 0:9b334a45a8ff 664 is selected during the I2S configuration phase, the Size parameter means the number
bogdanm 0:9b334a45a8ff 665 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
bogdanm 0:9b334a45a8ff 666 frame is selected the Size parameter means the number of 16-bit data length. */
bogdanm 0:9b334a45a8ff 667 if((tmp1 == I2S_DATAFORMAT_24B)||\
bogdanm 0:9b334a45a8ff 668 (tmp2 == I2S_DATAFORMAT_32B))
bogdanm 0:9b334a45a8ff 669 {
bogdanm 0:9b334a45a8ff 670 hi2s->TxXferSize = Size*2;
bogdanm 0:9b334a45a8ff 671 hi2s->TxXferCount = Size*2;
bogdanm 0:9b334a45a8ff 672 hi2s->RxXferSize = Size*2;
bogdanm 0:9b334a45a8ff 673 hi2s->RxXferCount = Size*2;
bogdanm 0:9b334a45a8ff 674 }
bogdanm 0:9b334a45a8ff 675 else
bogdanm 0:9b334a45a8ff 676 {
bogdanm 0:9b334a45a8ff 677 hi2s->TxXferSize = Size;
bogdanm 0:9b334a45a8ff 678 hi2s->TxXferCount = Size;
bogdanm 0:9b334a45a8ff 679 hi2s->RxXferSize = Size;
bogdanm 0:9b334a45a8ff 680 hi2s->RxXferCount = Size;
bogdanm 0:9b334a45a8ff 681 }
bogdanm 0:9b334a45a8ff 682
bogdanm 0:9b334a45a8ff 683 /* Process Locked */
bogdanm 0:9b334a45a8ff 684 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 685
bogdanm 0:9b334a45a8ff 686 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
bogdanm 0:9b334a45a8ff 687 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm 0:9b334a45a8ff 688
bogdanm 0:9b334a45a8ff 689 /* Set the I2S Rx DMA Half transfer complete callback */
bogdanm 0:9b334a45a8ff 690 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 /* Set the I2S Rx DMA transfer complete callback */
bogdanm 0:9b334a45a8ff 693 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695 /* Set the I2S Rx DMA error callback */
bogdanm 0:9b334a45a8ff 696 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
bogdanm 0:9b334a45a8ff 697
bogdanm 0:9b334a45a8ff 698 /* Set the I2S Tx DMA Half transfer complete callback */
bogdanm 0:9b334a45a8ff 699 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 /* Set the I2S Tx DMA transfer complete callback */
bogdanm 0:9b334a45a8ff 702 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704 /* Set the I2S Tx DMA error callback */
bogdanm 0:9b334a45a8ff 705 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
bogdanm 0:9b334a45a8ff 706
bogdanm 0:9b334a45a8ff 707 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 708 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 709 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
bogdanm 0:9b334a45a8ff 710 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
bogdanm 0:9b334a45a8ff 711 {
bogdanm 0:9b334a45a8ff 712 /* Enable the Rx DMA Stream */
bogdanm 0:9b334a45a8ff 713 tmp = (uint32_t*)&pRxData;
bogdanm 0:9b334a45a8ff 714 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716 /* Enable Rx DMA Request */
bogdanm 0:9b334a45a8ff 717 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
bogdanm 0:9b334a45a8ff 718
bogdanm 0:9b334a45a8ff 719 /* Enable the Tx DMA Stream */
bogdanm 0:9b334a45a8ff 720 tmp = (uint32_t*)&pTxData;
bogdanm 0:9b334a45a8ff 721 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
bogdanm 0:9b334a45a8ff 722
bogdanm 0:9b334a45a8ff 723 /* Enable Tx DMA Request */
bogdanm 0:9b334a45a8ff 724 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
bogdanm 0:9b334a45a8ff 725
bogdanm 0:9b334a45a8ff 726 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 727 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 728 {
bogdanm 0:9b334a45a8ff 729 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
bogdanm 0:9b334a45a8ff 730 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
bogdanm 0:9b334a45a8ff 731
bogdanm 0:9b334a45a8ff 732 /* Enable I2S peripheral after the I2Sext */
bogdanm 0:9b334a45a8ff 733 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 734 }
bogdanm 0:9b334a45a8ff 735 }
bogdanm 0:9b334a45a8ff 736 else
bogdanm 0:9b334a45a8ff 737 {
bogdanm 0:9b334a45a8ff 738 /* Enable the Tx DMA Stream */
bogdanm 0:9b334a45a8ff 739 tmp = (uint32_t*)&pTxData;
bogdanm 0:9b334a45a8ff 740 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
bogdanm 0:9b334a45a8ff 741
bogdanm 0:9b334a45a8ff 742 /* Enable Tx DMA Request */
bogdanm 0:9b334a45a8ff 743 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
bogdanm 0:9b334a45a8ff 744
bogdanm 0:9b334a45a8ff 745 /* Enable the Rx DMA Stream */
bogdanm 0:9b334a45a8ff 746 tmp = (uint32_t*)&pRxData;
bogdanm 0:9b334a45a8ff 747 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
bogdanm 0:9b334a45a8ff 748
bogdanm 0:9b334a45a8ff 749 /* Enable Rx DMA Request */
bogdanm 0:9b334a45a8ff 750 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 /* Check if the I2S is already enabled */
bogdanm 0:9b334a45a8ff 753 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm 0:9b334a45a8ff 754 {
bogdanm 0:9b334a45a8ff 755 /* Enable I2S peripheral before the I2Sext */
bogdanm 0:9b334a45a8ff 756 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 757
bogdanm 0:9b334a45a8ff 758 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
bogdanm 0:9b334a45a8ff 759 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
bogdanm 0:9b334a45a8ff 760 }
bogdanm 0:9b334a45a8ff 761 else
bogdanm 0:9b334a45a8ff 762 {
bogdanm 0:9b334a45a8ff 763 /* Check if Master Receiver mode is selected */
bogdanm 0:9b334a45a8ff 764 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm 0:9b334a45a8ff 765 {
bogdanm 0:9b334a45a8ff 766 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
bogdanm 0:9b334a45a8ff 767 access to the SPI_SR register. */
bogdanm 0:9b334a45a8ff 768 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm 0:9b334a45a8ff 769 }
bogdanm 0:9b334a45a8ff 770 }
bogdanm 0:9b334a45a8ff 771 }
bogdanm 0:9b334a45a8ff 772
bogdanm 0:9b334a45a8ff 773 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 774 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 775
bogdanm 0:9b334a45a8ff 776 return HAL_OK;
bogdanm 0:9b334a45a8ff 777 }
bogdanm 0:9b334a45a8ff 778 else
bogdanm 0:9b334a45a8ff 779 {
bogdanm 0:9b334a45a8ff 780 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 781 }
bogdanm 0:9b334a45a8ff 782 }
bogdanm 0:9b334a45a8ff 783
bogdanm 0:9b334a45a8ff 784 /**
bogdanm 0:9b334a45a8ff 785 * @brief Pauses the audio stream playing from the Media.
bogdanm 0:9b334a45a8ff 786 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 787 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 788 * @retval HAL status
bogdanm 0:9b334a45a8ff 789 */
bogdanm 0:9b334a45a8ff 790 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 791 {
bogdanm 0:9b334a45a8ff 792 /* Process Locked */
bogdanm 0:9b334a45a8ff 793 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 794
bogdanm 0:9b334a45a8ff 795 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm 0:9b334a45a8ff 796 {
bogdanm 0:9b334a45a8ff 797 /* Disable the I2S DMA Tx request */
bogdanm 0:9b334a45a8ff 798 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 799 }
bogdanm 0:9b334a45a8ff 800 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm 0:9b334a45a8ff 801 {
bogdanm 0:9b334a45a8ff 802 /* Disable the I2S DMA Rx request */
bogdanm 0:9b334a45a8ff 803 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 804 }
bogdanm 0:9b334a45a8ff 805 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
bogdanm 0:9b334a45a8ff 806 {
bogdanm 0:9b334a45a8ff 807 if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
bogdanm 0:9b334a45a8ff 808 {
bogdanm 0:9b334a45a8ff 809 /* Disable the I2S DMA Tx request */
bogdanm 0:9b334a45a8ff 810 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 811 /* Disable the I2SEx Rx DMA Request */
bogdanm 0:9b334a45a8ff 812 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 813 }
bogdanm 0:9b334a45a8ff 814 else
bogdanm 0:9b334a45a8ff 815 {
bogdanm 0:9b334a45a8ff 816 /* Disable the I2S DMA Rx request */
bogdanm 0:9b334a45a8ff 817 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 818 /* Disable the I2SEx Tx DMA Request */
bogdanm 0:9b334a45a8ff 819 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 820 }
bogdanm 0:9b334a45a8ff 821 }
bogdanm 0:9b334a45a8ff 822
bogdanm 0:9b334a45a8ff 823 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 824 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 825
bogdanm 0:9b334a45a8ff 826 return HAL_OK;
bogdanm 0:9b334a45a8ff 827 }
bogdanm 0:9b334a45a8ff 828
bogdanm 0:9b334a45a8ff 829 /**
bogdanm 0:9b334a45a8ff 830 * @brief Resumes the audio stream playing from the Media.
bogdanm 0:9b334a45a8ff 831 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 832 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 833 * @retval HAL status
bogdanm 0:9b334a45a8ff 834 */
bogdanm 0:9b334a45a8ff 835 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 836 {
bogdanm 0:9b334a45a8ff 837 /* Process Locked */
bogdanm 0:9b334a45a8ff 838 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 839
bogdanm 0:9b334a45a8ff 840 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm 0:9b334a45a8ff 841 {
bogdanm 0:9b334a45a8ff 842 /* Enable the I2S DMA Tx request */
bogdanm 0:9b334a45a8ff 843 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
bogdanm 0:9b334a45a8ff 844 }
bogdanm 0:9b334a45a8ff 845 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm 0:9b334a45a8ff 846 {
bogdanm 0:9b334a45a8ff 847 /* Enable the I2S DMA Rx request */
bogdanm 0:9b334a45a8ff 848 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
bogdanm 0:9b334a45a8ff 849 }
bogdanm 0:9b334a45a8ff 850 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
bogdanm 0:9b334a45a8ff 851 {
bogdanm 0:9b334a45a8ff 852 if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
bogdanm 0:9b334a45a8ff 853 {
bogdanm 0:9b334a45a8ff 854 /* Enable the I2S DMA Tx request */
bogdanm 0:9b334a45a8ff 855 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
bogdanm 0:9b334a45a8ff 856 /* Disable the I2SEx Rx DMA Request */
bogdanm 0:9b334a45a8ff 857 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
bogdanm 0:9b334a45a8ff 858 }
bogdanm 0:9b334a45a8ff 859 else
bogdanm 0:9b334a45a8ff 860 {
bogdanm 0:9b334a45a8ff 861 /* Enable the I2S DMA Rx request */
bogdanm 0:9b334a45a8ff 862 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
bogdanm 0:9b334a45a8ff 863 /* Enable the I2SEx Tx DMA Request */
bogdanm 0:9b334a45a8ff 864 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
bogdanm 0:9b334a45a8ff 865 }
bogdanm 0:9b334a45a8ff 866 }
bogdanm 0:9b334a45a8ff 867
bogdanm 0:9b334a45a8ff 868 /* If the I2S peripheral is still not enabled, enable it */
bogdanm 0:9b334a45a8ff 869 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
bogdanm 0:9b334a45a8ff 870 {
bogdanm 0:9b334a45a8ff 871 /* Enable I2S peripheral */
bogdanm 0:9b334a45a8ff 872 __HAL_I2S_ENABLE(hi2s);
bogdanm 0:9b334a45a8ff 873 }
bogdanm 0:9b334a45a8ff 874
bogdanm 0:9b334a45a8ff 875 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 876 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 877
bogdanm 0:9b334a45a8ff 878 return HAL_OK;
bogdanm 0:9b334a45a8ff 879 }
bogdanm 0:9b334a45a8ff 880
bogdanm 0:9b334a45a8ff 881 /**
bogdanm 0:9b334a45a8ff 882 * @brief Resumes the audio stream playing from the Media.
bogdanm 0:9b334a45a8ff 883 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 884 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 885 * @retval HAL status
bogdanm 0:9b334a45a8ff 886 */
bogdanm 0:9b334a45a8ff 887 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 888 {
bogdanm 0:9b334a45a8ff 889 /* Process Locked */
bogdanm 0:9b334a45a8ff 890 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 891
bogdanm 0:9b334a45a8ff 892 /* Disable the I2S Tx/Rx DMA requests */
bogdanm 0:9b334a45a8ff 893 hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
bogdanm 0:9b334a45a8ff 894 hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
bogdanm 0:9b334a45a8ff 895
bogdanm 0:9b334a45a8ff 896 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
bogdanm 0:9b334a45a8ff 897 {
bogdanm 0:9b334a45a8ff 898 /* Disable the I2S extended Tx/Rx DMA requests */
bogdanm 0:9b334a45a8ff 899 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 900 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 901 }
bogdanm 0:9b334a45a8ff 902
bogdanm 0:9b334a45a8ff 903 /* Abort the I2S DMA Stream tx */
bogdanm 0:9b334a45a8ff 904 if(hi2s->hdmatx != NULL)
bogdanm 0:9b334a45a8ff 905 {
bogdanm 0:9b334a45a8ff 906 HAL_DMA_Abort(hi2s->hdmatx);
bogdanm 0:9b334a45a8ff 907 }
bogdanm 0:9b334a45a8ff 908 /* Abort the I2S DMA Stream rx */
bogdanm 0:9b334a45a8ff 909 if(hi2s->hdmarx != NULL)
bogdanm 0:9b334a45a8ff 910 {
bogdanm 0:9b334a45a8ff 911 HAL_DMA_Abort(hi2s->hdmarx);
bogdanm 0:9b334a45a8ff 912 }
bogdanm 0:9b334a45a8ff 913
bogdanm 0:9b334a45a8ff 914 /* Disable I2S peripheral */
bogdanm 0:9b334a45a8ff 915 __HAL_I2S_DISABLE(hi2s);
bogdanm 0:9b334a45a8ff 916
bogdanm 0:9b334a45a8ff 917 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
bogdanm 0:9b334a45a8ff 918 {
bogdanm 0:9b334a45a8ff 919 /* Disable the I2Sext peripheral */
bogdanm 0:9b334a45a8ff 920 I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
bogdanm 0:9b334a45a8ff 921 }
bogdanm 0:9b334a45a8ff 922 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 923
bogdanm 0:9b334a45a8ff 924 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 925 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 926
bogdanm 0:9b334a45a8ff 927 return HAL_OK;
bogdanm 0:9b334a45a8ff 928 }
bogdanm 0:9b334a45a8ff 929
bogdanm 0:9b334a45a8ff 930 /**
bogdanm 0:9b334a45a8ff 931 * @brief This function handles I2S interrupt request.
bogdanm 0:9b334a45a8ff 932 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 933 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 934 * @retval None
bogdanm 0:9b334a45a8ff 935 */
bogdanm 0:9b334a45a8ff 936 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 937 {
bogdanm 0:9b334a45a8ff 938 uint32_t tmp1 = 0, tmp2 = 0;
bogdanm 0:9b334a45a8ff 939 __IO uint32_t tmpreg1 = 0;
bogdanm 0:9b334a45a8ff 940 if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
bogdanm 0:9b334a45a8ff 941 {
bogdanm 0:9b334a45a8ff 942 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm 0:9b334a45a8ff 943 {
bogdanm 0:9b334a45a8ff 944 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
bogdanm 0:9b334a45a8ff 945 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
bogdanm 0:9b334a45a8ff 946 /* I2S in mode Receiver ------------------------------------------------*/
bogdanm 0:9b334a45a8ff 947 if((tmp1 != RESET) && (tmp2 != RESET))
bogdanm 0:9b334a45a8ff 948 {
bogdanm 0:9b334a45a8ff 949 I2S_Receive_IT(hi2s);
bogdanm 0:9b334a45a8ff 950 }
bogdanm 0:9b334a45a8ff 951
bogdanm 0:9b334a45a8ff 952 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
bogdanm 0:9b334a45a8ff 953 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
bogdanm 0:9b334a45a8ff 954 /* I2S Overrun error interrupt occurred ---------------------------------*/
bogdanm 0:9b334a45a8ff 955 if((tmp1 != RESET) && (tmp2 != RESET))
bogdanm 0:9b334a45a8ff 956 {
bogdanm 0:9b334a45a8ff 957 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm 0:9b334a45a8ff 958 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
bogdanm 0:9b334a45a8ff 959 }
bogdanm 0:9b334a45a8ff 960 }
bogdanm 0:9b334a45a8ff 961
bogdanm 0:9b334a45a8ff 962 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm 0:9b334a45a8ff 963 {
bogdanm 0:9b334a45a8ff 964 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
bogdanm 0:9b334a45a8ff 965 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
bogdanm 0:9b334a45a8ff 966 /* I2S in mode Tramitter -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 967 if((tmp1 != RESET) && (tmp2 != RESET))
bogdanm 0:9b334a45a8ff 968 {
bogdanm 0:9b334a45a8ff 969 I2S_Transmit_IT(hi2s);
bogdanm 0:9b334a45a8ff 970 }
bogdanm 0:9b334a45a8ff 971
bogdanm 0:9b334a45a8ff 972 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
bogdanm 0:9b334a45a8ff 973 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
bogdanm 0:9b334a45a8ff 974 /* I2S Underrun error interrupt occurred --------------------------------*/
bogdanm 0:9b334a45a8ff 975 if((tmp1 != RESET) && (tmp2 != RESET))
bogdanm 0:9b334a45a8ff 976 {
bogdanm 0:9b334a45a8ff 977 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
bogdanm 0:9b334a45a8ff 978 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
bogdanm 0:9b334a45a8ff 979 }
bogdanm 0:9b334a45a8ff 980 }
bogdanm 0:9b334a45a8ff 981 }
bogdanm 0:9b334a45a8ff 982 else
bogdanm 0:9b334a45a8ff 983 {
bogdanm 0:9b334a45a8ff 984 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 985 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 986 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
bogdanm 0:9b334a45a8ff 987 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
bogdanm 0:9b334a45a8ff 988 {
bogdanm 0:9b334a45a8ff 989 tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE;
bogdanm 0:9b334a45a8ff 990 tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE;
bogdanm 0:9b334a45a8ff 991 /* I2Sext in mode Receiver ---------------------------------------------*/
bogdanm 0:9b334a45a8ff 992 if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE))
bogdanm 0:9b334a45a8ff 993 {
bogdanm 0:9b334a45a8ff 994 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 995 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 996 /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
bogdanm 0:9b334a45a8ff 997 the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
bogdanm 0:9b334a45a8ff 998 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
bogdanm 0:9b334a45a8ff 999 {
bogdanm 0:9b334a45a8ff 1000 I2SEx_TransmitReceive_IT(hi2s);
bogdanm 0:9b334a45a8ff 1001 }
bogdanm 0:9b334a45a8ff 1002 }
bogdanm 0:9b334a45a8ff 1003
bogdanm 0:9b334a45a8ff 1004 tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR;
bogdanm 0:9b334a45a8ff 1005 tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
mbed_official 19:112740acecfa 1006 /* I2Sext Overrun error interrupt occurred -----------------------------*/
bogdanm 0:9b334a45a8ff 1007 if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR))
bogdanm 0:9b334a45a8ff 1008 {
bogdanm 0:9b334a45a8ff 1009 /* Clear I2Sext OVR Flag */
bogdanm 0:9b334a45a8ff 1010 tmpreg1 = I2SxEXT(hi2s->Instance)->DR;
bogdanm 0:9b334a45a8ff 1011 tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
bogdanm 0:9b334a45a8ff 1012 hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR;
bogdanm 0:9b334a45a8ff 1013 UNUSED(tmpreg1);
bogdanm 0:9b334a45a8ff 1014 }
bogdanm 0:9b334a45a8ff 1015
bogdanm 0:9b334a45a8ff 1016 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
bogdanm 0:9b334a45a8ff 1017 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
bogdanm 0:9b334a45a8ff 1018 /* I2S in mode Tramitter -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1019 if((tmp1 != RESET) && (tmp2 != RESET))
bogdanm 0:9b334a45a8ff 1020 {
bogdanm 0:9b334a45a8ff 1021 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 1022 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 1023 /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
bogdanm 0:9b334a45a8ff 1024 the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
bogdanm 0:9b334a45a8ff 1025 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
bogdanm 0:9b334a45a8ff 1026 {
bogdanm 0:9b334a45a8ff 1027 I2SEx_TransmitReceive_IT(hi2s);
bogdanm 0:9b334a45a8ff 1028 }
bogdanm 0:9b334a45a8ff 1029 }
bogdanm 0:9b334a45a8ff 1030
bogdanm 0:9b334a45a8ff 1031 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
bogdanm 0:9b334a45a8ff 1032 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
mbed_official 19:112740acecfa 1033 /* I2S Underrun error interrupt occurred -------------------------------*/
bogdanm 0:9b334a45a8ff 1034 if((tmp1 != RESET) && (tmp2 != RESET))
bogdanm 0:9b334a45a8ff 1035 {
bogdanm 0:9b334a45a8ff 1036 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
bogdanm 0:9b334a45a8ff 1037 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
bogdanm 0:9b334a45a8ff 1038 }
bogdanm 0:9b334a45a8ff 1039 }
bogdanm 0:9b334a45a8ff 1040 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
bogdanm 0:9b334a45a8ff 1041 else
bogdanm 0:9b334a45a8ff 1042 {
bogdanm 0:9b334a45a8ff 1043 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
bogdanm 0:9b334a45a8ff 1044 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
bogdanm 0:9b334a45a8ff 1045 /* I2S in mode Receiver ------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1046 if((tmp1 != RESET) && (tmp2 != RESET))
bogdanm 0:9b334a45a8ff 1047 {
bogdanm 0:9b334a45a8ff 1048 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 1049 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 1050 /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
bogdanm 0:9b334a45a8ff 1051 the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
bogdanm 0:9b334a45a8ff 1052 if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
bogdanm 0:9b334a45a8ff 1053 {
bogdanm 0:9b334a45a8ff 1054 I2SEx_TransmitReceive_IT(hi2s);
bogdanm 0:9b334a45a8ff 1055 }
bogdanm 0:9b334a45a8ff 1056 }
bogdanm 0:9b334a45a8ff 1057
bogdanm 0:9b334a45a8ff 1058 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
bogdanm 0:9b334a45a8ff 1059 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
mbed_official 19:112740acecfa 1060 /* I2S Overrun error interrupt occurred --------------------------------*/
bogdanm 0:9b334a45a8ff 1061 if((tmp1 != RESET) && (tmp2 != RESET))
bogdanm 0:9b334a45a8ff 1062 {
bogdanm 0:9b334a45a8ff 1063 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm 0:9b334a45a8ff 1064 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
bogdanm 0:9b334a45a8ff 1065 }
bogdanm 0:9b334a45a8ff 1066
bogdanm 0:9b334a45a8ff 1067 tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE;
bogdanm 0:9b334a45a8ff 1068 tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE;
bogdanm 0:9b334a45a8ff 1069 /* I2Sext in mode Tramitter --------------------------------------------*/
bogdanm 0:9b334a45a8ff 1070 if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE))
bogdanm 0:9b334a45a8ff 1071 {
bogdanm 0:9b334a45a8ff 1072 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 1073 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 1074 /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
bogdanm 0:9b334a45a8ff 1075 the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
bogdanm 0:9b334a45a8ff 1076 if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
bogdanm 0:9b334a45a8ff 1077 {
bogdanm 0:9b334a45a8ff 1078 I2SEx_TransmitReceive_IT(hi2s);
bogdanm 0:9b334a45a8ff 1079 }
bogdanm 0:9b334a45a8ff 1080 }
bogdanm 0:9b334a45a8ff 1081
bogdanm 0:9b334a45a8ff 1082 tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR;
bogdanm 0:9b334a45a8ff 1083 tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
mbed_official 19:112740acecfa 1084 /* I2Sext Underrun error interrupt occurred ----------------------------*/
bogdanm 0:9b334a45a8ff 1085 if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR))
bogdanm 0:9b334a45a8ff 1086 {
bogdanm 0:9b334a45a8ff 1087 /* Clear I2Sext UDR Flag */
bogdanm 0:9b334a45a8ff 1088 tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
bogdanm 0:9b334a45a8ff 1089 hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR;
bogdanm 0:9b334a45a8ff 1090 UNUSED(tmpreg1);
bogdanm 0:9b334a45a8ff 1091 }
bogdanm 0:9b334a45a8ff 1092 }
bogdanm 0:9b334a45a8ff 1093 }
bogdanm 0:9b334a45a8ff 1094
bogdanm 0:9b334a45a8ff 1095 /* Call the Error call Back in case of Errors */
bogdanm 0:9b334a45a8ff 1096 if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
bogdanm 0:9b334a45a8ff 1097 {
bogdanm 0:9b334a45a8ff 1098 /* Set the I2S state ready to be able to start again the process */
bogdanm 0:9b334a45a8ff 1099 hi2s->State= HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1100 HAL_I2S_ErrorCallback(hi2s);
bogdanm 0:9b334a45a8ff 1101 }
bogdanm 0:9b334a45a8ff 1102 }
bogdanm 0:9b334a45a8ff 1103
bogdanm 0:9b334a45a8ff 1104 /**
bogdanm 0:9b334a45a8ff 1105 * @}
bogdanm 0:9b334a45a8ff 1106 */
bogdanm 0:9b334a45a8ff 1107
bogdanm 0:9b334a45a8ff 1108 /**
bogdanm 0:9b334a45a8ff 1109 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
bogdanm 0:9b334a45a8ff 1110 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1111 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1112 * @retval HAL status
bogdanm 0:9b334a45a8ff 1113 */
bogdanm 0:9b334a45a8ff 1114 HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1115 {
bogdanm 0:9b334a45a8ff 1116 uint32_t tmp1 = 0, tmp2 = 0;
bogdanm 0:9b334a45a8ff 1117
bogdanm 0:9b334a45a8ff 1118 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
bogdanm 0:9b334a45a8ff 1119 {
bogdanm 0:9b334a45a8ff 1120 /* Process Locked */
bogdanm 0:9b334a45a8ff 1121 __HAL_LOCK(hi2s);
bogdanm 0:9b334a45a8ff 1122
bogdanm 0:9b334a45a8ff 1123 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 1124 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
bogdanm 0:9b334a45a8ff 1125 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
bogdanm 0:9b334a45a8ff 1126 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
bogdanm 0:9b334a45a8ff 1127 {
bogdanm 0:9b334a45a8ff 1128 if(hi2s->TxXferCount != 0)
bogdanm 0:9b334a45a8ff 1129 {
bogdanm 0:9b334a45a8ff 1130 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE) != RESET)
bogdanm 0:9b334a45a8ff 1131 {
bogdanm 0:9b334a45a8ff 1132 /* Transmit data */
bogdanm 0:9b334a45a8ff 1133 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
bogdanm 0:9b334a45a8ff 1134 hi2s->TxXferCount--;
bogdanm 0:9b334a45a8ff 1135
bogdanm 0:9b334a45a8ff 1136 if(hi2s->TxXferCount == 0)
bogdanm 0:9b334a45a8ff 1137 {
bogdanm 0:9b334a45a8ff 1138 /* Disable TXE interrupt */
bogdanm 0:9b334a45a8ff 1139 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
bogdanm 0:9b334a45a8ff 1140 }
bogdanm 0:9b334a45a8ff 1141 }
bogdanm 0:9b334a45a8ff 1142 }
bogdanm 0:9b334a45a8ff 1143
bogdanm 0:9b334a45a8ff 1144 if(hi2s->RxXferCount != 0)
bogdanm 0:9b334a45a8ff 1145 {
bogdanm 0:9b334a45a8ff 1146 if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) == SPI_SR_RXNE)
bogdanm 0:9b334a45a8ff 1147 {
bogdanm 0:9b334a45a8ff 1148 /* Receive data */
bogdanm 0:9b334a45a8ff 1149 (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
bogdanm 0:9b334a45a8ff 1150 hi2s->RxXferCount--;
bogdanm 0:9b334a45a8ff 1151
bogdanm 0:9b334a45a8ff 1152 if(hi2s->RxXferCount == 0)
bogdanm 0:9b334a45a8ff 1153 {
bogdanm 0:9b334a45a8ff 1154 /* Disable I2Sext RXNE interrupt */
bogdanm 0:9b334a45a8ff 1155 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_RXNE;
bogdanm 0:9b334a45a8ff 1156 }
bogdanm 0:9b334a45a8ff 1157 }
bogdanm 0:9b334a45a8ff 1158 }
bogdanm 0:9b334a45a8ff 1159 }
bogdanm 0:9b334a45a8ff 1160 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
bogdanm 0:9b334a45a8ff 1161 else
bogdanm 0:9b334a45a8ff 1162 {
bogdanm 0:9b334a45a8ff 1163 if(hi2s->TxXferCount != 0)
bogdanm 0:9b334a45a8ff 1164 {
bogdanm 0:9b334a45a8ff 1165 if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) == SPI_SR_TXE)
bogdanm 0:9b334a45a8ff 1166 {
bogdanm 0:9b334a45a8ff 1167 /* Transmit data */
bogdanm 0:9b334a45a8ff 1168 I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
bogdanm 0:9b334a45a8ff 1169 hi2s->TxXferCount--;
bogdanm 0:9b334a45a8ff 1170
bogdanm 0:9b334a45a8ff 1171 if(hi2s->TxXferCount == 0)
bogdanm 0:9b334a45a8ff 1172 {
bogdanm 0:9b334a45a8ff 1173 /* Disable I2Sext TXE interrupt */
bogdanm 0:9b334a45a8ff 1174 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
bogdanm 0:9b334a45a8ff 1175
bogdanm 0:9b334a45a8ff 1176 HAL_I2S_TxCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1177 }
bogdanm 0:9b334a45a8ff 1178 }
bogdanm 0:9b334a45a8ff 1179 }
bogdanm 0:9b334a45a8ff 1180 if(hi2s->RxXferCount != 0)
bogdanm 0:9b334a45a8ff 1181 {
bogdanm 0:9b334a45a8ff 1182 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE) != RESET)
bogdanm 0:9b334a45a8ff 1183 {
bogdanm 0:9b334a45a8ff 1184 /* Receive data */
bogdanm 0:9b334a45a8ff 1185 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
bogdanm 0:9b334a45a8ff 1186 hi2s->RxXferCount--;
bogdanm 0:9b334a45a8ff 1187
bogdanm 0:9b334a45a8ff 1188 if(hi2s->RxXferCount == 0)
bogdanm 0:9b334a45a8ff 1189 {
bogdanm 0:9b334a45a8ff 1190 /* Disable RXNE interrupt */
bogdanm 0:9b334a45a8ff 1191 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
bogdanm 0:9b334a45a8ff 1192
bogdanm 0:9b334a45a8ff 1193 HAL_I2S_RxCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1194 }
bogdanm 0:9b334a45a8ff 1195 }
bogdanm 0:9b334a45a8ff 1196 }
bogdanm 0:9b334a45a8ff 1197 }
bogdanm 0:9b334a45a8ff 1198
bogdanm 0:9b334a45a8ff 1199 tmp1 = hi2s->RxXferCount;
bogdanm 0:9b334a45a8ff 1200 tmp2 = hi2s->TxXferCount;
bogdanm 0:9b334a45a8ff 1201 if((tmp1 == 0) && (tmp2 == 0))
bogdanm 0:9b334a45a8ff 1202 {
bogdanm 0:9b334a45a8ff 1203 /* Disable I2Sx ERR interrupt */
bogdanm 0:9b334a45a8ff 1204 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_ERR);
bogdanm 0:9b334a45a8ff 1205 /* Disable I2Sext ERR interrupt */
bogdanm 0:9b334a45a8ff 1206 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_ERR;
bogdanm 0:9b334a45a8ff 1207
bogdanm 0:9b334a45a8ff 1208 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1209 }
bogdanm 0:9b334a45a8ff 1210
bogdanm 0:9b334a45a8ff 1211 /* Process Unlocked */
bogdanm 0:9b334a45a8ff 1212 __HAL_UNLOCK(hi2s);
bogdanm 0:9b334a45a8ff 1213
bogdanm 0:9b334a45a8ff 1214 return HAL_OK;
bogdanm 0:9b334a45a8ff 1215 }
bogdanm 0:9b334a45a8ff 1216 else
bogdanm 0:9b334a45a8ff 1217 {
bogdanm 0:9b334a45a8ff 1218 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1219 }
bogdanm 0:9b334a45a8ff 1220 }
mbed_official 19:112740acecfa 1221 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx ||\
mbed_official 19:112740acecfa 1222 STM32F411xx || STM32F469xx || STM32F479xx */
bogdanm 0:9b334a45a8ff 1223 /**
bogdanm 0:9b334a45a8ff 1224 * @brief DMA I2S transmit process complete callback
bogdanm 0:9b334a45a8ff 1225 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1226 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 1227 * @retval None
bogdanm 0:9b334a45a8ff 1228 */
bogdanm 0:9b334a45a8ff 1229 void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 1230 {
bogdanm 0:9b334a45a8ff 1231 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
bogdanm 0:9b334a45a8ff 1232
bogdanm 0:9b334a45a8ff 1233 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 1234 {
bogdanm 0:9b334a45a8ff 1235 hi2s->TxXferCount = 0;
bogdanm 0:9b334a45a8ff 1236
bogdanm 0:9b334a45a8ff 1237 /* Disable Tx DMA Request */
bogdanm 0:9b334a45a8ff 1238 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 1239 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
bogdanm 0:9b334a45a8ff 1240 defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
mbed_official 19:112740acecfa 1241 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
mbed_official 19:112740acecfa 1242 defined(STM32F479xx)
bogdanm 0:9b334a45a8ff 1243 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
bogdanm 0:9b334a45a8ff 1244 {
bogdanm 0:9b334a45a8ff 1245 /* Disable Rx DMA Request for the slave*/
bogdanm 0:9b334a45a8ff 1246 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 1247 }
mbed_official 19:112740acecfa 1248 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\
mbed_official 19:112740acecfa 1249 STM32F469xx || STM32F479xx */
bogdanm 0:9b334a45a8ff 1250 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
bogdanm 0:9b334a45a8ff 1251 {
bogdanm 0:9b334a45a8ff 1252 if(hi2s->RxXferCount == 0)
bogdanm 0:9b334a45a8ff 1253 {
bogdanm 0:9b334a45a8ff 1254 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1255 }
bogdanm 0:9b334a45a8ff 1256 }
bogdanm 0:9b334a45a8ff 1257 else
bogdanm 0:9b334a45a8ff 1258 {
bogdanm 0:9b334a45a8ff 1259 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1260 }
bogdanm 0:9b334a45a8ff 1261 }
bogdanm 0:9b334a45a8ff 1262 HAL_I2S_TxCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1263 }
bogdanm 0:9b334a45a8ff 1264
bogdanm 0:9b334a45a8ff 1265 /**
bogdanm 0:9b334a45a8ff 1266 * @brief DMA I2S receive process complete callback
bogdanm 0:9b334a45a8ff 1267 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1268 * the configuration information for the specified DMA module.
bogdanm 0:9b334a45a8ff 1269 * @retval None
bogdanm 0:9b334a45a8ff 1270 */
bogdanm 0:9b334a45a8ff 1271 void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
bogdanm 0:9b334a45a8ff 1272 {
bogdanm 0:9b334a45a8ff 1273 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
bogdanm 0:9b334a45a8ff 1274
bogdanm 0:9b334a45a8ff 1275 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm 0:9b334a45a8ff 1276 {
bogdanm 0:9b334a45a8ff 1277 /* Disable Rx DMA Request */
bogdanm 0:9b334a45a8ff 1278 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm 0:9b334a45a8ff 1279 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
bogdanm 0:9b334a45a8ff 1280 defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
mbed_official 19:112740acecfa 1281 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
mbed_official 19:112740acecfa 1282 defined(STM32F479xx)
bogdanm 0:9b334a45a8ff 1283 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
bogdanm 0:9b334a45a8ff 1284 {
bogdanm 0:9b334a45a8ff 1285 /* Disable Tx DMA Request for the slave*/
bogdanm 0:9b334a45a8ff 1286 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm 0:9b334a45a8ff 1287 }
mbed_official 19:112740acecfa 1288 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\
mbed_official 19:112740acecfa 1289 STM32F469xx || STM32F479xx */
bogdanm 0:9b334a45a8ff 1290 hi2s->RxXferCount = 0;
bogdanm 0:9b334a45a8ff 1291 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
bogdanm 0:9b334a45a8ff 1292 {
bogdanm 0:9b334a45a8ff 1293 if(hi2s->TxXferCount == 0)
bogdanm 0:9b334a45a8ff 1294 {
bogdanm 0:9b334a45a8ff 1295 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1296 }
bogdanm 0:9b334a45a8ff 1297 }
bogdanm 0:9b334a45a8ff 1298 else
bogdanm 0:9b334a45a8ff 1299 {
bogdanm 0:9b334a45a8ff 1300 hi2s->State = HAL_I2S_STATE_READY;
bogdanm 0:9b334a45a8ff 1301 }
bogdanm 0:9b334a45a8ff 1302 }
bogdanm 0:9b334a45a8ff 1303 HAL_I2S_RxCpltCallback(hi2s);
bogdanm 0:9b334a45a8ff 1304 }
bogdanm 0:9b334a45a8ff 1305
bogdanm 0:9b334a45a8ff 1306 /**
bogdanm 0:9b334a45a8ff 1307 * @brief Get I2S clock Input based on Source clock selection in RCC
bogdanm 0:9b334a45a8ff 1308 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1309 * the configuration information for I2S module
bogdanm 0:9b334a45a8ff 1310 * @retval I2S Clock Input
bogdanm 0:9b334a45a8ff 1311 */
bogdanm 0:9b334a45a8ff 1312 uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s)
bogdanm 0:9b334a45a8ff 1313 {
bogdanm 0:9b334a45a8ff 1314 /* This variable used to store the VCO Input (value in Hz) */
bogdanm 0:9b334a45a8ff 1315 uint32_t vcoinput = 0;
bogdanm 0:9b334a45a8ff 1316 /* This variable used to store the VCO Output (value in Hz) */
bogdanm 0:9b334a45a8ff 1317 uint32_t vcooutput = 0;
bogdanm 0:9b334a45a8ff 1318 /* This variable used to store the I2S_CK_x (value in Hz) */
bogdanm 0:9b334a45a8ff 1319 uint32_t i2ssourceclock = 0;
bogdanm 0:9b334a45a8ff 1320
mbed_official 19:112740acecfa 1321 /* Configure 12S Clock based on I2S source clock selection */
mbed_official 19:112740acecfa 1322 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
bogdanm 0:9b334a45a8ff 1323 switch(hi2s->Init.ClockSource)
bogdanm 0:9b334a45a8ff 1324 {
bogdanm 0:9b334a45a8ff 1325 case I2S_CLOCK_EXTERNAL :
bogdanm 0:9b334a45a8ff 1326 {
bogdanm 0:9b334a45a8ff 1327 /* Set the I2S clock to the external clock value */
bogdanm 0:9b334a45a8ff 1328 i2ssourceclock = EXTERNAL_CLOCK_VALUE;
bogdanm 0:9b334a45a8ff 1329 break;
bogdanm 0:9b334a45a8ff 1330 }
mbed_official 19:112740acecfa 1331 #if defined(STM32F446xx)
bogdanm 0:9b334a45a8ff 1332 case I2S_CLOCK_PLL :
bogdanm 0:9b334a45a8ff 1333 {
bogdanm 0:9b334a45a8ff 1334 /* Configure the PLLI2S division factor */
bogdanm 0:9b334a45a8ff 1335 /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
bogdanm 0:9b334a45a8ff 1336 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
bogdanm 0:9b334a45a8ff 1337 {
bogdanm 0:9b334a45a8ff 1338 /* Get the I2S source clock value */
bogdanm 0:9b334a45a8ff 1339 vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
bogdanm 0:9b334a45a8ff 1340 }
bogdanm 0:9b334a45a8ff 1341 else
bogdanm 0:9b334a45a8ff 1342 {
bogdanm 0:9b334a45a8ff 1343 /* Get the I2S source clock value */
bogdanm 0:9b334a45a8ff 1344 vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
bogdanm 0:9b334a45a8ff 1345 }
bogdanm 0:9b334a45a8ff 1346
bogdanm 0:9b334a45a8ff 1347 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
bogdanm 0:9b334a45a8ff 1348 vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6)));
bogdanm 0:9b334a45a8ff 1349 /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
bogdanm 0:9b334a45a8ff 1350 i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28)));
bogdanm 0:9b334a45a8ff 1351 break;
bogdanm 0:9b334a45a8ff 1352 }
mbed_official 19:112740acecfa 1353 #endif /* STM32F446xx */
bogdanm 0:9b334a45a8ff 1354 case I2S_CLOCK_PLLR :
bogdanm 0:9b334a45a8ff 1355 {
bogdanm 0:9b334a45a8ff 1356 /* Configure the PLLI2S division factor */
bogdanm 0:9b334a45a8ff 1357 /* PLL_VCO Input = PLL_SOURCE/PLLM */
bogdanm 0:9b334a45a8ff 1358 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
bogdanm 0:9b334a45a8ff 1359 {
bogdanm 0:9b334a45a8ff 1360 /* Get the I2S source clock value */
bogdanm 0:9b334a45a8ff 1361 vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
bogdanm 0:9b334a45a8ff 1362 }
bogdanm 0:9b334a45a8ff 1363 else
bogdanm 0:9b334a45a8ff 1364 {
bogdanm 0:9b334a45a8ff 1365 /* Get the I2S source clock value */
bogdanm 0:9b334a45a8ff 1366 vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
bogdanm 0:9b334a45a8ff 1367 }
bogdanm 0:9b334a45a8ff 1368
bogdanm 0:9b334a45a8ff 1369 /* PLL_VCO Output = PLL_VCO Input * PLLN */
bogdanm 0:9b334a45a8ff 1370 vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6) & (RCC_PLLCFGR_PLLN >> 6)));
bogdanm 0:9b334a45a8ff 1371 /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
bogdanm 0:9b334a45a8ff 1372 i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28) & (RCC_PLLCFGR_PLLR >> 28)));
bogdanm 0:9b334a45a8ff 1373 break;
bogdanm 0:9b334a45a8ff 1374 }
bogdanm 0:9b334a45a8ff 1375 case I2S_CLOCK_PLLSRC :
bogdanm 0:9b334a45a8ff 1376 {
bogdanm 0:9b334a45a8ff 1377 /* Configure the PLLI2S division factor */
bogdanm 0:9b334a45a8ff 1378 /* PLL_VCO Input = PLL_SOURCE/PLLM */
bogdanm 0:9b334a45a8ff 1379 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
bogdanm 0:9b334a45a8ff 1380 {
bogdanm 0:9b334a45a8ff 1381 /* Get the I2S source clock value */
bogdanm 0:9b334a45a8ff 1382 i2ssourceclock = (uint32_t)(HSE_VALUE);
bogdanm 0:9b334a45a8ff 1383 }
bogdanm 0:9b334a45a8ff 1384 else
bogdanm 0:9b334a45a8ff 1385 {
bogdanm 0:9b334a45a8ff 1386 /* Get the I2S source clock value */
bogdanm 0:9b334a45a8ff 1387 i2ssourceclock = (uint32_t)(HSI_VALUE);
bogdanm 0:9b334a45a8ff 1388 }
bogdanm 0:9b334a45a8ff 1389 break;
bogdanm 0:9b334a45a8ff 1390 }
bogdanm 0:9b334a45a8ff 1391 default :
bogdanm 0:9b334a45a8ff 1392 {
bogdanm 0:9b334a45a8ff 1393 break;
bogdanm 0:9b334a45a8ff 1394 }
bogdanm 0:9b334a45a8ff 1395 }
mbed_official 19:112740acecfa 1396 #endif /* STM32F410xx || STM32F446xx */
mbed_official 19:112740acecfa 1397
bogdanm 0:9b334a45a8ff 1398 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
bogdanm 0:9b334a45a8ff 1399 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
mbed_official 19:112740acecfa 1400 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F469xx) || defined(STM32F479xx)
bogdanm 0:9b334a45a8ff 1401
bogdanm 0:9b334a45a8ff 1402 /* If an external I2S clock has to be used, the specific define should be set
bogdanm 0:9b334a45a8ff 1403 in the project configuration or in the stm32f4xx_conf.h file */
bogdanm 0:9b334a45a8ff 1404 if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
bogdanm 0:9b334a45a8ff 1405 {
bogdanm 0:9b334a45a8ff 1406 /* Set the I2S clock to the external clock value */
bogdanm 0:9b334a45a8ff 1407 i2ssourceclock = EXTERNAL_CLOCK_VALUE;
bogdanm 0:9b334a45a8ff 1408 }
bogdanm 0:9b334a45a8ff 1409 else
bogdanm 0:9b334a45a8ff 1410 {
bogdanm 0:9b334a45a8ff 1411 /* Configure the PLLI2S division factor */
bogdanm 0:9b334a45a8ff 1412 /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
bogdanm 0:9b334a45a8ff 1413 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
bogdanm 0:9b334a45a8ff 1414 {
bogdanm 0:9b334a45a8ff 1415 /* Get the I2S source clock value */
bogdanm 0:9b334a45a8ff 1416 vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
bogdanm 0:9b334a45a8ff 1417 }
bogdanm 0:9b334a45a8ff 1418 else
bogdanm 0:9b334a45a8ff 1419 {
bogdanm 0:9b334a45a8ff 1420 /* Get the I2S source clock value */
bogdanm 0:9b334a45a8ff 1421 vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
bogdanm 0:9b334a45a8ff 1422 }
bogdanm 0:9b334a45a8ff 1423
bogdanm 0:9b334a45a8ff 1424 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
bogdanm 0:9b334a45a8ff 1425 vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6)));
bogdanm 0:9b334a45a8ff 1426 /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
bogdanm 0:9b334a45a8ff 1427 i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28)));
bogdanm 0:9b334a45a8ff 1428 }
mbed_official 19:112740acecfa 1429 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
bogdanm 0:9b334a45a8ff 1430
bogdanm 0:9b334a45a8ff 1431 #if defined(STM32F411xE)
bogdanm 0:9b334a45a8ff 1432
bogdanm 0:9b334a45a8ff 1433 /* If an external I2S clock has to be used, the specific define should be set
bogdanm 0:9b334a45a8ff 1434 in the project configuration or in the stm32f4xx_conf.h file */
bogdanm 0:9b334a45a8ff 1435 if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
bogdanm 0:9b334a45a8ff 1436 {
bogdanm 0:9b334a45a8ff 1437 /* Set the I2S clock to the external clock value */
bogdanm 0:9b334a45a8ff 1438 i2ssourceclock = EXTERNAL_CLOCK_VALUE;
bogdanm 0:9b334a45a8ff 1439 }
bogdanm 0:9b334a45a8ff 1440 else
bogdanm 0:9b334a45a8ff 1441 {
bogdanm 0:9b334a45a8ff 1442 /* Configure the PLLI2S division factor */
bogdanm 0:9b334a45a8ff 1443 /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
bogdanm 0:9b334a45a8ff 1444 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
bogdanm 0:9b334a45a8ff 1445 {
bogdanm 0:9b334a45a8ff 1446 /* Get the I2S source clock value */
bogdanm 0:9b334a45a8ff 1447 vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
bogdanm 0:9b334a45a8ff 1448 }
bogdanm 0:9b334a45a8ff 1449 else
bogdanm 0:9b334a45a8ff 1450 {
bogdanm 0:9b334a45a8ff 1451 /* Get the I2S source clock value */
bogdanm 0:9b334a45a8ff 1452 vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
bogdanm 0:9b334a45a8ff 1453 }
bogdanm 0:9b334a45a8ff 1454
bogdanm 0:9b334a45a8ff 1455 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
bogdanm 0:9b334a45a8ff 1456 vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6)));
bogdanm 0:9b334a45a8ff 1457 /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
bogdanm 0:9b334a45a8ff 1458 i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28)));
bogdanm 0:9b334a45a8ff 1459 }
bogdanm 0:9b334a45a8ff 1460 #endif /* STM32F411xE */
bogdanm 0:9b334a45a8ff 1461
bogdanm 0:9b334a45a8ff 1462 /* the return result is the value of SAI clock */
bogdanm 0:9b334a45a8ff 1463 return i2ssourceclock;
bogdanm 0:9b334a45a8ff 1464 }
bogdanm 0:9b334a45a8ff 1465 /**
bogdanm 0:9b334a45a8ff 1466 * @}
bogdanm 0:9b334a45a8ff 1467 */
bogdanm 0:9b334a45a8ff 1468
mbed_official 19:112740acecfa 1469 /**
mbed_official 19:112740acecfa 1470 * @}
mbed_official 19:112740acecfa 1471 */
mbed_official 19:112740acecfa 1472
bogdanm 0:9b334a45a8ff 1473 #endif /* HAL_I2S_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1474 /**
bogdanm 0:9b334a45a8ff 1475 * @}
bogdanm 0:9b334a45a8ff 1476 */
bogdanm 0:9b334a45a8ff 1477
bogdanm 0:9b334a45a8ff 1478 /**
bogdanm 0:9b334a45a8ff 1479 * @}
bogdanm 0:9b334a45a8ff 1480 */
bogdanm 0:9b334a45a8ff 1481
bogdanm 0:9b334a45a8ff 1482 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/