Iftikhar Aziz / mbed-dev

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Dependents:   LSS_Rev_1

Fork of mbed-dev by Umar Naeem

targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_sys.c@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /*******************************************************************************
<> 157:ff67d9f36b67 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 3 *
<> 157:ff67d9f36b67 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 5 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 6 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 9 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 10 *
<> 157:ff67d9f36b67 11 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 12 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 13 *
<> 157:ff67d9f36b67 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 21 *
<> 157:ff67d9f36b67 22 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 24 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 25 *
<> 157:ff67d9f36b67 26 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 28 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 30 * ownership rights.
<> 157:ff67d9f36b67 31 *
<> 157:ff67d9f36b67 32 * $Date: 2016-06-17 12:59:44 -0500 (Fri, 17 Jun 2016) $
<> 157:ff67d9f36b67 33 * $Revision: 23365 $
<> 157:ff67d9f36b67 34 *
<> 157:ff67d9f36b67 35 ******************************************************************************/
<> 157:ff67d9f36b67 36
<> 157:ff67d9f36b67 37 #include <stddef.h>
<> 157:ff67d9f36b67 38 #include "mxc_config.h"
<> 157:ff67d9f36b67 39 #include "mxc_assert.h"
<> 157:ff67d9f36b67 40 #include "mxc_sys.h"
<> 157:ff67d9f36b67 41 #include "ioman.h"
<> 157:ff67d9f36b67 42 #include "clkman.h"
<> 157:ff67d9f36b67 43 #include "pwrseq_regs.h"
<> 157:ff67d9f36b67 44 #include "pwrman_regs.h"
<> 157:ff67d9f36b67 45 #include "spix_regs.h"
<> 157:ff67d9f36b67 46 #include "trim_regs.h"
<> 157:ff67d9f36b67 47
<> 157:ff67d9f36b67 48 /***** Definitions *****/
<> 157:ff67d9f36b67 49 #define SYS_RTC_CLK 32768UL
<> 157:ff67d9f36b67 50
<> 157:ff67d9f36b67 51 /******************************************************************************/
<> 157:ff67d9f36b67 52 uint32_t SYS_GetFreq(uint32_t clk_scale)
<> 157:ff67d9f36b67 53 {
<> 157:ff67d9f36b67 54 uint32_t freq;
<> 157:ff67d9f36b67 55 unsigned int clkdiv;
<> 157:ff67d9f36b67 56
<> 157:ff67d9f36b67 57 if (clk_scale == MXC_V_CLKMAN_CLK_SCALE_DISABLED) {
<> 157:ff67d9f36b67 58 freq = 0;
<> 157:ff67d9f36b67 59 } else {
<> 157:ff67d9f36b67 60 clkdiv = 1 << (clk_scale - 1);
<> 157:ff67d9f36b67 61 freq = SystemCoreClock / clkdiv;
<> 157:ff67d9f36b67 62 }
<> 157:ff67d9f36b67 63
<> 157:ff67d9f36b67 64 return freq;
<> 157:ff67d9f36b67 65 }
<> 157:ff67d9f36b67 66
<> 157:ff67d9f36b67 67 /******************************************************************************/
<> 157:ff67d9f36b67 68 uint32_t SYS_CPU_GetFreq(void)
<> 157:ff67d9f36b67 69 {
<> 157:ff67d9f36b67 70 return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_CPU));
<> 157:ff67d9f36b67 71 }
<> 157:ff67d9f36b67 72
<> 157:ff67d9f36b67 73 /******************************************************************************/
<> 157:ff67d9f36b67 74 int SYS_ADC_Init(void)
<> 157:ff67d9f36b67 75 {
<> 157:ff67d9f36b67 76 /* Power up the ADC AFE, enable clocks */
<> 157:ff67d9f36b67 77 MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED;
<> 157:ff67d9f36b67 78 MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE;
<> 157:ff67d9f36b67 79
<> 157:ff67d9f36b67 80 return E_NO_ERROR;
<> 157:ff67d9f36b67 81 }
<> 157:ff67d9f36b67 82
<> 157:ff67d9f36b67 83 /******************************************************************************/
<> 157:ff67d9f36b67 84 int SYS_AES_Init(void)
<> 157:ff67d9f36b67 85 {
<> 157:ff67d9f36b67 86 /* Set up clocks for AES block */
<> 157:ff67d9f36b67 87 /* Enable crypto ring oscillator, which is used by all TPU components (AES, uMAA, etc.) */
<> 157:ff67d9f36b67 88 CLKMAN_CryptoClockEnable(1);
<> 157:ff67d9f36b67 89
<> 157:ff67d9f36b67 90 /* Change prescaler to /1 */
<> 157:ff67d9f36b67 91 CLKMAN_SetClkScale(CLKMAN_CRYPTO_CLK_AES, CLKMAN_SCALE_DIV_1);
<> 157:ff67d9f36b67 92
<> 157:ff67d9f36b67 93 return E_NO_ERROR;
<> 157:ff67d9f36b67 94 }
<> 157:ff67d9f36b67 95
<> 157:ff67d9f36b67 96 /******************************************************************************/
<> 157:ff67d9f36b67 97 int SYS_GPIO_Init(void)
<> 157:ff67d9f36b67 98 {
<> 157:ff67d9f36b67 99 if (CLKMAN_GetClkScale(CLKMAN_CLK_GPIO) == CLKMAN_SCALE_DISABLED) {
<> 157:ff67d9f36b67 100 CLKMAN_SetClkScale(CLKMAN_CLK_GPIO, CLKMAN_SCALE_DIV_1);
<> 157:ff67d9f36b67 101 }
<> 157:ff67d9f36b67 102
<> 157:ff67d9f36b67 103 return E_NO_ERROR;
<> 157:ff67d9f36b67 104 }
<> 157:ff67d9f36b67 105
<> 157:ff67d9f36b67 106 /******************************************************************************/
<> 157:ff67d9f36b67 107 int SYS_UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *uart_cfg, const sys_cfg_uart_t *sys_cfg)
<> 157:ff67d9f36b67 108 {
<> 157:ff67d9f36b67 109 static int subsequent_call = 0;
<> 157:ff67d9f36b67 110 int err, idx;
<> 157:ff67d9f36b67 111 clkman_scale_t clk_scale;
<> 157:ff67d9f36b67 112 uint32_t min_baud;
<> 157:ff67d9f36b67 113
<> 157:ff67d9f36b67 114 if(sys_cfg == NULL)
<> 157:ff67d9f36b67 115 return E_NULL_PTR;
<> 157:ff67d9f36b67 116
<> 157:ff67d9f36b67 117 if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) {
<> 157:ff67d9f36b67 118 CLKMAN_SetClkScale(CLKMAN_CLK_UART, sys_cfg->clk_scale);
<> 157:ff67d9f36b67 119 } else if (!subsequent_call) {
<> 157:ff67d9f36b67 120 /* This clock divider is shared amongst all UARTs. Only change it if it
<> 157:ff67d9f36b67 121 * hasn't already been configured. UART_Init() will check for validity
<> 157:ff67d9f36b67 122 * for this baudrate.
<> 157:ff67d9f36b67 123 */
<> 157:ff67d9f36b67 124 subsequent_call = 1;
<> 157:ff67d9f36b67 125
<> 157:ff67d9f36b67 126 /* Setup the clock divider for the given baud rate */
<> 157:ff67d9f36b67 127 clk_scale = CLKMAN_SCALE_DISABLED;
<> 157:ff67d9f36b67 128 do {
<> 157:ff67d9f36b67 129 min_baud = ((SystemCoreClock >> clk_scale++) / (16 * (MXC_F_UART_BAUD_BAUD_DIVISOR >> MXC_F_UART_BAUD_BAUD_DIVISOR_POS)));
<> 157:ff67d9f36b67 130 } while (uart_cfg->baud < min_baud && clk_scale < CLKMAN_SCALE_AUTO);
<> 157:ff67d9f36b67 131
<> 157:ff67d9f36b67 132 /* check if baud rate cannot be reached */
<> 157:ff67d9f36b67 133 if(uart_cfg->baud < min_baud)
<> 157:ff67d9f36b67 134 return E_BAD_STATE;
<> 157:ff67d9f36b67 135
<> 157:ff67d9f36b67 136 CLKMAN_SetClkScale(CLKMAN_CLK_UART, clk_scale);
<> 157:ff67d9f36b67 137 }
<> 157:ff67d9f36b67 138
<> 157:ff67d9f36b67 139 if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) {
<> 157:ff67d9f36b67 140 return err;
<> 157:ff67d9f36b67 141 }
<> 157:ff67d9f36b67 142
<> 157:ff67d9f36b67 143 /* Reset the peripheral */
<> 157:ff67d9f36b67 144 idx = MXC_UART_GET_IDX(uart);
<> 157:ff67d9f36b67 145 MXC_PWRMAN->peripheral_reset |= (MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 << idx);
<> 157:ff67d9f36b67 146 MXC_PWRMAN->peripheral_reset &= ~((MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 << idx));
<> 157:ff67d9f36b67 147
<> 157:ff67d9f36b67 148 return E_NO_ERROR;
<> 157:ff67d9f36b67 149 }
<> 157:ff67d9f36b67 150
<> 157:ff67d9f36b67 151 /******************************************************************************/
<> 157:ff67d9f36b67 152 int SYS_UART_Shutdown(mxc_uart_regs_t *uart)
<> 157:ff67d9f36b67 153 {
<> 157:ff67d9f36b67 154 int err;
<> 157:ff67d9f36b67 155 int idx = MXC_UART_GET_IDX(uart);
<> 157:ff67d9f36b67 156 ioman_cfg_t io_cfg = (ioman_cfg_t)IOMAN_UART(idx, 0, 0, 0, 0, 0, 0);
<> 157:ff67d9f36b67 157
<> 157:ff67d9f36b67 158 if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) {
<> 157:ff67d9f36b67 159 return err;
<> 157:ff67d9f36b67 160 }
<> 157:ff67d9f36b67 161
<> 157:ff67d9f36b67 162 return E_NO_ERROR;
<> 157:ff67d9f36b67 163 }
<> 157:ff67d9f36b67 164
<> 157:ff67d9f36b67 165 /******************************************************************************/
<> 157:ff67d9f36b67 166 uint32_t SYS_UART_GetFreq(mxc_uart_regs_t *uart)
<> 157:ff67d9f36b67 167 {
<> 157:ff67d9f36b67 168 return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_UART));
<> 157:ff67d9f36b67 169 }
<> 157:ff67d9f36b67 170
<> 157:ff67d9f36b67 171 /******************************************************************************/
<> 157:ff67d9f36b67 172 int SYS_I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *cfg)
<> 157:ff67d9f36b67 173 {
<> 157:ff67d9f36b67 174 int err;
<> 157:ff67d9f36b67 175
<> 157:ff67d9f36b67 176 if(cfg == NULL)
<> 157:ff67d9f36b67 177 return E_NULL_PTR;
<> 157:ff67d9f36b67 178
<> 157:ff67d9f36b67 179 CLKMAN_SetClkScale(CLKMAN_CLK_I2CM, cfg->clk_scale);
<> 157:ff67d9f36b67 180 MXC_CLKMAN->i2c_timer_ctrl = 1;
<> 157:ff67d9f36b67 181
<> 157:ff67d9f36b67 182 if ((err = IOMAN_Config(&cfg->io_cfg)) != E_NO_ERROR) {
<> 157:ff67d9f36b67 183 return err;
<> 157:ff67d9f36b67 184 }
<> 157:ff67d9f36b67 185
<> 157:ff67d9f36b67 186 return E_NO_ERROR;
<> 157:ff67d9f36b67 187 }
<> 157:ff67d9f36b67 188
<> 157:ff67d9f36b67 189 /******************************************************************************/
<> 157:ff67d9f36b67 190 int SYS_I2CM_Shutdown(mxc_i2cm_regs_t *i2cm)
<> 157:ff67d9f36b67 191 {
<> 157:ff67d9f36b67 192 int err;
<> 157:ff67d9f36b67 193 int idx = MXC_I2CM_GET_IDX(i2cm);
<> 157:ff67d9f36b67 194 ioman_cfg_t io_cfg;
<> 157:ff67d9f36b67 195
<> 157:ff67d9f36b67 196 switch(idx)
<> 157:ff67d9f36b67 197 {
<> 157:ff67d9f36b67 198 case 0:
<> 157:ff67d9f36b67 199 io_cfg = (ioman_cfg_t)IOMAN_I2CM0(0, 0);
<> 157:ff67d9f36b67 200 break;
<> 157:ff67d9f36b67 201 case 1:
<> 157:ff67d9f36b67 202 io_cfg = (ioman_cfg_t)IOMAN_I2CM1(0, 0);
<> 157:ff67d9f36b67 203 break;
<> 157:ff67d9f36b67 204 case 2:
<> 157:ff67d9f36b67 205 io_cfg = (ioman_cfg_t)IOMAN_I2CM2(0, 0);
<> 157:ff67d9f36b67 206 break;
<> 157:ff67d9f36b67 207 default:
<> 157:ff67d9f36b67 208 return E_BAD_PARAM;
<> 157:ff67d9f36b67 209 }
<> 157:ff67d9f36b67 210
<> 157:ff67d9f36b67 211 if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) {
<> 157:ff67d9f36b67 212 return err;
<> 157:ff67d9f36b67 213 }
<> 157:ff67d9f36b67 214
<> 157:ff67d9f36b67 215 return E_NO_ERROR;
<> 157:ff67d9f36b67 216 }
<> 157:ff67d9f36b67 217
<> 157:ff67d9f36b67 218 /******************************************************************************/
<> 157:ff67d9f36b67 219 uint32_t SYS_I2CM_GetFreq(mxc_i2cm_regs_t *i2cm)
<> 157:ff67d9f36b67 220 {
<> 157:ff67d9f36b67 221 return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_I2CM));
<> 157:ff67d9f36b67 222 }
<> 157:ff67d9f36b67 223
<> 157:ff67d9f36b67 224 /******************************************************************************/
<> 157:ff67d9f36b67 225 int SYS_I2CS_Init(mxc_i2cs_regs_t *i2cs, const sys_cfg_i2cs_t *cfg)
<> 157:ff67d9f36b67 226 {
<> 157:ff67d9f36b67 227 int err;
<> 157:ff67d9f36b67 228
<> 157:ff67d9f36b67 229 if(cfg == NULL)
<> 157:ff67d9f36b67 230 return E_NULL_PTR;
<> 157:ff67d9f36b67 231
<> 157:ff67d9f36b67 232 CLKMAN_SetClkScale(CLKMAN_CLK_I2CS, cfg->clk_scale);
<> 157:ff67d9f36b67 233 MXC_CLKMAN->i2c_timer_ctrl = 1;
<> 157:ff67d9f36b67 234
<> 157:ff67d9f36b67 235 if ((err = IOMAN_Config(&cfg->io_cfg)) != E_NO_ERROR) {
<> 157:ff67d9f36b67 236 return err;
<> 157:ff67d9f36b67 237 }
<> 157:ff67d9f36b67 238
<> 157:ff67d9f36b67 239 return E_NO_ERROR;
<> 157:ff67d9f36b67 240 }
<> 157:ff67d9f36b67 241
<> 157:ff67d9f36b67 242 /******************************************************************************/
<> 157:ff67d9f36b67 243 int SYS_I2CS_Shutdown(mxc_i2cs_regs_t *i2cs)
<> 157:ff67d9f36b67 244 {
<> 157:ff67d9f36b67 245 int err;
<> 157:ff67d9f36b67 246 ioman_cfg_t io_cfg = (ioman_cfg_t)IOMAN_I2CS(0, 0);
<> 157:ff67d9f36b67 247
<> 157:ff67d9f36b67 248 if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) {
<> 157:ff67d9f36b67 249 return err;
<> 157:ff67d9f36b67 250 }
<> 157:ff67d9f36b67 251
<> 157:ff67d9f36b67 252 return E_NO_ERROR;
<> 157:ff67d9f36b67 253 }
<> 157:ff67d9f36b67 254
<> 157:ff67d9f36b67 255 /******************************************************************************/
<> 157:ff67d9f36b67 256 uint32_t SYS_I2CS_GetFreq(mxc_i2cs_regs_t *i2cs)
<> 157:ff67d9f36b67 257 {
<> 157:ff67d9f36b67 258 uint32_t freq, clkdiv;
<> 157:ff67d9f36b67 259
<> 157:ff67d9f36b67 260 if (CLKMAN_GetClkScale(CLKMAN_CLK_I2CS) == MXC_V_CLKMAN_CLK_SCALE_DISABLED) {
<> 157:ff67d9f36b67 261 freq = 0;
<> 157:ff67d9f36b67 262 } else {
<> 157:ff67d9f36b67 263 clkdiv = 1 << (CLKMAN_GetClkScale(CLKMAN_CLK_I2CS) - 1);
<> 157:ff67d9f36b67 264 freq = (SystemCoreClock / clkdiv);
<> 157:ff67d9f36b67 265 }
<> 157:ff67d9f36b67 266
<> 157:ff67d9f36b67 267 return freq;
<> 157:ff67d9f36b67 268 }
<> 157:ff67d9f36b67 269
<> 157:ff67d9f36b67 270 /******************************************************************************/
<> 157:ff67d9f36b67 271 int SYS_SPIM_Init(mxc_spim_regs_t *spim, const spim_cfg_t *spim_cfg, const sys_cfg_spim_t *sys_cfg)
<> 157:ff67d9f36b67 272 {
<> 157:ff67d9f36b67 273 int err, idx;
<> 157:ff67d9f36b67 274 clkman_scale_t clk_scale;
<> 157:ff67d9f36b67 275 uint32_t max_baud;
<> 157:ff67d9f36b67 276
<> 157:ff67d9f36b67 277 if(sys_cfg == NULL)
<> 157:ff67d9f36b67 278 return E_NULL_PTR;
<> 157:ff67d9f36b67 279
<> 157:ff67d9f36b67 280 idx = MXC_SPIM_GET_IDX(spim);
<> 157:ff67d9f36b67 281
<> 157:ff67d9f36b67 282 if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) {
<> 157:ff67d9f36b67 283 if(spim_cfg->baud > ((SystemCoreClock >> (sys_cfg->clk_scale - 1))/2)) {
<> 157:ff67d9f36b67 284 return E_BAD_PARAM;
<> 157:ff67d9f36b67 285 }
<> 157:ff67d9f36b67 286 CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIM0 + idx), sys_cfg->clk_scale);
<> 157:ff67d9f36b67 287 } else {
<> 157:ff67d9f36b67 288
<> 157:ff67d9f36b67 289 if(spim_cfg->baud > (SystemCoreClock/2)) {
<> 157:ff67d9f36b67 290 return E_BAD_PARAM;
<> 157:ff67d9f36b67 291 }
<> 157:ff67d9f36b67 292
<> 157:ff67d9f36b67 293 /* Setup the clock divider for the given baud rate */
<> 157:ff67d9f36b67 294 clk_scale = CLKMAN_SCALE_DISABLED;
<> 157:ff67d9f36b67 295 do {
<> 157:ff67d9f36b67 296 max_baud = ((SystemCoreClock >> clk_scale++) / 2);
<> 157:ff67d9f36b67 297 } while (spim_cfg->baud < max_baud && clk_scale < CLKMAN_SCALE_AUTO);
<> 157:ff67d9f36b67 298
<> 157:ff67d9f36b67 299 if(clk_scale == CLKMAN_SCALE_AUTO) {
<> 157:ff67d9f36b67 300 clk_scale--;
<> 157:ff67d9f36b67 301 }
<> 157:ff67d9f36b67 302
<> 157:ff67d9f36b67 303 CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIM0 + idx), clk_scale);
<> 157:ff67d9f36b67 304 }
<> 157:ff67d9f36b67 305
<> 157:ff67d9f36b67 306 if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) {
<> 157:ff67d9f36b67 307 return err;
<> 157:ff67d9f36b67 308 }
<> 157:ff67d9f36b67 309
<> 157:ff67d9f36b67 310 return E_NO_ERROR;
<> 157:ff67d9f36b67 311 }
<> 157:ff67d9f36b67 312
<> 157:ff67d9f36b67 313 /******************************************************************************/
<> 157:ff67d9f36b67 314 int SYS_SPIM_Shutdown(mxc_spim_regs_t *spim)
<> 157:ff67d9f36b67 315 {
<> 157:ff67d9f36b67 316 int err;
<> 157:ff67d9f36b67 317 int idx = MXC_SPIM_GET_IDX(spim);
<> 157:ff67d9f36b67 318 ioman_cfg_t io_cfg;
<> 157:ff67d9f36b67 319
<> 157:ff67d9f36b67 320 switch(idx)
<> 157:ff67d9f36b67 321 {
<> 157:ff67d9f36b67 322 case 0:
<> 157:ff67d9f36b67 323 io_cfg = (ioman_cfg_t)IOMAN_SPIM0(0, 0, 0, 0, 0, 0, 0, 0);
<> 157:ff67d9f36b67 324 break;
<> 157:ff67d9f36b67 325 case 1:
<> 157:ff67d9f36b67 326 io_cfg = (ioman_cfg_t)IOMAN_SPIM1(0, 0, 0, 0, 0, 0);
<> 157:ff67d9f36b67 327 break;
<> 157:ff67d9f36b67 328 case 2:
<> 157:ff67d9f36b67 329 io_cfg = (ioman_cfg_t)IOMAN_SPIM2(0, 0, 0, 0, 0, 0, 0, 0, 0);
<> 157:ff67d9f36b67 330 break;
<> 157:ff67d9f36b67 331 default:
<> 157:ff67d9f36b67 332 return E_BAD_PARAM;
<> 157:ff67d9f36b67 333 }
<> 157:ff67d9f36b67 334
<> 157:ff67d9f36b67 335 if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) {
<> 157:ff67d9f36b67 336 return err;
<> 157:ff67d9f36b67 337 }
<> 157:ff67d9f36b67 338
<> 157:ff67d9f36b67 339 return E_NO_ERROR;
<> 157:ff67d9f36b67 340 }
<> 157:ff67d9f36b67 341
<> 157:ff67d9f36b67 342 /******************************************************************************/
<> 157:ff67d9f36b67 343 uint32_t SYS_SPIM_GetFreq(mxc_spim_regs_t *spim)
<> 157:ff67d9f36b67 344 {
<> 157:ff67d9f36b67 345 int idx = MXC_SPIM_GET_IDX(spim);
<> 157:ff67d9f36b67 346 return SYS_GetFreq(CLKMAN_GetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIM0 + idx)));
<> 157:ff67d9f36b67 347 }
<> 157:ff67d9f36b67 348
<> 157:ff67d9f36b67 349 /******************************************************************************/
<> 157:ff67d9f36b67 350 int SYS_SPIX_Init(const sys_cfg_spix_t *sys_cfg, uint32_t baud)
<> 157:ff67d9f36b67 351 {
<> 157:ff67d9f36b67 352 int err;
<> 157:ff67d9f36b67 353 clkman_scale_t clk_scale;
<> 157:ff67d9f36b67 354 uint32_t min_baud;
<> 157:ff67d9f36b67 355
<> 157:ff67d9f36b67 356 if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) {
<> 157:ff67d9f36b67 357 CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIX), sys_cfg->clk_scale);
<> 157:ff67d9f36b67 358 } else {
<> 157:ff67d9f36b67 359 /* Setup the clock divider for the given baud rate */
<> 157:ff67d9f36b67 360 clk_scale = CLKMAN_SCALE_DISABLED;
<> 157:ff67d9f36b67 361 do {
<> 157:ff67d9f36b67 362 min_baud = ((SystemCoreClock >> clk_scale++) / (2 *
<> 157:ff67d9f36b67 363 (MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK >> MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS)));
<> 157:ff67d9f36b67 364 } while (baud < min_baud && clk_scale < CLKMAN_SCALE_AUTO);
<> 157:ff67d9f36b67 365
<> 157:ff67d9f36b67 366 /* check if baud rate cannot be reached */
<> 157:ff67d9f36b67 367 if(baud < min_baud)
<> 157:ff67d9f36b67 368 return E_BAD_STATE;
<> 157:ff67d9f36b67 369
<> 157:ff67d9f36b67 370 CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIX), clk_scale);
<> 157:ff67d9f36b67 371 }
<> 157:ff67d9f36b67 372
<> 157:ff67d9f36b67 373 if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) {
<> 157:ff67d9f36b67 374 return err;
<> 157:ff67d9f36b67 375 }
<> 157:ff67d9f36b67 376
<> 157:ff67d9f36b67 377 return E_NO_ERROR;
<> 157:ff67d9f36b67 378 }
<> 157:ff67d9f36b67 379
<> 157:ff67d9f36b67 380 /******************************************************************************/
<> 157:ff67d9f36b67 381 int SYS_SPIX_Shutdown()
<> 157:ff67d9f36b67 382 {
<> 157:ff67d9f36b67 383 int err;
<> 157:ff67d9f36b67 384 ioman_cfg_t io_cfg = IOMAN_SPIX(0, 0, 0, 0, 0, 0);
<> 157:ff67d9f36b67 385
<> 157:ff67d9f36b67 386 if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) {
<> 157:ff67d9f36b67 387 return err;
<> 157:ff67d9f36b67 388 }
<> 157:ff67d9f36b67 389
<> 157:ff67d9f36b67 390 return E_NO_ERROR;
<> 157:ff67d9f36b67 391 }
<> 157:ff67d9f36b67 392
<> 157:ff67d9f36b67 393 /******************************************************************************/
<> 157:ff67d9f36b67 394 uint32_t SYS_SPIX_GetFreq()
<> 157:ff67d9f36b67 395 {
<> 157:ff67d9f36b67 396 return SYS_GetFreq(CLKMAN_GetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIX)));
<> 157:ff67d9f36b67 397 }
<> 157:ff67d9f36b67 398
<> 157:ff67d9f36b67 399 /******************************************************************************/
<> 157:ff67d9f36b67 400 int SYS_OWM_Init(mxc_owm_regs_t *owm, const sys_cfg_owm_t *sys_cfg)
<> 157:ff67d9f36b67 401 {
<> 157:ff67d9f36b67 402 int err;
<> 157:ff67d9f36b67 403
<> 157:ff67d9f36b67 404 if(sys_cfg == NULL)
<> 157:ff67d9f36b67 405 return E_NULL_PTR;
<> 157:ff67d9f36b67 406
<> 157:ff67d9f36b67 407 if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO)
<> 157:ff67d9f36b67 408 {
<> 157:ff67d9f36b67 409 CLKMAN_SetClkScale(CLKMAN_CLK_OWM, sys_cfg->clk_scale);
<> 157:ff67d9f36b67 410 }
<> 157:ff67d9f36b67 411 else
<> 157:ff67d9f36b67 412 {
<> 157:ff67d9f36b67 413 CLKMAN_SetClkScale(CLKMAN_CLK_OWM, CLKMAN_SCALE_DIV_1);
<> 157:ff67d9f36b67 414 }
<> 157:ff67d9f36b67 415
<> 157:ff67d9f36b67 416 if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) {
<> 157:ff67d9f36b67 417 return err;
<> 157:ff67d9f36b67 418 }
<> 157:ff67d9f36b67 419
<> 157:ff67d9f36b67 420 return E_NO_ERROR;
<> 157:ff67d9f36b67 421 }
<> 157:ff67d9f36b67 422
<> 157:ff67d9f36b67 423 /******************************************************************************/
<> 157:ff67d9f36b67 424 int SYS_OWM_Shutdown(mxc_owm_regs_t *owm)
<> 157:ff67d9f36b67 425 {
<> 157:ff67d9f36b67 426 int err;
<> 157:ff67d9f36b67 427
<> 157:ff67d9f36b67 428 ioman_cfg_t io_cfg = IOMAN_OWM(0, 0);
<> 157:ff67d9f36b67 429
<> 157:ff67d9f36b67 430 if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) {
<> 157:ff67d9f36b67 431 return err;
<> 157:ff67d9f36b67 432 }
<> 157:ff67d9f36b67 433
<> 157:ff67d9f36b67 434 return E_NO_ERROR;
<> 157:ff67d9f36b67 435 }
<> 157:ff67d9f36b67 436
<> 157:ff67d9f36b67 437 /******************************************************************************/
<> 157:ff67d9f36b67 438 uint32_t SYS_OWM_GetFreq(mxc_owm_regs_t *owm)
<> 157:ff67d9f36b67 439 {
<> 157:ff67d9f36b67 440 return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_OWM));
<> 157:ff67d9f36b67 441 }
<> 157:ff67d9f36b67 442
<> 157:ff67d9f36b67 443 /******************************************************************************/
<> 157:ff67d9f36b67 444 uint32_t SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr)
<> 157:ff67d9f36b67 445 {
<> 157:ff67d9f36b67 446 return SystemCoreClock;
<> 157:ff67d9f36b67 447 }
<> 157:ff67d9f36b67 448
<> 157:ff67d9f36b67 449 /******************************************************************************/
<> 157:ff67d9f36b67 450 int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t *cfg)
<> 157:ff67d9f36b67 451 {
<> 157:ff67d9f36b67 452 int pin, gpio_index, tmr_index;
<> 157:ff67d9f36b67 453
<> 157:ff67d9f36b67 454 if (cfg != NULL)
<> 157:ff67d9f36b67 455 {
<> 157:ff67d9f36b67 456 /* Make sure the given GPIO mapps to the given TMR */
<> 157:ff67d9f36b67 457 for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++)
<> 157:ff67d9f36b67 458 {
<> 157:ff67d9f36b67 459 if(cfg->mask & (1 << pin))
<> 157:ff67d9f36b67 460 {
<> 157:ff67d9f36b67 461 gpio_index = (MXC_GPIO_MAX_PINS_PER_PORT * cfg->port) + pin;
<> 157:ff67d9f36b67 462 tmr_index = gpio_index % MXC_CFG_TMR_INSTANCES;
<> 157:ff67d9f36b67 463
<> 157:ff67d9f36b67 464 if(tmr_index == MXC_TMR_GET_IDX(tmr))
<> 157:ff67d9f36b67 465 return GPIO_Config(cfg);
<> 157:ff67d9f36b67 466 else
<> 157:ff67d9f36b67 467 return E_BAD_PARAM;
<> 157:ff67d9f36b67 468 }
<> 157:ff67d9f36b67 469 }
<> 157:ff67d9f36b67 470
<> 157:ff67d9f36b67 471 return E_BAD_PARAM;
<> 157:ff67d9f36b67 472
<> 157:ff67d9f36b67 473 } else {
<> 157:ff67d9f36b67 474 return E_NO_ERROR;
<> 157:ff67d9f36b67 475 }
<> 157:ff67d9f36b67 476 }
<> 157:ff67d9f36b67 477
<> 157:ff67d9f36b67 478 /******************************************************************************/
<> 157:ff67d9f36b67 479 uint32_t SYS_SysTick_GetFreq(void)
<> 157:ff67d9f36b67 480 {
<> 157:ff67d9f36b67 481 /* Determine is using internal (SystemCoreClock) or external (32768) clock */
<> 157:ff67d9f36b67 482 if ( (SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) || !(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
<> 157:ff67d9f36b67 483 return SystemCoreClock;
<> 157:ff67d9f36b67 484 } else {
<> 157:ff67d9f36b67 485 return SYS_RTC_CLK;
<> 157:ff67d9f36b67 486 }
<> 157:ff67d9f36b67 487 }
<> 157:ff67d9f36b67 488
<> 157:ff67d9f36b67 489 /******************************************************************************/
<> 157:ff67d9f36b67 490 uint32_t SYS_PT_GetFreq(void)
<> 157:ff67d9f36b67 491 {
<> 157:ff67d9f36b67 492 return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_PT));
<> 157:ff67d9f36b67 493 }
<> 157:ff67d9f36b67 494
<> 157:ff67d9f36b67 495 /******************************************************************************/
<> 157:ff67d9f36b67 496 void SYS_PT_Init(sys_pt_clk_scale clk_scale)
<> 157:ff67d9f36b67 497 {
<> 157:ff67d9f36b67 498 /* setup clock divider for pulse train clock */
<> 157:ff67d9f36b67 499 CLKMAN_SetClkScale(CLKMAN_CLK_PT, clk_scale);
<> 157:ff67d9f36b67 500 }
<> 157:ff67d9f36b67 501
<> 157:ff67d9f36b67 502 /******************************************************************************/
<> 157:ff67d9f36b67 503 int SYS_PT_Config(mxc_pt_regs_t *pt, const sys_cfg_pt_t *cfg)
<> 157:ff67d9f36b67 504 {
<> 157:ff67d9f36b67 505 int pt_index;
<> 157:ff67d9f36b67 506
<> 157:ff67d9f36b67 507 /* Make sure the given GPIO mapps to the given PT */
<> 157:ff67d9f36b67 508 pt_index = MXC_PT_GET_IDX(pt);
<> 157:ff67d9f36b67 509 if(pt_index < 0) {
<> 157:ff67d9f36b67 510 return E_NOT_SUPPORTED;
<> 157:ff67d9f36b67 511 }
<> 157:ff67d9f36b67 512
<> 157:ff67d9f36b67 513 /* Even number port */
<> 157:ff67d9f36b67 514 if(cfg->port%2 == 0) {
<> 157:ff67d9f36b67 515 /* Pin number should match PT number */
<> 157:ff67d9f36b67 516 if(!(cfg->mask & (0x1 << pt_index))) {
<> 157:ff67d9f36b67 517 return E_NOT_SUPPORTED;
<> 157:ff67d9f36b67 518 }
<> 157:ff67d9f36b67 519 } else {
<> 157:ff67d9f36b67 520 /* Pin number+8 should match PT */
<> 157:ff67d9f36b67 521 if(!((cfg->mask << 8) & (0x1 << pt_index))) {
<> 157:ff67d9f36b67 522 return E_NOT_SUPPORTED;
<> 157:ff67d9f36b67 523 }
<> 157:ff67d9f36b67 524 }
<> 157:ff67d9f36b67 525
<> 157:ff67d9f36b67 526 return GPIO_Config(cfg);
<> 157:ff67d9f36b67 527 }
<> 157:ff67d9f36b67 528
<> 157:ff67d9f36b67 529 /******************************************************************************/
<> 157:ff67d9f36b67 530 void SYS_USB_Enable(uint8_t enable)
<> 157:ff67d9f36b67 531 {
<> 157:ff67d9f36b67 532 /* Enable USB clock */
<> 157:ff67d9f36b67 533 CLKMAN_ClockGate(CLKMAN_USB_CLOCK, enable);
<> 157:ff67d9f36b67 534
<> 157:ff67d9f36b67 535 if(enable) {
<> 157:ff67d9f36b67 536 /* Enable USB Power */
<> 157:ff67d9f36b67 537 MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED;
<> 157:ff67d9f36b67 538 } else {
<> 157:ff67d9f36b67 539 /* Disable USB Power */
<> 157:ff67d9f36b67 540 MXC_PWRMAN->pwr_rst_ctrl &= ~MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED;
<> 157:ff67d9f36b67 541 }
<> 157:ff67d9f36b67 542 }
<> 157:ff67d9f36b67 543
<> 157:ff67d9f36b67 544 /******************************************************************************/
<> 157:ff67d9f36b67 545 int SYS_SysTick_Config(uint32_t ticks, int clk_src)
<> 157:ff67d9f36b67 546 {
<> 157:ff67d9f36b67 547
<> 157:ff67d9f36b67 548 if(ticks == 0)
<> 157:ff67d9f36b67 549 return E_BAD_PARAM;
<> 157:ff67d9f36b67 550
<> 157:ff67d9f36b67 551 /* If SystemClock, call default CMSIS config and return */
<> 157:ff67d9f36b67 552 if (clk_src) {
<> 157:ff67d9f36b67 553 return SysTick_Config(ticks);
<> 157:ff67d9f36b67 554 } else { /* External clock source requested
<> 157:ff67d9f36b67 555 enable RTC clock in run mode*/
<> 157:ff67d9f36b67 556 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN);
<> 157:ff67d9f36b67 557
<> 157:ff67d9f36b67 558 /* Disable SysTick Timer */
<> 157:ff67d9f36b67 559 SysTick->CTRL = 0;
<> 157:ff67d9f36b67 560 /* Check reload value for valid */
<> 157:ff67d9f36b67 561 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) {
<> 157:ff67d9f36b67 562 /* Reload value impossible */
<> 157:ff67d9f36b67 563 return E_BAD_PARAM;
<> 157:ff67d9f36b67 564 }
<> 157:ff67d9f36b67 565 /* set reload register */
<> 157:ff67d9f36b67 566 SysTick->LOAD = ticks - 1;
<> 157:ff67d9f36b67 567
<> 157:ff67d9f36b67 568 /* set Priority for Systick Interrupt */
<> 157:ff67d9f36b67 569 NVIC_SetPriority(SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
<> 157:ff67d9f36b67 570
<> 157:ff67d9f36b67 571 /* Load the SysTick Counter Value */
<> 157:ff67d9f36b67 572 SysTick->VAL = 0;
<> 157:ff67d9f36b67 573
<> 157:ff67d9f36b67 574 /* Enable SysTick IRQ and SysTick Timer leaving clock source as external */
<> 157:ff67d9f36b67 575 SysTick->CTRL = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
<> 157:ff67d9f36b67 576
<> 157:ff67d9f36b67 577 /* Function successful */
<> 157:ff67d9f36b67 578 return E_NO_ERROR;
<> 157:ff67d9f36b67 579 }
<> 157:ff67d9f36b67 580 }
<> 157:ff67d9f36b67 581
<> 157:ff67d9f36b67 582 /******************************************************************************/
<> 157:ff67d9f36b67 583 int SYS_SysTick_Delay(uint32_t ticks)
<> 157:ff67d9f36b67 584 {
<> 157:ff67d9f36b67 585 uint32_t cur_ticks, num_full, num_remain, previous_ticks, num_subtract, i;
<> 157:ff67d9f36b67 586 uint32_t reload, value, ctrl; /* save/restore variables */
<> 157:ff67d9f36b67 587
<> 157:ff67d9f36b67 588 if(ticks == 0)
<> 157:ff67d9f36b67 589 return E_BAD_PARAM;
<> 157:ff67d9f36b67 590
<> 157:ff67d9f36b67 591 /* If SysTick is not enabled we can take it for our delay */
<> 157:ff67d9f36b67 592 if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
<> 157:ff67d9f36b67 593
<> 157:ff67d9f36b67 594 /* Save current state in case it's disabled but already configured, restore at return.*/
<> 157:ff67d9f36b67 595 reload = SysTick->LOAD;
<> 157:ff67d9f36b67 596 value = SysTick->VAL;
<> 157:ff67d9f36b67 597 ctrl = SysTick->CTRL;
<> 157:ff67d9f36b67 598
<> 157:ff67d9f36b67 599 /* get the number of ticks less than max RELOAD. */
<> 157:ff67d9f36b67 600 num_remain = ticks % SysTick_LOAD_RELOAD_Msk;
<> 157:ff67d9f36b67 601
<> 157:ff67d9f36b67 602 /* if ticks is < Max SysTick Reload num_full will be 0, otherwise it will
<> 157:ff67d9f36b67 603 give us the number of max SysTicks cycles required */
<> 157:ff67d9f36b67 604 num_full = (ticks - 1) / SysTick_LOAD_RELOAD_Msk;
<> 157:ff67d9f36b67 605
<> 157:ff67d9f36b67 606 /* Do the required full systick countdowns */
<> 157:ff67d9f36b67 607 if (num_full) {
<> 157:ff67d9f36b67 608 /* load the max count value into systick */
<> 157:ff67d9f36b67 609 SysTick->LOAD = SysTick_LOAD_RELOAD_Msk;
<> 157:ff67d9f36b67 610 /* load the starting value */
<> 157:ff67d9f36b67 611 SysTick->VAL = 0;
<> 157:ff67d9f36b67 612 /*enable SysTick counter with SystemClock source internal, immediately forces LOAD register into VAL register */
<> 157:ff67d9f36b67 613 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
<> 157:ff67d9f36b67 614 /* CountFlag will get set when VAL reaches zero */
<> 157:ff67d9f36b67 615 for (i = num_full; i > 0; i--) {
<> 157:ff67d9f36b67 616 do {
<> 157:ff67d9f36b67 617 cur_ticks = SysTick->CTRL;
<> 157:ff67d9f36b67 618 } while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk));
<> 157:ff67d9f36b67 619 }
<> 157:ff67d9f36b67 620 /* Disable systick */
<> 157:ff67d9f36b67 621 SysTick->CTRL = 0;
<> 157:ff67d9f36b67 622 }
<> 157:ff67d9f36b67 623 /* Now handle the remainder of ticks */
<> 157:ff67d9f36b67 624 if (num_remain) {
<> 157:ff67d9f36b67 625 SysTick->LOAD = num_remain;
<> 157:ff67d9f36b67 626 SysTick->VAL = 0;
<> 157:ff67d9f36b67 627 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
<> 157:ff67d9f36b67 628 /* wait for countflag to get set */
<> 157:ff67d9f36b67 629 do {
<> 157:ff67d9f36b67 630 cur_ticks = SysTick->CTRL;
<> 157:ff67d9f36b67 631 } while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk));
<> 157:ff67d9f36b67 632 /* Disable systick */
<> 157:ff67d9f36b67 633 SysTick->CTRL = 0;
<> 157:ff67d9f36b67 634 }
<> 157:ff67d9f36b67 635
<> 157:ff67d9f36b67 636 /* restore original state of SysTick and return */
<> 157:ff67d9f36b67 637 SysTick->LOAD = reload;
<> 157:ff67d9f36b67 638 SysTick->VAL = value;
<> 157:ff67d9f36b67 639 SysTick->CTRL = ctrl;
<> 157:ff67d9f36b67 640
<> 157:ff67d9f36b67 641 return E_NO_ERROR;
<> 157:ff67d9f36b67 642
<> 157:ff67d9f36b67 643 } else { /* SysTick is enabled
<> 157:ff67d9f36b67 644 When SysTick is enabled count flag can not be used
<> 157:ff67d9f36b67 645 and the reload can not be changed.
<> 157:ff67d9f36b67 646 Do not read the CTRL register -> clears count flag */
<> 157:ff67d9f36b67 647
<> 157:ff67d9f36b67 648 /* Get the reload value for wrap/reload case */
<> 157:ff67d9f36b67 649 reload = SysTick->LOAD;
<> 157:ff67d9f36b67 650
<> 157:ff67d9f36b67 651 /* Read the starting systick value */
<> 157:ff67d9f36b67 652 previous_ticks = SysTick->VAL;
<> 157:ff67d9f36b67 653
<> 157:ff67d9f36b67 654 do {
<> 157:ff67d9f36b67 655 /* get current SysTick value */
<> 157:ff67d9f36b67 656 cur_ticks = SysTick->VAL;
<> 157:ff67d9f36b67 657 /* Check for wrap/reload of timer countval */
<> 157:ff67d9f36b67 658 if (cur_ticks > previous_ticks) {
<> 157:ff67d9f36b67 659 /* subtract count to 0 (previous_ticks) and wrap (reload value - cur_ticks) */
<> 157:ff67d9f36b67 660 num_subtract = (previous_ticks + (reload - cur_ticks));
<> 157:ff67d9f36b67 661 } else { /* standard case (no wrap)
<> 157:ff67d9f36b67 662 subtract off the number of ticks since last pass */
<> 157:ff67d9f36b67 663 num_subtract = (previous_ticks - cur_ticks);
<> 157:ff67d9f36b67 664 }
<> 157:ff67d9f36b67 665 /* check to see if we are done. */
<> 157:ff67d9f36b67 666 if (num_subtract >= ticks)
<> 157:ff67d9f36b67 667 return E_NO_ERROR;
<> 157:ff67d9f36b67 668 else
<> 157:ff67d9f36b67 669 ticks -= num_subtract;
<> 157:ff67d9f36b67 670 /* cur_ticks becomes previous_ticks for next timer read. */
<> 157:ff67d9f36b67 671 previous_ticks = cur_ticks;
<> 157:ff67d9f36b67 672 } while (ticks > 0);
<> 157:ff67d9f36b67 673 /* Should not ever be reached */
<> 157:ff67d9f36b67 674 return E_NO_ERROR;
<> 157:ff67d9f36b67 675 }
<> 157:ff67d9f36b67 676 }
<> 157:ff67d9f36b67 677
<> 157:ff67d9f36b67 678 /******************************************************************************/
<> 157:ff67d9f36b67 679 int SYS_RTC_Init(void)
<> 157:ff67d9f36b67 680 {
<> 157:ff67d9f36b67 681 /* Enable power for RTC for all LPx states */
<> 157:ff67d9f36b67 682 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN |
<> 157:ff67d9f36b67 683 MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
<> 157:ff67d9f36b67 684
<> 157:ff67d9f36b67 685 /* Enable clock to synchronizers */
<> 157:ff67d9f36b67 686 CLKMAN_SetClkScale(CLKMAN_CLK_SYNC, CLKMAN_SCALE_DIV_1);
<> 157:ff67d9f36b67 687
<> 157:ff67d9f36b67 688 return E_NO_ERROR;
<> 157:ff67d9f36b67 689 }
<> 157:ff67d9f36b67 690
<> 157:ff67d9f36b67 691 /******************************************************************************/
<> 157:ff67d9f36b67 692 void SYS_IOMAN_UseVDDIO(const gpio_cfg_t *cfg)
<> 157:ff67d9f36b67 693 {
<> 157:ff67d9f36b67 694 unsigned int startbit = (cfg->port * 8);
<> 157:ff67d9f36b67 695 volatile uint32_t *use_vddioh_reg = &MXC_IOMAN->use_vddioh_0 + (startbit / 32);
<> 157:ff67d9f36b67 696 *use_vddioh_reg &= ~cfg->mask << (startbit % 32);
<> 157:ff67d9f36b67 697 }
<> 157:ff67d9f36b67 698
<> 157:ff67d9f36b67 699 /******************************************************************************/
<> 157:ff67d9f36b67 700 void SYS_IOMAN_UseVDDIOH(const gpio_cfg_t *cfg)
<> 157:ff67d9f36b67 701 {
<> 157:ff67d9f36b67 702 unsigned int startbit = (cfg->port * 8);
<> 157:ff67d9f36b67 703 volatile uint32_t *use_vddioh_reg = &MXC_IOMAN->use_vddioh_0 + (startbit / 32);
<> 157:ff67d9f36b67 704 *use_vddioh_reg |= cfg->mask << (startbit % 32);
<> 157:ff67d9f36b67 705 }
<> 157:ff67d9f36b67 706
<> 157:ff67d9f36b67 707 /******************************************************************************/
<> 157:ff67d9f36b67 708 void SYS_WDT_Init(mxc_wdt_regs_t *wdt, const sys_cfg_wdt_t *cfg)
<> 157:ff67d9f36b67 709 {
<> 157:ff67d9f36b67 710
<> 157:ff67d9f36b67 711 if(cfg->clk == CLKMAN_WDT_SELECT_NANO_RING_OSCILLATOR)
<> 157:ff67d9f36b67 712 {
<> 157:ff67d9f36b67 713 /*enable nanoring in run mode */
<> 157:ff67d9f36b67 714 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_RUN);
<> 157:ff67d9f36b67 715 }
<> 157:ff67d9f36b67 716 else if(cfg->clk == CLKMAN_WDT_SELECT_32KHZ_RTC_OSCILLATOR)
<> 157:ff67d9f36b67 717 {
<> 157:ff67d9f36b67 718 /*enabled RTC in run mode */
<> 157:ff67d9f36b67 719 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN);
<> 157:ff67d9f36b67 720 }
<> 157:ff67d9f36b67 721
<> 157:ff67d9f36b67 722 if(wdt == MXC_WDT0) {
<> 157:ff67d9f36b67 723 /*select clock source */
<> 157:ff67d9f36b67 724 CLKMAN_WdtClkSelect(0, cfg->clk);
<> 157:ff67d9f36b67 725
<> 157:ff67d9f36b67 726 /*Set scale of clock (only used for system clock as source) */
<> 157:ff67d9f36b67 727 CLKMAN_SetClkScale(CLKMAN_CLK_WDT0, cfg->clk_scale);
<> 157:ff67d9f36b67 728
<> 157:ff67d9f36b67 729 /*Enable clock */
<> 157:ff67d9f36b67 730 CLKMAN_ClockGate(CLKMAN_WDT0_CLOCK, 1);
<> 157:ff67d9f36b67 731 } else if (wdt == MXC_WDT1) {
<> 157:ff67d9f36b67 732 /*select clock source */
<> 157:ff67d9f36b67 733 CLKMAN_WdtClkSelect(1, cfg->clk);
<> 157:ff67d9f36b67 734
<> 157:ff67d9f36b67 735 /*Set scale of clock (only used for system clock as source) */
<> 157:ff67d9f36b67 736 CLKMAN_SetClkScale(CLKMAN_CLK_WDT1, cfg->clk_scale);
<> 157:ff67d9f36b67 737
<> 157:ff67d9f36b67 738 /*Enable clock */
<> 157:ff67d9f36b67 739 CLKMAN_ClockGate(CLKMAN_WDT1_CLOCK, 1);
<> 157:ff67d9f36b67 740 }
<> 157:ff67d9f36b67 741 }
<> 157:ff67d9f36b67 742
<> 157:ff67d9f36b67 743 /******************************************************************************/
<> 157:ff67d9f36b67 744 void SYS_PRNG_Init(void)
<> 157:ff67d9f36b67 745 {
<> 157:ff67d9f36b67 746 /* Start crypto ring, unconditionally */
<> 157:ff67d9f36b67 747 CLKMAN_CryptoClockEnable(1);
<> 157:ff67d9f36b67 748
<> 157:ff67d9f36b67 749 /* If we find the dividers in anything other than off, don't touch them */
<> 157:ff67d9f36b67 750 if (CLKMAN_GetClkScale(CLKMAN_CRYPTO_CLK_PRNG) == CLKMAN_SCALE_DISABLED) {
<> 157:ff67d9f36b67 751 /* Div 1 mode */
<> 157:ff67d9f36b67 752 CLKMAN_SetClkScale(CLKMAN_CRYPTO_CLK_PRNG, CLKMAN_SCALE_DIV_1);
<> 157:ff67d9f36b67 753 }
<> 157:ff67d9f36b67 754
<> 157:ff67d9f36b67 755 if (CLKMAN_GetClkScale(CLKMAN_CLK_PRNG) == CLKMAN_SCALE_DISABLED) {
<> 157:ff67d9f36b67 756 /* Div 1 mode */
<> 157:ff67d9f36b67 757 CLKMAN_SetClkScale(CLKMAN_CLK_PRNG, CLKMAN_SCALE_DIV_1);
<> 157:ff67d9f36b67 758 }
<> 157:ff67d9f36b67 759 }
<> 157:ff67d9f36b67 760
<> 157:ff67d9f36b67 761 /******************************************************************************/
<> 157:ff67d9f36b67 762 void SYS_MAA_Init(void)
<> 157:ff67d9f36b67 763 {
<> 157:ff67d9f36b67 764 /* Start crypto ring, unconditionally */
<> 157:ff67d9f36b67 765 CLKMAN_CryptoClockEnable(1);
<> 157:ff67d9f36b67 766
<> 157:ff67d9f36b67 767 /* If we find the dividers in anything other than off, don't touch them */
<> 157:ff67d9f36b67 768 if (CLKMAN_GetClkScale(CLKMAN_CRYPTO_CLK_MAA) == CLKMAN_SCALE_DISABLED) {
<> 157:ff67d9f36b67 769 /* Div 1 mode */
<> 157:ff67d9f36b67 770 CLKMAN_SetClkScale(CLKMAN_CRYPTO_CLK_MAA, CLKMAN_SCALE_DIV_1);
<> 157:ff67d9f36b67 771 }
<> 157:ff67d9f36b67 772 }
<> 157:ff67d9f36b67 773
<> 157:ff67d9f36b67 774 /******************************************************************************/
<> 157:ff67d9f36b67 775 uint32_t SYS_SRAM_GetSize(void)
<> 157:ff67d9f36b67 776 {
<> 157:ff67d9f36b67 777 uint32_t memSize;
<> 157:ff67d9f36b67 778
<> 157:ff67d9f36b67 779 /* Read TRIM value*/
<> 157:ff67d9f36b67 780 int SRAMtrim = (MXC_TRIM->reg10_mem_size & MXC_F_TRIM_REG10_MEM_SIZE_SRAM) >> MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS;
<> 157:ff67d9f36b67 781
<> 157:ff67d9f36b67 782 /* Decode trim value into memory size in bytes */
<> 157:ff67d9f36b67 783 switch(SRAMtrim)
<> 157:ff67d9f36b67 784 {
<> 157:ff67d9f36b67 785 case MXC_V_TRIM_REG10_MEM_SRAM_THREE_FOURTHS_SIZE:
<> 157:ff67d9f36b67 786 memSize = (MXC_SRAM_FULL_MEM_SIZE >> 2) * 3;
<> 157:ff67d9f36b67 787 break;
<> 157:ff67d9f36b67 788
<> 157:ff67d9f36b67 789 case MXC_V_TRIM_REG10_MEM_SRAM_HALF_SIZE:
<> 157:ff67d9f36b67 790 memSize = MXC_SRAM_FULL_MEM_SIZE >> 1;
<> 157:ff67d9f36b67 791 break;
<> 157:ff67d9f36b67 792
<> 157:ff67d9f36b67 793 default: /* other values are FULL size */
<> 157:ff67d9f36b67 794 memSize = MXC_SRAM_FULL_MEM_SIZE;
<> 157:ff67d9f36b67 795 break;
<> 157:ff67d9f36b67 796 }
<> 157:ff67d9f36b67 797
<> 157:ff67d9f36b67 798 /* Returns size in bytes */
<> 157:ff67d9f36b67 799 return memSize;
<> 157:ff67d9f36b67 800 }
<> 157:ff67d9f36b67 801
<> 157:ff67d9f36b67 802 /******************************************************************************/
<> 157:ff67d9f36b67 803 uint32_t SYS_FLASH_GetSize(void)
<> 157:ff67d9f36b67 804 {
<> 157:ff67d9f36b67 805 uint32_t memSize;
<> 157:ff67d9f36b67 806
<> 157:ff67d9f36b67 807 /* Read TRIM value */
<> 157:ff67d9f36b67 808 int FLASHtrim = (MXC_TRIM->reg10_mem_size & MXC_F_TRIM_REG10_MEM_SIZE_FLASH) >> MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS;
<> 157:ff67d9f36b67 809
<> 157:ff67d9f36b67 810 /* Decode trim value into memory size in bytes*/
<> 157:ff67d9f36b67 811 switch(FLASHtrim)
<> 157:ff67d9f36b67 812 {
<> 157:ff67d9f36b67 813 case MXC_V_TRIM_REG10_MEM_FLASH_THREE_FOURTHS_SIZE:
<> 157:ff67d9f36b67 814 memSize = (MXC_FLASH_FULL_MEM_SIZE >> 2) * 3;
<> 157:ff67d9f36b67 815 break;
<> 157:ff67d9f36b67 816 case MXC_V_TRIM_REG10_MEM_FLASH_HALF_SIZE:
<> 157:ff67d9f36b67 817 memSize = (MXC_FLASH_FULL_MEM_SIZE >> 1);
<> 157:ff67d9f36b67 818 break;
<> 157:ff67d9f36b67 819 case MXC_V_TRIM_REG10_MEM_FLASH_THREE_EIGHTHS_SIZE:
<> 157:ff67d9f36b67 820 memSize = (MXC_FLASH_FULL_MEM_SIZE >> 3) * 3;
<> 157:ff67d9f36b67 821 break;
<> 157:ff67d9f36b67 822 case MXC_V_TRIM_REG10_MEM_FLASH_FOURTH_SIZE:
<> 157:ff67d9f36b67 823 memSize = (MXC_FLASH_FULL_MEM_SIZE >> 2);
<> 157:ff67d9f36b67 824 break;
<> 157:ff67d9f36b67 825 default: /* other values are FULL size */
<> 157:ff67d9f36b67 826 memSize = MXC_FLASH_FULL_MEM_SIZE;
<> 157:ff67d9f36b67 827 break;
<> 157:ff67d9f36b67 828 }
<> 157:ff67d9f36b67 829
<> 157:ff67d9f36b67 830 /* Returns size in bytes */
<> 157:ff67d9f36b67 831 return memSize;
<> 157:ff67d9f36b67 832 }