Iftikhar Aziz / mbed-dev

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Dependents:   LSS_Rev_1

Fork of mbed-dev by Umar Naeem

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c@144:ef7eb2e8f9f7
Child:
157:ff67d9f36b67
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_hash.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief HASH HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the HASH peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + HASH/HMAC Processing functions by algorithm using polling mode
<> 144:ef7eb2e8f9f7 12 * + HASH/HMAC functions by algorithm using interrupt mode
<> 144:ef7eb2e8f9f7 13 * + HASH/HMAC functions by algorithm using DMA mode
<> 144:ef7eb2e8f9f7 14 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 @verbatim
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 19 ==============================================================================
<> 144:ef7eb2e8f9f7 20 [..]
<> 144:ef7eb2e8f9f7 21 The HASH HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 22 (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
<> 144:ef7eb2e8f9f7 23 (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 24 (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
<> 144:ef7eb2e8f9f7 25 (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 26 (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 27 (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
<> 144:ef7eb2e8f9f7 28 (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())
<> 144:ef7eb2e8f9f7 29 (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 30 (+++) Configure and enable one DMA stream one for managing data transfer from
<> 144:ef7eb2e8f9f7 31 memory to peripheral (input stream). Managing data transfer from
<> 144:ef7eb2e8f9f7 32 peripheral to memory can be performed only using CPU
<> 144:ef7eb2e8f9f7 33 (+++) Associate the initialized DMA handle to the HASH DMA handle
<> 144:ef7eb2e8f9f7 34 using __HAL_LINKDMA()
<> 144:ef7eb2e8f9f7 35 (+++) Configure the priority and enable the NVIC for the transfer complete
<> 144:ef7eb2e8f9f7 36 interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 37 (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
<> 144:ef7eb2e8f9f7 38 (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
<> 144:ef7eb2e8f9f7 39 (##) For HMAC, the encryption key.
<> 144:ef7eb2e8f9f7 40 (##) For HMAC, the key size used for encryption.
<> 144:ef7eb2e8f9f7 41 (#)Three processing functions are available:
<> 144:ef7eb2e8f9f7 42 (##) Polling mode: processing APIs are blocking functions
<> 144:ef7eb2e8f9f7 43 i.e. they process the data and wait till the digest computation is finished
<> 144:ef7eb2e8f9f7 44 e.g. HAL_HASH_SHA1_Start()
<> 144:ef7eb2e8f9f7 45 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
<> 144:ef7eb2e8f9f7 46 i.e. they process the data under interrupt
<> 144:ef7eb2e8f9f7 47 e.g. HAL_HASH_SHA1_Start_IT()
<> 144:ef7eb2e8f9f7 48 (##) DMA mode: processing APIs are not blocking functions and the CPU is
<> 144:ef7eb2e8f9f7 49 not used for data transfer i.e. the data transfer is ensured by DMA
<> 144:ef7eb2e8f9f7 50 e.g. HAL_HASH_SHA1_Start_DMA()
<> 144:ef7eb2e8f9f7 51 (#)When the processing function is called at first time after HAL_HASH_Init()
<> 144:ef7eb2e8f9f7 52 the HASH peripheral is initialized and processes the buffer in input.
<> 144:ef7eb2e8f9f7 53 After that, the digest computation is started.
<> 144:ef7eb2e8f9f7 54 When processing multi-buffer use the accumulate function to write the
<> 144:ef7eb2e8f9f7 55 data in the peripheral without starting the digest computation. In last
<> 144:ef7eb2e8f9f7 56 buffer use the start function to input the last buffer ans start the digest
<> 144:ef7eb2e8f9f7 57 computation.
<> 144:ef7eb2e8f9f7 58 (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
<> 144:ef7eb2e8f9f7 59 (##) write (n-1)th data buffer in the peripheral without starting the digest computation
<> 144:ef7eb2e8f9f7 60 (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation
<> 144:ef7eb2e8f9f7 61 (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
<> 144:ef7eb2e8f9f7 62 (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().
<> 144:ef7eb2e8f9f7 63 After that, call the finish function in order to get the digest value
<> 144:ef7eb2e8f9f7 64 e.g. HAL_HASH_SHA1_Finish()
<> 144:ef7eb2e8f9f7 65 (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 @endverbatim
<> 144:ef7eb2e8f9f7 68 ******************************************************************************
<> 144:ef7eb2e8f9f7 69 * @attention
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 74 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 75 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 76 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 78 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 79 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 81 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 82 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 83 *
<> 144:ef7eb2e8f9f7 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 ******************************************************************************
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 #if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /** @defgroup HASH HASH
<> 144:ef7eb2e8f9f7 108 * @brief HASH HAL module driver.
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111 #ifdef HAL_HASH_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 118 /** @defgroup HASH_Private_Functions HASH Private Functions
<> 144:ef7eb2e8f9f7 119 * @{
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 122 static void HASH_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 123 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
<> 144:ef7eb2e8f9f7 124 static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @}
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 130 /** @addtogroup HASH_Private_Functions
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /**
<> 144:ef7eb2e8f9f7 135 * @brief DMA HASH Input Data complete callback.
<> 144:ef7eb2e8f9f7 136 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 137 * @retval None
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 140 {
<> 144:ef7eb2e8f9f7 141 HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 142 uint32_t inputaddr = 0;
<> 144:ef7eb2e8f9f7 143 uint32_t buffersize = 0;
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 /* Disable the DMA transfer */
<> 144:ef7eb2e8f9f7 148 HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 151 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /* Call Input data transfer complete callback */
<> 144:ef7eb2e8f9f7 154 HAL_HASH_InCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 155 }
<> 144:ef7eb2e8f9f7 156 else
<> 144:ef7eb2e8f9f7 157 {
<> 144:ef7eb2e8f9f7 158 /* Increment Interrupt counter */
<> 144:ef7eb2e8f9f7 159 hhash->HashInCount++;
<> 144:ef7eb2e8f9f7 160 /* Disable the DMA transfer before starting the next transfer */
<> 144:ef7eb2e8f9f7 161 HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 if(hhash->HashInCount <= 2)
<> 144:ef7eb2e8f9f7 164 {
<> 144:ef7eb2e8f9f7 165 /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
<> 144:ef7eb2e8f9f7 166 if(hhash->HashInCount == 1)
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 169 buffersize = hhash->HashBuffSize;
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171 /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
<> 144:ef7eb2e8f9f7 172 else if(hhash->HashInCount == 2)
<> 144:ef7eb2e8f9f7 173 {
<> 144:ef7eb2e8f9f7 174 inputaddr = (uint32_t)hhash->Init.pKey;
<> 144:ef7eb2e8f9f7 175 buffersize = hhash->Init.KeySize;
<> 144:ef7eb2e8f9f7 176 }
<> 144:ef7eb2e8f9f7 177 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 178 MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Set the HASH DMA transfer complete */
<> 144:ef7eb2e8f9f7 181 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Enable the DMA In DMA Stream */
<> 144:ef7eb2e8f9f7 184 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 187 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189 else
<> 144:ef7eb2e8f9f7 190 {
<> 144:ef7eb2e8f9f7 191 /* Disable the DMA transfer */
<> 144:ef7eb2e8f9f7 192 HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Reset the InCount */
<> 144:ef7eb2e8f9f7 195 hhash->HashInCount = 0;
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 198 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* Call Input data transfer complete callback */
<> 144:ef7eb2e8f9f7 201 HAL_HASH_InCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 202 }
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @brief DMA HASH communication error callback.
<> 144:ef7eb2e8f9f7 208 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 209 * @retval None
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 static void HASH_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 212 {
<> 144:ef7eb2e8f9f7 213 HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 214 hhash->State= HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 215 HAL_HASH_ErrorCallback(hhash);
<> 144:ef7eb2e8f9f7 216 }
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /**
<> 144:ef7eb2e8f9f7 219 * @brief Writes the input buffer in data register.
<> 144:ef7eb2e8f9f7 220 * @param pInBuffer: Pointer to input buffer
<> 144:ef7eb2e8f9f7 221 * @param Size: The size of input buffer
<> 144:ef7eb2e8f9f7 222 * @retval None
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 uint32_t buffercounter;
<> 144:ef7eb2e8f9f7 227 uint32_t inputaddr = (uint32_t) pInBuffer;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
<> 144:ef7eb2e8f9f7 230 {
<> 144:ef7eb2e8f9f7 231 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 232 inputaddr+=4;
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @brief Provides the message digest result.
<> 144:ef7eb2e8f9f7 238 * @param pMsgDigest: Pointer to the message digest
<> 144:ef7eb2e8f9f7 239 * @param Size: The size of the message digest in bytes
<> 144:ef7eb2e8f9f7 240 * @retval None
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
<> 144:ef7eb2e8f9f7 243 {
<> 144:ef7eb2e8f9f7 244 uint32_t msgdigest = (uint32_t)pMsgDigest;
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 switch(Size)
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 case 16:
<> 144:ef7eb2e8f9f7 249 /* Read the message digest */
<> 144:ef7eb2e8f9f7 250 *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
<> 144:ef7eb2e8f9f7 251 msgdigest+=4;
<> 144:ef7eb2e8f9f7 252 *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
<> 144:ef7eb2e8f9f7 253 msgdigest+=4;
<> 144:ef7eb2e8f9f7 254 *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
<> 144:ef7eb2e8f9f7 255 msgdigest+=4;
<> 144:ef7eb2e8f9f7 256 *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
<> 144:ef7eb2e8f9f7 257 break;
<> 144:ef7eb2e8f9f7 258 case 20:
<> 144:ef7eb2e8f9f7 259 /* Read the message digest */
<> 144:ef7eb2e8f9f7 260 *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
<> 144:ef7eb2e8f9f7 261 msgdigest+=4;
<> 144:ef7eb2e8f9f7 262 *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
<> 144:ef7eb2e8f9f7 263 msgdigest+=4;
<> 144:ef7eb2e8f9f7 264 *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
<> 144:ef7eb2e8f9f7 265 msgdigest+=4;
<> 144:ef7eb2e8f9f7 266 *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
<> 144:ef7eb2e8f9f7 267 msgdigest+=4;
<> 144:ef7eb2e8f9f7 268 *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
<> 144:ef7eb2e8f9f7 269 break;
<> 144:ef7eb2e8f9f7 270 case 28:
<> 144:ef7eb2e8f9f7 271 /* Read the message digest */
<> 144:ef7eb2e8f9f7 272 *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
<> 144:ef7eb2e8f9f7 273 msgdigest+=4;
<> 144:ef7eb2e8f9f7 274 *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
<> 144:ef7eb2e8f9f7 275 msgdigest+=4;
<> 144:ef7eb2e8f9f7 276 *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
<> 144:ef7eb2e8f9f7 277 msgdigest+=4;
<> 144:ef7eb2e8f9f7 278 *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
<> 144:ef7eb2e8f9f7 279 msgdigest+=4;
<> 144:ef7eb2e8f9f7 280 *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
<> 144:ef7eb2e8f9f7 281 msgdigest+=4;
<> 144:ef7eb2e8f9f7 282 *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
<> 144:ef7eb2e8f9f7 283 msgdigest+=4;
<> 144:ef7eb2e8f9f7 284 *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
<> 144:ef7eb2e8f9f7 285 break;
<> 144:ef7eb2e8f9f7 286 case 32:
<> 144:ef7eb2e8f9f7 287 /* Read the message digest */
<> 144:ef7eb2e8f9f7 288 *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
<> 144:ef7eb2e8f9f7 289 msgdigest+=4;
<> 144:ef7eb2e8f9f7 290 *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
<> 144:ef7eb2e8f9f7 291 msgdigest+=4;
<> 144:ef7eb2e8f9f7 292 *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
<> 144:ef7eb2e8f9f7 293 msgdigest+=4;
<> 144:ef7eb2e8f9f7 294 *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
<> 144:ef7eb2e8f9f7 295 msgdigest+=4;
<> 144:ef7eb2e8f9f7 296 *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
<> 144:ef7eb2e8f9f7 297 msgdigest+=4;
<> 144:ef7eb2e8f9f7 298 *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
<> 144:ef7eb2e8f9f7 299 msgdigest+=4;
<> 144:ef7eb2e8f9f7 300 *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
<> 144:ef7eb2e8f9f7 301 msgdigest+=4;
<> 144:ef7eb2e8f9f7 302 *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
<> 144:ef7eb2e8f9f7 303 break;
<> 144:ef7eb2e8f9f7 304 default:
<> 144:ef7eb2e8f9f7 305 break;
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307 }
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /**
<> 144:ef7eb2e8f9f7 310 * @}
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 314 /** @addtogroup HASH_Exported_Functions
<> 144:ef7eb2e8f9f7 315 * @{
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 320 * @brief Initialization and Configuration functions.
<> 144:ef7eb2e8f9f7 321 *
<> 144:ef7eb2e8f9f7 322 @verbatim
<> 144:ef7eb2e8f9f7 323 ===============================================================================
<> 144:ef7eb2e8f9f7 324 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 325 ===============================================================================
<> 144:ef7eb2e8f9f7 326 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 327 (+) Initialize the HASH according to the specified parameters
<> 144:ef7eb2e8f9f7 328 in the HASH_InitTypeDef and creates the associated handle.
<> 144:ef7eb2e8f9f7 329 (+) DeInitialize the HASH peripheral.
<> 144:ef7eb2e8f9f7 330 (+) Initialize the HASH MSP.
<> 144:ef7eb2e8f9f7 331 (+) DeInitialize HASH MSP.
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 @endverbatim
<> 144:ef7eb2e8f9f7 334 * @{
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @brief Initializes the HASH according to the specified parameters in the
<> 144:ef7eb2e8f9f7 339 HASH_HandleTypeDef and creates the associated handle.
<> 144:ef7eb2e8f9f7 340 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 341 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 342 * @retval HAL status
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 345 {
<> 144:ef7eb2e8f9f7 346 /* Check the hash handle allocation */
<> 144:ef7eb2e8f9f7 347 if(hhash == NULL)
<> 144:ef7eb2e8f9f7 348 {
<> 144:ef7eb2e8f9f7 349 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 350 }
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Check the parameters */
<> 144:ef7eb2e8f9f7 353 assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 if(hhash->State == HAL_HASH_STATE_RESET)
<> 144:ef7eb2e8f9f7 356 {
<> 144:ef7eb2e8f9f7 357 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 358 hhash->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 359 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 360 HAL_HASH_MspInit(hhash);
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 364 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Reset HashInCount, HashBuffSize and HashITCounter */
<> 144:ef7eb2e8f9f7 367 hhash->HashInCount = 0;
<> 144:ef7eb2e8f9f7 368 hhash->HashBuffSize = 0;
<> 144:ef7eb2e8f9f7 369 hhash->HashITCounter = 0;
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Set the data type */
<> 144:ef7eb2e8f9f7 372 HASH->CR |= (uint32_t) (hhash->Init.DataType);
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 375 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Set the default HASH phase */
<> 144:ef7eb2e8f9f7 378 hhash->Phase = HAL_HASH_PHASE_READY;
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /* Return function status */
<> 144:ef7eb2e8f9f7 381 return HAL_OK;
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /**
<> 144:ef7eb2e8f9f7 385 * @brief DeInitializes the HASH peripheral.
<> 144:ef7eb2e8f9f7 386 * @note This API must be called before starting a new processing.
<> 144:ef7eb2e8f9f7 387 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 388 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 389 * @retval HAL status
<> 144:ef7eb2e8f9f7 390 */
<> 144:ef7eb2e8f9f7 391 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393 /* Check the HASH handle allocation */
<> 144:ef7eb2e8f9f7 394 if(hhash == NULL)
<> 144:ef7eb2e8f9f7 395 {
<> 144:ef7eb2e8f9f7 396 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 397 }
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 400 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /* Set the default HASH phase */
<> 144:ef7eb2e8f9f7 403 hhash->Phase = HAL_HASH_PHASE_READY;
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /* Reset HashInCount, HashBuffSize and HashITCounter */
<> 144:ef7eb2e8f9f7 406 hhash->HashInCount = 0;
<> 144:ef7eb2e8f9f7 407 hhash->HashBuffSize = 0;
<> 144:ef7eb2e8f9f7 408 hhash->HashITCounter = 0;
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 411 HAL_HASH_MspDeInit(hhash);
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 414 hhash->State = HAL_HASH_STATE_RESET;
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Release Lock */
<> 144:ef7eb2e8f9f7 417 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Return function status */
<> 144:ef7eb2e8f9f7 420 return HAL_OK;
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /**
<> 144:ef7eb2e8f9f7 424 * @brief Initializes the HASH MSP.
<> 144:ef7eb2e8f9f7 425 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 426 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 427 * @retval None
<> 144:ef7eb2e8f9f7 428 */
<> 144:ef7eb2e8f9f7 429 __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 432 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 435 the HAL_HASH_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 436 */
<> 144:ef7eb2e8f9f7 437 }
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /**
<> 144:ef7eb2e8f9f7 440 * @brief DeInitializes HASH MSP.
<> 144:ef7eb2e8f9f7 441 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 442 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 443 * @retval None
<> 144:ef7eb2e8f9f7 444 */
<> 144:ef7eb2e8f9f7 445 __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 446 {
<> 144:ef7eb2e8f9f7 447 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 448 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 451 the HAL_HASH_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /**
<> 144:ef7eb2e8f9f7 456 * @brief Input data transfer complete callback.
<> 144:ef7eb2e8f9f7 457 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 458 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 459 * @retval None
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461 __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 462 {
<> 144:ef7eb2e8f9f7 463 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 464 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 467 the HAL_HASH_InCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469 }
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /**
<> 144:ef7eb2e8f9f7 472 * @brief Data transfer Error callback.
<> 144:ef7eb2e8f9f7 473 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 474 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 475 * @retval None
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477 __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 478 {
<> 144:ef7eb2e8f9f7 479 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 480 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 483 the HAL_HASH_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /**
<> 144:ef7eb2e8f9f7 488 * @brief Digest computation complete callback. It is used only with interrupt.
<> 144:ef7eb2e8f9f7 489 * @note This callback is not relevant with DMA.
<> 144:ef7eb2e8f9f7 490 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 491 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 492 * @retval None
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494 __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 497 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 500 the HAL_HASH_DgstCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502 }
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /**
<> 144:ef7eb2e8f9f7 505 * @}
<> 144:ef7eb2e8f9f7 506 */
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode
<> 144:ef7eb2e8f9f7 509 * @brief processing functions using polling mode
<> 144:ef7eb2e8f9f7 510 *
<> 144:ef7eb2e8f9f7 511 @verbatim
<> 144:ef7eb2e8f9f7 512 ===============================================================================
<> 144:ef7eb2e8f9f7 513 ##### HASH processing using polling mode functions#####
<> 144:ef7eb2e8f9f7 514 ===============================================================================
<> 144:ef7eb2e8f9f7 515 [..] This section provides functions allowing to calculate in polling mode
<> 144:ef7eb2e8f9f7 516 the hash value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 517 (+) MD5
<> 144:ef7eb2e8f9f7 518 (+) SHA1
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 @endverbatim
<> 144:ef7eb2e8f9f7 521 * @{
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /**
<> 144:ef7eb2e8f9f7 525 * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 526 The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 527 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 528 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 529 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 530 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 531 * If the Size is multiple of 64 bytes, appending the input buffer is possible.
<> 144:ef7eb2e8f9f7 532 * If the Size is not multiple of 64 bytes, the padding is managed by hardware
<> 144:ef7eb2e8f9f7 533 * and appending the input buffer is no more possible.
<> 144:ef7eb2e8f9f7 534 * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
<> 144:ef7eb2e8f9f7 535 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 536 * @retval HAL status
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Process Locked */
<> 144:ef7eb2e8f9f7 543 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 546 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 549 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 550 {
<> 144:ef7eb2e8f9f7 551 /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 552 the message digest of a new message */
<> 144:ef7eb2e8f9f7 553 HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 554 }
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /* Set the phase */
<> 144:ef7eb2e8f9f7 557 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 560 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 563 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 566 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* Get tick */
<> 144:ef7eb2e8f9f7 569 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 574 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 575 {
<> 144:ef7eb2e8f9f7 576 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 /* Change state */
<> 144:ef7eb2e8f9f7 579 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 582 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587 }
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* Read the message digest */
<> 144:ef7eb2e8f9f7 590 HASH_GetDigest(pOutBuffer, 16);
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 593 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 596 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Return function status */
<> 144:ef7eb2e8f9f7 599 return HAL_OK;
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /**
<> 144:ef7eb2e8f9f7 603 * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
<> 144:ef7eb2e8f9f7 604 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 605 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 606 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 607 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 608 * If the Size is multiple of 64 bytes, appending the input buffer is possible.
<> 144:ef7eb2e8f9f7 609 * If the Size is not multiple of 64 bytes, the padding is managed by hardware
<> 144:ef7eb2e8f9f7 610 * and appending the input buffer is no more possible.
<> 144:ef7eb2e8f9f7 611 * @retval HAL status
<> 144:ef7eb2e8f9f7 612 */
<> 144:ef7eb2e8f9f7 613 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 614 {
<> 144:ef7eb2e8f9f7 615 /* Process Locked */
<> 144:ef7eb2e8f9f7 616 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 619 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 622 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 623 {
<> 144:ef7eb2e8f9f7 624 /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 625 the message digest of a new message */
<> 144:ef7eb2e8f9f7 626 HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /* Set the phase */
<> 144:ef7eb2e8f9f7 630 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 633 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 636 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 639 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 642 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /* Return function status */
<> 144:ef7eb2e8f9f7 645 return HAL_OK;
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /**
<> 144:ef7eb2e8f9f7 649 * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 650 The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 651 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 652 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 653 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 654 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 655 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 656 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 657 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 658 * @retval HAL status
<> 144:ef7eb2e8f9f7 659 */
<> 144:ef7eb2e8f9f7 660 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* Process Locked */
<> 144:ef7eb2e8f9f7 665 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 668 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 671 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 672 {
<> 144:ef7eb2e8f9f7 673 /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 674 the message digest of a new message */
<> 144:ef7eb2e8f9f7 675 HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /* Set the phase */
<> 144:ef7eb2e8f9f7 679 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 682 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 685 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 688 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /* Get tick */
<> 144:ef7eb2e8f9f7 691 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 694 {
<> 144:ef7eb2e8f9f7 695 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 696 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 697 {
<> 144:ef7eb2e8f9f7 698 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 699 {
<> 144:ef7eb2e8f9f7 700 /* Change state */
<> 144:ef7eb2e8f9f7 701 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 704 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709 }
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 /* Read the message digest */
<> 144:ef7eb2e8f9f7 712 HASH_GetDigest(pOutBuffer, 20);
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 715 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 718 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Return function status */
<> 144:ef7eb2e8f9f7 721 return HAL_OK;
<> 144:ef7eb2e8f9f7 722 }
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /**
<> 144:ef7eb2e8f9f7 725 * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 726 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 727 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 728 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 729 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 730 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 731 * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
<> 144:ef7eb2e8f9f7 732 * @retval HAL status
<> 144:ef7eb2e8f9f7 733 */
<> 144:ef7eb2e8f9f7 734 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 735 {
<> 144:ef7eb2e8f9f7 736 /* Check the parameters */
<> 144:ef7eb2e8f9f7 737 assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Process Locked */
<> 144:ef7eb2e8f9f7 740 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 743 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 746 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 747 {
<> 144:ef7eb2e8f9f7 748 /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 749 the message digest of a new message */
<> 144:ef7eb2e8f9f7 750 HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 751 }
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /* Set the phase */
<> 144:ef7eb2e8f9f7 754 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 757 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 760 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 763 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 766 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /* Return function status */
<> 144:ef7eb2e8f9f7 769 return HAL_OK;
<> 144:ef7eb2e8f9f7 770 }
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /**
<> 144:ef7eb2e8f9f7 773 * @}
<> 144:ef7eb2e8f9f7 774 */
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode
<> 144:ef7eb2e8f9f7 777 * @brief processing functions using interrupt mode.
<> 144:ef7eb2e8f9f7 778 *
<> 144:ef7eb2e8f9f7 779 @verbatim
<> 144:ef7eb2e8f9f7 780 ===============================================================================
<> 144:ef7eb2e8f9f7 781 ##### HASH processing using interrupt mode functions #####
<> 144:ef7eb2e8f9f7 782 ===============================================================================
<> 144:ef7eb2e8f9f7 783 [..] This section provides functions allowing to calculate in interrupt mode
<> 144:ef7eb2e8f9f7 784 the hash value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 785 (+) MD5
<> 144:ef7eb2e8f9f7 786 (+) SHA1
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 @endverbatim
<> 144:ef7eb2e8f9f7 789 * @{
<> 144:ef7eb2e8f9f7 790 */
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /**
<> 144:ef7eb2e8f9f7 793 * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 794 * The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 795 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 796 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 797 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 798 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 799 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 800 * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
<> 144:ef7eb2e8f9f7 801 * @retval HAL status
<> 144:ef7eb2e8f9f7 802 */
<> 144:ef7eb2e8f9f7 803 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
<> 144:ef7eb2e8f9f7 804 {
<> 144:ef7eb2e8f9f7 805 uint32_t inputaddr;
<> 144:ef7eb2e8f9f7 806 uint32_t outputaddr;
<> 144:ef7eb2e8f9f7 807 uint32_t buffercounter;
<> 144:ef7eb2e8f9f7 808 uint32_t inputcounter;
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 /* Process Locked */
<> 144:ef7eb2e8f9f7 811 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 if(hhash->State == HAL_HASH_STATE_READY)
<> 144:ef7eb2e8f9f7 814 {
<> 144:ef7eb2e8f9f7 815 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 816 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 hhash->HashInCount = Size;
<> 144:ef7eb2e8f9f7 819 hhash->pHashInBuffPtr = pInBuffer;
<> 144:ef7eb2e8f9f7 820 hhash->pHashOutBuffPtr = pOutBuffer;
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 823 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 824 {
<> 144:ef7eb2e8f9f7 825 /* Select the SHA1 mode */
<> 144:ef7eb2e8f9f7 826 HASH->CR |= HASH_ALGOSELECTION_MD5;
<> 144:ef7eb2e8f9f7 827 /* Reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 828 the message digest of a new message */
<> 144:ef7eb2e8f9f7 829 HASH->CR |= HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 830 }
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /* Reset interrupt counter */
<> 144:ef7eb2e8f9f7 833 hhash->HashITCounter = 0;
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 /* Set the phase */
<> 144:ef7eb2e8f9f7 836 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 839 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /* Enable Interrupts */
<> 144:ef7eb2e8f9f7 842 HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Return function status */
<> 144:ef7eb2e8f9f7 845 return HAL_OK;
<> 144:ef7eb2e8f9f7 846 }
<> 144:ef7eb2e8f9f7 847 if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
<> 144:ef7eb2e8f9f7 848 {
<> 144:ef7eb2e8f9f7 849 outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
<> 144:ef7eb2e8f9f7 850 /* Read the Output block from the Output FIFO */
<> 144:ef7eb2e8f9f7 851 *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
<> 144:ef7eb2e8f9f7 852 outputaddr+=4;
<> 144:ef7eb2e8f9f7 853 *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
<> 144:ef7eb2e8f9f7 854 outputaddr+=4;
<> 144:ef7eb2e8f9f7 855 *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
<> 144:ef7eb2e8f9f7 856 outputaddr+=4;
<> 144:ef7eb2e8f9f7 857 *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 if(hhash->HashInCount == 0)
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 862 HASH->IMR = 0;
<> 144:ef7eb2e8f9f7 863 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 864 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 865 /* Call digest computation complete callback */
<> 144:ef7eb2e8f9f7 866 HAL_HASH_DgstCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 869 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /* Return function status */
<> 144:ef7eb2e8f9f7 872 return HAL_OK;
<> 144:ef7eb2e8f9f7 873 }
<> 144:ef7eb2e8f9f7 874 }
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
<> 144:ef7eb2e8f9f7 877 {
<> 144:ef7eb2e8f9f7 878 if(hhash->HashInCount >= 68)
<> 144:ef7eb2e8f9f7 879 {
<> 144:ef7eb2e8f9f7 880 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 881 /* Write the Input block in the Data IN register */
<> 144:ef7eb2e8f9f7 882 for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
<> 144:ef7eb2e8f9f7 883 {
<> 144:ef7eb2e8f9f7 884 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 885 inputaddr+=4;
<> 144:ef7eb2e8f9f7 886 }
<> 144:ef7eb2e8f9f7 887 if(hhash->HashITCounter == 0)
<> 144:ef7eb2e8f9f7 888 {
<> 144:ef7eb2e8f9f7 889 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 if(hhash->HashInCount >= 68)
<> 144:ef7eb2e8f9f7 892 {
<> 144:ef7eb2e8f9f7 893 /* Decrement buffer counter */
<> 144:ef7eb2e8f9f7 894 hhash->HashInCount -= 68;
<> 144:ef7eb2e8f9f7 895 hhash->pHashInBuffPtr+= 68;
<> 144:ef7eb2e8f9f7 896 }
<> 144:ef7eb2e8f9f7 897 else
<> 144:ef7eb2e8f9f7 898 {
<> 144:ef7eb2e8f9f7 899 hhash->HashInCount = 0;
<> 144:ef7eb2e8f9f7 900 hhash->pHashInBuffPtr+= hhash->HashInCount;
<> 144:ef7eb2e8f9f7 901 }
<> 144:ef7eb2e8f9f7 902 /* Set Interrupt counter */
<> 144:ef7eb2e8f9f7 903 hhash->HashITCounter = 1;
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905 else
<> 144:ef7eb2e8f9f7 906 {
<> 144:ef7eb2e8f9f7 907 /* Decrement buffer counter */
<> 144:ef7eb2e8f9f7 908 hhash->HashInCount -= 64;
<> 144:ef7eb2e8f9f7 909 hhash->pHashInBuffPtr+= 64;
<> 144:ef7eb2e8f9f7 910 }
<> 144:ef7eb2e8f9f7 911 }
<> 144:ef7eb2e8f9f7 912 else
<> 144:ef7eb2e8f9f7 913 {
<> 144:ef7eb2e8f9f7 914 /* Get the buffer address */
<> 144:ef7eb2e8f9f7 915 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 916 /* Get the buffer counter */
<> 144:ef7eb2e8f9f7 917 inputcounter = hhash->HashInCount;
<> 144:ef7eb2e8f9f7 918 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 919 HASH->IMR &= ~(HASH_IT_DINI);
<> 144:ef7eb2e8f9f7 920 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 921 __HAL_HASH_SET_NBVALIDBITS(inputcounter);
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 if((inputcounter > 4) && (inputcounter%4))
<> 144:ef7eb2e8f9f7 924 {
<> 144:ef7eb2e8f9f7 925 inputcounter = (inputcounter+4-inputcounter%4);
<> 144:ef7eb2e8f9f7 926 }
<> 144:ef7eb2e8f9f7 927 else if ((inputcounter < 4) && (inputcounter != 0))
<> 144:ef7eb2e8f9f7 928 {
<> 144:ef7eb2e8f9f7 929 inputcounter = 4;
<> 144:ef7eb2e8f9f7 930 }
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /* Write the Input block in the Data IN register */
<> 144:ef7eb2e8f9f7 933 for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
<> 144:ef7eb2e8f9f7 934 {
<> 144:ef7eb2e8f9f7 935 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 936 inputaddr+=4;
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 939 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 940 /* Reset buffer counter */
<> 144:ef7eb2e8f9f7 941 hhash->HashInCount = 0;
<> 144:ef7eb2e8f9f7 942 /* Call Input data transfer complete callback */
<> 144:ef7eb2e8f9f7 943 HAL_HASH_InCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 944 }
<> 144:ef7eb2e8f9f7 945 }
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 948 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /* Return function status */
<> 144:ef7eb2e8f9f7 951 return HAL_OK;
<> 144:ef7eb2e8f9f7 952 }
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /**
<> 144:ef7eb2e8f9f7 955 * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 956 * The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 957 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 958 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 959 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 960 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 961 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 962 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 963 * @retval HAL status
<> 144:ef7eb2e8f9f7 964 */
<> 144:ef7eb2e8f9f7 965 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
<> 144:ef7eb2e8f9f7 966 {
<> 144:ef7eb2e8f9f7 967 uint32_t inputaddr;
<> 144:ef7eb2e8f9f7 968 uint32_t outputaddr;
<> 144:ef7eb2e8f9f7 969 uint32_t buffercounter;
<> 144:ef7eb2e8f9f7 970 uint32_t inputcounter;
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 /* Process Locked */
<> 144:ef7eb2e8f9f7 973 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 if(hhash->State == HAL_HASH_STATE_READY)
<> 144:ef7eb2e8f9f7 976 {
<> 144:ef7eb2e8f9f7 977 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 978 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 hhash->HashInCount = Size;
<> 144:ef7eb2e8f9f7 981 hhash->pHashInBuffPtr = pInBuffer;
<> 144:ef7eb2e8f9f7 982 hhash->pHashOutBuffPtr = pOutBuffer;
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 985 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 986 {
<> 144:ef7eb2e8f9f7 987 /* Select the SHA1 mode */
<> 144:ef7eb2e8f9f7 988 HASH->CR |= HASH_ALGOSELECTION_SHA1;
<> 144:ef7eb2e8f9f7 989 /* Reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 990 the message digest of a new message */
<> 144:ef7eb2e8f9f7 991 HASH->CR |= HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 992 }
<> 144:ef7eb2e8f9f7 993
<> 144:ef7eb2e8f9f7 994 /* Reset interrupt counter */
<> 144:ef7eb2e8f9f7 995 hhash->HashITCounter = 0;
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 /* Set the phase */
<> 144:ef7eb2e8f9f7 998 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1001 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /* Enable Interrupts */
<> 144:ef7eb2e8f9f7 1004 HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 /* Return function status */
<> 144:ef7eb2e8f9f7 1007 return HAL_OK;
<> 144:ef7eb2e8f9f7 1008 }
<> 144:ef7eb2e8f9f7 1009 if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
<> 144:ef7eb2e8f9f7 1010 {
<> 144:ef7eb2e8f9f7 1011 outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
<> 144:ef7eb2e8f9f7 1012 /* Read the Output block from the Output FIFO */
<> 144:ef7eb2e8f9f7 1013 *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
<> 144:ef7eb2e8f9f7 1014 outputaddr+=4;
<> 144:ef7eb2e8f9f7 1015 *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
<> 144:ef7eb2e8f9f7 1016 outputaddr+=4;
<> 144:ef7eb2e8f9f7 1017 *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
<> 144:ef7eb2e8f9f7 1018 outputaddr+=4;
<> 144:ef7eb2e8f9f7 1019 *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
<> 144:ef7eb2e8f9f7 1020 outputaddr+=4;
<> 144:ef7eb2e8f9f7 1021 *(uint32_t*)(outputaddr) = __REV(HASH->HR[4]);
<> 144:ef7eb2e8f9f7 1022 if(hhash->HashInCount == 0)
<> 144:ef7eb2e8f9f7 1023 {
<> 144:ef7eb2e8f9f7 1024 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 1025 HASH->IMR = 0;
<> 144:ef7eb2e8f9f7 1026 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1027 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1028 /* Call digest computation complete callback */
<> 144:ef7eb2e8f9f7 1029 HAL_HASH_DgstCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1032 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /* Return function status */
<> 144:ef7eb2e8f9f7 1035 return HAL_OK;
<> 144:ef7eb2e8f9f7 1036 }
<> 144:ef7eb2e8f9f7 1037 }
<> 144:ef7eb2e8f9f7 1038 if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
<> 144:ef7eb2e8f9f7 1039 {
<> 144:ef7eb2e8f9f7 1040 if(hhash->HashInCount >= 68)
<> 144:ef7eb2e8f9f7 1041 {
<> 144:ef7eb2e8f9f7 1042 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 1043 /* Write the Input block in the Data IN register */
<> 144:ef7eb2e8f9f7 1044 for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
<> 144:ef7eb2e8f9f7 1045 {
<> 144:ef7eb2e8f9f7 1046 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 1047 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1048 }
<> 144:ef7eb2e8f9f7 1049 if(hhash->HashITCounter == 0)
<> 144:ef7eb2e8f9f7 1050 {
<> 144:ef7eb2e8f9f7 1051 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 if(hhash->HashInCount >= 68)
<> 144:ef7eb2e8f9f7 1054 {
<> 144:ef7eb2e8f9f7 1055 /* Decrement buffer counter */
<> 144:ef7eb2e8f9f7 1056 hhash->HashInCount -= 68;
<> 144:ef7eb2e8f9f7 1057 hhash->pHashInBuffPtr+= 68;
<> 144:ef7eb2e8f9f7 1058 }
<> 144:ef7eb2e8f9f7 1059 else
<> 144:ef7eb2e8f9f7 1060 {
<> 144:ef7eb2e8f9f7 1061 hhash->HashInCount = 0;
<> 144:ef7eb2e8f9f7 1062 hhash->pHashInBuffPtr+= hhash->HashInCount;
<> 144:ef7eb2e8f9f7 1063 }
<> 144:ef7eb2e8f9f7 1064 /* Set Interrupt counter */
<> 144:ef7eb2e8f9f7 1065 hhash->HashITCounter = 1;
<> 144:ef7eb2e8f9f7 1066 }
<> 144:ef7eb2e8f9f7 1067 else
<> 144:ef7eb2e8f9f7 1068 {
<> 144:ef7eb2e8f9f7 1069 /* Decrement buffer counter */
<> 144:ef7eb2e8f9f7 1070 hhash->HashInCount -= 64;
<> 144:ef7eb2e8f9f7 1071 hhash->pHashInBuffPtr+= 64;
<> 144:ef7eb2e8f9f7 1072 }
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074 else
<> 144:ef7eb2e8f9f7 1075 {
<> 144:ef7eb2e8f9f7 1076 /* Get the buffer address */
<> 144:ef7eb2e8f9f7 1077 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 1078 /* Get the buffer counter */
<> 144:ef7eb2e8f9f7 1079 inputcounter = hhash->HashInCount;
<> 144:ef7eb2e8f9f7 1080 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 1081 HASH->IMR &= ~(HASH_IT_DINI);
<> 144:ef7eb2e8f9f7 1082 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1083 __HAL_HASH_SET_NBVALIDBITS(inputcounter);
<> 144:ef7eb2e8f9f7 1084
<> 144:ef7eb2e8f9f7 1085 if((inputcounter > 4) && (inputcounter%4))
<> 144:ef7eb2e8f9f7 1086 {
<> 144:ef7eb2e8f9f7 1087 inputcounter = (inputcounter+4-inputcounter%4);
<> 144:ef7eb2e8f9f7 1088 }
<> 144:ef7eb2e8f9f7 1089 else if ((inputcounter < 4) && (inputcounter != 0))
<> 144:ef7eb2e8f9f7 1090 {
<> 144:ef7eb2e8f9f7 1091 inputcounter = 4;
<> 144:ef7eb2e8f9f7 1092 }
<> 144:ef7eb2e8f9f7 1093 /* Write the Input block in the Data IN register */
<> 144:ef7eb2e8f9f7 1094 for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
<> 144:ef7eb2e8f9f7 1095 {
<> 144:ef7eb2e8f9f7 1096 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 1097 inputaddr+=4;
<> 144:ef7eb2e8f9f7 1098 }
<> 144:ef7eb2e8f9f7 1099 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1100 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1101 /* Reset buffer counter */
<> 144:ef7eb2e8f9f7 1102 hhash->HashInCount = 0;
<> 144:ef7eb2e8f9f7 1103 /* Call Input data transfer complete callback */
<> 144:ef7eb2e8f9f7 1104 HAL_HASH_InCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 1105 }
<> 144:ef7eb2e8f9f7 1106 }
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1109 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 /* Return function status */
<> 144:ef7eb2e8f9f7 1112 return HAL_OK;
<> 144:ef7eb2e8f9f7 1113 }
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /**
<> 144:ef7eb2e8f9f7 1116 * @brief This function handles HASH interrupt request.
<> 144:ef7eb2e8f9f7 1117 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1118 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1119 * @retval None
<> 144:ef7eb2e8f9f7 1120 */
<> 144:ef7eb2e8f9f7 1121 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 1122 {
<> 144:ef7eb2e8f9f7 1123 switch(HASH->CR & HASH_CR_ALGO)
<> 144:ef7eb2e8f9f7 1124 {
<> 144:ef7eb2e8f9f7 1125 case HASH_ALGOSELECTION_MD5:
<> 144:ef7eb2e8f9f7 1126 HAL_HASH_MD5_Start_IT(hhash, NULL, 0, NULL);
<> 144:ef7eb2e8f9f7 1127 break;
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 case HASH_ALGOSELECTION_SHA1:
<> 144:ef7eb2e8f9f7 1130 HAL_HASH_SHA1_Start_IT(hhash, NULL, 0, NULL);
<> 144:ef7eb2e8f9f7 1131 break;
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 default:
<> 144:ef7eb2e8f9f7 1134 break;
<> 144:ef7eb2e8f9f7 1135 }
<> 144:ef7eb2e8f9f7 1136 }
<> 144:ef7eb2e8f9f7 1137
<> 144:ef7eb2e8f9f7 1138 /**
<> 144:ef7eb2e8f9f7 1139 * @}
<> 144:ef7eb2e8f9f7 1140 */
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 /** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode
<> 144:ef7eb2e8f9f7 1143 * @brief processing functions using DMA mode.
<> 144:ef7eb2e8f9f7 1144 *
<> 144:ef7eb2e8f9f7 1145 @verbatim
<> 144:ef7eb2e8f9f7 1146 ===============================================================================
<> 144:ef7eb2e8f9f7 1147 ##### HASH processing using DMA mode functions #####
<> 144:ef7eb2e8f9f7 1148 ===============================================================================
<> 144:ef7eb2e8f9f7 1149 [..] This section provides functions allowing to calculate in DMA mode
<> 144:ef7eb2e8f9f7 1150 the hash value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 1151 (+) MD5
<> 144:ef7eb2e8f9f7 1152 (+) SHA1
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154 @endverbatim
<> 144:ef7eb2e8f9f7 1155 * @{
<> 144:ef7eb2e8f9f7 1156 */
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /**
<> 144:ef7eb2e8f9f7 1159 * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to
<> 144:ef7eb2e8f9f7 1160 control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
<> 144:ef7eb2e8f9f7 1161 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1162 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1163 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1164 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1165 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1166 * @retval HAL status
<> 144:ef7eb2e8f9f7 1167 */
<> 144:ef7eb2e8f9f7 1168 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 1169 {
<> 144:ef7eb2e8f9f7 1170 uint32_t inputaddr = (uint32_t)pInBuffer;
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172 /* Process Locked */
<> 144:ef7eb2e8f9f7 1173 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1174
<> 144:ef7eb2e8f9f7 1175 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1176 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1179 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1180 {
<> 144:ef7eb2e8f9f7 1181 /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 1182 the message digest of a new message */
<> 144:ef7eb2e8f9f7 1183 HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 1184 }
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1187 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /* Set the phase */
<> 144:ef7eb2e8f9f7 1190 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1191
<> 144:ef7eb2e8f9f7 1192 /* Set the HASH DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1193 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 1194 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1195 hhash->hdmain->XferErrorCallback = HASH_DMAError;
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 /* Enable the DMA In DMA Stream */
<> 144:ef7eb2e8f9f7 1198 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 1201 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1204 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /* Return function status */
<> 144:ef7eb2e8f9f7 1207 return HAL_OK;
<> 144:ef7eb2e8f9f7 1208 }
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210 /**
<> 144:ef7eb2e8f9f7 1211 * @brief Returns the computed digest in MD5 mode
<> 144:ef7eb2e8f9f7 1212 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1213 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1214 * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
<> 144:ef7eb2e8f9f7 1215 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 1216 * @retval HAL status
<> 144:ef7eb2e8f9f7 1217 */
<> 144:ef7eb2e8f9f7 1218 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1219 {
<> 144:ef7eb2e8f9f7 1220 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 /* Process Locked */
<> 144:ef7eb2e8f9f7 1223 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 1226 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 /* Get tick */
<> 144:ef7eb2e8f9f7 1229 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1230
<> 144:ef7eb2e8f9f7 1231 while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
<> 144:ef7eb2e8f9f7 1232 {
<> 144:ef7eb2e8f9f7 1233 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1234 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1235 {
<> 144:ef7eb2e8f9f7 1236 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1237 {
<> 144:ef7eb2e8f9f7 1238 /* Change state */
<> 144:ef7eb2e8f9f7 1239 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1242 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1243
<> 144:ef7eb2e8f9f7 1244 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1245 }
<> 144:ef7eb2e8f9f7 1246 }
<> 144:ef7eb2e8f9f7 1247 }
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 /* Read the message digest */
<> 144:ef7eb2e8f9f7 1250 HASH_GetDigest(pOutBuffer, 16);
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 1253 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1256 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1257
<> 144:ef7eb2e8f9f7 1258 /* Return function status */
<> 144:ef7eb2e8f9f7 1259 return HAL_OK;
<> 144:ef7eb2e8f9f7 1260 }
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262 /**
<> 144:ef7eb2e8f9f7 1263 * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to
<> 144:ef7eb2e8f9f7 1264 control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
<> 144:ef7eb2e8f9f7 1265 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1266 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1267 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1268 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1269 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1270 * @retval HAL status
<> 144:ef7eb2e8f9f7 1271 */
<> 144:ef7eb2e8f9f7 1272 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 1273 {
<> 144:ef7eb2e8f9f7 1274 uint32_t inputaddr = (uint32_t)pInBuffer;
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 /* Process Locked */
<> 144:ef7eb2e8f9f7 1277 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1280 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1281
<> 144:ef7eb2e8f9f7 1282 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1283 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1284 {
<> 144:ef7eb2e8f9f7 1285 /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 1286 the message digest of a new message */
<> 144:ef7eb2e8f9f7 1287 HASH->CR |= HASH_ALGOSELECTION_SHA1;
<> 144:ef7eb2e8f9f7 1288 HASH->CR |= HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 1289 }
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1292 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 1293
<> 144:ef7eb2e8f9f7 1294 /* Set the phase */
<> 144:ef7eb2e8f9f7 1295 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1296
<> 144:ef7eb2e8f9f7 1297 /* Set the HASH DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1298 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 1299 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1300 hhash->hdmain->XferErrorCallback = HASH_DMAError;
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 /* Enable the DMA In DMA Stream */
<> 144:ef7eb2e8f9f7 1303 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 1306 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 1307
<> 144:ef7eb2e8f9f7 1308 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1309 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1310
<> 144:ef7eb2e8f9f7 1311 /* Return function status */
<> 144:ef7eb2e8f9f7 1312 return HAL_OK;
<> 144:ef7eb2e8f9f7 1313 }
<> 144:ef7eb2e8f9f7 1314
<> 144:ef7eb2e8f9f7 1315 /**
<> 144:ef7eb2e8f9f7 1316 * @brief Returns the computed digest in SHA1 mode.
<> 144:ef7eb2e8f9f7 1317 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1318 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1319 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 1320 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 1321 * @retval HAL status
<> 144:ef7eb2e8f9f7 1322 */
<> 144:ef7eb2e8f9f7 1323 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1324 {
<> 144:ef7eb2e8f9f7 1325 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 /* Process Locked */
<> 144:ef7eb2e8f9f7 1328 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 1331 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1332
<> 144:ef7eb2e8f9f7 1333 /* Get tick */
<> 144:ef7eb2e8f9f7 1334 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1335 while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
<> 144:ef7eb2e8f9f7 1336 {
<> 144:ef7eb2e8f9f7 1337 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1338 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1339 {
<> 144:ef7eb2e8f9f7 1340 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1341 {
<> 144:ef7eb2e8f9f7 1342 /* Change state */
<> 144:ef7eb2e8f9f7 1343 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1344
<> 144:ef7eb2e8f9f7 1345 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1346 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1349 }
<> 144:ef7eb2e8f9f7 1350 }
<> 144:ef7eb2e8f9f7 1351 }
<> 144:ef7eb2e8f9f7 1352
<> 144:ef7eb2e8f9f7 1353 /* Read the message digest */
<> 144:ef7eb2e8f9f7 1354 HASH_GetDigest(pOutBuffer, 20);
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 1357 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 /* Process UnLock */
<> 144:ef7eb2e8f9f7 1360 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1361
<> 144:ef7eb2e8f9f7 1362 /* Return function status */
<> 144:ef7eb2e8f9f7 1363 return HAL_OK;
<> 144:ef7eb2e8f9f7 1364 }
<> 144:ef7eb2e8f9f7 1365
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 /**
<> 144:ef7eb2e8f9f7 1368 * @}
<> 144:ef7eb2e8f9f7 1369 */
<> 144:ef7eb2e8f9f7 1370
<> 144:ef7eb2e8f9f7 1371 /** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode
<> 144:ef7eb2e8f9f7 1372 * @brief HMAC processing functions using polling mode .
<> 144:ef7eb2e8f9f7 1373 *
<> 144:ef7eb2e8f9f7 1374 @verbatim
<> 144:ef7eb2e8f9f7 1375 ===============================================================================
<> 144:ef7eb2e8f9f7 1376 ##### HMAC processing using polling mode functions #####
<> 144:ef7eb2e8f9f7 1377 ===============================================================================
<> 144:ef7eb2e8f9f7 1378 [..] This section provides functions allowing to calculate in polling mode
<> 144:ef7eb2e8f9f7 1379 the HMAC value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 1380 (+) MD5
<> 144:ef7eb2e8f9f7 1381 (+) SHA1
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 @endverbatim
<> 144:ef7eb2e8f9f7 1384 * @{
<> 144:ef7eb2e8f9f7 1385 */
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /**
<> 144:ef7eb2e8f9f7 1388 * @brief Initializes the HASH peripheral in HMAC MD5 mode
<> 144:ef7eb2e8f9f7 1389 * then processes pInBuffer. The digest is available in pOutBuffer
<> 144:ef7eb2e8f9f7 1390 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1391 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1392 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1393 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1394 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1395 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 1396 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 1397 * @retval HAL status
<> 144:ef7eb2e8f9f7 1398 */
<> 144:ef7eb2e8f9f7 1399 HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1400 {
<> 144:ef7eb2e8f9f7 1401 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 /* Process Locked */
<> 144:ef7eb2e8f9f7 1404 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1407 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1408
<> 144:ef7eb2e8f9f7 1409 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1410 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1411 {
<> 144:ef7eb2e8f9f7 1412 /* Check if key size is greater than 64 bytes */
<> 144:ef7eb2e8f9f7 1413 if(hhash->Init.KeySize > 64)
<> 144:ef7eb2e8f9f7 1414 {
<> 144:ef7eb2e8f9f7 1415 /* Select the HMAC MD5 mode */
<> 144:ef7eb2e8f9f7 1416 HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1417 }
<> 144:ef7eb2e8f9f7 1418 else
<> 144:ef7eb2e8f9f7 1419 {
<> 144:ef7eb2e8f9f7 1420 /* Select the HMAC MD5 mode */
<> 144:ef7eb2e8f9f7 1421 HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1422 }
<> 144:ef7eb2e8f9f7 1423 }
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 /* Set the phase */
<> 144:ef7eb2e8f9f7 1426 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1427
<> 144:ef7eb2e8f9f7 1428 /************************** STEP 1 ******************************************/
<> 144:ef7eb2e8f9f7 1429 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1430 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1433 HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1434
<> 144:ef7eb2e8f9f7 1435 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1436 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1437
<> 144:ef7eb2e8f9f7 1438 /* Get tick */
<> 144:ef7eb2e8f9f7 1439 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1442 {
<> 144:ef7eb2e8f9f7 1443 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1444 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1445 {
<> 144:ef7eb2e8f9f7 1446 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1447 {
<> 144:ef7eb2e8f9f7 1448 /* Change state */
<> 144:ef7eb2e8f9f7 1449 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1450
<> 144:ef7eb2e8f9f7 1451 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1452 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1453
<> 144:ef7eb2e8f9f7 1454 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1455 }
<> 144:ef7eb2e8f9f7 1456 }
<> 144:ef7eb2e8f9f7 1457 }
<> 144:ef7eb2e8f9f7 1458 /************************** STEP 2 ******************************************/
<> 144:ef7eb2e8f9f7 1459 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1460 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 1461
<> 144:ef7eb2e8f9f7 1462 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1463 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1466 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1467
<> 144:ef7eb2e8f9f7 1468 /* Get tick */
<> 144:ef7eb2e8f9f7 1469 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1470
<> 144:ef7eb2e8f9f7 1471 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1472 {
<> 144:ef7eb2e8f9f7 1473 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1474 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1475 {
<> 144:ef7eb2e8f9f7 1476 if((HAL_GetTick() - tickstart ) > Timeout)
<> 144:ef7eb2e8f9f7 1477 {
<> 144:ef7eb2e8f9f7 1478 /* Change state */
<> 144:ef7eb2e8f9f7 1479 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1480
<> 144:ef7eb2e8f9f7 1481 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1482 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1483
<> 144:ef7eb2e8f9f7 1484 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1485 }
<> 144:ef7eb2e8f9f7 1486 }
<> 144:ef7eb2e8f9f7 1487 }
<> 144:ef7eb2e8f9f7 1488 /************************** STEP 3 ******************************************/
<> 144:ef7eb2e8f9f7 1489 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1490 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1491
<> 144:ef7eb2e8f9f7 1492 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1493 HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1496 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1497
<> 144:ef7eb2e8f9f7 1498 /* Get tick */
<> 144:ef7eb2e8f9f7 1499 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1502 {
<> 144:ef7eb2e8f9f7 1503 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1504 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1505 {
<> 144:ef7eb2e8f9f7 1506 if((HAL_GetTick() - tickstart ) > Timeout)
<> 144:ef7eb2e8f9f7 1507 {
<> 144:ef7eb2e8f9f7 1508 /* Change state */
<> 144:ef7eb2e8f9f7 1509 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1510
<> 144:ef7eb2e8f9f7 1511 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1512 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1513
<> 144:ef7eb2e8f9f7 1514 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1515 }
<> 144:ef7eb2e8f9f7 1516 }
<> 144:ef7eb2e8f9f7 1517 }
<> 144:ef7eb2e8f9f7 1518
<> 144:ef7eb2e8f9f7 1519 /* Read the message digest */
<> 144:ef7eb2e8f9f7 1520 HASH_GetDigest(pOutBuffer, 16);
<> 144:ef7eb2e8f9f7 1521
<> 144:ef7eb2e8f9f7 1522 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1523 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1524
<> 144:ef7eb2e8f9f7 1525 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1526 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1527
<> 144:ef7eb2e8f9f7 1528 /* Return function status */
<> 144:ef7eb2e8f9f7 1529 return HAL_OK;
<> 144:ef7eb2e8f9f7 1530 }
<> 144:ef7eb2e8f9f7 1531
<> 144:ef7eb2e8f9f7 1532 /**
<> 144:ef7eb2e8f9f7 1533 * @brief Initializes the HASH peripheral in HMAC SHA1 mode
<> 144:ef7eb2e8f9f7 1534 * then processes pInBuffer. The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 1535 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1536 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1537 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1538 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1539 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1540 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 1541 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 1542 * @retval HAL status
<> 144:ef7eb2e8f9f7 1543 */
<> 144:ef7eb2e8f9f7 1544 HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1545 {
<> 144:ef7eb2e8f9f7 1546 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1547
<> 144:ef7eb2e8f9f7 1548 /* Process Locked */
<> 144:ef7eb2e8f9f7 1549 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1550
<> 144:ef7eb2e8f9f7 1551 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1552 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1553
<> 144:ef7eb2e8f9f7 1554 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1555 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1556 {
<> 144:ef7eb2e8f9f7 1557 /* Check if key size is greater than 64 bytes */
<> 144:ef7eb2e8f9f7 1558 if(hhash->Init.KeySize > 64)
<> 144:ef7eb2e8f9f7 1559 {
<> 144:ef7eb2e8f9f7 1560 /* Select the HMAC SHA1 mode */
<> 144:ef7eb2e8f9f7 1561 HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1562 }
<> 144:ef7eb2e8f9f7 1563 else
<> 144:ef7eb2e8f9f7 1564 {
<> 144:ef7eb2e8f9f7 1565 /* Select the HMAC SHA1 mode */
<> 144:ef7eb2e8f9f7 1566 HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1567 }
<> 144:ef7eb2e8f9f7 1568 }
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 /* Set the phase */
<> 144:ef7eb2e8f9f7 1571 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1572
<> 144:ef7eb2e8f9f7 1573 /************************** STEP 1 ******************************************/
<> 144:ef7eb2e8f9f7 1574 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1575 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1576
<> 144:ef7eb2e8f9f7 1577 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1578 HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1581 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1582
<> 144:ef7eb2e8f9f7 1583 /* Get tick */
<> 144:ef7eb2e8f9f7 1584 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1585
<> 144:ef7eb2e8f9f7 1586 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1587 {
<> 144:ef7eb2e8f9f7 1588 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1589 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1590 {
<> 144:ef7eb2e8f9f7 1591 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1592 {
<> 144:ef7eb2e8f9f7 1593 /* Change state */
<> 144:ef7eb2e8f9f7 1594 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1595
<> 144:ef7eb2e8f9f7 1596 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1597 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1598
<> 144:ef7eb2e8f9f7 1599 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1600 }
<> 144:ef7eb2e8f9f7 1601 }
<> 144:ef7eb2e8f9f7 1602 }
<> 144:ef7eb2e8f9f7 1603 /************************** STEP 2 ******************************************/
<> 144:ef7eb2e8f9f7 1604 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1605 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1608 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 1609
<> 144:ef7eb2e8f9f7 1610 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1611 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1612
<> 144:ef7eb2e8f9f7 1613 /* Get tick */
<> 144:ef7eb2e8f9f7 1614 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1615
<> 144:ef7eb2e8f9f7 1616 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1617 {
<> 144:ef7eb2e8f9f7 1618 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1619 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1620 {
<> 144:ef7eb2e8f9f7 1621 if((HAL_GetTick() - tickstart ) > Timeout)
<> 144:ef7eb2e8f9f7 1622 {
<> 144:ef7eb2e8f9f7 1623 /* Change state */
<> 144:ef7eb2e8f9f7 1624 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1625
<> 144:ef7eb2e8f9f7 1626 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1627 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1628
<> 144:ef7eb2e8f9f7 1629 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1630 }
<> 144:ef7eb2e8f9f7 1631 }
<> 144:ef7eb2e8f9f7 1632 }
<> 144:ef7eb2e8f9f7 1633 /************************** STEP 3 ******************************************/
<> 144:ef7eb2e8f9f7 1634 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1635 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1636
<> 144:ef7eb2e8f9f7 1637 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1638 HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1639
<> 144:ef7eb2e8f9f7 1640 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1641 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1642
<> 144:ef7eb2e8f9f7 1643 /* Get tick */
<> 144:ef7eb2e8f9f7 1644 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1645
<> 144:ef7eb2e8f9f7 1646 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1647 {
<> 144:ef7eb2e8f9f7 1648 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1649 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1650 {
<> 144:ef7eb2e8f9f7 1651 if((HAL_GetTick() - tickstart ) > Timeout)
<> 144:ef7eb2e8f9f7 1652 {
<> 144:ef7eb2e8f9f7 1653 /* Change state */
<> 144:ef7eb2e8f9f7 1654 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1655
<> 144:ef7eb2e8f9f7 1656 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1657 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1658
<> 144:ef7eb2e8f9f7 1659 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1660 }
<> 144:ef7eb2e8f9f7 1661 }
<> 144:ef7eb2e8f9f7 1662 }
<> 144:ef7eb2e8f9f7 1663 /* Read the message digest */
<> 144:ef7eb2e8f9f7 1664 HASH_GetDigest(pOutBuffer, 20);
<> 144:ef7eb2e8f9f7 1665
<> 144:ef7eb2e8f9f7 1666 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1667 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1668
<> 144:ef7eb2e8f9f7 1669 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1670 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1671
<> 144:ef7eb2e8f9f7 1672 /* Return function status */
<> 144:ef7eb2e8f9f7 1673 return HAL_OK;
<> 144:ef7eb2e8f9f7 1674 }
<> 144:ef7eb2e8f9f7 1675
<> 144:ef7eb2e8f9f7 1676 /**
<> 144:ef7eb2e8f9f7 1677 * @}
<> 144:ef7eb2e8f9f7 1678 */
<> 144:ef7eb2e8f9f7 1679
<> 144:ef7eb2e8f9f7 1680 /** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode
<> 144:ef7eb2e8f9f7 1681 * @brief HMAC processing functions using DMA mode .
<> 144:ef7eb2e8f9f7 1682 *
<> 144:ef7eb2e8f9f7 1683 @verbatim
<> 144:ef7eb2e8f9f7 1684 ===============================================================================
<> 144:ef7eb2e8f9f7 1685 ##### HMAC processing using DMA mode functions #####
<> 144:ef7eb2e8f9f7 1686 ===============================================================================
<> 144:ef7eb2e8f9f7 1687 [..] This section provides functions allowing to calculate in DMA mode
<> 144:ef7eb2e8f9f7 1688 the HMAC value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 1689 (+) MD5
<> 144:ef7eb2e8f9f7 1690 (+) SHA1
<> 144:ef7eb2e8f9f7 1691
<> 144:ef7eb2e8f9f7 1692 @endverbatim
<> 144:ef7eb2e8f9f7 1693 * @{
<> 144:ef7eb2e8f9f7 1694 */
<> 144:ef7eb2e8f9f7 1695
<> 144:ef7eb2e8f9f7 1696 /**
<> 144:ef7eb2e8f9f7 1697 * @brief Initializes the HASH peripheral in HMAC MD5 mode
<> 144:ef7eb2e8f9f7 1698 * then enables DMA to control data transfer.
<> 144:ef7eb2e8f9f7 1699 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1700 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1701 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1702 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1703 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1704 * @retval HAL status
<> 144:ef7eb2e8f9f7 1705 */
<> 144:ef7eb2e8f9f7 1706 HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 1707 {
<> 144:ef7eb2e8f9f7 1708 uint32_t inputaddr = 0;
<> 144:ef7eb2e8f9f7 1709
<> 144:ef7eb2e8f9f7 1710 /* Process Locked */
<> 144:ef7eb2e8f9f7 1711 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1712
<> 144:ef7eb2e8f9f7 1713 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1714 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1715
<> 144:ef7eb2e8f9f7 1716 /* Save buffer pointer and size in handle */
<> 144:ef7eb2e8f9f7 1717 hhash->pHashInBuffPtr = pInBuffer;
<> 144:ef7eb2e8f9f7 1718 hhash->HashBuffSize = Size;
<> 144:ef7eb2e8f9f7 1719 hhash->HashInCount = 0;
<> 144:ef7eb2e8f9f7 1720
<> 144:ef7eb2e8f9f7 1721 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1722 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1723 {
<> 144:ef7eb2e8f9f7 1724 /* Check if key size is greater than 64 bytes */
<> 144:ef7eb2e8f9f7 1725 if(hhash->Init.KeySize > 64)
<> 144:ef7eb2e8f9f7 1726 {
<> 144:ef7eb2e8f9f7 1727 /* Select the HMAC MD5 mode */
<> 144:ef7eb2e8f9f7 1728 HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1729 }
<> 144:ef7eb2e8f9f7 1730 else
<> 144:ef7eb2e8f9f7 1731 {
<> 144:ef7eb2e8f9f7 1732 /* Select the HMAC MD5 mode */
<> 144:ef7eb2e8f9f7 1733 HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1734 }
<> 144:ef7eb2e8f9f7 1735 }
<> 144:ef7eb2e8f9f7 1736
<> 144:ef7eb2e8f9f7 1737 /* Set the phase */
<> 144:ef7eb2e8f9f7 1738 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1739
<> 144:ef7eb2e8f9f7 1740 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1741 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1742
<> 144:ef7eb2e8f9f7 1743 /* Get the key address */
<> 144:ef7eb2e8f9f7 1744 inputaddr = (uint32_t)(hhash->Init.pKey);
<> 144:ef7eb2e8f9f7 1745
<> 144:ef7eb2e8f9f7 1746 /* Set the HASH DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1747 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 1748 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1749 hhash->hdmain->XferErrorCallback = HASH_DMAError;
<> 144:ef7eb2e8f9f7 1750
<> 144:ef7eb2e8f9f7 1751 /* Enable the DMA In DMA Stream */
<> 144:ef7eb2e8f9f7 1752 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
<> 144:ef7eb2e8f9f7 1753 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 1754 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 1755
<> 144:ef7eb2e8f9f7 1756 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1757 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1758
<> 144:ef7eb2e8f9f7 1759 /* Return function status */
<> 144:ef7eb2e8f9f7 1760 return HAL_OK;
<> 144:ef7eb2e8f9f7 1761 }
<> 144:ef7eb2e8f9f7 1762
<> 144:ef7eb2e8f9f7 1763 /**
<> 144:ef7eb2e8f9f7 1764 * @brief Initializes the HASH peripheral in HMAC SHA1 mode
<> 144:ef7eb2e8f9f7 1765 * then enables DMA to control data transfer.
<> 144:ef7eb2e8f9f7 1766 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1767 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1768 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1769 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1770 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1771 * @retval HAL status
<> 144:ef7eb2e8f9f7 1772 */
<> 144:ef7eb2e8f9f7 1773 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 1774 {
<> 144:ef7eb2e8f9f7 1775 uint32_t inputaddr = 0;
<> 144:ef7eb2e8f9f7 1776
<> 144:ef7eb2e8f9f7 1777 /* Process Locked */
<> 144:ef7eb2e8f9f7 1778 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1779
<> 144:ef7eb2e8f9f7 1780 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1781 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1782
<> 144:ef7eb2e8f9f7 1783 /* Save buffer pointer and size in handle */
<> 144:ef7eb2e8f9f7 1784 hhash->pHashInBuffPtr = pInBuffer;
<> 144:ef7eb2e8f9f7 1785 hhash->HashBuffSize = Size;
<> 144:ef7eb2e8f9f7 1786 hhash->HashInCount = 0;
<> 144:ef7eb2e8f9f7 1787
<> 144:ef7eb2e8f9f7 1788 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1789 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1790 {
<> 144:ef7eb2e8f9f7 1791 /* Check if key size is greater than 64 bytes */
<> 144:ef7eb2e8f9f7 1792 if(hhash->Init.KeySize > 64)
<> 144:ef7eb2e8f9f7 1793 {
<> 144:ef7eb2e8f9f7 1794 /* Select the HMAC SHA1 mode */
<> 144:ef7eb2e8f9f7 1795 HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1796 }
<> 144:ef7eb2e8f9f7 1797 else
<> 144:ef7eb2e8f9f7 1798 {
<> 144:ef7eb2e8f9f7 1799 /* Select the HMAC SHA1 mode */
<> 144:ef7eb2e8f9f7 1800 HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1801 }
<> 144:ef7eb2e8f9f7 1802 }
<> 144:ef7eb2e8f9f7 1803
<> 144:ef7eb2e8f9f7 1804 /* Set the phase */
<> 144:ef7eb2e8f9f7 1805 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1806
<> 144:ef7eb2e8f9f7 1807 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1808 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1809
<> 144:ef7eb2e8f9f7 1810 /* Get the key address */
<> 144:ef7eb2e8f9f7 1811 inputaddr = (uint32_t)(hhash->Init.pKey);
<> 144:ef7eb2e8f9f7 1812
<> 144:ef7eb2e8f9f7 1813 /* Set the HASH DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1814 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 1815 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1816 hhash->hdmain->XferErrorCallback = HASH_DMAError;
<> 144:ef7eb2e8f9f7 1817
<> 144:ef7eb2e8f9f7 1818 /* Enable the DMA In DMA Stream */
<> 144:ef7eb2e8f9f7 1819 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
<> 144:ef7eb2e8f9f7 1820 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 1821 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 1822
<> 144:ef7eb2e8f9f7 1823 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1824 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1825
<> 144:ef7eb2e8f9f7 1826 /* Return function status */
<> 144:ef7eb2e8f9f7 1827 return HAL_OK;
<> 144:ef7eb2e8f9f7 1828 }
<> 144:ef7eb2e8f9f7 1829
<> 144:ef7eb2e8f9f7 1830 /**
<> 144:ef7eb2e8f9f7 1831 * @}
<> 144:ef7eb2e8f9f7 1832 */
<> 144:ef7eb2e8f9f7 1833
<> 144:ef7eb2e8f9f7 1834 /** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions
<> 144:ef7eb2e8f9f7 1835 * @brief Peripheral State functions.
<> 144:ef7eb2e8f9f7 1836 *
<> 144:ef7eb2e8f9f7 1837 @verbatim
<> 144:ef7eb2e8f9f7 1838 ===============================================================================
<> 144:ef7eb2e8f9f7 1839 ##### Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1840 ===============================================================================
<> 144:ef7eb2e8f9f7 1841 [..]
<> 144:ef7eb2e8f9f7 1842 This subsection permits to get in run-time the status of the peripheral.
<> 144:ef7eb2e8f9f7 1843
<> 144:ef7eb2e8f9f7 1844 @endverbatim
<> 144:ef7eb2e8f9f7 1845 * @{
<> 144:ef7eb2e8f9f7 1846 */
<> 144:ef7eb2e8f9f7 1847
<> 144:ef7eb2e8f9f7 1848 /**
<> 144:ef7eb2e8f9f7 1849 * @brief return the HASH state
<> 144:ef7eb2e8f9f7 1850 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1851 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1852 * @retval HAL state
<> 144:ef7eb2e8f9f7 1853 */
<> 144:ef7eb2e8f9f7 1854 HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 1855 {
<> 144:ef7eb2e8f9f7 1856 return hhash->State;
<> 144:ef7eb2e8f9f7 1857 }
<> 144:ef7eb2e8f9f7 1858
<> 144:ef7eb2e8f9f7 1859 /**
<> 144:ef7eb2e8f9f7 1860 * @}
<> 144:ef7eb2e8f9f7 1861 */
<> 144:ef7eb2e8f9f7 1862
<> 144:ef7eb2e8f9f7 1863 /**
<> 144:ef7eb2e8f9f7 1864 * @}
<> 144:ef7eb2e8f9f7 1865 */
<> 144:ef7eb2e8f9f7 1866
<> 144:ef7eb2e8f9f7 1867 #endif /* HAL_HASH_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1868
<> 144:ef7eb2e8f9f7 1869 /**
<> 144:ef7eb2e8f9f7 1870 * @}
<> 144:ef7eb2e8f9f7 1871 */
<> 144:ef7eb2e8f9f7 1872 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 1873
<> 144:ef7eb2e8f9f7 1874 /**
<> 144:ef7eb2e8f9f7 1875 * @}
<> 144:ef7eb2e8f9f7 1876 */
<> 144:ef7eb2e8f9f7 1877
<> 144:ef7eb2e8f9f7 1878 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/