Iftikhar Aziz / mbed-dev

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Dependents:   LSS_Rev_1

Fork of mbed-dev by Umar Naeem

targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_NUVOTON/TARGET_NUC472/StdDriver/nuc472_pwm.h@144:ef7eb2e8f9f7
Child:
150:02e0a0aed4ec
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file pwm.h
<> 144:ef7eb2e8f9f7 3 * @version V1.00
<> 144:ef7eb2e8f9f7 4 * $Revision: 19 $
<> 144:ef7eb2e8f9f7 5 * $Date: 14/10/06 1:36p $
<> 144:ef7eb2e8f9f7 6 * @brief NUC472/NUC442 PWM driver header file
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * @note
<> 144:ef7eb2e8f9f7 9 * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
<> 144:ef7eb2e8f9f7 10 *****************************************************************************/
<> 144:ef7eb2e8f9f7 11 #ifndef __PWM_H__
<> 144:ef7eb2e8f9f7 12 #define __PWM_H__
<> 144:ef7eb2e8f9f7 13
<> 144:ef7eb2e8f9f7 14 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 15 extern "C"
<> 144:ef7eb2e8f9f7 16 {
<> 144:ef7eb2e8f9f7 17 #endif
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
<> 144:ef7eb2e8f9f7 21 @{
<> 144:ef7eb2e8f9f7 22 */
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 /** @addtogroup NUC472_442_PWM_Driver PWM Driver
<> 144:ef7eb2e8f9f7 25 @{
<> 144:ef7eb2e8f9f7 26 */
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 /** @addtogroup NUC472_442_PWM_EXPORTED_CONSTANTS PWM Exported Constants
<> 144:ef7eb2e8f9f7 29 @{
<> 144:ef7eb2e8f9f7 30 */
<> 144:ef7eb2e8f9f7 31 #define PWM_CHANNEL_NUM (6) /*!< PWM channel number \hideinitializer */
<> 144:ef7eb2e8f9f7 32 #define PWM_CH_0_MASK (1UL) /*!< PWM channel 0 mask \hideinitializer */
<> 144:ef7eb2e8f9f7 33 #define PWM_CH_1_MASK (2UL) /*!< PWM channel 1 mask \hideinitializer */
<> 144:ef7eb2e8f9f7 34 #define PWM_CH_2_MASK (4UL) /*!< PWM channel 2 mask \hideinitializer */
<> 144:ef7eb2e8f9f7 35 #define PWM_CH_3_MASK (8UL) /*!< PWM channel 3 mask \hideinitializer */
<> 144:ef7eb2e8f9f7 36 #define PWM_CH_4_MASK (16UL) /*!< PWM channel 4 mask \hideinitializer */
<> 144:ef7eb2e8f9f7 37 #define PWM_CH_5_MASK (32UL) /*!< PWM channel 5 mask \hideinitializer */
<> 144:ef7eb2e8f9f7 38 #define PWM_CH_6_MASK (64UL) /*!< PWM channel 6 mask \hideinitializer */
<> 144:ef7eb2e8f9f7 39 #define PWM_CH_7_MASK (128UL) /*!< PWM channel 7 mask \hideinitializer */
<> 144:ef7eb2e8f9f7 40 #define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 \hideinitializer */
<> 144:ef7eb2e8f9f7 41 #define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 \hideinitializer */
<> 144:ef7eb2e8f9f7 42 #define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 \hideinitializer */
<> 144:ef7eb2e8f9f7 43 #define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 \hideinitializer */
<> 144:ef7eb2e8f9f7 44 #define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 \hideinitializer */
<> 144:ef7eb2e8f9f7 45 #define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type \hideinitializer */
<> 144:ef7eb2e8f9f7 46 #define PWM_CENTER_ALIGNED (1UL) /*!< PWM working in center aligned type \hideinitializer */
<> 144:ef7eb2e8f9f7 47 #define PWM_TRIGGER_ADC_RISING_EDGE_POINT (0x1000000UL) /*!< PWM trigger ADC while output rising edge is detected \hideinitializer */
<> 144:ef7eb2e8f9f7 48 #define PWM_TRIGGER_ADC_FALLING_EDGE_POINT (0x10000UL) /*!< PWM trigger ADC while output falling edge is detected \hideinitializer */
<> 144:ef7eb2e8f9f7 49 #define PWM_TRIGGER_ADC_CENTER_POINT (0x100UL) /*!< PWM trigger ADC while counter matches (CNR + 1) \hideinitializer */
<> 144:ef7eb2e8f9f7 50 #define PWM_TRIGGER_ADC_PERIOD_POINT (0x1UL) /*!< PWM trigger ADC while counter down count to 0 \hideinitializer */
<> 144:ef7eb2e8f9f7 51 #define PWM_BRK0_BKP0 (0UL) /*!< Brake0 signal source from external pin BKP0 \hideinitializer */
<> 144:ef7eb2e8f9f7 52 #define PWM_BRK0_CPO0 (PWM_BRKCTL_CPO0BKEN_Msk) /*!< Brake0 signal source from analog comparator 0 output \hideinitializer */
<> 144:ef7eb2e8f9f7 53 #define PWM_BRK0_CPO1 (PWM_BRKCTL_CPO1BKEN_Msk) /*!< Brake0 signal source from analog comparator 1 output \hideinitializer */
<> 144:ef7eb2e8f9f7 54 #define PWM_BRK0_CPO2 (PWM_BRKCTL_CPO2BKEN_Msk) /*!< Brake0 signal source from analog comparator 2 output \hideinitializer */
<> 144:ef7eb2e8f9f7 55 #define PWM_BK1SEL_BKP1 (0UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from external pin BKP1 \hideinitializer */
<> 144:ef7eb2e8f9f7 56 #define PWM_BK1SEL_CPO0 (1UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 0 output \hideinitializer */
<> 144:ef7eb2e8f9f7 57 #define PWM_BK1SEL_CPO1 (2UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 1 output \hideinitializer */
<> 144:ef7eb2e8f9f7 58 #define PWM_PERIOD_INT_UNDERFLOW (0) /*!< PWM period interrupt trigger if counter underflow \hideinitializer */
<> 144:ef7eb2e8f9f7 59 #define PWM_PERIOD_INT_MATCH_CNR (1UL) /*!< PWM period interrupt trigger if counter match CNR \hideinitializer */
<> 144:ef7eb2e8f9f7 60 #define PWM_DUTY_INT_MATCH_CMR_DN (0) /*!< PWM duty interrupt if counter match CNR during down counting \hideinitializer */
<> 144:ef7eb2e8f9f7 61 #define PWM_DUTY_INT_MATCH_CMR_UP (0x100UL) /*!< PWM duty interrupt if counter match CNR during up counting \hideinitializer */
<> 144:ef7eb2e8f9f7 62 #define PWM_FALLING_LATCH_INT_ENABLE (0x1000000UL) /*!< PWM falling latch interrupt enable \hideinitializer */
<> 144:ef7eb2e8f9f7 63 #define PWM_RISING_LATCH_INT_ENABLE (0x10000UL) /*!< PWM rising latch interrupt enable \hideinitializer */
<> 144:ef7eb2e8f9f7 64 #define PWM_RISING_FALLING_LATCH_INT_ENABLE (0x1010000UL) /*!< PWM rising latch interrupt enable \hideinitializer */
<> 144:ef7eb2e8f9f7 65 #define PWM_FALLING_LATCH_INT_FLAG (PWM_FALLING_LATCH_INT_ENABLE) /*!< PWM falling latch condition happened \hideinitializer */
<> 144:ef7eb2e8f9f7 66 #define PWM_RISING_LATCH_INT_FLAG (PWM_RISING_LATCH_INT_ENABLE) /*!< PWM rising latch condition happened \hideinitializer */
<> 144:ef7eb2e8f9f7 67 #define PWM_RISING_FALLING_LATCH_INT_FLAG (PWM_RISING_FALLING_LATCH_INT_ENABLE) /*!< PWM rising latch condition happened \hideinitializer */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /*@}*/ /* end of group NUC472_442_PWM_EXPORTED_CONSTANTS */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /** @addtogroup NUC472_442_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
<> 144:ef7eb2e8f9f7 73 @{
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /**
<> 144:ef7eb2e8f9f7 77 * @brief This macro enable complementary mode
<> 144:ef7eb2e8f9f7 78 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 79 * @return None
<> 144:ef7eb2e8f9f7 80 * \hideinitializer
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82 #define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) (pwm->CTL = pwm->CTL | PWM_CTL_OUTMODE_Msk)
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /**
<> 144:ef7eb2e8f9f7 85 * @brief This macro disable complementary mode, and enable independent mode.
<> 144:ef7eb2e8f9f7 86 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 87 * @return None
<> 144:ef7eb2e8f9f7 88 * \hideinitializer
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90 #define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) (pwm->CTL = pwm->CTL & ~PWM_CTL_OUTMODE_Msk)
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /**
<> 144:ef7eb2e8f9f7 93 * @brief This macro enable group mode
<> 144:ef7eb2e8f9f7 94 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 95 * @return None
<> 144:ef7eb2e8f9f7 96 * \hideinitializer
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98 #define PWM_ENABLE_GROUP_MODE(pwm) (pwm->CTL = pwm->CTL | PWM_CTL_GROUPEN_Msk)
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /**
<> 144:ef7eb2e8f9f7 101 * @brief This macro disable group mode
<> 144:ef7eb2e8f9f7 102 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 103 * @return None
<> 144:ef7eb2e8f9f7 104 * \hideinitializer
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106 #define PWM_DISABLE_GROUP_MODE(pwm) (pwm->CTL = pwm->CTL & ~PWM_CTL_GROUPEN_Msk)
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /**
<> 144:ef7eb2e8f9f7 109 * @brief This macro enable synchronous mode
<> 144:ef7eb2e8f9f7 110 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 111 * @return None
<> 144:ef7eb2e8f9f7 112 * \hideinitializer
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114 #define PWM_ENABLE_SYNC_MODE(pwm) (pwm->CTL = pwm->CTL | PWM_CTL_SYNCEN_Msk)
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @brief This macro disable synchronous mode, and enable independent mode.
<> 144:ef7eb2e8f9f7 118 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 119 * @return None
<> 144:ef7eb2e8f9f7 120 * \hideinitializer
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 #define PWM_DISABLE_SYNC_MODE(pwm) (pwm->CTL = pwm->CTL & ~PWM_CTL_SYNCEN_Msk)
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @brief This macro enable output inverter of specified channel(s)
<> 144:ef7eb2e8f9f7 126 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 127 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
<> 144:ef7eb2e8f9f7 128 * Bit 0 represents channel 0, bit 1 represents channel 1...
<> 144:ef7eb2e8f9f7 129 * @return None
<> 144:ef7eb2e8f9f7 130 * \hideinitializer
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 #define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) (pwm->CTL |= (u32ChannelMask << PWM_CTL_PINV_Pos)
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /**
<> 144:ef7eb2e8f9f7 135 * @brief This macro get captured rising data
<> 144:ef7eb2e8f9f7 136 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 137 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 138 * @return None
<> 144:ef7eb2e8f9f7 139 * \hideinitializer
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141 #define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->RCAPDAT0 + 2 * u32ChannelNum))
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /**
<> 144:ef7eb2e8f9f7 144 * @brief This macro get captured falling data
<> 144:ef7eb2e8f9f7 145 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 146 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 147 * @return None
<> 144:ef7eb2e8f9f7 148 * \hideinitializer
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 #define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->FCAPDAT0 + 2 * u32ChannelNum))
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /**
<> 144:ef7eb2e8f9f7 153 * @brief This macro mask output output logic to high or low
<> 144:ef7eb2e8f9f7 154 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 155 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
<> 144:ef7eb2e8f9f7 156 * Bit 0 represents channel 0, bit 1 represents channel 1...
<> 144:ef7eb2e8f9f7 157 * @param[in] u32LevelMask Output logic to high or low
<> 144:ef7eb2e8f9f7 158 * @return None
<> 144:ef7eb2e8f9f7 159 * \hideinitializer
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161 #define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) (pwm->MSKEN |= u32ChannelMask)
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @brief This macro set the prescaler of the selected channel
<> 144:ef7eb2e8f9f7 165 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 166 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 167 * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF
<> 144:ef7eb2e8f9f7 168 * @return None
<> 144:ef7eb2e8f9f7 169 * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
<> 144:ef7eb2e8f9f7 170 * channel 1 will also be affected.
<> 144:ef7eb2e8f9f7 171 * \hideinitializer
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173 #define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
<> 144:ef7eb2e8f9f7 174 (pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @brief This macro set the divider of the selected channel
<> 144:ef7eb2e8f9f7 178 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 179 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 180 * @param[in] u32Divider Clock divider of specified channel. Valid values are
<> 144:ef7eb2e8f9f7 181 * - \ref PWM_CLK_DIV_1
<> 144:ef7eb2e8f9f7 182 * - \ref PWM_CLK_DIV_2
<> 144:ef7eb2e8f9f7 183 * - \ref PWM_CLK_DIV_4
<> 144:ef7eb2e8f9f7 184 * - \ref PWM_CLK_DIV_8
<> 144:ef7eb2e8f9f7 185 * - \ref PWM_CLK_DIV_16
<> 144:ef7eb2e8f9f7 186 * @return None
<> 144:ef7eb2e8f9f7 187 * \hideinitializer
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189 #define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
<> 144:ef7eb2e8f9f7 190 (pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /**
<> 144:ef7eb2e8f9f7 193 * @brief This macro set the duty of the selected channel
<> 144:ef7eb2e8f9f7 194 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 195 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 196 * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
<> 144:ef7eb2e8f9f7 197 * @return None
<> 144:ef7eb2e8f9f7 198 * @note This new setting will take effect on next PWM period
<> 144:ef7eb2e8f9f7 199 * \hideinitializer
<> 144:ef7eb2e8f9f7 200 */
<> 144:ef7eb2e8f9f7 201 #define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) (pwm->CMPDAT[u32ChannelNum] = (u32CMR))
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @brief This macro set the period of the selected channel
<> 144:ef7eb2e8f9f7 205 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 206 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
<> 144:ef7eb2e8f9f7 207 * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
<> 144:ef7eb2e8f9f7 208 * @return None
<> 144:ef7eb2e8f9f7 209 * @note This new setting will take effect on next PWM period
<> 144:ef7eb2e8f9f7 210 * @note PWM counter will stop if period length set to 0
<> 144:ef7eb2e8f9f7 211 * \hideinitializer
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213 #define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) (pwm->PERIOD[u32ChannelNum] = (u32CNR))
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /**
<> 144:ef7eb2e8f9f7 216 * @brief This macro set the PWM aligned type
<> 144:ef7eb2e8f9f7 217 * @param[in] pwm The base address of PWM module
<> 144:ef7eb2e8f9f7 218 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
<> 144:ef7eb2e8f9f7 219 * Bit 0 represents channel 0, bit 1 represents channel 1...
<> 144:ef7eb2e8f9f7 220 * @param[in] u32AlignedType PWM aligned type, valid values are:
<> 144:ef7eb2e8f9f7 221 * - \ref PWM_EDGE_ALIGNED
<> 144:ef7eb2e8f9f7 222 * - \ref PWM_CENTER_ALIGNED
<> 144:ef7eb2e8f9f7 223 * @return None
<> 144:ef7eb2e8f9f7 224 * \hideinitializer
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226 #define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
<> 144:ef7eb2e8f9f7 227 (pwm->CTL = (pwm->CTL & ~(u32ChannelMask << PWM_CTL_CNTMODE_Pos) | (u32AlignedType << PWM_CTL_CNTMODE_Pos))
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
<> 144:ef7eb2e8f9f7 231 uint32_t u32ChannelNum,
<> 144:ef7eb2e8f9f7 232 uint32_t u32Frequency,
<> 144:ef7eb2e8f9f7 233 uint32_t u32DutyCycle);
<> 144:ef7eb2e8f9f7 234 uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
<> 144:ef7eb2e8f9f7 235 uint32_t u32ChannelNum,
<> 144:ef7eb2e8f9f7 236 uint32_t u32Frequency,
<> 144:ef7eb2e8f9f7 237 uint32_t u32DutyCycle,
<> 144:ef7eb2e8f9f7 238 uint32_t u32Frequency2);
<> 144:ef7eb2e8f9f7 239 uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
<> 144:ef7eb2e8f9f7 240 uint32_t u32ChannelNum,
<> 144:ef7eb2e8f9f7 241 uint32_t u32UnitTimeNsec,
<> 144:ef7eb2e8f9f7 242 uint32_t u32CaptureEdge);
<> 144:ef7eb2e8f9f7 243 void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
<> 144:ef7eb2e8f9f7 244 void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
<> 144:ef7eb2e8f9f7 245 void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
<> 144:ef7eb2e8f9f7 246 void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
<> 144:ef7eb2e8f9f7 247 void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
<> 144:ef7eb2e8f9f7 248 void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
<> 144:ef7eb2e8f9f7 249 uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
<> 144:ef7eb2e8f9f7 250 void PWM_EnableFaultBrake(PWM_T *pwm,
<> 144:ef7eb2e8f9f7 251 uint32_t u32ChannelMask,
<> 144:ef7eb2e8f9f7 252 uint32_t u32LevelMask,
<> 144:ef7eb2e8f9f7 253 uint32_t u32BrakeSource);
<> 144:ef7eb2e8f9f7 254 void PWM_ClearFaultBrakeFlag(PWM_T *pwm, uint32_t u32BrakeSource);
<> 144:ef7eb2e8f9f7 255 void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
<> 144:ef7eb2e8f9f7 256 void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
<> 144:ef7eb2e8f9f7 257 void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
<> 144:ef7eb2e8f9f7 258 void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
<> 144:ef7eb2e8f9f7 259 void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
<> 144:ef7eb2e8f9f7 260 void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
<> 144:ef7eb2e8f9f7 261 void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
<> 144:ef7eb2e8f9f7 262 void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
<> 144:ef7eb2e8f9f7 263 void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
<> 144:ef7eb2e8f9f7 264 uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
<> 144:ef7eb2e8f9f7 265 void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
<> 144:ef7eb2e8f9f7 266 void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
<> 144:ef7eb2e8f9f7 267 void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
<> 144:ef7eb2e8f9f7 268 uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
<> 144:ef7eb2e8f9f7 269 void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
<> 144:ef7eb2e8f9f7 270 void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
<> 144:ef7eb2e8f9f7 271 void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
<> 144:ef7eb2e8f9f7 272 uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
<> 144:ef7eb2e8f9f7 273 void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
<> 144:ef7eb2e8f9f7 274 void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
<> 144:ef7eb2e8f9f7 275 void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
<> 144:ef7eb2e8f9f7 276 uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /*@}*/ /* end of group NUC472_442_PWM_EXPORTED_FUNCTIONS */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /*@}*/ /* end of group NUC472_442_PWM_Driver */
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /*@}*/ /* end of group NUC472_442_Device_Driver */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288 #endif
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 #endif //__PWM_H__
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/