u8g_dev_uc1701_dogs102.c

00001 /*
00002 
00003   u8g_dev_uc1701_dogs102.c
00004 
00005   Universal 8bit Graphics Library
00006   
00007   Copyright (c) 2011, olikraus@gmail.com
00008   All rights reserved.
00009 
00010   Redistribution and use in source and binary forms, with or without modification, 
00011   are permitted provided that the following conditions are met:
00012 
00013   * Redistributions of source code must retain the above copyright notice, this list 
00014     of conditions and the following disclaimer.
00015     
00016   * Redistributions in binary form must reproduce the above copyright notice, this 
00017     list of conditions and the following disclaimer in the documentation and/or other 
00018     materials provided with the distribution.
00019 
00020   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 
00021   CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
00022   INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
00023   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
00024   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
00025   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
00026   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
00027   NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
00028   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
00029   CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
00030   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00031   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00032   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
00033   
00034   
00035 */
00036 
00037 #include "u8g.h"
00038 
00039 #define WIDTH 102
00040 #define HEIGHT 64
00041 #define PAGE_HEIGHT 8
00042 
00043 static const uint8_t u8g_dev_dogs102_init_seq[] PROGMEM = {
00044   U8G_ESC_CS(0),             /* disable chip */
00045   U8G_ESC_ADR(0),           /* instruction mode */
00046   U8G_ESC_RST(1),           /* do reset low pulse with (1*16)+2 milliseconds */
00047   U8G_ESC_CS(1),             /* enable chip */
00048   
00049   0x0e2,                    /* soft reset */
00050   0x040,                        /* set display start line to 0 */
00051   0x0a1,                        /* ADC set to reverse */
00052   0x0c0,                        /* common output mode */
00053   0x0a6,                        /* display normal, bit val 0: LCD pixel off. */
00054   0x0a2,                        /* LCD bias 1/9 */
00055   0x02f,                        /* all power  control circuits on */
00056   0x027,                        /* regulator, booster and follower */
00057   0x081,                        /* set contrast */
00058   0x00e,                        /* contrast value, EA default: 0x010, previous value for S102: 0x0e */
00059   0x0fa,                        /* Set Temp compensation */ 
00060   0x090,                        /* 0.11 deg/c WP Off WC Off*/
00061   0x0a4,                        /* normal display  */
00062   0x0af,                        /* display on */
00063   U8G_ESC_DLY(100),       /* delay 100 ms */
00064   0x0a5,                        /* display all points, ST7565, UC1610 */
00065   U8G_ESC_DLY(100),       /* delay 100 ms */
00066   U8G_ESC_DLY(100),       /* delay 100 ms */
00067   0x0a4,                        /* normal display */
00068   U8G_ESC_CS(0),             /* disable chip */
00069   U8G_ESC_END                /* end of sequence */
00070 };
00071 
00072 static const uint8_t u8g_dev_dogs102_data_start[] PROGMEM = {
00073   U8G_ESC_ADR(0),           /* instruction mode */
00074   U8G_ESC_CS(1),             /* enable chip */
00075   0x010,        /* set upper 4 bit of the col adr to 0 */
00076   0x000,        /* set lower 4 bit of the col adr to 0 */      
00077   U8G_ESC_END                /* end of sequence */
00078 };
00079 
00080 uint8_t u8g_dev_dogs102_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00081 {
00082   switch(msg)
00083   {
00084     case U8G_DEV_MSG_INIT:
00085       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
00086       u8g_WriteEscSeqP(u8g, dev, u8g_dev_dogs102_init_seq);
00087       break;
00088     case U8G_DEV_MSG_STOP:
00089       break;
00090     case U8G_DEV_MSG_PAGE_NEXT:
00091       {
00092         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00093         u8g_WriteEscSeqP(u8g, dev, u8g_dev_dogs102_data_start);    
00094         u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (ST7565R) */
00095         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00096         if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
00097           return 0;
00098         u8g_SetChipSelect(u8g, dev, 0);
00099       }
00100       break;
00101     case U8G_DEV_MSG_CONTRAST:
00102       u8g_SetChipSelect(u8g, dev, 1);
00103       u8g_SetAddress(u8g, dev, 0);          /* instruction mode */
00104       u8g_WriteByte(u8g, dev, 0x081);
00105       u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
00106       u8g_SetChipSelect(u8g, dev, 0);      
00107       return 1;
00108   }
00109   return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
00110 }
00111 
00112 uint8_t u8g_dev_uc1701_dogs102_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00113 {
00114   switch(msg)
00115   {
00116     case U8G_DEV_MSG_INIT:
00117       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
00118       u8g_WriteEscSeqP(u8g, dev, u8g_dev_dogs102_init_seq);
00119       break;
00120     case U8G_DEV_MSG_STOP:
00121       break;
00122     case U8G_DEV_MSG_PAGE_NEXT:
00123       {
00124         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00125     
00126         u8g_WriteEscSeqP(u8g, dev, u8g_dev_dogs102_data_start);    
00127         u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page)); /* select current page (ST7565R) */
00128         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00129     u8g_WriteSequence(u8g, dev, pb->width, pb->buf); 
00130         u8g_SetChipSelect(u8g, dev, 0);
00131     
00132         u8g_WriteEscSeqP(u8g, dev, u8g_dev_dogs102_data_start);    
00133         u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
00134         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00135     u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width); 
00136         u8g_SetChipSelect(u8g, dev, 0);
00137       }
00138       break;
00139     case U8G_DEV_MSG_CONTRAST:
00140       u8g_SetChipSelect(u8g, dev, 1);
00141       u8g_SetAddress(u8g, dev, 0);          /* instruction mode */
00142       u8g_WriteByte(u8g, dev, 0x081);
00143       u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
00144       u8g_SetChipSelect(u8g, dev, 0);      
00145       return 1;
00146   }
00147   return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
00148 }
00149 
00150 U8G_PB_DEV(u8g_dev_uc1701_dogs102_sw_spi , WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_dogs102_fn, U8G_COM_SW_SPI);
00151 U8G_PB_DEV(u8g_dev_uc1701_dogs102_hw_spi , WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_dogs102_fn, U8G_COM_HW_SPI);
00152 
00153 uint8_t u8g_dev_uc1701_dogs102_2x_buf[WIDTH*2] U8G_NOCOMMON ; 
00154 u8g_pb_t u8g_dev_uc1701_dogs102_2x_pb = { {16, HEIGHT, 0, 0, 0},  WIDTH, u8g_dev_uc1701_dogs102_2x_buf}; 
00155 u8g_dev_t u8g_dev_uc1701_dogs102_2x_sw_spi = { u8g_dev_uc1701_dogs102_2x_fn, &u8g_dev_uc1701_dogs102_2x_pb, U8G_COM_SW_SPI };
00156 u8g_dev_t u8g_dev_uc1701_dogs102_2x_hw_spi = { u8g_dev_uc1701_dogs102_2x_fn, &u8g_dev_uc1701_dogs102_2x_pb, U8G_COM_HW_SPI };
00157 
00158