u8g_dev_st7687_c144mvgd.c

00001 /*
00002 
00003   u8g_dev_st7687_c144mvgd.c (1.44" TFT)
00004   
00005   Status: Started, but not finished
00006 
00007   Universal 8bit Graphics Library
00008   
00009   Copyright (c) 2012, olikraus@gmail.com
00010   All rights reserved.
00011 
00012   Redistribution and use in source and binary forms, with or without modification, 
00013   are permitted provided that the following conditions are met:
00014 
00015   * Redistributions of source code must retain the above copyright notice, this list 
00016     of conditions and the following disclaimer.
00017     
00018   * Redistributions in binary form must reproduce the above copyright notice, this 
00019     list of conditions and the following disclaimer in the documentation and/or other 
00020     materials provided with the distribution.
00021 
00022   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 
00023   CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
00024   INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
00025   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
00026   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
00027   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
00028   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
00029   NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
00030   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
00031   CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
00032   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00033   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00034   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
00035   
00036   
00037 */
00038 
00039 #include "u8g.h"
00040 
00041 #define WIDTH 128
00042 #define HEIGHT 128
00043 #define PAGE_HEIGHT 8
00044 
00045 
00046 #ifdef FIRST_VERSION
00047 /* 
00048 see also: read.pudn.com/downloads115/sourcecode/app/484503/LCM_Display.c__.htm 
00049 http://en.pudn.com/downloads115/sourcecode/app/detail484503_en.html
00050 */
00051 
00052 static const uint8_t u8g_dev_st7687_c144mvgd_init_seq[] PROGMEM = {
00053   U8G_ESC_CS(0),             /* disable chip */
00054   U8G_ESC_ADR(0),           /* instruction mode */
00055   U8G_ESC_CS(1),             /* enable chip */
00056   U8G_ESC_RST(15),           /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
00057   
00058   0x001,                        /* A0=0, SW reset */
00059   U8G_ESC_DLY(200),         /* delay 200 ms */
00060   
00061   0x0d7,                        /* EEPROM data auto re-load control */
00062   U8G_ESC_ADR(1),           /* data mode */
00063   0x09f,                             /* ARD = 1 */
00064   U8G_ESC_ADR(0),           /* instruction mode */
00065   U8G_ESC_DLY(100),         /* delay 100 ms */
00066   
00067   0x0e0,                        /* EEPROM control in */
00068   U8G_ESC_ADR(1),           /* data mode */
00069   0x000,                             /*  */
00070   U8G_ESC_ADR(0),           /* instruction mode */
00071   U8G_ESC_DLY(100),         /* delay 100 ms */
00072   
00073 #ifdef NOT_REQUIRED  
00074   0x0fa,                        /* EEPROM function selection 8.1.66 */
00075   U8G_ESC_ADR(1),           /* data mode */
00076   0x000,                             /*  */
00077   U8G_ESC_ADR(0),           /* instruction mode */
00078   U8G_ESC_DLY(100),         /* delay 100 ms */
00079 #endif 
00080 
00081   0x0e3,                        /* Read from EEPROM, 8.1.55 */
00082   U8G_ESC_DLY(100),         /* delay 100 ms */
00083 
00084   0x0e1,                        /* EEPROM control out, 8.1.53 */
00085   U8G_ESC_DLY(100),         /* delay 100 ms */
00086   
00087   //0x028,                        /* display off */
00088   0x011,                                /* Sleep out & booster on */
00089   U8G_ESC_DLY(100),         /* delay 100 ms */
00090   
00091   0x0c0,                        /* Vop setting, 8.1.42 */
00092   U8G_ESC_ADR(1),           /* data mode */
00093   0x000,                             /*  */
00094   0x001,                             /*  3.6 + 256*0.04 = 13.84 Volt */
00095   U8G_ESC_ADR(0),           /* instruction mode */
00096   U8G_ESC_DLY(100),         /* delay 100 ms */
00097   
00098   0x0c3,                                /* Bias selection, 8.1.45 */
00099   U8G_ESC_ADR(1),           /* data mode */
00100   0x003,
00101   U8G_ESC_ADR(0),           /* instruction mode */
00102   
00103   0x0c4,                                /* Booster setting 8.1.46 */
00104   U8G_ESC_ADR(1),           /* data mode */
00105   0x007,
00106   U8G_ESC_ADR(0),           /* instruction mode */
00107   
00108   0x0c5,                                /* ??? */
00109   U8G_ESC_ADR(1),           /* data mode */
00110   0x001,
00111   U8G_ESC_ADR(0),           /* instruction mode */
00112   
00113   0x0cb,                                /* FV3 with Booster x2 control, 8.1.47 */
00114   U8G_ESC_ADR(1),           /* data mode */
00115   0x001,
00116   U8G_ESC_ADR(0),           /* instruction mode */
00117   
00118   0x036,                                /* Memory data access control, 8.1.28 */
00119   U8G_ESC_ADR(1),           /* data mode */
00120   0x080,
00121   U8G_ESC_ADR(0),           /* instruction mode */
00122 
00123   0x0b5,                                /* N-line control, 8.1.37 */
00124   U8G_ESC_ADR(1),           /* data mode */
00125   0x089,
00126   U8G_ESC_ADR(0),           /* instruction mode */
00127 
00128 
00129   0x0d0,                                /* Analog circuit setting, 8.1.49 */
00130   U8G_ESC_ADR(1),           /* data mode */
00131   0x01d,
00132   U8G_ESC_ADR(0),           /* instruction mode */
00133 
00134   0x0b7,                                /* Com/Seg Scan Direction, 8.1.38 */
00135   U8G_ESC_ADR(1),           /* data mode */
00136   0x040,
00137   U8G_ESC_ADR(0),           /* instruction mode */
00138 
00139   0x025,                                /* Write contrast, 8.1.17 */
00140   U8G_ESC_ADR(1),           /* data mode */
00141   0x03f,
00142   U8G_ESC_ADR(0),           /* instruction mode */
00143 
00144   0x03a,                                /* Interface pixel format, 8.1.32 */
00145   U8G_ESC_ADR(1),           /* data mode */
00146   0x004,                                /* 3: 12 bit per pixel Type A, 4: 12 bit Type B, 5: 16bit per pixel */
00147   U8G_ESC_ADR(0),           /* instruction mode */
00148 
00149   0x0b0,                                /* Display Duty setting, 8.1.34 */
00150   U8G_ESC_ADR(1),           /* data mode */
00151   0x07f,
00152   U8G_ESC_ADR(0),           /* instruction mode */
00153 
00154   0x0f0,                                /* Frame Freq. in Temp range A,B,C and D, 8.1.59 */
00155   U8G_ESC_ADR(1),           /* data mode */
00156   0x007,
00157   0x00c,
00158   0x00c,
00159   0x015,
00160   U8G_ESC_ADR(0),           /* instruction mode */
00161 
00162   0x0f9,                                /* Frame RGB Value, 8.1.65 */
00163   U8G_ESC_ADR(1),           /* data mode */
00164   0x000,
00165   0x005,
00166   0x008,
00167   0x00a,
00168   0x00c,
00169   0x00e,
00170   0x010,
00171   0x011,
00172   0x012,
00173   0x013,
00174   0x014,
00175   0x015,
00176   0x016,
00177   0x018,
00178   0x01a,
00179   0x01b,
00180   U8G_ESC_ADR(0),           /* instruction mode */
00181 
00182   0x0f9,                                /* Frame RGB Value, 8.1.65 */
00183   U8G_ESC_ADR(1),           /* data mode */
00184   0x000,
00185   0x000,
00186   0x000,
00187   0x000,
00188   0x033,
00189   0x055,
00190   0x055,
00191   0x055,
00192   U8G_ESC_ADR(0),           /* instruction mode */
00193 
00194   0x029,                        /* display on */
00195 
00196   U8G_ESC_CS(0),             /* disable chip */
00197   U8G_ESC_END                /* end of sequence */
00198 
00199 };
00200 
00201 #else
00202 
00203 /*
00204 http://www.waitingforfriday.com/images/e/e3/FTM144D01N_test.zip
00205 */
00206 
00207 static const uint8_t u8g_dev_st7687_c144mvgd_init_seq[] PROGMEM = {
00208   U8G_ESC_CS(0),             /* disable chip */
00209   U8G_ESC_ADR(0),           /* instruction mode */
00210   U8G_ESC_CS(1),             /* enable chip */
00211   U8G_ESC_RST(15),           /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
00212 
00213   0x011,                                /* Sleep out & booster on */
00214   U8G_ESC_DLY(5),         /* delay 5 ms */
00215     
00216   0x03a,                                /* Interface pixel format, 8.1.32 */
00217   U8G_ESC_ADR(1),           /* data mode */
00218   0x004,                                /* 3: 12 bit per pixel Type A, 4: 12 bit Type B, 5: 16bit per pixel */
00219   U8G_ESC_ADR(0),           /* instruction mode */
00220   
00221   
00222   0x026,                                /* SET_GAMMA_CURVE */
00223   U8G_ESC_ADR(1),           /* data mode */
00224   0x004,                                
00225   U8G_ESC_ADR(0),           /* instruction mode */
00226 
00227   0x0f2,                                /* GAM_R_SEL */
00228   U8G_ESC_ADR(1),           /* data mode */
00229   0x001,                                /* enable gamma adj */                                
00230   U8G_ESC_ADR(0),           /* instruction mode */
00231 
00232 
00233   0x0e0,                                /* POSITIVE_GAMMA_CORRECT */
00234   U8G_ESC_ADR(1),           /* data mode */
00235   0x3f,
00236     0x25,
00237     0x1c,
00238     0x1e,
00239     0x20,
00240     0x12,
00241     0x2a,
00242     0x90,
00243     0x24,
00244     0x11,
00245     0x00,
00246     0x00,
00247     0x00,
00248     0x00,
00249     0x00,    
00250   U8G_ESC_ADR(0),           /* instruction mode */
00251 
00252   0x0e1,                                /* NEGATIVE_GAMMA_CORRECT */
00253   U8G_ESC_ADR(1),           /* data mode */
00254     0x20,
00255     0x20,
00256     0x20,
00257     0x20,
00258     0x05,
00259     0x00,
00260     0x15,
00261     0xa7,
00262     0x3d,
00263     0x18,
00264     0x25,
00265     0x2a,
00266     0x2b,
00267     0x2b,
00268     0x3a,
00269   U8G_ESC_ADR(0),           /* instruction mode */
00270      
00271   0x0b1,                                /* FRAME_RATE_CONTROL1 */
00272   U8G_ESC_ADR(1),           /* data mode */
00273   0x008,                                /* DIVA = 8 */
00274   0x008,                                /* VPA = 8 */
00275   U8G_ESC_ADR(0),           /* instruction mode */
00276 
00277 
00278   0x0b4,                                /* DISPLAY_INVERSION */
00279   U8G_ESC_ADR(1),           /* data mode */
00280   0x007,                                /* NLA = 1, NLB = 1, NLC = 1 (all on Frame Inversion) */
00281   U8G_ESC_ADR(0),           /* instruction mode */
00282     
00283   0x0c0,                                /* POWER_CONTROL1 */
00284   U8G_ESC_ADR(1),           /* data mode */
00285   0x00a,                                /* VRH = 10:  GVDD = 4.30 */
00286   0x002,                                /* VC = 2: VCI1 = 2.65 */
00287   U8G_ESC_ADR(0),           /* instruction mode */
00288    
00289   0x0c1,                                /* POWER_CONTROL2 */
00290   U8G_ESC_ADR(1),           /* data mode */
00291   0x002,                                /* BT = 2: AVDD = 2xVCI1, VCL = -1xVCI1, VGH = 5xVCI1, VGL = -2xVCI1 */
00292   U8G_ESC_ADR(0),           /* instruction mode */
00293       
00294   0x0c5,                                /* VCOM_CONTROL1 */
00295   U8G_ESC_ADR(1),           /* data mode */
00296   0x050,                                /* VMH = 80: VCOMH voltage = 4.5 */
00297   0x05b,                                /* VML = 91: VCOML voltage = -0.225 */
00298   U8G_ESC_ADR(0),           /* instruction mode */
00299 
00300   0x0c7,                                /* VCOM_OFFSET_CONTROL */
00301   U8G_ESC_ADR(1),           /* data mode */
00302   0x040,                                /* nVM = 0, VMF = 64: VCOMH output = VMH, VCOML output = VML */
00303   U8G_ESC_ADR(0),           /* instruction mode */
00304 
00305   0x02a,                                /* SET_COLUMN_ADDRESS */
00306   U8G_ESC_ADR(1),           /* data mode */
00307   0x000,                                /*  */
00308   0x000,                                /*  */
00309   0x000,                                /*  */
00310   0x07f,                                /*  */
00311   U8G_ESC_ADR(0),           /* instruction mode */
00312 
00313   0x02b,                                /* SET_PAGE_ADDRESS */
00314   U8G_ESC_ADR(1),           /* data mode */
00315   0x000,                                /*  */
00316   0x000,                                /*  */
00317   0x000,                                /*  */
00318   0x07f,                                /*  */
00319   U8G_ESC_ADR(0),           /* instruction mode */
00320 
00321   0x036,                                /* SET_ADDRESS_MODE */
00322   U8G_ESC_ADR(1),           /* data mode */
00323   0x000,                                /* Select display orientation */
00324   U8G_ESC_ADR(0),           /* instruction mode */
00325     
00326 
00327   0x029,                        /* display on */
00328   
00329   0x02c,                         /* write start */
00330   
00331   U8G_ESC_CS(0),             /* disable chip */
00332   U8G_ESC_END                /* end of sequence */
00333 
00334 };
00335 
00336 #endif
00337 
00338 
00339 
00340 
00341 /* calculate bytes for Type B 4096 color display */
00342 static uint8_t get_byte_1(uint8_t v)
00343 {
00344   v >>= 4;
00345   v &= 0x0e;
00346   return v;
00347 }
00348 
00349 static uint8_t get_byte_2(uint8_t v)
00350 {
00351   uint8_t w;
00352   w = v;
00353   w &= 3;
00354   w = (w<<2) | w;
00355   v <<= 3;
00356   v &= 0x0e0;
00357   w |= v;
00358   return w;
00359 }
00360 
00361 uint8_t u8g_dev_st7687_c144mvgd_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00362 {
00363   switch(msg)
00364   {
00365     case U8G_DEV_MSG_INIT:
00366       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
00367       u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7687_c144mvgd_init_seq);
00368       break;
00369     case U8G_DEV_MSG_STOP:
00370       break;
00371     case U8G_DEV_MSG_PAGE_NEXT:
00372       {
00373         uint8_t y, i, j;
00374         uint8_t *ptr;
00375         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00376         
00377         u8g_SetAddress(u8g, dev, 0);           /* cmd mode */
00378         u8g_SetChipSelect(u8g, dev, 1);
00379         y = pb->p.page_y0;
00380         ptr = pb->buf;
00381         
00382         u8g_SetAddress(u8g, dev, 0);           /* cmd mode */
00383         u8g_WriteByte(u8g, dev, 0x02a );      /* Column address set 8.1.20 */
00384         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00385         u8g_WriteByte(u8g, dev, 0x000 );      /* x0 */
00386         u8g_WriteByte(u8g, dev, WIDTH-1 );      /* x1 */
00387         u8g_SetAddress(u8g, dev, 0);           /* cmd mode */
00388         u8g_WriteByte(u8g, dev, 0x02b );      /* Row address set 8.1.21 */
00389         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00390         u8g_WriteByte(u8g, dev, y );      /* y0 */
00391         u8g_WriteByte(u8g, dev, y+PAGE_HEIGHT-1 );      /* y1 */
00392         u8g_SetAddress(u8g, dev, 0);           /* cmd mode */
00393         u8g_WriteByte(u8g, dev, 0x02c );      /* Memory write 8.1.22 */
00394         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00395         
00396         for( i = 0; i < PAGE_HEIGHT; i ++ )
00397         {
00398           
00399           for( j = 0; j < WIDTH; j ++ )
00400           {
00401             u8g_WriteByte(u8g, dev, get_byte_1(*ptr) );     
00402             u8g_WriteByte(u8g, dev, get_byte_2(*ptr) );                 
00403             ptr++;
00404           }
00405         }
00406         u8g_SetAddress(u8g, dev, 0);           /* cmd mode */
00407         u8g_SetChipSelect(u8g, dev, 0);
00408       }
00409       break;
00410   }
00411   return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
00412 }
00413 
00414 
00415 uint8_t u8g_st7687_c144mvgd_8h8_buf[WIDTH*8] U8G_NOCOMMON ; 
00416 u8g_pb_t u8g_st7687_c144mvgd_8h8_pb = { {8, HEIGHT, 0, 0, 0},  WIDTH, u8g_st7687_c144mvgd_8h8_buf}; 
00417 
00418 u8g_dev_t u8g_dev_st7687_c144mvgd_sw_spi = { u8g_dev_st7687_c144mvgd_fn, &u8g_st7687_c144mvgd_8h8_pb, u8g_com_arduino_sw_spi_fn };
00419 
00420 u8g_dev_t u8g_dev_st7687_c144mvgd_8bit = { u8g_dev_st7687_c144mvgd_fn, &u8g_st7687_c144mvgd_8h8_pb, U8G_COM_PARALLEL };
00421