u8g_dev_st7565_nhd_c12864.c

00001 /*
00002 
00003   u8g_dev_st7565_nhd_c12864.c
00004 
00005   Support for the NHD-C12864A1Z-FSB-FBW (Newhaven Display)
00006 
00007   Universal 8bit Graphics Library
00008   
00009   Copyright (c) 2012, olikraus@gmail.com
00010   All rights reserved.
00011 
00012   Redistribution and use in source and binary forms, with or without modification, 
00013   are permitted provided that the following conditions are met:
00014 
00015   * Redistributions of source code must retain the above copyright notice, this list 
00016     of conditions and the following disclaimer.
00017     
00018   * Redistributions in binary form must reproduce the above copyright notice, this 
00019     list of conditions and the following disclaimer in the documentation and/or other 
00020     materials provided with the distribution.
00021 
00022   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 
00023   CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
00024   INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
00025   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
00026   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
00027   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
00028   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
00029   NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
00030   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
00031   CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
00032   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00033   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00034   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
00035   
00036   
00037 */
00038 
00039 #include "u8g.h"
00040 
00041 #define WIDTH 128
00042 #define HEIGHT 64
00043 #define PAGE_HEIGHT 8
00044 
00045 const uint8_t u8g_dev_st7565_nhd_c12864_init_seq[] PROGMEM = {
00046   U8G_ESC_CS(0),             /* disable chip */
00047   U8G_ESC_ADR(0),           /* instruction mode */
00048   U8G_ESC_RST(10),           /* do reset low pulse with (10*16)+2 milliseconds */
00049   U8G_ESC_CS(1),             /* enable chip */
00050   
00051   0x040,                        /* set display start line */
00052   0x0a1,                        /* ADC set to reverse */
00053   0x0c0,                        /* common output mode: set scan direction normal operation */
00054   0x0a6,                           /* display normal, bit val 0: LCD pixel off. */
00055   0x0a2,                        /* LCD bias 1/9 */
00056   0x02f,                        /* all power  control circuits on */
00057   0x0f8,                        /* set booster ratio to */
00058   0x000,                        /* 4x */
00059   0x027,                        /* set V0 voltage resistor ratio to large */
00060   0x081,                        /* set contrast */
00061   0x008,                        /* contrast: 0x008 is a good value for NHD C12864, Nov 2012: User reports that 0x1a is much better */
00062   0x0ac,                        /* indicator */
00063   0x000,                        /* disable */
00064   0x0af,                        /* display on */
00065 
00066   U8G_ESC_DLY(100),       /* delay 100 ms */
00067   0x0a5,                        /* display all points, ST7565 */
00068   U8G_ESC_DLY(100),       /* delay 100 ms */
00069   U8G_ESC_DLY(100),       /* delay 100 ms */
00070   0x0a4,                        /* normal display */
00071   U8G_ESC_CS(0),             /* disable chip */
00072   U8G_ESC_END                /* end of sequence */
00073 };
00074 
00075 static const uint8_t u8g_dev_st7565_nhd_c12864_data_start[] PROGMEM = {
00076   U8G_ESC_ADR(0),           /* instruction mode */
00077   U8G_ESC_CS(1),             /* enable chip */
00078   0x010,        /* set upper 4 bit of the col adr to 0 */
00079   0x004,        /* set lower 4 bit of the col adr to 4 (NHD C12864) */  
00080   U8G_ESC_END                /* end of sequence */
00081 };
00082 
00083 static const uint8_t u8g_dev_st7565_c12864_sleep_on[] PROGMEM = {
00084   U8G_ESC_ADR(0),           /* instruction mode */
00085   U8G_ESC_CS(1),             /* enable chip */
00086   0x0ac,        /* static indicator off */
00087   0x000,                        /* indicator register set (not sure if this is required) */
00088   0x0ae,        /* display off */      
00089   0x0a5,        /* all points on */      
00090   U8G_ESC_CS(1),             /* disable chip */
00091   U8G_ESC_END                /* end of sequence */
00092 };
00093 
00094 static const uint8_t u8g_dev_st7565_c12864_sleep_off[] PROGMEM = {
00095   U8G_ESC_ADR(0),           /* instruction mode */
00096   U8G_ESC_CS(1),             /* enable chip */
00097   0x0a4,        /* all points off */      
00098   0x0af,        /* display on */      
00099   U8G_ESC_DLY(50),       /* delay 50 ms */
00100   U8G_ESC_CS(1),             /* disable chip */
00101   U8G_ESC_END                /* end of sequence */
00102 };
00103 
00104 uint8_t u8g_dev_st7565_nhd_c12864_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00105 {
00106   switch(msg)
00107   {
00108     case U8G_DEV_MSG_INIT:
00109       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
00110       u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_nhd_c12864_init_seq);
00111       break;
00112     case U8G_DEV_MSG_STOP:
00113       break;
00114     case U8G_DEV_MSG_PAGE_NEXT:
00115       {
00116         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00117         u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_nhd_c12864_data_start);    
00118         u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (ST7565R) */
00119         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00120         if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
00121           return 0;
00122         u8g_SetChipSelect(u8g, dev, 0);
00123       }
00124       break;
00125     case U8G_DEV_MSG_CONTRAST:
00126       u8g_SetChipSelect(u8g, dev, 1);
00127       u8g_SetAddress(u8g, dev, 0);          /* instruction mode */
00128       u8g_WriteByte(u8g, dev, 0x081);
00129       u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
00130       u8g_SetChipSelect(u8g, dev, 0);      
00131       return 1;
00132     case U8G_DEV_MSG_SLEEP_ON:
00133       u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_c12864_sleep_on);    
00134       return 1;
00135     case U8G_DEV_MSG_SLEEP_OFF:
00136       u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_c12864_sleep_off);    
00137       return 1;
00138   }
00139   return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
00140 }
00141 
00142 uint8_t u8g_dev_st7565_nhd_c12864_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00143 {
00144   switch(msg)
00145   {
00146     case U8G_DEV_MSG_INIT:
00147       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
00148       u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_nhd_c12864_init_seq);
00149       break;
00150     case U8G_DEV_MSG_STOP:
00151       break;
00152     case U8G_DEV_MSG_PAGE_NEXT:
00153       {
00154         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00155     
00156         u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_nhd_c12864_data_start);    
00157         u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page)); /* select current page (ST7565R) */
00158         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00159     u8g_WriteSequence(u8g, dev, pb->width, pb->buf); 
00160         u8g_SetChipSelect(u8g, dev, 0);
00161     
00162         u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_nhd_c12864_data_start);    
00163         u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
00164         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00165     u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
00166         u8g_SetChipSelect(u8g, dev, 0);
00167       }
00168       break;
00169     case U8G_DEV_MSG_CONTRAST:
00170       u8g_SetChipSelect(u8g, dev, 1);
00171       u8g_SetAddress(u8g, dev, 0);          /* instruction mode */
00172       u8g_WriteByte(u8g, dev, 0x081);
00173       u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
00174       u8g_SetChipSelect(u8g, dev, 0);      
00175       return 1;
00176     case U8G_DEV_MSG_SLEEP_ON:
00177       u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_c12864_sleep_on);    
00178       return 1;
00179     case U8G_DEV_MSG_SLEEP_OFF:
00180       u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_c12864_sleep_off);    
00181       return 1;
00182   }
00183   return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
00184 }
00185 
00186 U8G_PB_DEV(u8g_dev_st7565_nhd_c12864_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_nhd_c12864_fn, U8G_COM_SW_SPI);
00187 U8G_PB_DEV(u8g_dev_st7565_nhd_c12864_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_nhd_c12864_fn, U8G_COM_HW_SPI);
00188 
00189 
00190 uint8_t u8g_dev_st7565_nhd_c12864_2x_buf[WIDTH*2] U8G_NOCOMMON ; 
00191 u8g_pb_t u8g_dev_st7565_nhd_c12864_2x_pb = { {16, HEIGHT, 0, 0, 0},  WIDTH, u8g_dev_st7565_nhd_c12864_2x_buf}; 
00192 u8g_dev_t u8g_dev_st7565_nhd_c12864_2x_sw_spi = { u8g_dev_st7565_nhd_c12864_2x_fn, &u8g_dev_st7565_nhd_c12864_2x_pb, U8G_COM_SW_SPI };
00193 u8g_dev_t u8g_dev_st7565_nhd_c12864_2x_hw_spi = { u8g_dev_st7565_nhd_c12864_2x_fn, &u8g_dev_st7565_nhd_c12864_2x_pb, U8G_COM_HW_SPI };
00194 
00195