u8g_dev_st7565_64128n.c

00001 /*
00002 
00003   u8g_dev_st7565_64128n.c (Displaytech)
00004 
00005   Universal 8bit Graphics Library
00006   
00007   Copyright (c) 2011, olikraus@gmail.com
00008   All rights reserved.
00009 
00010   Redistribution and use in source and binary forms, with or without modification, 
00011   are permitted provided that the following conditions are met:
00012 
00013   * Redistributions of source code must retain the above copyright notice, this list 
00014     of conditions and the following disclaimer.
00015     
00016   * Redistributions in binary form must reproduce the above copyright notice, this 
00017     list of conditions and the following disclaimer in the documentation and/or other 
00018     materials provided with the distribution.
00019 
00020   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 
00021   CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
00022   INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
00023   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
00024   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
00025   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
00026   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
00027   NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
00028   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
00029   CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
00030   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00031   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00032   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
00033   
00034   
00035 */
00036 
00037 #include "u8g.h"
00038 
00039 #define WIDTH 128
00040 #define HEIGHT 64
00041 #define PAGE_HEIGHT 8
00042 
00043 /* init sequence from https://github.com/adafruit/ST7565-LCD/blob/master/ST7565/ST7565.cpp */
00044 static const uint8_t u8g_dev_st7565_64128n_init_seq[] PROGMEM = {
00045      U8G_ESC_CS(0),            /* disable chip */
00046       U8G_ESC_ADR(0),          /* instruction mode */
00047       U8G_ESC_CS(1),           /* enable chip */
00048       U8G_ESC_RST(15),         /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
00049 
00050       0x0A2,                   /* 0x0a2: LCD bias 1/9 (according to Displaytech 64128N datasheet) */
00051       0x0A0,                   /* Normal ADC Select (according to Displaytech 64128N datasheet) */
00052 
00053       0x0c8,                   /* common output mode: set scan direction normal operation/SHL Select, 0x0c0 --> SHL = 0, normal, 0x0c8 --> SHL = 1 */
00054       0x040,                   /* Display start line for Displaytech 64128N */
00055 
00056       0x028 | 0x04,            /* power control: turn on voltage converter */
00057       U8G_ESC_DLY(50),         /* delay 50 ms */
00058 
00059       0x028 | 0x06,            /* power control: turn on voltage regulator */
00060       U8G_ESC_DLY(50),         /* delay 50 ms */
00061 
00062       0x028 | 0x07,            /* power control: turn on voltage follower */
00063       U8G_ESC_DLY(50),         /* delay 50 ms */
00064 
00065       0x010,                   /* Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N */
00066 
00067       0x0a6,                   /* display normal, bit val 0: LCD pixel off. */
00068 
00069       0x081,                   /* set contrast */
00070       0x01e,                   /* Contrast value. Setting for controlling brightness of Displaytech 64128N */
00071 
00072 
00073       0x0af,                   /* display on */
00074 
00075       U8G_ESC_DLY(100),        /* delay 100 ms */
00076       0x0a5,                   /* display all points, ST7565 */
00077       U8G_ESC_DLY(100),        /* delay 100 ms */
00078       U8G_ESC_DLY(100),        /* delay 100 ms */
00079       0x0a4,                   /* normal display */
00080       U8G_ESC_CS(0),           /* disable chip */
00081       U8G_ESC_END              /* end of sequence */
00082 };
00083 
00084 static const uint8_t u8g_dev_st7565_64128n_data_start[] PROGMEM = {
00085   U8G_ESC_ADR(0),           /* instruction mode */
00086   U8G_ESC_CS(1),            /* enable chip */
00087   0x010,                    /* set upper 4 bit of the col adr to 0x10 */
00088   0x000,                    /* set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N */      
00089   U8G_ESC_END               /* end of sequence */
00090 };
00091 
00092 static const uint8_t u8g_dev_st7565_64128n_sleep_on[] PROGMEM = {
00093   U8G_ESC_ADR(0),           /* instruction mode */
00094   U8G_ESC_CS(1),             /* enable chip */
00095   0x0ac,        /* static indicator off */
00096   0x000,                        /* indicator register set (not sure if this is required) */
00097   0x0ae,        /* display off */      
00098   0x0a5,        /* all points on */      
00099   U8G_ESC_CS(1),             /* disable chip */
00100   U8G_ESC_END                /* end of sequence */
00101 };
00102 
00103 static const uint8_t u8g_dev_st7565_64128n_sleep_off[] PROGMEM = {
00104   U8G_ESC_ADR(0),           /* instruction mode */
00105   U8G_ESC_CS(1),             /* enable chip */
00106   0x0a4,        /* all points off */      
00107   0x0af,        /* display on */      
00108   U8G_ESC_DLY(50),       /* delay 50 ms */
00109   U8G_ESC_CS(1),             /* disable chip */
00110   U8G_ESC_END                /* end of sequence */
00111 };
00112 
00113 uint8_t u8g_dev_st7565_64128n_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00114 {
00115   switch(msg)
00116   {
00117     case U8G_DEV_MSG_INIT:
00118       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
00119       u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_init_seq);
00120       break;
00121     case U8G_DEV_MSG_STOP:
00122       break;
00123     case U8G_DEV_MSG_PAGE_NEXT:
00124       {
00125         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00126         u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_data_start);    
00127         u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (ST7565R) */
00128         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00129         if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
00130           return 0;
00131         u8g_SetChipSelect(u8g, dev, 0);
00132       }
00133       break;
00134     case U8G_DEV_MSG_CONTRAST:
00135       u8g_SetChipSelect(u8g, dev, 1);
00136       u8g_SetAddress(u8g, dev, 0);          /* instruction mode */
00137       u8g_WriteByte(u8g, dev, 0x081);
00138       u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
00139       u8g_SetChipSelect(u8g, dev, 0);      
00140       return 1;
00141     case U8G_DEV_MSG_SLEEP_ON:
00142       u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_sleep_on);    
00143       return 1;
00144     case U8G_DEV_MSG_SLEEP_OFF:
00145       u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_sleep_off);    
00146       return 1;
00147   }
00148   return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
00149 }
00150 
00151 uint8_t u8g_dev_st7565_64128n_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00152 {
00153   switch(msg)
00154   {
00155     case U8G_DEV_MSG_INIT:
00156       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
00157       u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_init_seq);
00158       break;
00159     case U8G_DEV_MSG_STOP:
00160       break;
00161     case U8G_DEV_MSG_PAGE_NEXT:
00162       {
00163         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00164     
00165         u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_data_start);    
00166         u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page)); /* select current page (ST7565R) */
00167         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00168     u8g_WriteSequence(u8g, dev, pb->width, pb->buf); 
00169         u8g_SetChipSelect(u8g, dev, 0);
00170     
00171         u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_data_start);    
00172         u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
00173         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00174     u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width); 
00175         u8g_SetChipSelect(u8g, dev, 0);
00176       }
00177       break;
00178     case U8G_DEV_MSG_CONTRAST:
00179       u8g_SetChipSelect(u8g, dev, 1);
00180       u8g_SetAddress(u8g, dev, 0);          /* instruction mode */
00181       u8g_WriteByte(u8g, dev, 0x081);
00182       u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
00183       u8g_SetChipSelect(u8g, dev, 0);      
00184       return 1;
00185     case U8G_DEV_MSG_SLEEP_ON:
00186       u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_sleep_on);    
00187       return 1;
00188     case U8G_DEV_MSG_SLEEP_OFF:
00189       u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_sleep_off);    
00190       return 1;
00191   }
00192   return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
00193 }
00194 
00195 U8G_PB_DEV(u8g_dev_st7565_64128n_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_64128n_fn, U8G_COM_SW_SPI);
00196 U8G_PB_DEV(u8g_dev_st7565_64128n_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_64128n_fn, U8G_COM_HW_SPI);
00197 U8G_PB_DEV(u8g_dev_st7565_64128n_parallel, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_64128n_fn, U8G_COM_PARALLEL);
00198 
00199 uint8_t u8g_dev_st7565_64128n_2x_buf[WIDTH*2] U8G_NOCOMMON ; 
00200 u8g_pb_t u8g_dev_st7565_64128n_2x_pb = { {16, HEIGHT, 0, 0, 0},  WIDTH, u8g_dev_st7565_64128n_2x_buf}; 
00201 u8g_dev_t u8g_dev_st7565_64128n_2x_sw_spi = { u8g_dev_st7565_64128n_2x_fn, &u8g_dev_st7565_64128n_2x_pb, U8G_COM_SW_SPI };
00202 u8g_dev_t u8g_dev_st7565_64128n_2x_hw_spi = { u8g_dev_st7565_64128n_2x_fn, &u8g_dev_st7565_64128n_2x_pb, U8G_COM_HW_SPI };
00203 u8g_dev_t u8g_dev_st7565_64128n_2x_hw_parallel = { u8g_dev_st7565_64128n_2x_fn, &u8g_dev_st7565_64128n_2x_pb, U8G_COM_PARALLEL };
00204