u8g_dev_ssd1351_128x128.c

00001 /*
00002 
00003   u8g_dev_ssd1351_128x128.c
00004 
00005   Universal 8bit Graphics Library
00006   
00007   Copyright (c) 2013, jamjardavies@gmail.com
00008   Copyright (c) 2013, olikraus@gmail.com
00009   All rights reserved.
00010 
00011   Redistribution and use in source and binary forms, with or without modification, 
00012   are permitted provided that the following conditions are met:
00013 
00014   * Redistributions of source code must retain the above copyright notice, this list 
00015     of conditions and the following disclaimer.
00016     
00017   * Redistributions in binary form must reproduce the above copyright notice, this 
00018     list of conditions and the following disclaimer in the documentation and/or other 
00019     materials provided with the distribution.
00020 
00021   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 
00022   CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
00023   INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
00024   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
00025   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
00026   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
00027   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
00028   NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
00029   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
00030   CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
00031   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00032   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00033   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
00034   
00035   History:
00036   Initial version   20 May 2013 jamjardavies@gmail.com  
00037   indexed device    22 May 2013 olikraus@gmail.com
00038   
00039 */
00040 
00041 #include "u8g.h"
00042 
00043 #define WIDTH       128
00044 #define HEIGHT      128
00045 #define PAGE_HEIGHT 8
00046 
00047 static const uint8_t u8g_dev_ssd1351_128x128_init_seq[] PROGMEM = {
00048     U8G_ESC_CS(0),                  /* disable chip */
00049     U8G_ESC_DLY(50),
00050     U8G_ESC_ADR(0),                 /* instruction mode */
00051     U8G_ESC_RST(1),                 /* do reset low pulse with (1*16)+2 milliseconds */
00052     U8G_ESC_CS(1),                  /* enable chip */
00053     U8G_ESC_DLY(50),
00054 
00055     0xfd,                           /* Command Lock */
00056     U8G_ESC_ADR(1),
00057     0x12,                       
00058 
00059     U8G_ESC_ADR(0),                 /* instruction mode */
00060     0xfd,
00061     U8G_ESC_ADR(1),
00062     0xb1,                           /* Command Lock */
00063 
00064     U8G_ESC_ADR(0),                 /* instruction mode */
00065     0xae,                           /* Set Display Off */
00066 
00067     U8G_ESC_ADR(0),                 /* instruction mode */
00068     0xb3,
00069     U8G_ESC_ADR(1),
00070     0xf1,                           /* Front Clock Div */
00071 
00072     U8G_ESC_ADR(0),                 /* instruction mode */
00073     0xca,
00074     U8G_ESC_ADR(1),
00075     0x7f,                           /* Set Multiplex Ratio */
00076 
00077     U8G_ESC_ADR(0),                 /* instruction mode */
00078     0xa0,
00079     U8G_ESC_ADR(1),
00080     0xb4,                           /* Set Colour Depth */
00081 
00082     U8G_ESC_ADR(0),                 /* instruction mode */
00083     0x15,
00084     U8G_ESC_ADR(1),
00085     0x00, 0x7f,                     /* Set Column Address */
00086 
00087     U8G_ESC_ADR(0),                 /* instruction mode */
00088     0x75,
00089     U8G_ESC_ADR(1),
00090     0x00, 0x7f,                     /* Set Row Address */
00091 
00092     U8G_ESC_ADR(0),                 /* instruction mode */
00093     0xa1,
00094     U8G_ESC_ADR(1),
00095     0x00,                           /* Set Display Start Line */
00096 
00097     U8G_ESC_ADR(0),                 /* instruction mode */
00098     0xa2,
00099     U8G_ESC_ADR(1),
00100     0x00,                           /* Set Display Offset */
00101 
00102     U8G_ESC_ADR(0),                 /* instruction mode */
00103     0xb5,
00104     U8G_ESC_ADR(1),
00105     0x00,                           /* Set GPIO */
00106 
00107     U8G_ESC_ADR(0),                 /* instruction mode */
00108     0xab,
00109     U8G_ESC_ADR(1),
00110     0x01,                           /* Set Function Selection */
00111 
00112     U8G_ESC_ADR(0),                 /* instruction mode */
00113     0xb1,
00114     U8G_ESC_ADR(1),
00115     0x32,                           /* Set Phase Length */
00116 
00117     U8G_ESC_ADR(0),                 /* instruction mode */
00118     0xb4,
00119     U8G_ESC_ADR(1),
00120     0xa0, 0xb5, 0x55,               /* Set Segment Low Voltage */
00121 
00122     U8G_ESC_ADR(0),                 /* instruction mode */
00123     0xbb,
00124     U8G_ESC_ADR(1),
00125     0x17,                           /* Set Precharge Voltage */
00126 
00127     U8G_ESC_ADR(0),                 /* instruction mode */
00128     0xbe,
00129     U8G_ESC_ADR(1),
00130     0x05,                           /* Set VComH Voltage */
00131 
00132     U8G_ESC_ADR(0),                 /* instruction mode */
00133     0xc1,
00134     U8G_ESC_ADR(1),
00135     0xc8, 0x80, 0xc8,               /* Set Contrast */
00136 
00137     U8G_ESC_ADR(0),                 /* instruction mode */
00138     0xc7,
00139     U8G_ESC_ADR(1),
00140     0x0f,                           /* Set Master Contrast */
00141 
00142     U8G_ESC_ADR(0),                 /* instruction mode */
00143     0xb6,
00144     U8G_ESC_ADR(1),
00145     0x01,                           /* Set Second Precharge Period */
00146 
00147     U8G_ESC_ADR(0),                 /* instruction mode */
00148     0xa6,                           /* Set Display Mode Reset */
00149 
00150 
00151     U8G_ESC_ADR(0),                 /* instruction mode */
00152     0xb8,                           /* Set CMD Grayscale Lookup */
00153     U8G_ESC_ADR(1),
00154     0x05,
00155     0x06,
00156     0x07,
00157     0x08,
00158     0x09,
00159     0x0a,
00160     0x0b,
00161     0x0c,
00162     0x0D,
00163     0x0E,
00164     0x0F,
00165     0x10,
00166     0x11,
00167     0x12,
00168     0x13,
00169     0x14,
00170     0x15,
00171     0x16,
00172     0x18,
00173     0x1a,
00174     0x1b,
00175     0x1C,
00176     0x1D,
00177     0x1F,
00178     0x21,
00179     0x23,
00180     0x25,
00181     0x27,
00182     0x2A,
00183     0x2D,
00184     0x30,
00185     0x33,
00186     0x36,
00187     0x39,
00188     0x3C,
00189     0x3F,
00190     0x42,
00191     0x45,
00192     0x48,
00193     0x4C,
00194     0x50,
00195     0x54,
00196     0x58,
00197     0x5C,
00198     0x60,
00199     0x64,
00200     0x68,
00201     0x6C,
00202     0x70,
00203     0x74,
00204     0x78,
00205     0x7D,
00206     0x82,
00207     0x87,
00208     0x8C,
00209     0x91,
00210     0x96,
00211     0x9B,
00212     0xA0,
00213     0xA5,
00214     0xAA,
00215     0xAF,
00216     0xB4,
00217 
00218     U8G_ESC_ADR(0),
00219     0xaf,                           /* Set Display On */
00220     0x5c,
00221     U8G_ESC_DLY(50),
00222     U8G_ESC_CS(0),                  /* disable chip */
00223     U8G_ESC_ADR(1),
00224     U8G_ESC_END                     /* end of sequence */
00225 };
00226 
00227 
00228 /* set gpio to high */
00229 static const uint8_t u8g_dev_ssd1351_128x128gh_init_seq[] PROGMEM = {
00230     U8G_ESC_CS(0),                  /* disable chip */
00231     U8G_ESC_DLY(50),
00232     U8G_ESC_ADR(0),                 /* instruction mode */
00233     U8G_ESC_RST(1),                 /* do reset low pulse with (1*16)+2 milliseconds */
00234     U8G_ESC_CS(1),                  /* enable chip */
00235     U8G_ESC_DLY(50),
00236 
00237     0xfd,                           /* Command Lock */
00238     U8G_ESC_ADR(1),
00239     0x12,                       
00240 
00241     U8G_ESC_ADR(0),                 /* instruction mode */
00242     0xfd,
00243     U8G_ESC_ADR(1),
00244     0xb1,                           /* Command Lock */
00245 
00246     U8G_ESC_ADR(0),                 /* instruction mode */
00247     0xae,                           /* Set Display Off */
00248 
00249     U8G_ESC_ADR(0),                 /* instruction mode */
00250     0xb3,
00251     U8G_ESC_ADR(1),
00252     0xf1,                           /* Front Clock Div */
00253 
00254     U8G_ESC_ADR(0),                 /* instruction mode */
00255     0xca,
00256     U8G_ESC_ADR(1),
00257     0x7f,                           /* Set Multiplex Ratio */
00258 
00259     U8G_ESC_ADR(0),                 /* instruction mode */
00260     0xa0,
00261     U8G_ESC_ADR(1),
00262     0xb4,                           /* Set Colour Depth */
00263 
00264     U8G_ESC_ADR(0),                 /* instruction mode */
00265     0x15,
00266     U8G_ESC_ADR(1),
00267     0x00, 0x7f,                     /* Set Column Address */
00268 
00269     U8G_ESC_ADR(0),                 /* instruction mode */
00270     0x75,
00271     U8G_ESC_ADR(1),
00272     0x00, 0x7f,                     /* Set Row Address */
00273 
00274     U8G_ESC_ADR(0),                 /* instruction mode */
00275     0xa1,
00276     U8G_ESC_ADR(1),
00277     0x00,                           /* Set Display Start Line */
00278 
00279     U8G_ESC_ADR(0),                 /* instruction mode */
00280     0xa2,
00281     U8G_ESC_ADR(1),
00282     0x00,                           /* Set Display Offset */
00283 
00284     U8G_ESC_ADR(0),                 /* instruction mode */
00285     0xb5,
00286     U8G_ESC_ADR(1),
00287     0x03,                           /* Set GPIO to High Level */
00288 
00289     U8G_ESC_ADR(0),                 /* instruction mode */
00290     0xab,
00291     U8G_ESC_ADR(1),
00292     0x01,                           /* Set Function Selection */
00293 
00294     U8G_ESC_ADR(0),                 /* instruction mode */
00295     0xb1,
00296     U8G_ESC_ADR(1),
00297     0x32,                           /* Set Phase Length */
00298 
00299     U8G_ESC_ADR(0),                 /* instruction mode */
00300     0xb4,
00301     U8G_ESC_ADR(1),
00302     0xa0, 0xb5, 0x55,               /* Set Segment Low Voltage */
00303 
00304     U8G_ESC_ADR(0),                 /* instruction mode */
00305     0xbb,
00306     U8G_ESC_ADR(1),
00307     0x17,                           /* Set Precharge Voltage */
00308 
00309     U8G_ESC_ADR(0),                 /* instruction mode */
00310     0xbe,
00311     U8G_ESC_ADR(1),
00312     0x05,                           /* Set VComH Voltage */
00313 
00314     U8G_ESC_ADR(0),                 /* instruction mode */
00315     0xc1,
00316     U8G_ESC_ADR(1),
00317     0xc8, 0x80, 0xc8,               /* Set Contrast */
00318 
00319     U8G_ESC_ADR(0),                 /* instruction mode */
00320     0xc7,
00321     U8G_ESC_ADR(1),
00322     0x0f,                           /* Set Master Contrast */
00323 
00324     U8G_ESC_ADR(0),                 /* instruction mode */
00325     0xb6,
00326     U8G_ESC_ADR(1),
00327     0x01,                           /* Set Second Precharge Period */
00328 
00329     U8G_ESC_ADR(0),                 /* instruction mode */
00330     0xa6,                           /* Set Display Mode Reset */
00331 
00332 
00333     U8G_ESC_ADR(0),                 /* instruction mode */
00334     0xb8,                           /* Set CMD Grayscale Lookup */
00335     U8G_ESC_ADR(1),
00336     0x05,
00337     0x06,
00338     0x07,
00339     0x08,
00340     0x09,
00341     0x0a,
00342     0x0b,
00343     0x0c,
00344     0x0D,
00345     0x0E,
00346     0x0F,
00347     0x10,
00348     0x11,
00349     0x12,
00350     0x13,
00351     0x14,
00352     0x15,
00353     0x16,
00354     0x18,
00355     0x1a,
00356     0x1b,
00357     0x1C,
00358     0x1D,
00359     0x1F,
00360     0x21,
00361     0x23,
00362     0x25,
00363     0x27,
00364     0x2A,
00365     0x2D,
00366     0x30,
00367     0x33,
00368     0x36,
00369     0x39,
00370     0x3C,
00371     0x3F,
00372     0x42,
00373     0x45,
00374     0x48,
00375     0x4C,
00376     0x50,
00377     0x54,
00378     0x58,
00379     0x5C,
00380     0x60,
00381     0x64,
00382     0x68,
00383     0x6C,
00384     0x70,
00385     0x74,
00386     0x78,
00387     0x7D,
00388     0x82,
00389     0x87,
00390     0x8C,
00391     0x91,
00392     0x96,
00393     0x9B,
00394     0xA0,
00395     0xA5,
00396     0xAA,
00397     0xAF,
00398     0xB4,
00399 
00400     U8G_ESC_ADR(0),
00401     0xaf,                           /* Set Display On */
00402     0x5c,
00403     U8G_ESC_DLY(50),
00404     U8G_ESC_CS(0),                  /* disable chip */
00405     U8G_ESC_ADR(1),
00406     U8G_ESC_END                     /* end of sequence */
00407 };
00408 
00409 #define u8g_dev_ssd1351_128x128_init_seq u8g_dev_ssd1351_128x128_init_seq
00410 
00411 static const uint8_t u8g_dev_ssd1351_128x128_column_seq[] PROGMEM = {
00412     U8G_ESC_CS(1),
00413     U8G_ESC_ADR(0), 0x15,
00414     U8G_ESC_ADR(1), 0x00, 0x7f,
00415     U8G_ESC_ADR(0), 0x75,
00416     U8G_ESC_ADR(1), 0x00, 0x7f,
00417     U8G_ESC_ADR(0), 0x5c,
00418     U8G_ESC_ADR(1),
00419     U8G_ESC_CS(0),
00420     U8G_ESC_END
00421 };
00422 
00423 #define RGB332_STREAM_BYTES 8
00424 static uint8_t u8g_ssd1351_stream_bytes[RGB332_STREAM_BYTES*3];
00425 
00426 void u8g_ssd1351_to_stream(uint8_t *ptr)
00427 {
00428   uint8_t cnt = RGB332_STREAM_BYTES;
00429   uint8_t val;
00430   uint8_t *dest = u8g_ssd1351_stream_bytes;
00431   for( cnt = 0; cnt < RGB332_STREAM_BYTES; cnt++ )
00432   {
00433       val = *ptr++;
00434       *dest++ = ((val & 0xe0) >> 2);
00435       *dest++ = ((val & 0x1c) << 1);
00436       *dest++ = ((val & 0x03) << 4);
00437   } 
00438 }
00439 
00440 
00441 #ifdef OBSOLETE
00442 // Convert the internal RGB 332 to R
00443 static uint8_t u8g_ssd1351_get_r(uint8_t colour)
00444 {
00445     //return ((colour & 0xe0) >> 5) * 9;
00446     //return ((colour & 0xe0) >> 5) * 8;
00447     return ((colour & 0xe0) >> 2) ;
00448 }
00449 
00450 // Convert the internal RGB 332 to G
00451 static uint8_t u8g_ssd1351_get_g(uint8_t colour)
00452 {
00453     //return ((colour & 0x1c) >> 2) * 9;
00454     //return ((colour & 0x1c) >> 2) * 8;
00455     return ((colour & 0x1c) << 1);
00456 }
00457 
00458 // Convert the internal RGB 332 to B
00459 static uint8_t u8g_ssd1351_get_b(uint8_t colour)
00460 {
00461     //return (colour & 0x03) * 21;
00462     return (colour & 0x03) * 16;
00463 }
00464 #endif
00465 
00466 
00467 uint8_t u8g_dev_ssd1351_128x128_332_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00468 {
00469 //  u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00470 
00471     switch(msg)
00472     {
00473     case U8G_DEV_MSG_INIT:
00474         u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
00475         u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_init_seq);
00476         break;
00477 
00478     case U8G_DEV_MSG_STOP:
00479         break;
00480 
00481     case U8G_DEV_MSG_PAGE_FIRST:
00482         u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
00483         break;
00484 
00485     case U8G_DEV_MSG_PAGE_NEXT:
00486         {
00487             u8g_uint_t x;
00488             uint8_t page_height;
00489             uint8_t i;
00490             u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00491             uint8_t *ptr = pb->buf;
00492 
00493             u8g_SetChipSelect(u8g, dev, 1);
00494 
00495             page_height = pb->p.page_y1;
00496             page_height -= pb->p.page_y0;
00497             page_height++;
00498             for( i = 0; i < page_height; i++ )
00499             {
00500               
00501               for (x = 0; x < pb->width; x+=RGB332_STREAM_BYTES)
00502               {
00503                 u8g_ssd1351_to_stream(ptr);
00504                 u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
00505                 ptr += RGB332_STREAM_BYTES;
00506               }
00507             }
00508             u8g_SetChipSelect(u8g, dev, 0);
00509         }
00510 
00511         break;
00512     case U8G_DEV_MSG_GET_MODE:
00513       return U8G_MODE_R3G3B2;
00514     }
00515 
00516     return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
00517 }
00518 
00519 uint8_t u8g_dev_ssd1351_128x128gh_332_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00520 {
00521 //  u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00522 
00523     switch(msg)
00524     {
00525     case U8G_DEV_MSG_INIT:
00526         u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
00527         u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128gh_init_seq);
00528         break;
00529 
00530     case U8G_DEV_MSG_STOP:
00531         break;
00532 
00533     case U8G_DEV_MSG_PAGE_FIRST:
00534         u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
00535         break;
00536 
00537     case U8G_DEV_MSG_PAGE_NEXT:
00538         {
00539             u8g_uint_t x;
00540             uint8_t page_height;
00541             uint8_t i;
00542             u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00543             uint8_t *ptr = pb->buf;
00544 
00545             u8g_SetChipSelect(u8g, dev, 1);
00546 
00547             page_height = pb->p.page_y1;
00548             page_height -= pb->p.page_y0;
00549             page_height++;
00550             for( i = 0; i < page_height; i++ )
00551             {
00552               
00553               for (x = 0; x < pb->width; x+=RGB332_STREAM_BYTES)
00554               {
00555                 u8g_ssd1351_to_stream(ptr);
00556                 u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
00557                 ptr += RGB332_STREAM_BYTES;
00558               }
00559             }
00560             u8g_SetChipSelect(u8g, dev, 0);
00561         }
00562 
00563         break;
00564     case U8G_DEV_MSG_GET_MODE:
00565       return U8G_MODE_R3G3B2;
00566     }
00567 
00568     return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
00569 }
00570 
00571 static uint8_t u8g_dev_ssd1351_128x128_r[256];
00572 static uint8_t u8g_dev_ssd1351_128x128_g[256];
00573 static uint8_t u8g_dev_ssd1351_128x128_b[256];
00574 
00575 uint8_t u8g_dev_ssd1351_128x128_idx_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00576 {
00577 //  u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00578 
00579     switch(msg)
00580     {
00581     case U8G_DEV_MSG_INIT:
00582         u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
00583         u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_init_seq);
00584         break;
00585 
00586     case U8G_DEV_MSG_STOP:
00587         break;
00588     
00589     case U8G_DEV_MSG_SET_COLOR_ENTRY:
00590           u8g_dev_ssd1351_128x128_r[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->r;
00591           u8g_dev_ssd1351_128x128_g[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->g;
00592           u8g_dev_ssd1351_128x128_b[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->b;
00593           break;
00594     
00595     case U8G_DEV_MSG_PAGE_FIRST:
00596         u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
00597         break;
00598 
00599     case U8G_DEV_MSG_PAGE_NEXT:
00600         {
00601             int x;
00602             u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00603             uint8_t *ptr = pb->buf;
00604 
00605             u8g_SetChipSelect(u8g, dev, 1);
00606 
00607             for (x = 0; x < pb->width; x++)
00608             {
00609                 u8g_WriteByte(u8g, dev, u8g_dev_ssd1351_128x128_r[(*ptr)>>2]);
00610                 u8g_WriteByte(u8g, dev, u8g_dev_ssd1351_128x128_g[(*ptr)>>2]);
00611                 u8g_WriteByte(u8g, dev, u8g_dev_ssd1351_128x128_b[(*ptr)>>2]);
00612 
00613                 ptr++;
00614             }
00615 
00616             u8g_SetChipSelect(u8g, dev, 0);
00617         }
00618 
00619         break;
00620     case U8G_DEV_MSG_GET_MODE:
00621       return U8G_MODE_INDEX;
00622     }
00623 
00624     return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
00625 }
00626 
00627 void u8g_ssd1351_hicolor_to_stream(uint8_t *ptr)
00628 {
00629   register uint8_t cnt = RGB332_STREAM_BYTES;
00630   register uint8_t low, high, r, g, b;
00631   uint8_t *dest = u8g_ssd1351_stream_bytes;
00632   for( cnt = 0; cnt < RGB332_STREAM_BYTES; cnt++ )
00633   {
00634     low = *ptr++;
00635     high = *ptr++;
00636     
00637     r = high & ~7;
00638     r >>= 2;
00639     b = low & 31;
00640     b <<= 1;
00641     g = high & 7;
00642     g <<= 3;
00643     g |= (low>>5)&7;
00644     
00645     *dest++ = r;
00646     *dest++ = g;
00647     *dest++ = b;
00648   } 
00649 }
00650 
00651 
00652 uint8_t u8g_dev_ssd1351_128x128_hicolor_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00653 {
00654   switch(msg)
00655   {
00656     case U8G_DEV_MSG_INIT:
00657       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
00658       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_init_seq);
00659       break;
00660     case U8G_DEV_MSG_STOP:
00661       break;
00662     case U8G_DEV_MSG_PAGE_FIRST:
00663       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
00664       break;
00665     case U8G_DEV_MSG_PAGE_NEXT:
00666       {
00667         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00668         uint8_t i, j;
00669         uint8_t page_height;
00670     uint8_t *ptr = pb->buf;
00671 
00672     u8g_SetChipSelect(u8g, dev, 1);
00673 
00674         page_height = pb->p.page_y1;
00675         page_height -= pb->p.page_y0;
00676         page_height++;
00677         for( j = 0; j < page_height; j++ )
00678         {
00679         for (i = 0; i < pb->width; i+=RGB332_STREAM_BYTES)
00680         {
00681           u8g_ssd1351_hicolor_to_stream(ptr);
00682           u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
00683           ptr += RGB332_STREAM_BYTES*2;
00684         }
00685       
00686         }
00687 
00688     u8g_SetChipSelect(u8g, dev, 0);
00689     
00690       }
00691       break;    /* continue to base fn */
00692     case U8G_DEV_MSG_GET_MODE:
00693      return U8G_MODE_HICOLOR;
00694   }
00695   return u8g_dev_pbxh16_base_fn(u8g, dev, msg, arg);
00696 }
00697 
00698 uint8_t u8g_dev_ssd1351_128x128gh_hicolor_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00699 {
00700   switch(msg)
00701   {
00702     case U8G_DEV_MSG_INIT:
00703       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
00704       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128gh_init_seq);
00705       break;
00706     case U8G_DEV_MSG_STOP:
00707       break;
00708     case U8G_DEV_MSG_PAGE_FIRST:
00709       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
00710       break;
00711     case U8G_DEV_MSG_PAGE_NEXT:
00712       {
00713         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00714         uint8_t i, j;
00715         uint8_t page_height;
00716     uint8_t *ptr = pb->buf;
00717 
00718     u8g_SetChipSelect(u8g, dev, 1);
00719 
00720         page_height = pb->p.page_y1;
00721         page_height -= pb->p.page_y0;
00722         page_height++;
00723         for( j = 0; j < page_height; j++ )
00724         {
00725         for (i = 0; i < pb->width; i+=RGB332_STREAM_BYTES)
00726         {
00727           u8g_ssd1351_hicolor_to_stream(ptr);
00728           u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
00729           ptr += RGB332_STREAM_BYTES*2;
00730         }
00731       
00732         }
00733 
00734     u8g_SetChipSelect(u8g, dev, 0);
00735     
00736       }
00737       break;    /* continue to base fn */
00738     case U8G_DEV_MSG_GET_MODE:
00739      return U8G_MODE_HICOLOR;
00740   }
00741   return u8g_dev_pbxh16_base_fn(u8g, dev, msg, arg);
00742 }
00743 
00744 
00745 uint8_t u8g_dev_ssd1351_128x128_byte_buf[WIDTH*PAGE_HEIGHT] U8G_NOCOMMON ; 
00746 
00747 u8g_pb_t u8g_dev_ssd1351_128x128_byte_pb = { {PAGE_HEIGHT, HEIGHT, 0, 0, 0},  WIDTH, u8g_dev_ssd1351_128x128_byte_buf};  
00748 u8g_dev_t u8g_dev_ssd1351_128x128_332_sw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_SW_SPI };
00749 u8g_dev_t u8g_dev_ssd1351_128x128_332_hw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_HW_SPI };
00750 u8g_dev_t u8g_dev_ssd1351_128x128gh_332_sw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_SW_SPI };
00751 u8g_dev_t u8g_dev_ssd1351_128x128gh_332_hw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_HW_SPI };
00752 
00753 //u8g_dev_t u8g_dev_ssd1351_128x128_idx_sw_spi = { u8g_dev_ssd1351_128x128_idx_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_SW_SPI };
00754 //u8g_dev_t u8g_dev_ssd1351_128x128_idx_hw_spi = { u8g_dev_ssd1351_128x128_idx_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_HW_SPI };
00755 
00756 
00757 /* only half of the height, because two bytes are needed for one pixel */
00758 u8g_pb_t u8g_dev_ssd1351_128x128_hicolor_byte_pb = { {PAGE_HEIGHT/2, HEIGHT, 0, 0, 0},  WIDTH, u8g_dev_ssd1351_128x128_byte_buf}; 
00759 u8g_dev_t u8g_dev_ssd1351_128x128_hicolor_sw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_SW_SPI };
00760 u8g_dev_t u8g_dev_ssd1351_128x128_hicolor_hw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_HW_SPI };
00761 u8g_dev_t u8g_dev_ssd1351_128x128gh_hicolor_sw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_SW_SPI };
00762 u8g_dev_t u8g_dev_ssd1351_128x128gh_hicolor_hw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_HW_SPI };
00763 
00764 
00765 uint8_t u8g_dev_ssd1351_128x128_4x_byte_buf[WIDTH*PAGE_HEIGHT*4] U8G_NOCOMMON ; 
00766 
00767 u8g_pb_t u8g_dev_ssd1351_128x128_4x_332_byte_pb = { {PAGE_HEIGHT*4, HEIGHT, 0, 0, 0},  WIDTH, u8g_dev_ssd1351_128x128_4x_byte_buf};  
00768 u8g_dev_t u8g_dev_ssd1351_128x128_4x_332_sw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_SW_SPI };
00769 u8g_dev_t u8g_dev_ssd1351_128x128_4x_332_hw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_HW_SPI };
00770 u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_332_sw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_SW_SPI };
00771 u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_332_hw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_HW_SPI };
00772 
00773 u8g_pb_t u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb = { {PAGE_HEIGHT/2*4, HEIGHT, 0, 0, 0},  WIDTH, u8g_dev_ssd1351_128x128_4x_byte_buf}; 
00774 u8g_dev_t u8g_dev_ssd1351_128x128_4x_hicolor_sw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_SW_SPI };
00775 u8g_dev_t u8g_dev_ssd1351_128x128_4x_hicolor_hw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_HW_SPI };
00776 u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_hicolor_sw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_SW_SPI };
00777 u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_hicolor_hw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_HW_SPI };
00778 
00779 
00780 /*
00781 U8G_PB_DEV(u8g_dev_ssd1351_128x128_332_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_332_fn, U8G_COM_SW_SPI);
00782 U8G_PB_DEV(u8g_dev_ssd1351_128x128_332_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_332_fn, U8G_COM_HW_SPI);
00783 
00784 U8G_PB_DEV(u8g_dev_ssd1351_128x128_idx_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_idx_fn, U8G_COM_SW_SPI);
00785 U8G_PB_DEV(u8g_dev_ssd1351_128x128_idx_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_idx_fn, U8G_COM_HW_SPI);
00786 */
00787 
00788