u8g_dev_ssd1325_nhd27oled_gr.c

00001 /*
00002 
00003   u8g_dev_ssd1325_nhd27oled_gr.c
00004   
00005   2-Bit (gray level) Driver for SSD1325 Controller (OLED Display)
00006   Tested with NHD-2.7-12864UCY3
00007 
00008   Universal 8bit Graphics Library
00009   
00010   Copyright (c) 2011, olikraus@gmail.com
00011   All rights reserved.
00012 
00013   Redistribution and use in source and binary forms, with or without modification, 
00014   are permitted provided that the following conditions are met:
00015 
00016   * Redistributions of source code must retain the above copyright notice, this list 
00017     of conditions and the following disclaimer.
00018     
00019   * Redistributions in binary form must reproduce the above copyright notice, this 
00020     list of conditions and the following disclaimer in the documentation and/or other 
00021     materials provided with the distribution.
00022 
00023   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 
00024   CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
00025   INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
00026   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
00027   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
00028   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
00029   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
00030   NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
00031   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
00032   CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
00033   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00034   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00035   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
00036   
00037   SSD130x       Monochrom OLED Controller
00038   SSD131x       Character OLED Controller
00039   SSD132x       Graylevel OLED Controller
00040   SSD1331       Color OLED Controller       
00041 
00042 */
00043 
00044 #ifdef OBSOLETE_CODE
00045 
00046 #include "u8g.h"
00047 
00048 #define WIDTH 128
00049 #define HEIGHT 64
00050 
00051 /* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */
00052 static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq[] PROGMEM = {
00053   U8G_ESC_DLY(10),              /* delay 10 ms */
00054   U8G_ESC_CS(0),                 /* disable chip */
00055   U8G_ESC_ADR(0),               /* instruction mode */
00056   U8G_ESC_RST(1),               /* do reset low pulse with (1*16)+2 milliseconds */
00057   U8G_ESC_CS(1),                /* enable chip */
00058   0x0ae,                                /* display off, sleep mode */
00059   0x0b3, 0x091,                    /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
00060   0x0a8, 0x03f,                     /* multiplex ratio: 0x03f * 1/64 duty */
00061   0x0a2, 0x04c,                     /* display offset, shift mapping ram counter */
00062   0x0a1, 0x000,                     /* display start line */
00063   0x0ad, 0x002,                     /* master configuration: disable embedded DC-DC, enable internal VCOMH */
00064   0x0a0, 0x056,                     /* remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
00065   0x086,                                /* full current range (0x084, 0x085, 0x086) */
00066   0x0b8,                                /* set gray scale table */
00067       //0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
00068       0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x077, 0x077,            // 4L mode uses 0, 2, 4, 7
00069   0x081, 0x070,                    /* contrast, brightness, 0..128, Newhaven: 0x040 */
00070   0x0b2, 0x051,                    /* frame frequency (row period) */
00071   0x0b1, 0x055,                    /* phase length */
00072   0x0bc, 0x010,                    /* pre-charge voltage level */
00073   0x0b4, 0x002,                    /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
00074   0x0b0, 0x028,                    /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
00075   0x0be, 0x01c,                     /* VCOMH voltage */
00076   0x0bf, 0x002|0x00d,           /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
00077   0x0a5,                                 /* all pixel on */
00078   0x0af,                                  /* display on */
00079   U8G_ESC_DLY(100),             /* delay 100 ms */
00080   U8G_ESC_DLY(100),             /* delay 100 ms */
00081   0x0a4,                                 /* normal display mode */
00082   U8G_ESC_CS(0),             /* disable chip */
00083   U8G_ESC_END                /* end of sequence */
00084 };
00085 
00086 static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq[] PROGMEM = {
00087   U8G_ESC_ADR(0),               /* instruction mode */
00088   U8G_ESC_CS(1),                /* enable chip */
00089   0x015,       /* column address... */
00090   0x000,       /* start at column 0 */
00091   0x03f,       /* end at column 63 (which is y == 127), because there are two pixel in one column */
00092   0x075,       /* row address... */
00093   U8G_ESC_END                /* end of sequence */
00094 };
00095 
00096 
00097 static void u8g_dev_ssd1325_2bit_prepare_page(u8g_t *u8g, u8g_dev_t *dev)
00098 {
00099   uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
00100   
00101   u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq);
00102   
00103   page <<= 2;
00104   u8g_WriteByte(u8g, dev, page);       /* start at the selected page */
00105   page += 3;
00106   u8g_WriteByte(u8g, dev, page);       /* end within the selected page */  
00107   
00108   u8g_SetAddress(u8g, dev, 1);          /* data mode */
00109 }
00110 
00111 static void u8g_dev_ssd1325_2bit_2x_prepare_page(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
00112 {
00113   uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
00114   
00115   u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq);
00116   
00117   page <<= 1;
00118   page += is_odd;
00119   
00120   
00121   page <<= 2;
00122   u8g_WriteByte(u8g, dev, page);       /* start at the selected page */
00123   page += 3;
00124   u8g_WriteByte(u8g, dev, page);       /* end within the selected page */  
00125   
00126   u8g_SetAddress(u8g, dev, 1);          /* data mode */
00127 }
00128 
00129 /* assumes row autoincrement and activated nibble remap */
00130 static  void u8g_dev_ssd1325_2bit_write_4_pixel(u8g_t *u8g, u8g_dev_t *dev, uint8_t left, uint8_t right)
00131 {
00132   uint8_t d, tmp, cnt;
00133   cnt = 4;
00134   do    
00135   {
00136     d = left;
00137     d &= 3;
00138     d <<= 4;    
00139     tmp = right;    
00140     tmp &= 3;
00141     d |= tmp;
00142     d <<= 2;
00143     u8g_WriteByte(u8g, dev, d);
00144     left >>= 2;
00145     right >>= 2;
00146     cnt--;
00147   }while ( cnt > 0 );
00148 }
00149 
00150 static void u8g_dev_ssd1325_2bit_write_buffer(u8g_t *u8g, u8g_dev_t *dev)
00151 {
00152   uint8_t cnt, left, right;
00153   uint8_t *ptr;
00154   u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00155   
00156   cnt = pb->width;
00157   cnt >>= 1;
00158   ptr = pb->buf;
00159   do
00160   {
00161     left = *ptr++;
00162     right = *ptr++;
00163     u8g_dev_ssd1325_2bit_write_4_pixel(u8g, dev, left, right);
00164     cnt--;
00165   } while( cnt > 0 );
00166 }
00167 
00168 static void u8g_dev_ssd1325_2bit_2x_write_buffer(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
00169 {
00170   uint8_t cnt, left, right;
00171   uint8_t *ptr;
00172   u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00173   
00174   ptr = pb->buf;
00175   cnt = pb->width;
00176   if ( is_odd )
00177     ptr += cnt;
00178   cnt >>= 1;
00179   do
00180   {
00181     left = *ptr++;
00182     right = *ptr++;
00183     u8g_dev_ssd1325_2bit_write_4_pixel(u8g, dev, left, right);
00184     cnt--;
00185   } while( cnt > 0 );
00186 }
00187 
00188 static uint8_t u8g_dev_ssd1325_nhd27oled_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00189 {
00190   switch(msg)
00191   {
00192     case U8G_DEV_MSG_INIT:
00193       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
00194       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
00195       break;
00196     case U8G_DEV_MSG_STOP:
00197       break;
00198     case U8G_DEV_MSG_PAGE_NEXT:
00199       {
00200         u8g_dev_ssd1325_2bit_prepare_page(u8g, dev);
00201         u8g_dev_ssd1325_2bit_write_buffer(u8g, dev);
00202         u8g_SetChipSelect(u8g, dev, 0);        
00203       }
00204       break;
00205     case U8G_DEV_MSG_CONTRAST:
00206       u8g_SetChipSelect(u8g, dev, 1);
00207       u8g_SetAddress(u8g, dev, 0);          /* instruction mode */
00208       u8g_WriteByte(u8g, dev, 0x081);
00209       u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
00210       u8g_SetChipSelect(u8g, dev, 0);      
00211       return 1;
00212   }
00213   return u8g_dev_pb8v2_base_fn(u8g, dev, msg, arg);
00214 }
00215 
00216 static uint8_t u8g_dev_ssd1325_nhd27oled_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00217 {
00218   switch(msg)
00219   {
00220     case U8G_DEV_MSG_INIT:
00221       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
00222       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
00223       break;
00224     case U8G_DEV_MSG_STOP:
00225       break;
00226     case U8G_DEV_MSG_PAGE_NEXT:
00227       {
00228         u8g_dev_ssd1325_2bit_2x_prepare_page(u8g, dev, 0);
00229         u8g_dev_ssd1325_2bit_2x_write_buffer(u8g, dev, 0);
00230         u8g_dev_ssd1325_2bit_2x_prepare_page(u8g, dev, 1);
00231         u8g_dev_ssd1325_2bit_2x_write_buffer(u8g, dev, 1);
00232         u8g_SetChipSelect(u8g, dev, 0);        
00233       }
00234       break;
00235     case U8G_DEV_MSG_CONTRAST:
00236       u8g_SetChipSelect(u8g, dev, 1);
00237       u8g_SetAddress(u8g, dev, 0);          /* instruction mode */
00238       u8g_WriteByte(u8g, dev, 0x081);
00239       u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
00240       u8g_SetChipSelect(u8g, dev, 0);      
00241       return 1;
00242   }
00243   return u8g_dev_pb16v2_base_fn(u8g, dev, msg, arg);
00244 }
00245 
00246 //U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_SW_SPI);
00247 //U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_HW_SPI);
00248 
00249 //uint8_t u8g_dev_ssd1325_nhd27oled_2x_buf[WIDTH*2] U8G_NOCOMMON ; 
00250 //u8g_pb_t u8g_dev_ssd1325_nhd27oled_2x_pb = { {8, HEIGHT, 0, 0, 0},  WIDTH, u8g_dev_ssd1325_nhd27oled_2x_buf}; 
00251 //u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_sw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_SW_SPI };
00252 //u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_hw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_HW_SPI };
00253 
00254 
00255 #endif /* OBSOLETE_CODE */
00256