u8g_dev_ssd1325_nhd27oled_bw.c

00001 /*
00002 
00003   u8g_dev_ssd1325_nhd27oled_bw.c
00004   
00005   1-Bit (BW) Driver for SSD1325 Controller (OLED Display)
00006   Tested with NHD-2.7-12864UCY3
00007 
00008   Universal 8bit Graphics Library
00009   
00010   Copyright (c) 2011, olikraus@gmail.com
00011   All rights reserved.
00012 
00013   Redistribution and use in source and binary forms, with or without modification, 
00014   are permitted provided that the following conditions are met:
00015 
00016   * Redistributions of source code must retain the above copyright notice, this list 
00017     of conditions and the following disclaimer.
00018     
00019   * Redistributions in binary form must reproduce the above copyright notice, this 
00020     list of conditions and the following disclaimer in the documentation and/or other 
00021     materials provided with the distribution.
00022 
00023   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 
00024   CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
00025   INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
00026   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
00027   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
00028   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
00029   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
00030   NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
00031   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
00032   CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
00033   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00034   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00035   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
00036   
00037   SSD130x       Monochrom OLED Controller
00038   SSD131x       Character OLED Controller
00039   SSD132x       Graylevel OLED Controller
00040   SSD1331       Color OLED Controller       
00041 
00042 */
00043 
00044 #ifdef OBSOLETE_CODE
00045 
00046 #include "u8g.h"
00047 
00048 #define WIDTH 128
00049 #define HEIGHT 64
00050 #define PAGE_HEIGHT 8
00051 
00052 /* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */
00053 static const uint8_t u8g_dev_ssd1325_1bit_nhd_27_12864ucy3_init_seq[] PROGMEM = {
00054   U8G_ESC_DLY(10),              /* delay 10 ms */
00055   U8G_ESC_CS(0),                 /* disable chip */
00056   U8G_ESC_ADR(0),               /* instruction mode */
00057   U8G_ESC_RST(1),               /* do reset low pulse with (1*16)+2 milliseconds */
00058   U8G_ESC_CS(1),                /* enable chip */
00059   0x0ae,                                /* display off, sleep mode */
00060   0x0b3, 0x091,                    /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
00061   0x0a8, 0x03f,                     /* multiplex ratio: 0x03f * 1/64 duty */
00062   0x0a2, 0x04c,                     /* display offset, shift mapping ram counter */
00063   0x0a1, 0x000,                     /* display start line */
00064   0x0ad, 0x002,                     /* master configuration: disable embedded DC-DC, enable internal VCOMH */
00065   0x0a0, 0x056,                     /* remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
00066   0x086,                                /* full current range (0x084, 0x085, 0x086) */
00067   0x0b8,                                /* set gray scale table */
00068       0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
00069   0x081, 0x070,                    /* contrast, brightness, 0..128, Newhaven: 0x040 */
00070   0x0b2, 0x051,                    /* frame frequency (row period) */
00071   0x0b1, 0x055,                    /* phase length */
00072   0x0bc, 0x010,                    /* pre-charge voltage level */
00073   0x0b4, 0x002,                    /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
00074   0x0b0, 0x028,                    /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
00075   0x0be, 0x01c,                     /* VCOMH voltage */
00076   0x0bf, 0x002|0x00d,           /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
00077   0x0a5,                                 /* all pixel on */
00078   0x0af,                                  /* display on */
00079   U8G_ESC_DLY(100),             /* delay 100 ms */
00080   U8G_ESC_DLY(100),             /* delay 100 ms */
00081   0x0a4,                                 /* normal display mode */
00082   U8G_ESC_CS(0),             /* disable chip */
00083   U8G_ESC_END                /* end of sequence */
00084 };
00085 
00086 static const uint8_t u8g_dev_ssd1325_1bit_nhd_27_12864ucy3_prepare_page_seq[] PROGMEM = {
00087   U8G_ESC_ADR(0),               /* instruction mode */
00088   U8G_ESC_CS(1),                /* enable chip */
00089   0x015,       /* column address... */
00090   0x000,       /* start at column 0 */
00091   0x03f,       /* end at column 63 (which is y == 127), because there are two pixel in one column */
00092   0x075,       /* row address... */
00093   U8G_ESC_END                /* end of sequence */
00094 };
00095 
00096 
00097 static void u8g_dev_ssd1325_1bit_prepare_page(u8g_t *u8g, u8g_dev_t *dev)
00098 {
00099   uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
00100   
00101   u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_1bit_nhd_27_12864ucy3_prepare_page_seq);
00102   
00103   page <<= 3;
00104   u8g_WriteByte(u8g, dev, page);       /* start at the selected page */
00105   page += 7;
00106   u8g_WriteByte(u8g, dev, page);       /* end within the selected page */  
00107   
00108   u8g_SetAddress(u8g, dev, 1);          /* data mode */
00109 }
00110 
00111 static void u8g_dev_ssd1325_1bit_2x_prepare_page(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
00112 {
00113   uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
00114   
00115   u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_1bit_nhd_27_12864ucy3_prepare_page_seq);
00116   
00117   page <<= 1;
00118   page += is_odd;
00119   
00120   page <<= 3;
00121   u8g_WriteByte(u8g, dev, page);       /* start at the selected page */
00122   page += 7;
00123   u8g_WriteByte(u8g, dev, page);       /* end within the selected page */  
00124   
00125   u8g_SetAddress(u8g, dev, 1);          /* data mode */
00126 }
00127 
00128 /* assumes row autoincrement and activated nibble remap */
00129 #ifdef OLD
00130 static  void _OLD_u8g_dev_ssd1325_1bit_write_16_pixel(u8g_t *u8g, u8g_dev_t *dev, uint8_t left, uint8_t right)
00131 {
00132   uint8_t d, cnt;
00133   cnt = 8;
00134   do
00135   {
00136     d = 0;
00137     if ( left & 1 )
00138       d |= 0x0f0;
00139     if ( right & 1 )
00140       d |= 0x00f;
00141     u8g_WriteByte(u8g, dev, d);
00142     left >>= 1;
00143     right >>= 1;
00144     cnt--;
00145   }while ( cnt > 0 );
00146 }
00147 #endif
00148 
00149 static  void u8g_dev_ssd1325_1bit_write_16_pixel(u8g_t *u8g, u8g_dev_t *dev, uint8_t left, uint8_t right)
00150 {
00151   uint8_t d, cnt;
00152   static uint8_t buf[8];
00153   cnt = 8;
00154   do
00155   {
00156     d = 0;
00157     if ( left & 128 )
00158       d |= 0x0f0;
00159     if ( right & 128 )
00160       d |= 0x00f;
00161     cnt--;
00162     buf[cnt] = d;
00163     left <<= 1;
00164     right <<= 1;
00165   }while ( cnt > 0 );
00166   u8g_WriteSequence(u8g, dev, 8, buf);
00167 }
00168 
00169 static void u8g_dev_ssd1325_1bit_write_buffer(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
00170 {
00171   uint8_t cnt, left, right;
00172   uint8_t *ptr;
00173   u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00174   
00175   ptr = pb->buf;
00176   cnt = pb->width;
00177   if ( is_odd )
00178     ptr += cnt;
00179   cnt >>= 1;
00180   do
00181   {
00182     left = *ptr++;
00183     right = *ptr++;
00184     u8g_dev_ssd1325_1bit_write_16_pixel(u8g, dev, left, right);
00185     cnt--;
00186   } while( cnt > 0 );
00187 }
00188 
00189 uint8_t u8g_dev_ssd1325_nhd27oled_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00190 {
00191   switch(msg)
00192   {
00193     case U8G_DEV_MSG_INIT:
00194       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
00195       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_1bit_nhd_27_12864ucy3_init_seq);
00196       break;
00197     case U8G_DEV_MSG_STOP:
00198       break;
00199     case U8G_DEV_MSG_PAGE_NEXT:
00200       {
00201         u8g_dev_ssd1325_1bit_prepare_page(u8g, dev);
00202         u8g_dev_ssd1325_1bit_write_buffer(u8g, dev, 0);
00203         u8g_SetChipSelect(u8g, dev, 0);        
00204       }
00205       break;
00206     case U8G_DEV_MSG_CONTRAST:
00207       u8g_SetChipSelect(u8g, dev, 1);
00208       u8g_SetAddress(u8g, dev, 0);          /* instruction mode */
00209       u8g_WriteByte(u8g, dev, 0x081);
00210       u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
00211       u8g_SetChipSelect(u8g, dev, 0);      
00212       break;
00213   }
00214   return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
00215 }
00216 
00217 uint8_t u8g_dev_ssd1325_nhd27oled_2x_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00218 {
00219   switch(msg)
00220   {
00221     case U8G_DEV_MSG_INIT:
00222       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
00223       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_1bit_nhd_27_12864ucy3_init_seq);
00224       break;
00225     case U8G_DEV_MSG_STOP:
00226       break;
00227     case U8G_DEV_MSG_PAGE_NEXT:
00228       {
00229         u8g_dev_ssd1325_1bit_2x_prepare_page(u8g, dev, 0);
00230         u8g_dev_ssd1325_1bit_write_buffer(u8g, dev, 0);
00231         u8g_dev_ssd1325_1bit_2x_prepare_page(u8g, dev, 1);
00232         u8g_dev_ssd1325_1bit_write_buffer(u8g, dev, 1);
00233         u8g_SetChipSelect(u8g, dev, 0);        
00234       }
00235       break;
00236     case U8G_DEV_MSG_CONTRAST:
00237       u8g_SetChipSelect(u8g, dev, 1);
00238       u8g_SetAddress(u8g, dev, 0);          /* instruction mode */
00239       u8g_WriteByte(u8g, dev, 0x081);
00240       u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
00241       u8g_SetChipSelect(u8g, dev, 0);      
00242       break;
00243   }
00244   return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
00245 }
00246 
00247 /* disabled, see bw_new.c */
00248 /*
00249 U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_bw_sw_spi , WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1325_nhd27oled_bw_fn, U8G_COM_SW_SPI);
00250 U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_bw_hw_spi , WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1325_nhd27oled_bw_fn, U8G_COM_HW_SPI);
00251 U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_bw_parallel , WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1325_nhd27oled_bw_fn, U8G_COM_FAST_PARALLEL);
00252 */
00253 
00254 /*
00255 uint8_t u8g_dev_ssd1325_nhd27oled_2x_bw_buf[WIDTH*2] U8G_NOCOMMON ; 
00256 u8g_pb_t u8g_dev_ssd1325_nhd27oled_2x_bw_pb = { {16, HEIGHT, 0, 0, 0},  WIDTH, u8g_dev_ssd1325_nhd27oled_2x_bw_buf}; 
00257 u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_sw_spi = { u8g_dev_ssd1325_nhd27oled_2x_bw_fn, &u8g_dev_ssd1325_nhd27oled_2x_bw_pb, U8G_COM_SW_SPI };
00258 u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_hw_spi = { u8g_dev_ssd1325_nhd27oled_2x_bw_fn, &u8g_dev_ssd1325_nhd27oled_2x_bw_pb, U8G_COM_HW_SPI };
00259 u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_parallel = { u8g_dev_ssd1325_nhd27oled_2x_bw_fn, &u8g_dev_ssd1325_nhd27oled_2x_bw_pb, U8G_COM_FAST_PARALLEL };
00260 */
00261 
00262 #endif
00263 
00264