u8g_dev_ssd1306_128x64.c

00001 /*
00002 
00003   u8g_dev_ssd1306_128x64.c
00004 
00005   Universal 8bit Graphics Library
00006   
00007   Copyright (c) 2011, olikraus@gmail.com
00008   All rights reserved.
00009 
00010   Redistribution and use in source and binary forms, with or without modification, 
00011   are permitted provided that the following conditions are met:
00012 
00013   * Redistributions of source code must retain the above copyright notice, this list 
00014     of conditions and the following disclaimer.
00015     
00016   * Redistributions in binary form must reproduce the above copyright notice, this 
00017     list of conditions and the following disclaimer in the documentation and/or other 
00018     materials provided with the distribution.
00019 
00020   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 
00021   CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
00022   INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
00023   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
00024   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
00025   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
00026   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
00027   NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
00028   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
00029   CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
00030   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00031   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00032   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
00033   
00034   
00035 */
00036 
00037 #include "u8g.h"
00038 
00039 #define WIDTH 128
00040 #define HEIGHT 64
00041 #define PAGE_HEIGHT 8
00042 
00043 /* init sequence adafruit 128x64 OLED (NOT TESTED) */
00044 static const uint8_t u8g_dev_ssd1306_128x64_adafruit1_init_seq[] PROGMEM = {
00045   U8G_ESC_CS(0),             /* disable chip */
00046   U8G_ESC_ADR(0),           /* instruction mode */
00047   U8G_ESC_RST(1),           /* do reset low pulse with (1*16)+2 milliseconds */
00048   U8G_ESC_CS(1),             /* enable chip */
00049 
00050   0x0ae,                /* display off, sleep mode */
00051   0x0d5, 0x080,     /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
00052   0x0a8, 0x03f,     /* */
00053 
00054   0x0d3, 0x000,     /*  */
00055 
00056   0x040,                /* start line */
00057   
00058   0x08d, 0x010,     /* [1] charge pump setting (p62): 0x014 enable, 0x010 disable */
00059 
00060   0x020, 0x000,     /* */
00061   0x0a1,                /* segment remap a0/a1*/
00062   0x0c8,                /* c0: scan dir normal, c8: reverse */
00063   0x0da, 0x012,     /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
00064   0x081, 0x09f,     /* [1] set contrast control */
00065   0x0d9, 0x022,     /* [1] pre-charge period 0x022/f1*/
00066   0x0db, 0x040,     /* vcomh deselect level */
00067   
00068   0x02e,                /* 2012-05-27: Deactivate scroll */ 
00069   0x0a4,                /* output ram to display */
00070   0x0a6,                /* none inverted normal display mode */
00071   0x0af,                /* display on */
00072 
00073   U8G_ESC_CS(0),             /* disable chip */
00074   U8G_ESC_END                /* end of sequence */
00075 };
00076 
00077 /* init sequence adafruit 128x64 OLED (NOT TESTED) */
00078 static const uint8_t u8g_dev_ssd1306_128x64_adafruit2_init_seq[] PROGMEM = {
00079   U8G_ESC_CS(0),             /* disable chip */
00080   U8G_ESC_ADR(0),           /* instruction mode */
00081   U8G_ESC_RST(1),           /* do reset low pulse with (1*16)+2 milliseconds */
00082   U8G_ESC_CS(1),             /* enable chip */
00083 
00084   0x0ae,                /* display off, sleep mode */
00085   0x0d5, 0x080,     /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
00086   0x0a8, 0x03f,     /* */
00087 
00088   0x0d3, 0x000,     /*  */
00089 
00090   0x040,                /* start line */
00091   
00092   0x08d, 0x014,     /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
00093 
00094   0x020, 0x000,     /* */
00095   0x0a1,                /* segment remap a0/a1*/
00096   0x0c8,                /* c0: scan dir normal, c8: reverse */
00097   0x0da, 0x012,     /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
00098   0x081, 0x0cf,     /* [2] set contrast control */
00099   0x0d9, 0x0f1,     /* [2] pre-charge period 0x022/f1*/
00100   0x0db, 0x040,     /* vcomh deselect level */
00101   
00102   0x02e,                /* 2012-05-27: Deactivate scroll */ 
00103   0x0a4,                /* output ram to display */
00104   0x0a6,                /* none inverted normal display mode */
00105   0x0af,                /* display on */
00106 
00107   U8G_ESC_CS(0),             /* disable chip */
00108   U8G_ESC_END                /* end of sequence */
00109 };
00110 
00111 /* init sequence adafruit 128x64 OLED (NOT TESTED), like adafruit3, but with page addressing mode */
00112 static const uint8_t u8g_dev_ssd1306_128x64_adafruit3_init_seq[] PROGMEM = {
00113   U8G_ESC_CS(0),             /* disable chip */
00114   U8G_ESC_ADR(0),           /* instruction mode */
00115   U8G_ESC_RST(1),           /* do reset low pulse with (1*16)+2 milliseconds */
00116   U8G_ESC_CS(1),             /* enable chip */
00117 
00118   0x0ae,                /* display off, sleep mode */
00119   0x0d5, 0x080,     /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
00120   0x0a8, 0x03f,     /* */
00121 
00122   0x0d3, 0x000,     /*  */
00123 
00124   0x040,                /* start line */
00125   
00126   0x08d, 0x014,     /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
00127 
00128   0x020, 0x002,     /* 2012-05-27: page addressing mode */
00129   0x0a1,                /* segment remap a0/a1*/
00130   0x0c8,                /* c0: scan dir normal, c8: reverse */
00131   0x0da, 0x012,     /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
00132   0x081, 0x0cf,     /* [2] set contrast control */
00133   0x0d9, 0x0f1,     /* [2] pre-charge period 0x022/f1*/
00134   0x0db, 0x040,     /* vcomh deselect level */
00135   
00136   0x02e,                /* 2012-05-27: Deactivate scroll */ 
00137   0x0a4,                /* output ram to display */
00138   0x0a6,                /* none inverted normal display mode */
00139   0x0af,                /* display on */
00140 
00141   U8G_ESC_CS(0),             /* disable chip */
00142   U8G_ESC_END                /* end of sequence */
00143 };
00144 
00145 /* init sequence Univision datasheet (NOT TESTED) */
00146 static const uint8_t u8g_dev_ssd1306_128x64_univision_init_seq[] PROGMEM = {
00147   U8G_ESC_CS(0),             /* disable chip */
00148   U8G_ESC_ADR(0),           /* instruction mode */
00149   U8G_ESC_RST(1),           /* do reset low pulse with (1*16)+2 milliseconds */
00150   U8G_ESC_CS(1),             /* enable chip */
00151 
00152   0x0ae,                /* display off, sleep mode */
00153   0x0d5, 0x080,     /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
00154   0x0a8, 0x03f,     /* multiplex ratio */
00155   0x0d3, 0x000,     /* display offset */
00156   0x040,                /* start line */
00157   0x08d, 0x010,     /* charge pump setting (p62): 0x014 enable, 0x010 disable */
00158   0x0a1,                /* segment remap a0/a1*/
00159   0x0c8,                /* c0: scan dir normal, c8: reverse */
00160   0x0da, 0x012,     /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
00161   0x081, 0x09f,     /* set contrast control */
00162   0x0d9, 0x022,     /* pre-charge period */
00163   0x0db, 0x040,     /* vcomh deselect level */
00164   0x022, 0x000,     /* page addressing mode WRONG: 3 byte cmd! */
00165   0x0a4,                /* output ram to display */
00166   0x0a6,                /* none inverted normal display mode */
00167   0x0af,                /* display on */
00168   U8G_ESC_CS(0),             /* disable chip */
00169   U8G_ESC_END                /* end of sequence */
00170 };
00171 
00172 /* select one init sequence here */
00173 //#define u8g_dev_ssd1306_128x64_init_seq u8g_dev_ssd1306_128x64_univision_init_seq
00174 //#define u8g_dev_ssd1306_128x64_init_seq u8g_dev_ssd1306_128x64_adafruit1_init_seq
00175 //#define u8g_dev_ssd1306_128x64_init_seq u8g_dev_ssd1306_128x64_adafruit2_init_seq
00176 #define u8g_dev_ssd1306_128x64_init_seq u8g_dev_ssd1306_128x64_adafruit3_init_seq
00177 
00178 
00179 static const uint8_t u8g_dev_ssd1306_128x64_data_start[] PROGMEM = {
00180   U8G_ESC_ADR(0),           /* instruction mode */
00181   U8G_ESC_CS(1),             /* enable chip */
00182   0x010,        /* set upper 4 bit of the col adr to 0 */
00183   0x000,        /* set lower 4 bit of the col adr to 4  */
00184   U8G_ESC_END                /* end of sequence */
00185 };
00186 
00187 static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
00188   U8G_ESC_ADR(0),           /* instruction mode */
00189   U8G_ESC_CS(1),             /* enable chip */
00190   0x0ae,        /* display off */      
00191   U8G_ESC_CS(1),             /* disable chip */
00192   U8G_ESC_END                /* end of sequence */
00193 };
00194 
00195 static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
00196   U8G_ESC_ADR(0),           /* instruction mode */
00197   U8G_ESC_CS(1),             /* enable chip */
00198   0x0af,        /* display on */      
00199   U8G_ESC_DLY(50),       /* delay 50 ms */
00200   U8G_ESC_CS(1),             /* disable chip */
00201   U8G_ESC_END                /* end of sequence */
00202 };
00203 
00204 uint8_t u8g_dev_ssd1306_128x64_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00205 {
00206   switch(msg)
00207   {
00208     case U8G_DEV_MSG_INIT:
00209       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
00210       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x64_init_seq);
00211       break;
00212     case U8G_DEV_MSG_STOP:
00213       break;
00214     case U8G_DEV_MSG_PAGE_NEXT:
00215       {
00216         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00217         u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x64_data_start);    
00218         u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (SSD1306) */
00219         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00220         if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
00221           return 0;
00222         u8g_SetChipSelect(u8g, dev, 0);
00223       }
00224       break;
00225     case U8G_DEV_MSG_SLEEP_ON:
00226       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);    
00227       return 1;
00228     case U8G_DEV_MSG_SLEEP_OFF:
00229       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);    
00230       return 1;
00231   }
00232   return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
00233 }
00234 
00235 uint8_t u8g_dev_ssd1306_128x64_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00236 {
00237   switch(msg)
00238   {
00239     case U8G_DEV_MSG_INIT:
00240       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
00241       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x64_init_seq);
00242       break;
00243     case U8G_DEV_MSG_STOP:
00244       break;
00245     case U8G_DEV_MSG_PAGE_NEXT:
00246       {
00247         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00248     
00249         u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x64_data_start);    
00250         u8g_WriteByte(u8g, dev, 0x0b0 | (pb->p.page*2)); /* select current page (SSD1306) */
00251         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00252     u8g_WriteSequence(u8g, dev, pb->width, pb->buf); 
00253         u8g_SetChipSelect(u8g, dev, 0);
00254     
00255         u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x64_data_start);    
00256         u8g_WriteByte(u8g, dev, 0x0b0 | (pb->p.page*2+1)); /* select current page (SSD1306) */
00257         u8g_SetAddress(u8g, dev, 1);           /* data mode */
00258     u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width); 
00259         u8g_SetChipSelect(u8g, dev, 0);
00260       }
00261       break;
00262     case U8G_DEV_MSG_SLEEP_ON:
00263       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);    
00264       return 1;
00265     case U8G_DEV_MSG_SLEEP_OFF:
00266       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);    
00267       return 1;
00268   }
00269   return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
00270 }
00271 
00272 U8G_PB_DEV(u8g_dev_ssd1306_128x64_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x64_fn, U8G_COM_SW_SPI);
00273 U8G_PB_DEV(u8g_dev_ssd1306_128x64_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x64_fn, U8G_COM_HW_SPI);
00274 U8G_PB_DEV(u8g_dev_ssd1306_128x64_i2c, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x64_fn, U8G_COM_SSD_I2C);
00275 
00276 uint8_t u8g_dev_ssd1306_128x64_2x_buf[WIDTH*2] U8G_NOCOMMON ; 
00277 u8g_pb_t u8g_dev_ssd1306_128x64_2x_pb = { {16, HEIGHT, 0, 0, 0},  WIDTH, u8g_dev_ssd1306_128x64_2x_buf}; 
00278 u8g_dev_t u8g_dev_ssd1306_128x64_2x_sw_spi = { u8g_dev_ssd1306_128x64_2x_fn, &u8g_dev_ssd1306_128x64_2x_pb, U8G_COM_SW_SPI };
00279 u8g_dev_t u8g_dev_ssd1306_128x64_2x_hw_spi = { u8g_dev_ssd1306_128x64_2x_fn, &u8g_dev_ssd1306_128x64_2x_pb, U8G_COM_HW_SPI };
00280 u8g_dev_t u8g_dev_ssd1306_128x64_2x_i2c = { u8g_dev_ssd1306_128x64_2x_fn, &u8g_dev_ssd1306_128x64_2x_pb, U8G_COM_SSD_I2C };
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