u8g_dev_ssd1306_128x32.c

00001 /*
00002 
00003   u8g_dev_ssd1306_128x32.c
00004 
00005   Universal 8bit Graphics Library
00006   
00007   Copyright (c) 2011, olikraus@gmail.com
00008   All rights reserved.
00009 
00010   Redistribution and use in source and binary forms, with or without modification, 
00011   are permitted provided that the following conditions are met:
00012 
00013   * Redistributions of source code must retain the above copyright notice, this list 
00014     of conditions and the following disclaimer.
00015     
00016   * Redistributions in binary form must reproduce the above copyright notice, this 
00017     list of conditions and the following disclaimer in the documentation and/or other 
00018     materials provided with the distribution.
00019 
00020   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 
00021   CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
00022   INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
00023   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
00024   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
00025   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
00026   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
00027   NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
00028   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
00029   CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
00030   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00031   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00032   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
00033 
00034   
00035   23 Feb 2013: Fixed, Issue 147
00036 
00037 */
00038 
00039 
00040 #include "u8g.h"
00041 
00042 #define WIDTH 128
00043 #define HEIGHT 32
00044 #define PAGE_HEIGHT 8
00045 
00046 
00047 /* init sequence adafruit 128x32 OLED (NOT TESTED) */
00048 static const uint8_t u8g_dev_ssd1306_128x32_adafruit1_init_seq[] PROGMEM = {
00049   U8G_ESC_CS(0),        /* disable chip */
00050   U8G_ESC_ADR(0),       /* instruction mode */
00051   U8G_ESC_RST(1),       /* do reset low pulse with (1*16)+2 milliseconds */
00052   U8G_ESC_CS(1),        /* enable chip */
00053 
00054   0x0ae,                /* display off, sleep mode */
00055   0x0d5, 0x080,         /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
00056   0x0a8, 0x03f,         /* */
00057 
00058   0x0d3, 0x000,         /*  */
00059 
00060   0x040,                /* start line */
00061   
00062   0x08d, 0x010,         /* [1] charge pump setting (p62): 0x014 enable, 0x010 disable */
00063 
00064   0x020, 0x000,         /* */
00065   0x0a1,                /* segment remap a0/a1*/
00066   0x0c8,                /* c0: scan dir normal, c8: reverse */
00067   0x0da, 0x012,         /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
00068   0x081, 0x09f,         /* [1] set contrast control */
00069   0x0d9, 0x022,         /* [1] pre-charge period 0x022/f1*/
00070   0x0db, 0x040,         /* vcomh deselect level */
00071   
00072   0x02e,                /* 2012-05-27: Deactivate scroll */ 
00073   0x0a4,                /* output ram to display */
00074   0x0a6,                /* none inverted normal display mode */
00075   0x0af,                /* display on */
00076 
00077   U8G_ESC_CS(0),        /* disable chip */
00078   U8G_ESC_END           /* end of sequence */
00079 };
00080 
00081 
00082 /* init sequence adafruit 128x32 OLED (NOT TESTED) */
00083 static const uint8_t u8g_dev_ssd1306_128x32_adafruit2_init_seq[] PROGMEM = {
00084   U8G_ESC_CS(0),        /* disable chip */
00085   U8G_ESC_ADR(0),       /* instruction mode */
00086   U8G_ESC_RST(1),       /* do reset low pulse with (1*16)+2 milliseconds */
00087   U8G_ESC_CS(1),        /* enable chip */
00088 
00089   0x0ae,                /* display off, sleep mode */
00090   0x0d5, 0x080,         /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
00091   0x0a8, 0x03f,         /* */
00092 
00093   0x0d3, 0x000,         /*  */
00094 
00095   0x040,                /* start line */
00096   
00097   0x08d, 0x014,         /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
00098 
00099   0x020, 0x000,         /* */
00100   0x0a1,                /* segment remap a0/a1*/
00101   0x0c8,                /* c0: scan dir normal, c8: reverse */
00102   0x0da, 0x012,         /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
00103   0x081, 0x0cf,         /* [2] set contrast control */
00104   0x0d9, 0x0f1,         /* [2] pre-charge period 0x022/f1*/
00105   0x0db, 0x040,         /* vcomh deselect level */
00106   
00107   0x02e,                /* 2012-05-27: Deactivate scroll */ 
00108   0x0a4,                /* output ram to display */
00109   0x0a6,                /* none inverted normal display mode */
00110   0x0af,                /* display on */
00111 
00112   U8G_ESC_CS(0),        /* disable chip */
00113   U8G_ESC_END           /* end of sequence */
00114 };
00115 
00116 
00117 /* init sequence adafruit 128x32 OLED (TESTED - WORKING 23.02.13), like adafruit3, but with page addressing mode */
00118 static const uint8_t u8g_dev_ssd1306_128x32_adafruit3_init_seq[] PROGMEM = {
00119   U8G_ESC_CS(0),        /* disable chip */
00120   U8G_ESC_ADR(0),       /* instruction mode */
00121   U8G_ESC_RST(1),       /* do reset low pulse with (1*16)+2 milliseconds */
00122   U8G_ESC_CS(1),        /* enable chip */
00123 
00124   0x0ae,                /* display off, sleep mode */
00125   0x0d5, 0x080,         /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
00126   0x0a8, 0x01f,         /* Feb 23, 2013: 128x32 OLED: 0x01f,  128x32 OLED 0x03f */
00127 
00128   0x0d3, 0x000,         /*  */
00129 
00130   0x040,                /* start line */
00131   
00132   0x08d, 0x014,         /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */ 
00133 
00134   0x020, 0x002,         /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), Feb 23, 2013: 128x32 OLED: 0x002,  128x32 OLED 0x012 */
00135   0x0a1,                /* segment remap a0/a1*/
00136   0x0c8,                /* c0: scan dir normal, c8: reverse */
00137   0x0da, 0x002,         /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
00138   0x081, 0x0cf,         /* [2] set contrast control */
00139   0x0d9, 0x0f1,         /* [2] pre-charge period 0x022/f1*/
00140   0x0db, 0x040,         /* vcomh deselect level */
00141   
00142   0x02e,                /* 2012-05-27: Deactivate scroll */ 
00143   0x0a4,                /* output ram to display */
00144   0x0a6,                /* none inverted normal display mode */
00145   0x0af,                /* display on */
00146 
00147   U8G_ESC_CS(0),        /* disable chip */
00148   U8G_ESC_END           /* end of sequence */
00149 };
00150 
00151 
00152 /* init sequence Univision datasheet (NOT TESTED) */
00153 static const uint8_t u8g_dev_ssd1306_128x32_univision_init_seq[] PROGMEM = {
00154   U8G_ESC_CS(0),        /* disable chip */
00155   U8G_ESC_ADR(0),       /* instruction mode */
00156   U8G_ESC_RST(1),       /* do reset low pulse with (1*16)+2 milliseconds */
00157   U8G_ESC_CS(1),        /* enable chip */
00158 
00159   0x0ae,                /* display off, sleep mode */
00160   0x0d5, 0x080,         /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
00161   0x0a8, 0x03f,         /* multiplex ratio */
00162   0x0d3, 0x000,         /* display offset */
00163   0x040,                /* start line */
00164   0x08d, 0x010,         /* charge pump setting (p62): 0x014 enable, 0x010 disable */
00165   0x0a1,                /* segment remap a0/a1*/
00166   0x0c8,                /* c0: scan dir normal, c8: reverse */
00167   0x0da, 0x012,         /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
00168   0x081, 0x09f,         /* set contrast control */
00169   0x0d9, 0x022,         /* pre-charge period */
00170   0x0db, 0x040,         /* vcomh deselect level */
00171   0x022, 0x000,         /* page addressing mode WRONG: 3 byte cmd! */
00172   0x0a4,                /* output ram to display */
00173   0x0a6,                /* none inverted normal display mode */
00174   0x0af,                /* display on */
00175   U8G_ESC_CS(0),        /* disable chip */
00176   U8G_ESC_END           /* end of sequence */
00177 };
00178 
00179 
00180 /* select one init sequence here */
00181 //define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_univision_init_seq
00182 //define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit1_init_seq
00183 //define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit2_init_seq
00184 #define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit3_init_seq
00185 
00186 
00187 static const uint8_t u8g_dev_ssd1306_128x32_data_start[] PROGMEM = {
00188   U8G_ESC_ADR(0),       /* instruction mode */
00189   U8G_ESC_CS(1),        /* enable chip */
00190   0x010,                /* set upper 4 bit of the col adr. to 0 */
00191   0x000,                /* set lower 4 bit of the col adr. to 4  */
00192   U8G_ESC_END           /* end of sequence */
00193 };
00194 
00195 static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
00196   U8G_ESC_ADR(0),           /* instruction mode */
00197   U8G_ESC_CS(1),             /* enable chip */
00198   0x0ae,        /* display off */      
00199   U8G_ESC_CS(1),             /* disable chip */
00200   U8G_ESC_END                /* end of sequence */
00201 };
00202 
00203 static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
00204   U8G_ESC_ADR(0),           /* instruction mode */
00205   U8G_ESC_CS(1),             /* enable chip */
00206   0x0af,        /* display on */      
00207   U8G_ESC_DLY(50),       /* delay 50 ms */
00208   U8G_ESC_CS(1),             /* disable chip */
00209   U8G_ESC_END                /* end of sequence */
00210 };
00211 
00212 uint8_t u8g_dev_ssd1306_128x32_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00213 {
00214   switch(msg)
00215   {
00216     case U8G_DEV_MSG_INIT:
00217       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
00218       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_init_seq);
00219       break;
00220     case U8G_DEV_MSG_STOP:
00221       break;
00222     case U8G_DEV_MSG_PAGE_NEXT:
00223       {
00224         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00225         u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_data_start);    
00226         u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page);    /* select current page (SSD1306) */
00227         u8g_SetAddress(u8g, dev, 1);                    /* data mode */
00228         if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
00229           return 0;
00230         u8g_SetChipSelect(u8g, dev, 0);
00231       }
00232       break;
00233     case U8G_DEV_MSG_SLEEP_ON:
00234       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);    
00235       return 1;
00236     case U8G_DEV_MSG_SLEEP_OFF:
00237       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);    
00238       return 1;
00239 }
00240   
00241   return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
00242 }
00243 
00244 uint8_t u8g_dev_ssd1306_128x32_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00245 {
00246   switch(msg)
00247   {
00248     case U8G_DEV_MSG_INIT:
00249       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
00250       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_init_seq);
00251       break;
00252     case U8G_DEV_MSG_STOP:
00253       break;
00254     case U8G_DEV_MSG_PAGE_NEXT:
00255       {
00256         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00257     
00258         u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_data_start);    
00259         u8g_WriteByte(u8g, dev, 0x0b0 | (pb->p.page*2));    /* select current page (SSD1306) */
00260         u8g_SetAddress(u8g, dev, 1);                    /* data mode */
00261     u8g_WriteSequence(u8g, dev, pb->width, pb->buf); 
00262         u8g_SetChipSelect(u8g, dev, 0);
00263     
00264         u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_data_start);    
00265         u8g_WriteByte(u8g, dev, 0x0b0 | (pb->p.page*2+1));  /* select current page (SSD1306) */
00266         u8g_SetAddress(u8g, dev, 1);                    /* data mode */
00267     u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width); 
00268         u8g_SetChipSelect(u8g, dev, 0);
00269       }
00270       break;
00271     case U8G_DEV_MSG_SLEEP_ON:
00272       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);    
00273       return 1;
00274     case U8G_DEV_MSG_SLEEP_OFF:
00275       u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);    
00276       return 1;
00277   }
00278   return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
00279 }
00280 
00281 U8G_PB_DEV(u8g_dev_ssd1306_128x32_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x32_fn, U8G_COM_SW_SPI);
00282 U8G_PB_DEV(u8g_dev_ssd1306_128x32_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x32_fn, U8G_COM_HW_SPI);
00283 U8G_PB_DEV(u8g_dev_ssd1306_128x32_i2c, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x32_fn, U8G_COM_SSD_I2C);
00284 
00285 uint8_t u8g_dev_ssd1306_128x32_2x_buf[WIDTH*2] U8G_NOCOMMON ; 
00286 u8g_pb_t u8g_dev_ssd1306_128x32_2x_pb = { {16, HEIGHT, 0, 0, 0},  WIDTH, u8g_dev_ssd1306_128x32_2x_buf}; 
00287 u8g_dev_t u8g_dev_ssd1306_128x32_2x_sw_spi = { u8g_dev_ssd1306_128x32_2x_fn, &u8g_dev_ssd1306_128x32_2x_pb, U8G_COM_SW_SPI };
00288 u8g_dev_t u8g_dev_ssd1306_128x32_2x_hw_spi = { u8g_dev_ssd1306_128x32_2x_fn, &u8g_dev_ssd1306_128x32_2x_pb, U8G_COM_HW_SPI };
00289 u8g_dev_t u8g_dev_ssd1306_128x32_2x_i2c = { u8g_dev_ssd1306_128x32_2x_fn, &u8g_dev_ssd1306_128x32_2x_pb, U8G_COM_SSD_I2C };
00290