u8g_dev_lc7981_320x64.c

00001 /*
00002 
00003   u8g_dev_lc7981_320x64.c
00004 
00005   Note: Requires 16 bit mode (Must be enabled in u8g.h)
00006   
00007   Tested with Varitronix MGLS32064-03.pdf
00008   
00009   Universal 8bit Graphics Library
00010   
00011   Copyright (c) 2012, olikraus@gmail.com
00012   All rights reserved.
00013 
00014   Redistribution and use in source and binary forms, with or without modification, 
00015   are permitted provided that the following conditions are met:
00016 
00017   * Redistributions of source code must retain the above copyright notice, this list 
00018     of conditions and the following disclaimer.
00019     
00020   * Redistributions in binary form must reproduce the above copyright notice, this 
00021     list of conditions and the following disclaimer in the documentation and/or other 
00022     materials provided with the distribution.
00023 
00024   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 
00025   CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
00026   INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
00027   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
00028   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
00029   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
00030   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
00031   NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
00032   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
00033   CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
00034   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00035   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00036   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
00037   
00038   
00039 */
00040 
00041 #include "u8g.h"
00042 
00043 #ifdef U8G_16BIT
00044 #define WIDTH 320
00045 #else
00046 #define WIDTH 240
00047 #endif
00048 
00049 #define HEIGHT 64
00050 #define PAGE_HEIGHT 8
00051 
00052 
00053 /*
00054   http://www.gaw.ru/pdf/lcd/lcm/Varitronix/graf/MGLS32064-03.pdf
00055 */
00056 
00057 static const uint8_t u8g_dev_lc7981_320x64_init_seq[] PROGMEM = {
00058   U8G_ESC_CS(0),             /* disable chip */
00059   U8G_ESC_ADR(1),           /* instruction mode */
00060   U8G_ESC_RST(15),           /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
00061   U8G_ESC_CS(1),             /* enable chip */
00062   U8G_ESC_DLY(50),         /* delay 50 ms */
00063   
00064   
00065   U8G_ESC_ADR(1),               /* instruction mode */
00066   0x000,                                /* mode register */
00067   U8G_ESC_ADR(0),               /* data mode */
00068   0x032,                                /* display on (bit 5), master mode on (bit 4), graphics mode on (bit 1)*/
00069 
00070   U8G_ESC_ADR(1),               /* instruction mode */
00071   0x001,                                /* character/bits per pixel pitch */
00072   U8G_ESC_ADR(0),               /* data mode */
00073   0x007,                                /* 8 bits per pixel */
00074 
00075   U8G_ESC_ADR(1),               /* instruction mode */
00076   0x002,                                /* number of chars/byte width of the screen */
00077   U8G_ESC_ADR(0),               /* data mode */
00078   WIDTH/8-1,                         /* 8 bits per pixel */
00079 
00080   U8G_ESC_ADR(1),               /* instruction mode */
00081   0x003,                                /* time division */
00082   U8G_ESC_ADR(0),               /* data mode */
00083   0x07f,                                /*  */
00084 
00085   U8G_ESC_ADR(1),               /* instruction mode */
00086   0x008,                                /* display start low */
00087   U8G_ESC_ADR(0),               /* data mode */
00088   0x000,                                /*  */
00089 
00090   U8G_ESC_ADR(1),               /* instruction mode */
00091   0x009,                                /* display start high */
00092   U8G_ESC_ADR(0),               /* data mode */
00093   0x000,                                /*  */
00094     
00095   U8G_ESC_DLY(10),               /* delay 10 ms */
00096   
00097   U8G_ESC_CS(0),             /* disable chip */
00098   U8G_ESC_END                /* end of sequence */
00099 };
00100 
00101 uint8_t u8g_dev_lc7981_320x64_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
00102 {
00103   switch(msg)
00104   {
00105     case U8G_DEV_MSG_INIT:
00106       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_NONE);
00107       u8g_WriteEscSeqP(u8g, dev, u8g_dev_lc7981_320x64_init_seq);
00108       break;
00109     case U8G_DEV_MSG_STOP:
00110       break;
00111     case U8G_DEV_MSG_PAGE_NEXT:
00112       {
00113         uint8_t y, i;
00114         uint16_t disp_ram_adr;
00115         uint8_t *ptr;
00116         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
00117         
00118         u8g_SetAddress(u8g, dev, 1);           /* cmd mode */
00119         u8g_SetChipSelect(u8g, dev, 1);
00120         y = pb->p.page_y0;
00121         ptr = pb->buf;
00122         disp_ram_adr = WIDTH/8;
00123         disp_ram_adr *= y;
00124         for( i = 0; i < 8; i ++ )
00125         {
00126           u8g_SetAddress(u8g, dev, 1);           /* cmd mode */
00127           u8g_WriteByte(u8g, dev, 0x00a );      /* display ram (cursor) address low byte */
00128           u8g_SetAddress(u8g, dev, 0);           /* data mode */
00129           u8g_WriteByte(u8g, dev, disp_ram_adr & 0x0ff );  
00130 
00131           u8g_SetAddress(u8g, dev, 1);           /* cmd mode */
00132           u8g_WriteByte(u8g, dev, 0x00b );      /* display ram (cursor) address hight byte */
00133           u8g_SetAddress(u8g, dev, 0);           /* data mode */
00134           u8g_WriteByte(u8g, dev, disp_ram_adr >> 8 );  
00135           
00136           u8g_SetAddress(u8g, dev, 1);           /* cmd mode */
00137           u8g_WriteByte(u8g, dev, 0x00c );      /* write data */
00138           u8g_SetAddress(u8g, dev, 0);           /* data mode */
00139           u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
00140           ptr += WIDTH/8;
00141           disp_ram_adr += WIDTH/8;
00142         }
00143         u8g_SetChipSelect(u8g, dev, 0);
00144       }
00145       break;
00146   }
00147   return u8g_dev_pb8h1f_base_fn(u8g, dev, msg, arg);
00148 }
00149 
00150 U8G_PB_DEV(u8g_dev_lc7981_320x64_8bit, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_lc7981_320x64_fn, U8G_COM_FAST_PARALLEL);
00151 
00152