u8g_com_atmega_hw_spi.c

00001 /*
00002   
00003   u8g_com_atmega_hw_spi.c
00004 
00005   Universal 8bit Graphics Library
00006   
00007   Copyright (c) 2012, olikraus@gmail.com
00008   All rights reserved.
00009 
00010   Redistribution and use in source and binary forms, with or without modification, 
00011   are permitted provided that the following conditions are met:
00012 
00013   * Redistributions of source code must retain the above copyright notice, this list 
00014     of conditions and the following disclaimer.
00015     
00016   * Redistributions in binary form must reproduce the above copyright notice, this 
00017     list of conditions and the following disclaimer in the documentation and/or other 
00018     materials provided with the distribution.
00019 
00020   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 
00021   CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
00022   INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
00023   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
00024   DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
00025   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
00026   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
00027   NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
00028   LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
00029   CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
00030   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00031   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00032   ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
00033   
00034   
00035   Assumes, that 
00036     MOSI is at PORTB, Pin 3
00037   and
00038     SCK is at PORTB, Pin 5
00039 
00040   Update for ATOMIC operation done (01 Jun 2013)
00041     U8G_ATOMIC_OR(ptr, val)
00042     U8G_ATOMIC_AND(ptr, val)
00043     U8G_ATOMIC_START()
00044     U8G_ATOMIC_END()
00045  
00046 
00047 
00048 */
00049 
00050 #include "u8g.h"
00051 
00052 
00053 #if defined(__AVR__)
00054 #define U8G_ATMEGA_HW_SPI
00055 
00056 /* remove the definition for attiny */
00057 #if __AVR_ARCH__ == 2
00058 #undef U8G_ATMEGA_HW_SPI
00059 #endif
00060 #if __AVR_ARCH__ == 25
00061 #undef U8G_ATMEGA_HW_SPI
00062 #endif
00063 #endif
00064 
00065 
00066 #if defined(U8G_ATMEGA_HW_SPI)
00067 
00068 #include <avr/interrupt.h>
00069 #include <avr/io.h>
00070 
00071 
00072 static uint8_t u8g_atmega_spi_out(uint8_t data)
00073 {
00074   /* unsigned char x = 100; */
00075   /* send data */
00076   SPDR = data;
00077   /* wait for transmission */
00078   while (!(SPSR & (1<<SPIF))) 
00079     ;
00080   /* clear the SPIF flag by reading SPDR */
00081   return  SPDR;
00082 }
00083 
00084 
00085 uint8_t u8g_com_atmega_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
00086 {
00087   switch(msg)
00088   {
00089     case U8G_COM_MSG_STOP:
00090       break;
00091     
00092     case U8G_COM_MSG_INIT:
00093 
00094       u8g_SetPIOutput(u8g, U8G_PI_CS);
00095       u8g_SetPIOutput(u8g, U8G_PI_A0);
00096       
00097       U8G_ATOMIC_START();
00098       
00099       DDRB |= _BV(3);          /* D0, MOSI */
00100       DDRB |= _BV(5);          /* SCK */
00101       DDRB |= _BV(2);       /* slave select */
00102     
00103       PORTB &= ~_BV(3);        /* D0, MOSI = 0 */
00104       PORTB &= ~_BV(5);        /* SCK = 0 */
00105       
00106       U8G_ATOMIC_END();
00107       
00108       u8g_SetPILevel(u8g, U8G_PI_CS, 1);
00109 
00110       /*
00111         SPR1 SPR0
00112             0   0       fclk/4    x
00113             0   1       fclk/16
00114             1   0       fclk/64      
00115             1   1       fclk/128
00116       */
00117       SPCR = 0;
00118       SPCR =  (1<<SPE) | (1<<MSTR)|(0<<SPR1)|(0<<SPR0)|(0<<CPOL)|(0<<CPHA);
00119 #ifdef U8G_HW_SPI_2X
00120       SPSR = (1 << SPI2X);  /* double speed, issue 89 */
00121 #endif
00122 
00123       break;
00124     
00125     case U8G_COM_MSG_ADDRESS:                     /* define cmd (arg_val = 0) or data mode (arg_val = 1) */
00126       u8g_SetPILevel(u8g, U8G_PI_A0, arg_val);
00127       break;
00128 
00129     case U8G_COM_MSG_CHIP_SELECT:
00130       
00131       if ( arg_val == 0 )
00132       {
00133         /* disable */
00134         u8g_SetPILevel(u8g, U8G_PI_CS, 1);
00135       }
00136       else
00137       {
00138         PORTB &= ~_BV(5);        /* SCK = 0 */
00139         /* enable */
00140         u8g_SetPILevel(u8g, U8G_PI_CS, 0); /* CS = 0 (low active) */
00141       }
00142       
00143       break;
00144       
00145     case U8G_COM_MSG_RESET:
00146       u8g_SetPILevel(u8g, U8G_PI_RESET, arg_val);
00147       break;
00148     
00149     case U8G_COM_MSG_WRITE_BYTE:
00150       u8g_atmega_spi_out(arg_val);
00151       break;
00152     
00153     case U8G_COM_MSG_WRITE_SEQ:
00154       {
00155         register uint8_t *ptr = arg_ptr;
00156         while( arg_val > 0 )
00157         {
00158           u8g_atmega_spi_out(*ptr++);
00159           arg_val--;
00160         }
00161       }
00162       break;
00163     case U8G_COM_MSG_WRITE_SEQ_P:
00164       {
00165         register uint8_t *ptr = arg_ptr;
00166         while( arg_val > 0 )
00167         {
00168           u8g_atmega_spi_out(u8g_pgm_read(ptr));
00169           ptr++;
00170           arg_val--;
00171         }
00172       }
00173       break;
00174   }
00175   return 1;
00176 }
00177 
00178 #else
00179 
00180 uint8_t u8g_com_atmega_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
00181 {
00182   return 1;
00183 }
00184 
00185 #endif
00186 
00187 
00188