david dicarlo / mbed-src-FLL48

mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).

Fork of mbed-src by mbed official

The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h

targets/hal/TARGET_NXP/TARGET_LPC11XX/gpio_irq_api.c@20:4263a77256ae, 2013-09-10 (annotated)

Committer:
bogdanm
Date:
Tue Sep 10 15:14:19 2013 +0300
Revision:
20:4263a77256ae
Parent:
19:398f4c622e1b 
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 19:398f4c622e1b 1 /* mbed Microcontroller Library
bogdanm 19:398f4c622e1b 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 19:398f4c622e1b 3 *
bogdanm 19:398f4c622e1b 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 19:398f4c622e1b 5 * you may not use this file except in compliance with the License.
bogdanm 19:398f4c622e1b 6 * You may obtain a copy of the License at
bogdanm 19:398f4c622e1b 7 *
bogdanm 19:398f4c622e1b 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 19:398f4c622e1b 9 *
bogdanm 19:398f4c622e1b 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 19:398f4c622e1b 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 19:398f4c622e1b 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 19:398f4c622e1b 13 * See the License for the specific language governing permissions and
bogdanm 19:398f4c622e1b 14 * limitations under the License.
bogdanm 19:398f4c622e1b 15 */
bogdanm 19:398f4c622e1b 16 #include <stddef.h>
bogdanm 19:398f4c622e1b 17 #include "cmsis.h"
bogdanm 19:398f4c622e1b 18 #include "gpio_irq_api.h"
bogdanm 19:398f4c622e1b 19 #include "error.h"
bogdanm 19:398f4c622e1b 20 #include "gpio_api.h"
bogdanm 19:398f4c622e1b 21
bogdanm 20:4263a77256ae 22 // The chip is capable of 42 GPIO interrupts.
bogdanm 20:4263a77256ae 23 // PIO0_0..PIO0_11, PIO1_0..PIO1_11, PIO2_0..PIO2_11, PIO3_0..PIO3_5
bogdanm 20:4263a77256ae 24 #define CHANNEL_NUM 42
bogdanm 19:398f4c622e1b 25
bogdanm 19:398f4c622e1b 26 static uint32_t channel_ids[CHANNEL_NUM] = {0};
bogdanm 19:398f4c622e1b 27 static gpio_irq_handler irq_handler;
bogdanm 19:398f4c622e1b 28
bogdanm 20:4263a77256ae 29 static inline int numofbits(uint32_t bits)
bogdanm 20:4263a77256ae 30 {
bogdanm 20:4263a77256ae 31 // Count number of bits
bogdanm 20:4263a77256ae 32 bits = (bits & 0x55555555) + (bits >> 1 & 0x55555555);
bogdanm 20:4263a77256ae 33 bits = (bits & 0x33333333) + (bits >> 2 & 0x33333333);
bogdanm 20:4263a77256ae 34 bits = (bits & 0x0f0f0f0f) + (bits >> 4 & 0x0f0f0f0f);
bogdanm 20:4263a77256ae 35 bits = (bits & 0x00ff00ff) + (bits >> 8 & 0x00ff00ff);
bogdanm 20:4263a77256ae 36 return (bits & 0x0000ffff) + (bits >>16 & 0x0000ffff);
bogdanm 20:4263a77256ae 37 }
bogdanm 20:4263a77256ae 38
bogdanm 20:4263a77256ae 39 static inline void handle_interrupt_in(uint32_t port) {
bogdanm 19:398f4c622e1b 40 // Find out whether the interrupt has been triggered by a high or low value...
bogdanm 19:398f4c622e1b 41 // As the LPC1114 doesn't have a specific register for this, we'll just have to read
bogdanm 19:398f4c622e1b 42 // the level of the pin as if it were just a normal input...
bogdanm 20:4263a77256ae 43
bogdanm 20:4263a77256ae 44 uint32_t channel;
bogdanm 20:4263a77256ae 45
bogdanm 19:398f4c622e1b 46 // Get the number of the pin being used and the port typedef
bogdanm 20:4263a77256ae 47 LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (port * 0x10000)));
bogdanm 20:4263a77256ae 48
bogdanm 20:4263a77256ae 49 // Get index of function table from Mask Interrupt Status register
bogdanm 20:4263a77256ae 50 channel = numofbits(port_reg->MIS - 1);
bogdanm 20:4263a77256ae 51
bogdanm 20:4263a77256ae 52 if (port_reg->MIS & port_reg->IBE) {
bogdanm 20:4263a77256ae 53 // both edge, read the level of pin
bogdanm 20:4263a77256ae 54 if ((port_reg->DATA & port_reg->MIS) != 0)
bogdanm 19:398f4c622e1b 55 irq_handler(channel_ids[channel], IRQ_RISE);
bogdanm 19:398f4c622e1b 56 else
bogdanm 19:398f4c622e1b 57 irq_handler(channel_ids[channel], IRQ_FALL);
bogdanm 19:398f4c622e1b 58 }
bogdanm 20:4263a77256ae 59 else if (port_reg->MIS & port_reg->IEV) {
bogdanm 20:4263a77256ae 60 irq_handler(channel_ids[channel], IRQ_RISE);
bogdanm 20:4263a77256ae 61 }
bogdanm 20:4263a77256ae 62 else {
bogdanm 20:4263a77256ae 63 irq_handler(channel_ids[channel], IRQ_FALL);
bogdanm 20:4263a77256ae 64 }
bogdanm 19:398f4c622e1b 65
bogdanm 19:398f4c622e1b 66 // Clear the interrupt...
bogdanm 20:4263a77256ae 67 port_reg->IC = port_reg->MIS;
bogdanm 19:398f4c622e1b 68 }
bogdanm 19:398f4c622e1b 69
bogdanm 19:398f4c622e1b 70 void gpio_irq0(void) {handle_interrupt_in(0);}
bogdanm 19:398f4c622e1b 71 void gpio_irq1(void) {handle_interrupt_in(1);}
bogdanm 19:398f4c622e1b 72 void gpio_irq2(void) {handle_interrupt_in(2);}
bogdanm 19:398f4c622e1b 73 void gpio_irq3(void) {handle_interrupt_in(3);}
bogdanm 19:398f4c622e1b 74
bogdanm 19:398f4c622e1b 75 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
bogdanm 20:4263a77256ae 76 int channel;
bogdanm 20:4263a77256ae 77 uint32_t port_num;
bogdanm 20:4263a77256ae 78
bogdanm 19:398f4c622e1b 79 if (pin == NC) return -1;
bogdanm 19:398f4c622e1b 80
bogdanm 19:398f4c622e1b 81 // Firstly, we'll put some data in *obj so we can keep track of stuff.
bogdanm 19:398f4c622e1b 82 obj->pin = pin;
bogdanm 20:4263a77256ae 83
bogdanm 20:4263a77256ae 84 // Set the handler to be the pointer at the top...
bogdanm 20:4263a77256ae 85 irq_handler = handler;
bogdanm 20:4263a77256ae 86
bogdanm 19:398f4c622e1b 87 // Which port are we using?
bogdanm 20:4263a77256ae 88 port_num = ((pin & 0xF000) >> PORT_SHIFT);
bogdanm 20:4263a77256ae 89
bogdanm 20:4263a77256ae 90 switch (port_num) {
bogdanm 20:4263a77256ae 91 case 0:
bogdanm 19:398f4c622e1b 92 NVIC_SetVector(EINT0_IRQn, (uint32_t)gpio_irq0);
bogdanm 19:398f4c622e1b 93 NVIC_EnableIRQ(EINT0_IRQn);
bogdanm 19:398f4c622e1b 94 break;
bogdanm 20:4263a77256ae 95 case 1:
bogdanm 19:398f4c622e1b 96 NVIC_SetVector(EINT1_IRQn, (uint32_t)gpio_irq1);
bogdanm 19:398f4c622e1b 97 NVIC_EnableIRQ(EINT1_IRQn);
bogdanm 19:398f4c622e1b 98 break;
bogdanm 20:4263a77256ae 99 case 2:
bogdanm 19:398f4c622e1b 100 NVIC_SetVector(EINT2_IRQn, (uint32_t)gpio_irq2);
bogdanm 19:398f4c622e1b 101 NVIC_EnableIRQ(EINT2_IRQn);
bogdanm 19:398f4c622e1b 102 break;
bogdanm 20:4263a77256ae 103 case 3:
bogdanm 19:398f4c622e1b 104 NVIC_SetVector(EINT3_IRQn, (uint32_t)gpio_irq3);
bogdanm 19:398f4c622e1b 105 NVIC_EnableIRQ(EINT3_IRQn);
bogdanm 19:398f4c622e1b 106 break;
bogdanm 19:398f4c622e1b 107 default:
bogdanm 20:4263a77256ae 108 return -1;
bogdanm 19:398f4c622e1b 109 }
bogdanm 20:4263a77256ae 110
bogdanm 20:4263a77256ae 111 // Generate index of function pointer table
bogdanm 20:4263a77256ae 112 // PIO0_0 - PIO0_11 : 0..11
bogdanm 20:4263a77256ae 113 // PIO1_0 - PIO1_11 : 12..23
bogdanm 20:4263a77256ae 114 // PIO2_0 - PIO2_11 : 24..35
bogdanm 20:4263a77256ae 115 // PIO3_0 - PIO3_5 : 36..41
bogdanm 20:4263a77256ae 116 channel = (port_num * 12) + ((pin & 0x0F00) >> PIN_SHIFT);
bogdanm 20:4263a77256ae 117
bogdanm 19:398f4c622e1b 118 channel_ids[channel] = id;
bogdanm 19:398f4c622e1b 119 obj->ch = channel;
bogdanm 20:4263a77256ae 120
bogdanm 19:398f4c622e1b 121 return 0;
bogdanm 19:398f4c622e1b 122 }
bogdanm 19:398f4c622e1b 123
bogdanm 19:398f4c622e1b 124 void gpio_irq_free(gpio_irq_t *obj) {
bogdanm 19:398f4c622e1b 125 channel_ids[obj->ch] = 0;
bogdanm 19:398f4c622e1b 126 }
bogdanm 19:398f4c622e1b 127
bogdanm 19:398f4c622e1b 128 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
bogdanm 19:398f4c622e1b 129 // Firstly, check if there is an existing event stored...
bogdanm 19:398f4c622e1b 130
bogdanm 19:398f4c622e1b 131 LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (((obj->pin & 0xF000) >> PORT_SHIFT) * 0x10000)));
bogdanm 19:398f4c622e1b 132
bogdanm 19:398f4c622e1b 133 // Need to get the pin number of the pin, not the value of the enum
bogdanm 20:4263a77256ae 134 uint32_t pin_num = (1 << ((obj->pin & 0x0f00) >> PIN_SHIFT));
bogdanm 19:398f4c622e1b 135
bogdanm 20:4263a77256ae 136 // Clear
bogdanm 20:4263a77256ae 137 port_reg->IC |= pin_num;
bogdanm 20:4263a77256ae 138
bogdanm 20:4263a77256ae 139 // Make it edge sensitive.
bogdanm 20:4263a77256ae 140 port_reg->IS &= ~pin_num;
bogdanm 19:398f4c622e1b 141
bogdanm 20:4263a77256ae 142 if ( (port_reg->IE & pin_num) != 0) {
bogdanm 20:4263a77256ae 143 // We have an event.
bogdanm 20:4263a77256ae 144 // Enable both edge interrupts.
bogdanm 19:398f4c622e1b 145
bogdanm 19:398f4c622e1b 146 if (enable) {
bogdanm 20:4263a77256ae 147 port_reg->IBE |= pin_num;
bogdanm 20:4263a77256ae 148 port_reg->IE |= pin_num;
bogdanm 19:398f4c622e1b 149 }
bogdanm 19:398f4c622e1b 150 else {
bogdanm 19:398f4c622e1b 151 // These all need to be opposite, to reenable the other one.
bogdanm 20:4263a77256ae 152 port_reg->IBE &= ~pin_num;
bogdanm 19:398f4c622e1b 153
bogdanm 19:398f4c622e1b 154 if (event == IRQ_RISE)
bogdanm 20:4263a77256ae 155 port_reg->IEV &= ~pin_num;
bogdanm 19:398f4c622e1b 156 else
bogdanm 20:4263a77256ae 157 port_reg->IEV |= pin_num;
bogdanm 19:398f4c622e1b 158
bogdanm 20:4263a77256ae 159 port_reg->IE |= pin_num;
bogdanm 19:398f4c622e1b 160 }
bogdanm 19:398f4c622e1b 161 }
bogdanm 19:398f4c622e1b 162 else {
bogdanm 19:398f4c622e1b 163 // One edge
bogdanm 20:4263a77256ae 164 port_reg->IBE &= ~pin_num;
bogdanm 19:398f4c622e1b 165 // Rising/falling?
bogdanm 19:398f4c622e1b 166 if (event == IRQ_RISE)
bogdanm 20:4263a77256ae 167 port_reg->IEV |= pin_num;
bogdanm 19:398f4c622e1b 168 else
bogdanm 20:4263a77256ae 169 port_reg->IEV &= ~pin_num;
bogdanm 20:4263a77256ae 170
bogdanm 20:4263a77256ae 171 if (enable) {
bogdanm 20:4263a77256ae 172 port_reg->IE |= pin_num;
bogdanm 20:4263a77256ae 173 }
bogdanm 19:398f4c622e1b 174 }
bogdanm 19:398f4c622e1b 175
bogdanm 19:398f4c622e1b 176 }