david dicarlo / mbed-src-FLL48

mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).

Fork of mbed-src by mbed official

The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h

targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s@20:4263a77256ae, 2013-09-10 (annotated)

Committer:
bogdanm
Date:
Tue Sep 10 15:14:19 2013 +0300
Revision:
20:4263a77256ae
Parent:
targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s@13:0645d8841f51 
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 ;/*****************************************************************************
emilmont 10:3bc89ef62ce7 2 ; * @file: startup_LPC8xx.s
emilmont 10:3bc89ef62ce7 3 ; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
emilmont 10:3bc89ef62ce7 4 ; * for the NXP LPC8xx Device Series
emilmont 10:3bc89ef62ce7 5 ; * @version: V1.0
emilmont 10:3bc89ef62ce7 6 ; * @date: 16. Aug. 2012
emilmont 10:3bc89ef62ce7 7 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
emilmont 10:3bc89ef62ce7 8 ; *
emilmont 10:3bc89ef62ce7 9 ; * Copyright (C) 2012 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 10 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
emilmont 10:3bc89ef62ce7 11 ; * processor based microcontrollers. This file can be freely distributed
emilmont 10:3bc89ef62ce7 12 ; * within development tools that are supporting such ARM based processors.
emilmont 10:3bc89ef62ce7 13 ; *
emilmont 10:3bc89ef62ce7 14 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 10:3bc89ef62ce7 15 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 10:3bc89ef62ce7 16 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 10:3bc89ef62ce7 17 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 10:3bc89ef62ce7 18 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 10:3bc89ef62ce7 19 ; *
emilmont 10:3bc89ef62ce7 20 ; *****************************************************************************/
emilmont 10:3bc89ef62ce7 21
emilmont 10:3bc89ef62ce7 22
emilmont 10:3bc89ef62ce7 23 ; <h> Stack Configuration
emilmont 10:3bc89ef62ce7 24 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
emilmont 10:3bc89ef62ce7 25 ; </h>
emilmont 10:3bc89ef62ce7 26
emilmont 10:3bc89ef62ce7 27 Stack_Size EQU 0x00000200
emilmont 10:3bc89ef62ce7 28
emilmont 10:3bc89ef62ce7 29 AREA STACK, NOINIT, READWRITE, ALIGN=3
emilmont 10:3bc89ef62ce7 30 EXPORT __initial_sp
emilmont 10:3bc89ef62ce7 31
emilmont 10:3bc89ef62ce7 32 Stack_Mem SPACE Stack_Size
emilmont 10:3bc89ef62ce7 33 __initial_sp EQU 0x10001000
emilmont 10:3bc89ef62ce7 34
emilmont 10:3bc89ef62ce7 35
emilmont 10:3bc89ef62ce7 36 ; <h> Heap Configuration
emilmont 10:3bc89ef62ce7 37 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
emilmont 10:3bc89ef62ce7 38 ; </h>
emilmont 10:3bc89ef62ce7 39
emilmont 10:3bc89ef62ce7 40 Heap_Size EQU 0x00000000
emilmont 10:3bc89ef62ce7 41
emilmont 10:3bc89ef62ce7 42 AREA HEAP, NOINIT, READWRITE, ALIGN=3
emilmont 10:3bc89ef62ce7 43 EXPORT __heap_base
emilmont 10:3bc89ef62ce7 44 EXPORT __heap_limit
emilmont 10:3bc89ef62ce7 45
emilmont 10:3bc89ef62ce7 46 __heap_base
emilmont 10:3bc89ef62ce7 47 Heap_Mem SPACE Heap_Size
emilmont 10:3bc89ef62ce7 48 __heap_limit
emilmont 10:3bc89ef62ce7 49
emilmont 10:3bc89ef62ce7 50 PRESERVE8
emilmont 10:3bc89ef62ce7 51 THUMB
emilmont 10:3bc89ef62ce7 52
emilmont 10:3bc89ef62ce7 53
emilmont 10:3bc89ef62ce7 54 ; Vector Table Mapped to Address 0 at Reset
emilmont 10:3bc89ef62ce7 55
emilmont 10:3bc89ef62ce7 56 AREA RESET, DATA, READONLY
emilmont 10:3bc89ef62ce7 57 EXPORT __Vectors
emilmont 10:3bc89ef62ce7 58
emilmont 10:3bc89ef62ce7 59 __Vectors DCD __initial_sp ; Top of Stack
emilmont 10:3bc89ef62ce7 60 DCD Reset_Handler ; Reset Handler
emilmont 10:3bc89ef62ce7 61 DCD NMI_Handler ; NMI Handler
emilmont 10:3bc89ef62ce7 62 DCD HardFault_Handler ; Hard Fault Handler
emilmont 10:3bc89ef62ce7 63 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 64 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 65 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 66 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 67 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 68 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 69 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 70 DCD SVC_Handler ; SVCall Handler
emilmont 10:3bc89ef62ce7 71 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 72 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 73 DCD PendSV_Handler ; PendSV Handler
emilmont 10:3bc89ef62ce7 74 DCD SysTick_Handler ; SysTick Handler
emilmont 10:3bc89ef62ce7 75
emilmont 10:3bc89ef62ce7 76 ; External Interrupts
emilmont 10:3bc89ef62ce7 77 DCD SPI0_IRQHandler ; SPI0 controller
emilmont 10:3bc89ef62ce7 78 DCD SPI1_IRQHandler ; SPI1 controller
emilmont 10:3bc89ef62ce7 79 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 80 DCD UART0_IRQHandler ; UART0
emilmont 10:3bc89ef62ce7 81 DCD UART1_IRQHandler ; UART1
emilmont 10:3bc89ef62ce7 82 DCD UART2_IRQHandler ; UART2
emilmont 10:3bc89ef62ce7 83 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 84 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 85 DCD I2C_IRQHandler ; I2C controller
emilmont 10:3bc89ef62ce7 86 DCD SCT_IRQHandler ; Smart Counter Timer
emilmont 10:3bc89ef62ce7 87 DCD MRT_IRQHandler ; Multi-Rate Timer
emilmont 10:3bc89ef62ce7 88 DCD CMP_IRQHandler ; Comparator
emilmont 10:3bc89ef62ce7 89 DCD WDT_IRQHandler ; PIO1 (0:11)
emilmont 10:3bc89ef62ce7 90 DCD BOD_IRQHandler ; Brown Out Detect
emilmont 10:3bc89ef62ce7 91 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 92 DCD WKT_IRQHandler ; Wakeup timer
emilmont 10:3bc89ef62ce7 93 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 94 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 95 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 96 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 97 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 98 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 99 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 100 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 101 DCD PININT0_IRQHandler ; PIO INT0
emilmont 10:3bc89ef62ce7 102 DCD PININT1_IRQHandler ; PIO INT1
emilmont 10:3bc89ef62ce7 103 DCD PININT2_IRQHandler ; PIO INT2
emilmont 10:3bc89ef62ce7 104 DCD PININT3_IRQHandler ; PIO INT3
emilmont 10:3bc89ef62ce7 105 DCD PININT4_IRQHandler ; PIO INT4
emilmont 10:3bc89ef62ce7 106 DCD PININT5_IRQHandler ; PIO INT5
emilmont 10:3bc89ef62ce7 107 DCD PININT6_IRQHandler ; PIO INT6
emilmont 10:3bc89ef62ce7 108 DCD PININT7_IRQHandler ; PIO INT7
emilmont 10:3bc89ef62ce7 109
emilmont 10:3bc89ef62ce7 110
emilmont 10:3bc89ef62ce7 111 IF :LNOT::DEF:NO_CRP
emilmont 10:3bc89ef62ce7 112 AREA |.ARM.__at_0x02FC|, CODE, READONLY
emilmont 10:3bc89ef62ce7 113 CRP_Key DCD 0xFFFFFFFF
emilmont 10:3bc89ef62ce7 114 ENDIF
emilmont 10:3bc89ef62ce7 115
emilmont 10:3bc89ef62ce7 116
emilmont 10:3bc89ef62ce7 117 AREA |.text|, CODE, READONLY
emilmont 10:3bc89ef62ce7 118
emilmont 10:3bc89ef62ce7 119
emilmont 10:3bc89ef62ce7 120 ; Reset Handler
emilmont 10:3bc89ef62ce7 121
emilmont 10:3bc89ef62ce7 122 Reset_Handler PROC
emilmont 10:3bc89ef62ce7 123 EXPORT Reset_Handler [WEAK]
emilmont 10:3bc89ef62ce7 124 IMPORT SystemInit
emilmont 10:3bc89ef62ce7 125 IMPORT __main
emilmont 10:3bc89ef62ce7 126 LDR R0, =SystemInit
emilmont 10:3bc89ef62ce7 127 BLX R0
emilmont 10:3bc89ef62ce7 128 LDR R0, =__main
emilmont 10:3bc89ef62ce7 129 BX R0
emilmont 10:3bc89ef62ce7 130 ENDP
emilmont 10:3bc89ef62ce7 131
emilmont 10:3bc89ef62ce7 132
emilmont 10:3bc89ef62ce7 133 ; Dummy Exception Handlers (infinite loops which can be modified)
emilmont 10:3bc89ef62ce7 134 ; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled
emilmont 10:3bc89ef62ce7 135 ; for particular peripheral.
emilmont 10:3bc89ef62ce7 136 ;NMI_Handler PROC
emilmont 10:3bc89ef62ce7 137 ; EXPORT NMI_Handler [WEAK]
emilmont 10:3bc89ef62ce7 138 ; B .
emilmont 10:3bc89ef62ce7 139 ; ENDP
emilmont 10:3bc89ef62ce7 140 HardFault_Handler\
emilmont 10:3bc89ef62ce7 141 PROC
emilmont 10:3bc89ef62ce7 142 EXPORT HardFault_Handler [WEAK]
emilmont 10:3bc89ef62ce7 143 B .
emilmont 10:3bc89ef62ce7 144 ENDP
emilmont 10:3bc89ef62ce7 145 SVC_Handler PROC
emilmont 10:3bc89ef62ce7 146 EXPORT SVC_Handler [WEAK]
emilmont 10:3bc89ef62ce7 147 B .
emilmont 10:3bc89ef62ce7 148 ENDP
emilmont 10:3bc89ef62ce7 149 PendSV_Handler PROC
emilmont 10:3bc89ef62ce7 150 EXPORT PendSV_Handler [WEAK]
emilmont 10:3bc89ef62ce7 151 B .
emilmont 10:3bc89ef62ce7 152 ENDP
emilmont 10:3bc89ef62ce7 153 SysTick_Handler PROC
emilmont 10:3bc89ef62ce7 154 EXPORT SysTick_Handler [WEAK]
emilmont 10:3bc89ef62ce7 155 B .
emilmont 10:3bc89ef62ce7 156 ENDP
emilmont 10:3bc89ef62ce7 157
emilmont 10:3bc89ef62ce7 158 Default_Handler PROC
emilmont 10:3bc89ef62ce7 159
emilmont 10:3bc89ef62ce7 160 EXPORT NMI_Handler [WEAK]
emilmont 10:3bc89ef62ce7 161 EXPORT SPI0_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 162 EXPORT SPI1_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 163 EXPORT UART0_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 164 EXPORT UART1_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 165 EXPORT UART2_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 166 EXPORT I2C_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 167 EXPORT SCT_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 168 EXPORT MRT_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 169 EXPORT CMP_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 170 EXPORT WDT_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 171 EXPORT BOD_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 172
emilmont 10:3bc89ef62ce7 173 EXPORT WKT_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 174
emilmont 10:3bc89ef62ce7 175 EXPORT PININT0_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 176 EXPORT PININT1_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 177 EXPORT PININT2_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 178 EXPORT PININT3_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 179 EXPORT PININT4_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 180 EXPORT PININT5_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 181 EXPORT PININT6_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 182 EXPORT PININT7_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 183
emilmont 10:3bc89ef62ce7 184 NMI_Handler
emilmont 10:3bc89ef62ce7 185 SPI0_IRQHandler
emilmont 10:3bc89ef62ce7 186 SPI1_IRQHandler
emilmont 10:3bc89ef62ce7 187 UART0_IRQHandler
emilmont 10:3bc89ef62ce7 188 UART1_IRQHandler
emilmont 10:3bc89ef62ce7 189 UART2_IRQHandler
emilmont 10:3bc89ef62ce7 190 I2C_IRQHandler
emilmont 10:3bc89ef62ce7 191 SCT_IRQHandler
emilmont 10:3bc89ef62ce7 192 MRT_IRQHandler
emilmont 10:3bc89ef62ce7 193 CMP_IRQHandler
emilmont 10:3bc89ef62ce7 194 WDT_IRQHandler
emilmont 10:3bc89ef62ce7 195 BOD_IRQHandler
emilmont 10:3bc89ef62ce7 196 WKT_IRQHandler
emilmont 10:3bc89ef62ce7 197 PININT0_IRQHandler
emilmont 10:3bc89ef62ce7 198 PININT1_IRQHandler
emilmont 10:3bc89ef62ce7 199 PININT2_IRQHandler
emilmont 10:3bc89ef62ce7 200 PININT3_IRQHandler
emilmont 10:3bc89ef62ce7 201 PININT4_IRQHandler
emilmont 10:3bc89ef62ce7 202 PININT5_IRQHandler
emilmont 10:3bc89ef62ce7 203 PININT6_IRQHandler
emilmont 10:3bc89ef62ce7 204 PININT7_IRQHandler
emilmont 10:3bc89ef62ce7 205
emilmont 10:3bc89ef62ce7 206 B .
emilmont 10:3bc89ef62ce7 207
emilmont 10:3bc89ef62ce7 208 ENDP
emilmont 10:3bc89ef62ce7 209
emilmont 10:3bc89ef62ce7 210 ALIGN
emilmont 10:3bc89ef62ce7 211 END