mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).
Fork of mbed-src by
The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h
targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c@20:4263a77256ae, 2013-09-10 (annotated)
- Committer:
- bogdanm
- Date:
- Tue Sep 10 15:14:19 2013 +0300
- Revision:
- 20:4263a77256ae
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 20:4263a77256ae | 1 | /* |
bogdanm | 20:4263a77256ae | 2 | * @brief LPC43xx System Initialization |
bogdanm | 20:4263a77256ae | 3 | * |
bogdanm | 20:4263a77256ae | 4 | * @note |
bogdanm | 20:4263a77256ae | 5 | * Copyright(C) NXP Semiconductors, 2012 |
bogdanm | 20:4263a77256ae | 6 | * All rights reserved. |
bogdanm | 20:4263a77256ae | 7 | * |
bogdanm | 20:4263a77256ae | 8 | * @par |
bogdanm | 20:4263a77256ae | 9 | * Software that is described herein is for illustrative purposes only |
bogdanm | 20:4263a77256ae | 10 | * which provides customers with programming information regarding the |
bogdanm | 20:4263a77256ae | 11 | * LPC products. This software is supplied "AS IS" without any warranties of |
bogdanm | 20:4263a77256ae | 12 | * any kind, and NXP Semiconductors and its licensor disclaim any and |
bogdanm | 20:4263a77256ae | 13 | * all warranties, express or implied, including all implied warranties of |
bogdanm | 20:4263a77256ae | 14 | * merchantability, fitness for a particular purpose and non-infringement of |
bogdanm | 20:4263a77256ae | 15 | * intellectual property rights. NXP Semiconductors assumes no responsibility |
bogdanm | 20:4263a77256ae | 16 | * or liability for the use of the software, conveys no license or rights under any |
bogdanm | 20:4263a77256ae | 17 | * patent, copyright, mask work right, or any other intellectual property rights in |
bogdanm | 20:4263a77256ae | 18 | * or to any products. NXP Semiconductors reserves the right to make changes |
bogdanm | 20:4263a77256ae | 19 | * in the software without notification. NXP Semiconductors also makes no |
bogdanm | 20:4263a77256ae | 20 | * representation or warranty that such application will be suitable for the |
bogdanm | 20:4263a77256ae | 21 | * specified use without further testing or modification. |
bogdanm | 20:4263a77256ae | 22 | * |
bogdanm | 20:4263a77256ae | 23 | * @par |
bogdanm | 20:4263a77256ae | 24 | * Permission to use, copy, modify, and distribute this software and its |
bogdanm | 20:4263a77256ae | 25 | * documentation is hereby granted, under NXP Semiconductors' and its |
bogdanm | 20:4263a77256ae | 26 | * licensor's relevant copyrights in the software, without fee, provided that it |
bogdanm | 20:4263a77256ae | 27 | * is used in conjunction with NXP Semiconductors microcontrollers. This |
bogdanm | 20:4263a77256ae | 28 | * copyright, permission, and disclaimer notice must appear in all copies of |
bogdanm | 20:4263a77256ae | 29 | * this code. |
bogdanm | 20:4263a77256ae | 30 | * |
bogdanm | 20:4263a77256ae | 31 | * Modified by Micromint USA <support@micromint.com> |
bogdanm | 20:4263a77256ae | 32 | */ |
bogdanm | 20:4263a77256ae | 33 | #include "LPC43xx.h" |
bogdanm | 20:4263a77256ae | 34 | |
bogdanm | 20:4263a77256ae | 35 | #define COUNT_OF(a) (sizeof(a)/sizeof(a[0])) |
bogdanm | 20:4263a77256ae | 36 | |
bogdanm | 20:4263a77256ae | 37 | /* Clock variables */ |
bogdanm | 20:4263a77256ae | 38 | //uint32_t SystemCoreClock = CRYSTAL_MAIN_FREQ_IN; /*!< System Clock Frequency (Core Clock)*/ |
bogdanm | 20:4263a77256ae | 39 | uint32_t SystemCoreClock = 204000000; |
bogdanm | 20:4263a77256ae | 40 | |
bogdanm | 20:4263a77256ae | 41 | #if !defined(CORE_M0) |
bogdanm | 20:4263a77256ae | 42 | /* SCU pin definitions for pin muxing */ |
bogdanm | 20:4263a77256ae | 43 | typedef struct { |
bogdanm | 20:4263a77256ae | 44 | __IO uint32_t *reg; /* SCU register address */ |
bogdanm | 20:4263a77256ae | 45 | uint16_t mode; /* SCU pin mode and function */ |
bogdanm | 20:4263a77256ae | 46 | } PINMUX_GRP_T; |
bogdanm | 20:4263a77256ae | 47 | |
bogdanm | 20:4263a77256ae | 48 | /* Local functions */ |
bogdanm | 20:4263a77256ae | 49 | static void SystemCoreClockUpdate(void); |
bogdanm | 20:4263a77256ae | 50 | static void SystemSetupClock(void); |
bogdanm | 20:4263a77256ae | 51 | static void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n); |
bogdanm | 20:4263a77256ae | 52 | static void SystemSetupMemory(void); |
bogdanm | 20:4263a77256ae | 53 | static void WaitUs(uint32_t us); |
bogdanm | 20:4263a77256ae | 54 | |
bogdanm | 20:4263a77256ae | 55 | /* Pins to initialize before clocks are configured */ |
bogdanm | 20:4263a77256ae | 56 | static const PINMUX_GRP_T pre_clock_mux[] = { |
bogdanm | 20:4263a77256ae | 57 | /* SPIFI pins */ |
bogdanm | 20:4263a77256ae | 58 | {SCU_REG(0x3, 3), (SCU_PINIO_FAST | 0x3)}, // P3_3 SPIFI CLK |
bogdanm | 20:4263a77256ae | 59 | {SCU_REG(0x3, 4), (SCU_PINIO_FAST | 0x3)}, // P3_4 SPIFI D3 |
bogdanm | 20:4263a77256ae | 60 | {SCU_REG(0x3, 5), (SCU_PINIO_FAST | 0x3)}, // P3_5 SPIFI D2 |
bogdanm | 20:4263a77256ae | 61 | {SCU_REG(0x3, 6), (SCU_PINIO_FAST | 0x3)}, // P3_6 SPIFI D1 |
bogdanm | 20:4263a77256ae | 62 | {SCU_REG(0x3, 7), (SCU_PINIO_FAST | 0x3)}, // P3_7 SPIFI D0 |
bogdanm | 20:4263a77256ae | 63 | {SCU_REG(0x3, 8), (SCU_PINIO_FAST | 0x3)} // P3_8 SPIFI CS/SSEL |
bogdanm | 20:4263a77256ae | 64 | }; |
bogdanm | 20:4263a77256ae | 65 | |
bogdanm | 20:4263a77256ae | 66 | /* Pins to initialize after clocks are configured */ |
bogdanm | 20:4263a77256ae | 67 | static const PINMUX_GRP_T post_clock_mux[] = { |
bogdanm | 20:4263a77256ae | 68 | /* Boot pins */ |
bogdanm | 20:4263a77256ae | 69 | {SCU_REG(0x1, 1), (SCU_PINIO_FAST | 0x0)}, // P1_1 BOOT0 |
bogdanm | 20:4263a77256ae | 70 | {SCU_REG(0x1, 2), (SCU_PINIO_FAST | 0x0)}, // P1_2 BOOT1 |
bogdanm | 20:4263a77256ae | 71 | {SCU_REG(0x2, 8), (SCU_PINIO_FAST | 0x0)}, // P2_8 BOOT2 |
bogdanm | 20:4263a77256ae | 72 | {SCU_REG(0x2, 9), (SCU_PINIO_FAST | 0x0)} // P2_9 BOOT3 |
bogdanm | 20:4263a77256ae | 73 | }; |
bogdanm | 20:4263a77256ae | 74 | #endif /* !defined(CORE_M0) */ |
bogdanm | 20:4263a77256ae | 75 | |
bogdanm | 20:4263a77256ae | 76 | /* |
bogdanm | 20:4263a77256ae | 77 | * SystemInit() - Initialize the system |
bogdanm | 20:4263a77256ae | 78 | */ |
bogdanm | 20:4263a77256ae | 79 | void SystemInit(void) |
bogdanm | 20:4263a77256ae | 80 | { |
bogdanm | 20:4263a77256ae | 81 | #if !defined(CORE_M0) |
bogdanm | 20:4263a77256ae | 82 | unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08; |
bogdanm | 20:4263a77256ae | 83 | |
bogdanm | 20:4263a77256ae | 84 | #if defined(__ARMCC_VERSION) |
bogdanm | 20:4263a77256ae | 85 | extern void *__Vectors; |
bogdanm | 20:4263a77256ae | 86 | |
bogdanm | 20:4263a77256ae | 87 | *pSCB_VTOR = (unsigned int) &__Vectors; |
bogdanm | 20:4263a77256ae | 88 | #elif defined(__IAR_SYSTEMS_ICC__) |
bogdanm | 20:4263a77256ae | 89 | extern void *__vector_table; |
bogdanm | 20:4263a77256ae | 90 | |
bogdanm | 20:4263a77256ae | 91 | *pSCB_VTOR = (unsigned int) &__vector_table; |
bogdanm | 20:4263a77256ae | 92 | #else /* defined(__GNUC__) and others */ |
bogdanm | 20:4263a77256ae | 93 | extern void *g_pfnVectors; |
bogdanm | 20:4263a77256ae | 94 | |
bogdanm | 20:4263a77256ae | 95 | *pSCB_VTOR = (unsigned int) &g_pfnVectors; |
bogdanm | 20:4263a77256ae | 96 | #endif |
bogdanm | 20:4263a77256ae | 97 | |
bogdanm | 20:4263a77256ae | 98 | #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1 |
bogdanm | 20:4263a77256ae | 99 | /* Initialize floating point */ |
bogdanm | 20:4263a77256ae | 100 | fpuInit(); |
bogdanm | 20:4263a77256ae | 101 | #endif |
bogdanm | 20:4263a77256ae | 102 | |
bogdanm | 20:4263a77256ae | 103 | SystemSetupPins(pre_clock_mux, COUNT_OF(pre_clock_mux)); /* Configure pins */ |
bogdanm | 20:4263a77256ae | 104 | |
bogdanm | 20:4263a77256ae | 105 | SystemSetupClock(); /* Configure processor and peripheral clocks */ |
bogdanm | 20:4263a77256ae | 106 | SystemSetupPins(post_clock_mux, COUNT_OF(post_clock_mux)); /* Configure pins */ |
bogdanm | 20:4263a77256ae | 107 | SystemSetupMemory(); /* Configure external memory */ |
bogdanm | 20:4263a77256ae | 108 | #endif /* !defined(CORE_M0) */ |
bogdanm | 20:4263a77256ae | 109 | |
bogdanm | 20:4263a77256ae | 110 | SystemCoreClockUpdate(); /* Update SystemCoreClock variable */ |
bogdanm | 20:4263a77256ae | 111 | } |
bogdanm | 20:4263a77256ae | 112 | |
bogdanm | 20:4263a77256ae | 113 | /* |
bogdanm | 20:4263a77256ae | 114 | * SystemCoreClockUpdate() - Update SystemCoreClock variable |
bogdanm | 20:4263a77256ae | 115 | */ |
bogdanm | 20:4263a77256ae | 116 | void SystemCoreClockUpdate(void) |
bogdanm | 20:4263a77256ae | 117 | { |
bogdanm | 20:4263a77256ae | 118 | } |
bogdanm | 20:4263a77256ae | 119 | |
bogdanm | 20:4263a77256ae | 120 | #if !defined(CORE_M0) |
bogdanm | 20:4263a77256ae | 121 | /* |
bogdanm | 20:4263a77256ae | 122 | * SystemSetupClock() - Set processor and peripheral clocks |
bogdanm | 20:4263a77256ae | 123 | */ |
bogdanm | 20:4263a77256ae | 124 | void SystemSetupClock(void) |
bogdanm | 20:4263a77256ae | 125 | { |
bogdanm | 20:4263a77256ae | 126 | #if (CLOCK_SETUP) |
bogdanm | 20:4263a77256ae | 127 | /* Switch main clock to Internal RC (IRC) */ |
bogdanm | 20:4263a77256ae | 128 | LPC_CGU->BASE_CLK[CLK_BASE_MX] = ((1 << 11) | (CLKIN_IRC << 24)); |
bogdanm | 20:4263a77256ae | 129 | |
bogdanm | 20:4263a77256ae | 130 | /* Enable the oscillator and wait 100 us */ |
bogdanm | 20:4263a77256ae | 131 | LPC_CGU->XTAL_OSC_CTRL = 0; |
bogdanm | 20:4263a77256ae | 132 | WaitUs(100); |
bogdanm | 20:4263a77256ae | 133 | |
bogdanm | 20:4263a77256ae | 134 | #if (SPIFI_INIT) |
bogdanm | 20:4263a77256ae | 135 | /* Switch IDIVA clock to IRC and connect to SPIFI clock */ |
bogdanm | 20:4263a77256ae | 136 | LPC_CGU->IDIV_CTRL[CLK_IDIV_A] = ((1 << 11) | (CLKIN_IRC << 24)); |
bogdanm | 20:4263a77256ae | 137 | LPC_CGU->BASE_CLK[CLK_BASE_SPIFI] = ((1 << 11) | (CLKIN_IDIVA << 24)); |
bogdanm | 20:4263a77256ae | 138 | #endif /* SPIFI_INIT */ |
bogdanm | 20:4263a77256ae | 139 | |
bogdanm | 20:4263a77256ae | 140 | /* Power down PLL1 */ |
bogdanm | 20:4263a77256ae | 141 | LPC_CGU->PLL1_CTRL |= 1; |
bogdanm | 20:4263a77256ae | 142 | |
bogdanm | 20:4263a77256ae | 143 | /* Change PLL1 to 108 Mhz (msel=9, 12 MHz*9=108 MHz) */ |
bogdanm | 20:4263a77256ae | 144 | // LPC_CGU->PLL1_CTRL = (DIRECT << 7) | (PSEL << 8) | (1 << 11) | (P(NSEL-1) << 12) | ((MSEL-1) << 16) | (CLKIN_PLL1 << 24); |
bogdanm | 20:4263a77256ae | 145 | LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (8 << 16) | (CLKIN_PLL1 << 24); |
bogdanm | 20:4263a77256ae | 146 | while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */ |
bogdanm | 20:4263a77256ae | 147 | WaitUs(100); |
bogdanm | 20:4263a77256ae | 148 | |
bogdanm | 20:4263a77256ae | 149 | /* Change PLL1 to 204 Mhz (msel=17, 12 MHz*17=204 MHz) */ |
bogdanm | 20:4263a77256ae | 150 | LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (16 << 16) | (CLKIN_PLL1 << 24); |
bogdanm | 20:4263a77256ae | 151 | while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */ |
bogdanm | 20:4263a77256ae | 152 | |
bogdanm | 20:4263a77256ae | 153 | /* Switch main clock to PLL1 */ |
bogdanm | 20:4263a77256ae | 154 | LPC_CGU->BASE_CLK[CLK_BASE_MX] = ((1 << 11) | (CLKIN_PLL1 << 24)); |
bogdanm | 20:4263a77256ae | 155 | SystemCoreClock = 204000000; |
bogdanm | 20:4263a77256ae | 156 | #endif /* CLOCK_SETUP */ |
bogdanm | 20:4263a77256ae | 157 | } |
bogdanm | 20:4263a77256ae | 158 | |
bogdanm | 20:4263a77256ae | 159 | /* |
bogdanm | 20:4263a77256ae | 160 | * SystemSetupPins() - Configure MCU pins |
bogdanm | 20:4263a77256ae | 161 | */ |
bogdanm | 20:4263a77256ae | 162 | void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n) |
bogdanm | 20:4263a77256ae | 163 | { |
bogdanm | 20:4263a77256ae | 164 | uint16_t i; |
bogdanm | 20:4263a77256ae | 165 | |
bogdanm | 20:4263a77256ae | 166 | for (i = 0; i < n; i++) { |
bogdanm | 20:4263a77256ae | 167 | *(mux[i].reg) = mux[i].mode; |
bogdanm | 20:4263a77256ae | 168 | } |
bogdanm | 20:4263a77256ae | 169 | } |
bogdanm | 20:4263a77256ae | 170 | |
bogdanm | 20:4263a77256ae | 171 | /* |
bogdanm | 20:4263a77256ae | 172 | * SystemSetupMemory() - Configure external memory |
bogdanm | 20:4263a77256ae | 173 | */ |
bogdanm | 20:4263a77256ae | 174 | void SystemSetupMemory(void) |
bogdanm | 20:4263a77256ae | 175 | { |
bogdanm | 20:4263a77256ae | 176 | #if (MEMORY_SETUP) |
bogdanm | 20:4263a77256ae | 177 | /* None required for boards without external memory */ |
bogdanm | 20:4263a77256ae | 178 | #endif /* MEMORY_SETUP */ |
bogdanm | 20:4263a77256ae | 179 | } |
bogdanm | 20:4263a77256ae | 180 | |
bogdanm | 20:4263a77256ae | 181 | #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1 |
bogdanm | 20:4263a77256ae | 182 | /* |
bogdanm | 20:4263a77256ae | 183 | * fpuInit() - Early initialization of the FPU |
bogdanm | 20:4263a77256ae | 184 | */ |
bogdanm | 20:4263a77256ae | 185 | void fpuInit(void) |
bogdanm | 20:4263a77256ae | 186 | { |
bogdanm | 20:4263a77256ae | 187 | // from ARM TRM manual: |
bogdanm | 20:4263a77256ae | 188 | // ; CPACR is located at address 0xE000ED88 |
bogdanm | 20:4263a77256ae | 189 | // LDR.W R0, =0xE000ED88 |
bogdanm | 20:4263a77256ae | 190 | // ; Read CPACR |
bogdanm | 20:4263a77256ae | 191 | // LDR R1, [R0] |
bogdanm | 20:4263a77256ae | 192 | // ; Set bits 20-23 to enable CP10 and CP11 coprocessors |
bogdanm | 20:4263a77256ae | 193 | // ORR R1, R1, #(0xF << 20) |
bogdanm | 20:4263a77256ae | 194 | // ; Write back the modified value to the CPACR |
bogdanm | 20:4263a77256ae | 195 | // STR R1, [R0] |
bogdanm | 20:4263a77256ae | 196 | |
bogdanm | 20:4263a77256ae | 197 | volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR; |
bogdanm | 20:4263a77256ae | 198 | volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0; |
bogdanm | 20:4263a77256ae | 199 | volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1; |
bogdanm | 20:4263a77256ae | 200 | volatile uint32_t Cpacr; |
bogdanm | 20:4263a77256ae | 201 | volatile uint32_t Mvfr0; |
bogdanm | 20:4263a77256ae | 202 | volatile uint32_t Mvfr1; |
bogdanm | 20:4263a77256ae | 203 | char vfpPresent = 0; |
bogdanm | 20:4263a77256ae | 204 | |
bogdanm | 20:4263a77256ae | 205 | Mvfr0 = *regMvfr0; |
bogdanm | 20:4263a77256ae | 206 | Mvfr1 = *regMvfr1; |
bogdanm | 20:4263a77256ae | 207 | |
bogdanm | 20:4263a77256ae | 208 | vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1)); |
bogdanm | 20:4263a77256ae | 209 | |
bogdanm | 20:4263a77256ae | 210 | if (vfpPresent) { |
bogdanm | 20:4263a77256ae | 211 | Cpacr = *regCpacr; |
bogdanm | 20:4263a77256ae | 212 | Cpacr |= (0xF << 20); |
bogdanm | 20:4263a77256ae | 213 | *regCpacr = Cpacr; // enable CP10 and CP11 for full access |
bogdanm | 20:4263a77256ae | 214 | } |
bogdanm | 20:4263a77256ae | 215 | |
bogdanm | 20:4263a77256ae | 216 | } |
bogdanm | 20:4263a77256ae | 217 | #endif /* defined(__FPU_PRESENT) && __FPU_PRESENT == 1 */ |
bogdanm | 20:4263a77256ae | 218 | |
bogdanm | 20:4263a77256ae | 219 | /* Approximate delay function */ |
bogdanm | 20:4263a77256ae | 220 | #define CPU_NANOSEC(x) (((uint64_t) (x) * SystemCoreClock) / 1000000000) |
bogdanm | 20:4263a77256ae | 221 | |
bogdanm | 20:4263a77256ae | 222 | static void WaitUs(uint32_t us) |
bogdanm | 20:4263a77256ae | 223 | { |
bogdanm | 20:4263a77256ae | 224 | uint32_t cyc = us * CPU_NANOSEC(1000) / 4; |
bogdanm | 20:4263a77256ae | 225 | while (cyc--) |
bogdanm | 20:4263a77256ae | 226 | ; |
bogdanm | 20:4263a77256ae | 227 | } |
bogdanm | 20:4263a77256ae | 228 | |
bogdanm | 20:4263a77256ae | 229 | #endif /* !defined(CORE_M0) */ |