david dicarlo / mbed-src-FLL48

mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).

Fork of mbed-src by mbed official

The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h

targets/cmsis/TARGET_NXP/TARGET_LPC11CXX/system_LPC11xx.c@20:4263a77256ae, 2013-09-10 (annotated)

Committer:
bogdanm
Date:
Tue Sep 10 15:14:19 2013 +0300
Revision:
20:4263a77256ae
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 20:4263a77256ae 1 /**************************************************************************//**
bogdanm 20:4263a77256ae 2 * @file system_LPC11xx.c
bogdanm 20:4263a77256ae 3 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
bogdanm 20:4263a77256ae 4 * for the NXP LPC11xx/LPC11Cxx Devices
bogdanm 20:4263a77256ae 5 * @version V1.10
bogdanm 20:4263a77256ae 6 * @date 24. November 2010
bogdanm 20:4263a77256ae 7 *
bogdanm 20:4263a77256ae 8 * @note
bogdanm 20:4263a77256ae 9 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
bogdanm 20:4263a77256ae 10 *
bogdanm 20:4263a77256ae 11 * @par
bogdanm 20:4263a77256ae 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 20:4263a77256ae 13 * processor based microcontrollers. This file can be freely distributed
bogdanm 20:4263a77256ae 14 * within development tools that are supporting such ARM based processors.
bogdanm 20:4263a77256ae 15 *
bogdanm 20:4263a77256ae 16 * @par
bogdanm 20:4263a77256ae 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 20:4263a77256ae 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 20:4263a77256ae 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 20:4263a77256ae 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 20:4263a77256ae 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 20:4263a77256ae 22 *
bogdanm 20:4263a77256ae 23 ******************************************************************************/
bogdanm 20:4263a77256ae 24
bogdanm 20:4263a77256ae 25
bogdanm 20:4263a77256ae 26 #include <stdint.h>
bogdanm 20:4263a77256ae 27 #include "LPC11xx.h"
bogdanm 20:4263a77256ae 28
bogdanm 20:4263a77256ae 29 /*
bogdanm 20:4263a77256ae 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
bogdanm 20:4263a77256ae 31 */
bogdanm 20:4263a77256ae 32
bogdanm 20:4263a77256ae 33 /*--------------------- Clock Configuration ----------------------------------
bogdanm 20:4263a77256ae 34 //
bogdanm 20:4263a77256ae 35 // <e> Clock Configuration
bogdanm 20:4263a77256ae 36 // <h> System Oscillator Control Register (SYSOSCCTRL)
bogdanm 20:4263a77256ae 37 // <o1.0> BYPASS: System Oscillator Bypass Enable
bogdanm 20:4263a77256ae 38 // <i> If enabled then PLL input (sys_osc_clk) is fed
bogdanm 20:4263a77256ae 39 // <i> directly from XTALIN and XTALOUT pins.
bogdanm 20:4263a77256ae 40 // <o1.9> FREQRANGE: System Oscillator Frequency Range
bogdanm 20:4263a77256ae 41 // <i> Determines frequency range for Low-power oscillator.
bogdanm 20:4263a77256ae 42 // <0=> 1 - 20 MHz
bogdanm 20:4263a77256ae 43 // <1=> 15 - 25 MHz
bogdanm 20:4263a77256ae 44 // </h>
bogdanm 20:4263a77256ae 45 //
bogdanm 20:4263a77256ae 46 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
bogdanm 20:4263a77256ae 47 // <o2.0..4> DIVSEL: Select Divider for Fclkana
bogdanm 20:4263a77256ae 48 // <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
bogdanm 20:4263a77256ae 49 // <0-31>
bogdanm 20:4263a77256ae 50 // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
bogdanm 20:4263a77256ae 51 // <0=> Undefined
bogdanm 20:4263a77256ae 52 // <1=> 0.5 MHz
bogdanm 20:4263a77256ae 53 // <2=> 0.8 MHz
bogdanm 20:4263a77256ae 54 // <3=> 1.1 MHz
bogdanm 20:4263a77256ae 55 // <4=> 1.4 MHz
bogdanm 20:4263a77256ae 56 // <5=> 1.6 MHz
bogdanm 20:4263a77256ae 57 // <6=> 1.8 MHz
bogdanm 20:4263a77256ae 58 // <7=> 2.0 MHz
bogdanm 20:4263a77256ae 59 // <8=> 2.2 MHz
bogdanm 20:4263a77256ae 60 // <9=> 2.4 MHz
bogdanm 20:4263a77256ae 61 // <10=> 2.6 MHz
bogdanm 20:4263a77256ae 62 // <11=> 2.7 MHz
bogdanm 20:4263a77256ae 63 // <12=> 2.9 MHz
bogdanm 20:4263a77256ae 64 // <13=> 3.1 MHz
bogdanm 20:4263a77256ae 65 // <14=> 3.2 MHz
bogdanm 20:4263a77256ae 66 // <15=> 3.4 MHz
bogdanm 20:4263a77256ae 67 // </h>
bogdanm 20:4263a77256ae 68 //
bogdanm 20:4263a77256ae 69 // <h> System PLL Control Register (SYSPLLCTRL)
bogdanm 20:4263a77256ae 70 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
bogdanm 20:4263a77256ae 71 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
bogdanm 20:4263a77256ae 72 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
bogdanm 20:4263a77256ae 73 // <o3.0..4> MSEL: Feedback Divider Selection
bogdanm 20:4263a77256ae 74 // <i> M = MSEL + 1
bogdanm 20:4263a77256ae 75 // <0-31>
bogdanm 20:4263a77256ae 76 // <o3.5..6> PSEL: Post Divider Selection
bogdanm 20:4263a77256ae 77 // <0=> P = 1
bogdanm 20:4263a77256ae 78 // <1=> P = 2
bogdanm 20:4263a77256ae 79 // <2=> P = 4
bogdanm 20:4263a77256ae 80 // <3=> P = 8
bogdanm 20:4263a77256ae 81 // </h>
bogdanm 20:4263a77256ae 82 //
bogdanm 20:4263a77256ae 83 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
bogdanm 20:4263a77256ae 84 // <o4.0..1> SEL: System PLL Clock Source
bogdanm 20:4263a77256ae 85 // <0=> IRC Oscillator
bogdanm 20:4263a77256ae 86 // <1=> System Oscillator
bogdanm 20:4263a77256ae 87 // <2=> Reserved
bogdanm 20:4263a77256ae 88 // <3=> Reserved
bogdanm 20:4263a77256ae 89 // </h>
bogdanm 20:4263a77256ae 90 //
bogdanm 20:4263a77256ae 91 // <h> Main Clock Source Select Register (MAINCLKSEL)
bogdanm 20:4263a77256ae 92 // <o5.0..1> SEL: Clock Source for Main Clock
bogdanm 20:4263a77256ae 93 // <0=> IRC Oscillator
bogdanm 20:4263a77256ae 94 // <1=> Input Clock to System PLL
bogdanm 20:4263a77256ae 95 // <2=> WDT Oscillator
bogdanm 20:4263a77256ae 96 // <3=> System PLL Clock Out
bogdanm 20:4263a77256ae 97 // </h>
bogdanm 20:4263a77256ae 98 //
bogdanm 20:4263a77256ae 99 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
bogdanm 20:4263a77256ae 100 // <o6.0..7> DIV: System AHB Clock Divider
bogdanm 20:4263a77256ae 101 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
bogdanm 20:4263a77256ae 102 // <i> 0 = is disabled
bogdanm 20:4263a77256ae 103 // <0-255>
bogdanm 20:4263a77256ae 104 // </h>
bogdanm 20:4263a77256ae 105 // </e>
bogdanm 20:4263a77256ae 106 */
bogdanm 20:4263a77256ae 107 #define CLOCK_SETUP 1
bogdanm 20:4263a77256ae 108 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 20:4263a77256ae 109 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 20:4263a77256ae 110 #define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
bogdanm 20:4263a77256ae 111 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
bogdanm 20:4263a77256ae 112 #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
bogdanm 20:4263a77256ae 113 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
bogdanm 20:4263a77256ae 114
bogdanm 20:4263a77256ae 115 /*
bogdanm 20:4263a77256ae 116 //-------- <<< end of configuration section >>> ------------------------------
bogdanm 20:4263a77256ae 117 */
bogdanm 20:4263a77256ae 118
bogdanm 20:4263a77256ae 119 /*----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 120 Check the register settings
bogdanm 20:4263a77256ae 121 *----------------------------------------------------------------------------*/
bogdanm 20:4263a77256ae 122 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
bogdanm 20:4263a77256ae 123 #define CHECK_RSVD(val, mask) (val & mask)
bogdanm 20:4263a77256ae 124
bogdanm 20:4263a77256ae 125 /* Clock Configuration -------------------------------------------------------*/
bogdanm 20:4263a77256ae 126 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
bogdanm 20:4263a77256ae 127 #error "SYSOSCCTRL: Invalid values of reserved bits!"
bogdanm 20:4263a77256ae 128 #endif
bogdanm 20:4263a77256ae 129
bogdanm 20:4263a77256ae 130 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
bogdanm 20:4263a77256ae 131 #error "WDTOSCCTRL: Invalid values of reserved bits!"
bogdanm 20:4263a77256ae 132 #endif
bogdanm 20:4263a77256ae 133
bogdanm 20:4263a77256ae 134 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
bogdanm 20:4263a77256ae 135 #error "SYSPLLCLKSEL: Value out of range!"
bogdanm 20:4263a77256ae 136 #endif
bogdanm 20:4263a77256ae 137
bogdanm 20:4263a77256ae 138 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
bogdanm 20:4263a77256ae 139 #error "SYSPLLCTRL: Invalid values of reserved bits!"
bogdanm 20:4263a77256ae 140 #endif
bogdanm 20:4263a77256ae 141
bogdanm 20:4263a77256ae 142 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
bogdanm 20:4263a77256ae 143 #error "MAINCLKSEL: Invalid values of reserved bits!"
bogdanm 20:4263a77256ae 144 #endif
bogdanm 20:4263a77256ae 145
bogdanm 20:4263a77256ae 146 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
bogdanm 20:4263a77256ae 147 #error "SYSAHBCLKDIV: Value out of range!"
bogdanm 20:4263a77256ae 148 #endif
bogdanm 20:4263a77256ae 149
bogdanm 20:4263a77256ae 150
bogdanm 20:4263a77256ae 151 /*----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 152 DEFINES
bogdanm 20:4263a77256ae 153 *----------------------------------------------------------------------------*/
bogdanm 20:4263a77256ae 154
bogdanm 20:4263a77256ae 155 /*----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 156 Define clocks
bogdanm 20:4263a77256ae 157 *----------------------------------------------------------------------------*/
bogdanm 20:4263a77256ae 158 #define __XTAL (12000000UL) /* Oscillator frequency */
bogdanm 20:4263a77256ae 159 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
bogdanm 20:4263a77256ae 160 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
bogdanm 20:4263a77256ae 161
bogdanm 20:4263a77256ae 162
bogdanm 20:4263a77256ae 163 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
bogdanm 20:4263a77256ae 164 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
bogdanm 20:4263a77256ae 165
bogdanm 20:4263a77256ae 166 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 20:4263a77256ae 167 #if (__FREQSEL == 0)
bogdanm 20:4263a77256ae 168 #define __WDT_OSC_CLK ( 0) /* undefined */
bogdanm 20:4263a77256ae 169 #elif (__FREQSEL == 1)
bogdanm 20:4263a77256ae 170 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
bogdanm 20:4263a77256ae 171 #elif (__FREQSEL == 2)
bogdanm 20:4263a77256ae 172 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
bogdanm 20:4263a77256ae 173 #elif (__FREQSEL == 3)
bogdanm 20:4263a77256ae 174 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
bogdanm 20:4263a77256ae 175 #elif (__FREQSEL == 4)
bogdanm 20:4263a77256ae 176 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
bogdanm 20:4263a77256ae 177 #elif (__FREQSEL == 5)
bogdanm 20:4263a77256ae 178 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
bogdanm 20:4263a77256ae 179 #elif (__FREQSEL == 6)
bogdanm 20:4263a77256ae 180 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
bogdanm 20:4263a77256ae 181 #elif (__FREQSEL == 7)
bogdanm 20:4263a77256ae 182 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
bogdanm 20:4263a77256ae 183 #elif (__FREQSEL == 8)
bogdanm 20:4263a77256ae 184 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
bogdanm 20:4263a77256ae 185 #elif (__FREQSEL == 9)
bogdanm 20:4263a77256ae 186 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
bogdanm 20:4263a77256ae 187 #elif (__FREQSEL == 10)
bogdanm 20:4263a77256ae 188 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
bogdanm 20:4263a77256ae 189 #elif (__FREQSEL == 11)
bogdanm 20:4263a77256ae 190 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
bogdanm 20:4263a77256ae 191 #elif (__FREQSEL == 12)
bogdanm 20:4263a77256ae 192 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
bogdanm 20:4263a77256ae 193 #elif (__FREQSEL == 13)
bogdanm 20:4263a77256ae 194 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
bogdanm 20:4263a77256ae 195 #elif (__FREQSEL == 14)
bogdanm 20:4263a77256ae 196 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
bogdanm 20:4263a77256ae 197 #else
bogdanm 20:4263a77256ae 198 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
bogdanm 20:4263a77256ae 199 #endif
bogdanm 20:4263a77256ae 200
bogdanm 20:4263a77256ae 201 /* sys_pllclkin calculation */
bogdanm 20:4263a77256ae 202 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
bogdanm 20:4263a77256ae 203 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
bogdanm 20:4263a77256ae 204 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 20:4263a77256ae 205 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
bogdanm 20:4263a77256ae 206 #else
bogdanm 20:4263a77256ae 207 #define __SYS_PLLCLKIN (0)
bogdanm 20:4263a77256ae 208 #endif
bogdanm 20:4263a77256ae 209
bogdanm 20:4263a77256ae 210 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
bogdanm 20:4263a77256ae 211
bogdanm 20:4263a77256ae 212 /* main clock calculation */
bogdanm 20:4263a77256ae 213 #if ((MAINCLKSEL_Val & 0x03) == 0)
bogdanm 20:4263a77256ae 214 #define __MAIN_CLOCK (__IRC_OSC_CLK)
bogdanm 20:4263a77256ae 215 #elif ((MAINCLKSEL_Val & 0x03) == 1)
bogdanm 20:4263a77256ae 216 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
bogdanm 20:4263a77256ae 217 #elif ((MAINCLKSEL_Val & 0x03) == 2)
bogdanm 20:4263a77256ae 218 #if (__FREQSEL == 0)
bogdanm 20:4263a77256ae 219 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
bogdanm 20:4263a77256ae 220 #else
bogdanm 20:4263a77256ae 221 #define __MAIN_CLOCK (__WDT_OSC_CLK)
bogdanm 20:4263a77256ae 222 #endif
bogdanm 20:4263a77256ae 223 #elif ((MAINCLKSEL_Val & 0x03) == 3)
bogdanm 20:4263a77256ae 224 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
bogdanm 20:4263a77256ae 225 #else
bogdanm 20:4263a77256ae 226 #define __MAIN_CLOCK (0)
bogdanm 20:4263a77256ae 227 #endif
bogdanm 20:4263a77256ae 228
bogdanm 20:4263a77256ae 229 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
bogdanm 20:4263a77256ae 230
bogdanm 20:4263a77256ae 231 #else
bogdanm 20:4263a77256ae 232 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
bogdanm 20:4263a77256ae 233 #endif // CLOCK_SETUP
bogdanm 20:4263a77256ae 234
bogdanm 20:4263a77256ae 235
bogdanm 20:4263a77256ae 236 /*----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 237 Clock Variable definitions
bogdanm 20:4263a77256ae 238 *----------------------------------------------------------------------------*/
bogdanm 20:4263a77256ae 239 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
bogdanm 20:4263a77256ae 240
bogdanm 20:4263a77256ae 241
bogdanm 20:4263a77256ae 242 /*----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 243 Clock functions
bogdanm 20:4263a77256ae 244 *----------------------------------------------------------------------------*/
bogdanm 20:4263a77256ae 245 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
bogdanm 20:4263a77256ae 246 {
bogdanm 20:4263a77256ae 247 uint32_t wdt_osc = 0;
bogdanm 20:4263a77256ae 248
bogdanm 20:4263a77256ae 249 /* Determine clock frequency according to clock register values */
bogdanm 20:4263a77256ae 250 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
bogdanm 20:4263a77256ae 251 case 0: wdt_osc = 0; break;
bogdanm 20:4263a77256ae 252 case 1: wdt_osc = 500000; break;
bogdanm 20:4263a77256ae 253 case 2: wdt_osc = 800000; break;
bogdanm 20:4263a77256ae 254 case 3: wdt_osc = 1100000; break;
bogdanm 20:4263a77256ae 255 case 4: wdt_osc = 1400000; break;
bogdanm 20:4263a77256ae 256 case 5: wdt_osc = 1600000; break;
bogdanm 20:4263a77256ae 257 case 6: wdt_osc = 1800000; break;
bogdanm 20:4263a77256ae 258 case 7: wdt_osc = 2000000; break;
bogdanm 20:4263a77256ae 259 case 8: wdt_osc = 2200000; break;
bogdanm 20:4263a77256ae 260 case 9: wdt_osc = 2400000; break;
bogdanm 20:4263a77256ae 261 case 10: wdt_osc = 2600000; break;
bogdanm 20:4263a77256ae 262 case 11: wdt_osc = 2700000; break;
bogdanm 20:4263a77256ae 263 case 12: wdt_osc = 2900000; break;
bogdanm 20:4263a77256ae 264 case 13: wdt_osc = 3100000; break;
bogdanm 20:4263a77256ae 265 case 14: wdt_osc = 3200000; break;
bogdanm 20:4263a77256ae 266 case 15: wdt_osc = 3400000; break;
bogdanm 20:4263a77256ae 267 }
bogdanm 20:4263a77256ae 268 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
bogdanm 20:4263a77256ae 269
bogdanm 20:4263a77256ae 270 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
bogdanm 20:4263a77256ae 271 case 0: /* Internal RC oscillator */
bogdanm 20:4263a77256ae 272 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 20:4263a77256ae 273 break;
bogdanm 20:4263a77256ae 274 case 1: /* Input Clock to System PLL */
bogdanm 20:4263a77256ae 275 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 20:4263a77256ae 276 case 0: /* Internal RC oscillator */
bogdanm 20:4263a77256ae 277 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 20:4263a77256ae 278 break;
bogdanm 20:4263a77256ae 279 case 1: /* System oscillator */
bogdanm 20:4263a77256ae 280 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 20:4263a77256ae 281 break;
bogdanm 20:4263a77256ae 282 case 2: /* Reserved */
bogdanm 20:4263a77256ae 283 case 3: /* Reserved */
bogdanm 20:4263a77256ae 284 SystemCoreClock = 0;
bogdanm 20:4263a77256ae 285 break;
bogdanm 20:4263a77256ae 286 }
bogdanm 20:4263a77256ae 287 break;
bogdanm 20:4263a77256ae 288 case 2: /* WDT Oscillator */
bogdanm 20:4263a77256ae 289 SystemCoreClock = wdt_osc;
bogdanm 20:4263a77256ae 290 break;
bogdanm 20:4263a77256ae 291 case 3: /* System PLL Clock Out */
bogdanm 20:4263a77256ae 292 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 20:4263a77256ae 293 case 0: /* Internal RC oscillator */
bogdanm 20:4263a77256ae 294 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
bogdanm 20:4263a77256ae 295 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 20:4263a77256ae 296 } else {
bogdanm 20:4263a77256ae 297 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 20:4263a77256ae 298 }
bogdanm 20:4263a77256ae 299 break;
bogdanm 20:4263a77256ae 300 case 1: /* System oscillator */
bogdanm 20:4263a77256ae 301 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
bogdanm 20:4263a77256ae 302 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 20:4263a77256ae 303 } else {
bogdanm 20:4263a77256ae 304 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 20:4263a77256ae 305 }
bogdanm 20:4263a77256ae 306 break;
bogdanm 20:4263a77256ae 307 case 2: /* Reserved */
bogdanm 20:4263a77256ae 308 case 3: /* Reserved */
bogdanm 20:4263a77256ae 309 SystemCoreClock = 0;
bogdanm 20:4263a77256ae 310 break;
bogdanm 20:4263a77256ae 311 }
bogdanm 20:4263a77256ae 312 break;
bogdanm 20:4263a77256ae 313 }
bogdanm 20:4263a77256ae 314
bogdanm 20:4263a77256ae 315 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
bogdanm 20:4263a77256ae 316
bogdanm 20:4263a77256ae 317 }
bogdanm 20:4263a77256ae 318
bogdanm 20:4263a77256ae 319 /**
bogdanm 20:4263a77256ae 320 * Initialize the system
bogdanm 20:4263a77256ae 321 *
bogdanm 20:4263a77256ae 322 * @param none
bogdanm 20:4263a77256ae 323 * @return none
bogdanm 20:4263a77256ae 324 *
bogdanm 20:4263a77256ae 325 * @brief Setup the microcontroller system.
bogdanm 20:4263a77256ae 326 * Initialize the System.
bogdanm 20:4263a77256ae 327 */
bogdanm 20:4263a77256ae 328 void SystemInit (void) {
bogdanm 20:4263a77256ae 329 volatile uint32_t i;
bogdanm 20:4263a77256ae 330
bogdanm 20:4263a77256ae 331 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 20:4263a77256ae 332
bogdanm 20:4263a77256ae 333 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 20:4263a77256ae 334 LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
bogdanm 20:4263a77256ae 335 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
bogdanm 20:4263a77256ae 336 for (i = 0; i < 200; i++) __NOP();
bogdanm 20:4263a77256ae 337 #endif
bogdanm 20:4263a77256ae 338
bogdanm 20:4263a77256ae 339 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
bogdanm 20:4263a77256ae 340 LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
bogdanm 20:4263a77256ae 341 LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
bogdanm 20:4263a77256ae 342 LPC_SYSCON->SYSPLLCLKUEN = 0x01;
bogdanm 20:4263a77256ae 343 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
bogdanm 20:4263a77256ae 344 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
bogdanm 20:4263a77256ae 345 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
bogdanm 20:4263a77256ae 346 LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
bogdanm 20:4263a77256ae 347 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
bogdanm 20:4263a77256ae 348 #endif
bogdanm 20:4263a77256ae 349
bogdanm 20:4263a77256ae 350 #if (((MAINCLKSEL_Val & 0x03) == 2) )
bogdanm 20:4263a77256ae 351 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
bogdanm 20:4263a77256ae 352 LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
bogdanm 20:4263a77256ae 353 for (i = 0; i < 200; i++) __NOP();
bogdanm 20:4263a77256ae 354 #endif
bogdanm 20:4263a77256ae 355
bogdanm 20:4263a77256ae 356 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
bogdanm 20:4263a77256ae 357 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
bogdanm 20:4263a77256ae 358 LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
bogdanm 20:4263a77256ae 359 LPC_SYSCON->MAINCLKUEN = 0x01;
bogdanm 20:4263a77256ae 360 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
bogdanm 20:4263a77256ae 361
bogdanm 20:4263a77256ae 362 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
bogdanm 20:4263a77256ae 363 #endif
bogdanm 20:4263a77256ae 364 /* System clock to the IOCON needs to be enabled or
bogdanm 20:4263a77256ae 365 most of the I/O related peripherals won't work. */
bogdanm 20:4263a77256ae 366 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
bogdanm 20:4263a77256ae 367 }