david dicarlo / mbed-src-FLL48

mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).

Fork of mbed-src by mbed official

The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h

targets/cmsis/TARGET_Freescale/TARGET_KL05Z/system_MKL05Z4.c@20:4263a77256ae, 2013-09-10 (annotated)

Committer:
bogdanm
Date:
Tue Sep 10 15:14:19 2013 +0300
Revision:
20:4263a77256ae
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 20:4263a77256ae 1 #include <stdint.h>
bogdanm 20:4263a77256ae 2 #include "MKL05Z4.h"
bogdanm 20:4263a77256ae 3
bogdanm 20:4263a77256ae 4 #define DISABLE_WDOG 1
bogdanm 20:4263a77256ae 5
bogdanm 20:4263a77256ae 6 /* Predefined clock setups
bogdanm 20:4263a77256ae 7 Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
bogdanm 20:4263a77256ae 8 Reference clock source for MCG module is the slow internal clock source 32.768kHz
bogdanm 20:4263a77256ae 9 Core clock = 47.97MHz, BusClock = 23.48MHz
bogdanm 20:4263a77256ae 10 */
bogdanm 20:4263a77256ae 11
bogdanm 20:4263a77256ae 12 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
bogdanm 20:4263a77256ae 13 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
bogdanm 20:4263a77256ae 14 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
bogdanm 20:4263a77256ae 15 #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
bogdanm 20:4263a77256ae 16
bogdanm 20:4263a77256ae 17 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
bogdanm 20:4263a77256ae 18
bogdanm 20:4263a77256ae 19 void SystemInit(void) {
bogdanm 20:4263a77256ae 20 #if (DISABLE_WDOG)
bogdanm 20:4263a77256ae 21 /* Disable the WDOG module */
bogdanm 20:4263a77256ae 22 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
bogdanm 20:4263a77256ae 23 SIM->COPC = (uint32_t)0x00u;
bogdanm 20:4263a77256ae 24 #endif /* (DISABLE_WDOG) */
bogdanm 20:4263a77256ae 25
bogdanm 20:4263a77256ae 26 SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTA_MASK); /* Enable clock gate for ports to enable pin routing */
bogdanm 20:4263a77256ae 27 /* SIM_SCGC5: LPTMR=1 */
bogdanm 20:4263a77256ae 28 SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
bogdanm 20:4263a77256ae 29 /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
bogdanm 20:4263a77256ae 30 SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
bogdanm 20:4263a77256ae 31 /* SIM_SOPT1: OSC32KSEL=0 */
bogdanm 20:4263a77256ae 32 SIM->SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
bogdanm 20:4263a77256ae 33 /* SIM_SOPT2: TPMSRC=2 */
bogdanm 20:4263a77256ae 34 SIM->SOPT2 = (uint32_t)((SIM->SOPT2 & (uint32_t)~(uint32_t)(SIM_SOPT2_TPMSRC(0x01))) |
bogdanm 20:4263a77256ae 35 (uint32_t)(SIM_SOPT2_TPMSRC(0x02))); /* Set the TPM clock */
bogdanm 20:4263a77256ae 36 /* PORTA_PCR3: ISF=0,MUX=0 */
bogdanm 20:4263a77256ae 37 PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
bogdanm 20:4263a77256ae 38 /* MCG_SC: FCRDIV=1 */
bogdanm 20:4263a77256ae 39 MCG->SC = (uint8_t)((MCG->SC & (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x06))) |
bogdanm 20:4263a77256ae 40 (uint8_t)(MCG_SC_FCRDIV(0x01)));
bogdanm 20:4263a77256ae 41 /* Switch to FEI Mode */
bogdanm 20:4263a77256ae 42 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
bogdanm 20:4263a77256ae 43 MCG->C1 = MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) |
bogdanm 20:4263a77256ae 44 MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK;
bogdanm 20:4263a77256ae 45 /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
bogdanm 20:4263a77256ae 46 MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
bogdanm 20:4263a77256ae 47 /* MCG_C4: DMX32=1,DRST_DRS=1 */
bogdanm 20:4263a77256ae 48 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(MCG_C4_DRST_DRS(0x02))) |
bogdanm 20:4263a77256ae 49 (uint8_t)(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x01)));
bogdanm 20:4263a77256ae 50 /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 20:4263a77256ae 51 OSC0->CR = OSC_CR_ERCLKEN_MASK;
bogdanm 20:4263a77256ae 52 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
bogdanm 20:4263a77256ae 53 }
bogdanm 20:4263a77256ae 54 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
bogdanm 20:4263a77256ae 55 }
bogdanm 20:4263a77256ae 56 }
bogdanm 20:4263a77256ae 57
bogdanm 20:4263a77256ae 58 void SystemCoreClockUpdate(void) {
bogdanm 20:4263a77256ae 59 uint32_t MCGOUTClock;
bogdanm 20:4263a77256ae 60 uint8_t Divider;
bogdanm 20:4263a77256ae 61
bogdanm 20:4263a77256ae 62 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
bogdanm 20:4263a77256ae 63 /* FLL is selected */
bogdanm 20:4263a77256ae 64 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
bogdanm 20:4263a77256ae 65 /* External reference clock is selected */
bogdanm 20:4263a77256ae 66 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 20:4263a77256ae 67 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
bogdanm 20:4263a77256ae 68 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
bogdanm 20:4263a77256ae 69 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
bogdanm 20:4263a77256ae 70 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
bogdanm 20:4263a77256ae 71 }
bogdanm 20:4263a77256ae 72 } else {
bogdanm 20:4263a77256ae 73 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
bogdanm 20:4263a77256ae 74 }
bogdanm 20:4263a77256ae 75
bogdanm 20:4263a77256ae 76 /* Select correct multiplier to calculate the MCG output clock */
bogdanm 20:4263a77256ae 77 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
bogdanm 20:4263a77256ae 78 case 0x0u:
bogdanm 20:4263a77256ae 79 MCGOUTClock *= 640u;
bogdanm 20:4263a77256ae 80 break;
bogdanm 20:4263a77256ae 81 case 0x20u:
bogdanm 20:4263a77256ae 82 MCGOUTClock *= 1280u;
bogdanm 20:4263a77256ae 83 break;
bogdanm 20:4263a77256ae 84 case 0x40u:
bogdanm 20:4263a77256ae 85 MCGOUTClock *= 1920u;
bogdanm 20:4263a77256ae 86 break;
bogdanm 20:4263a77256ae 87 case 0x60u:
bogdanm 20:4263a77256ae 88 MCGOUTClock *= 2560u;
bogdanm 20:4263a77256ae 89 break;
bogdanm 20:4263a77256ae 90 case 0x80u:
bogdanm 20:4263a77256ae 91 MCGOUTClock *= 732u;
bogdanm 20:4263a77256ae 92 break;
bogdanm 20:4263a77256ae 93 case 0xA0u:
bogdanm 20:4263a77256ae 94 MCGOUTClock *= 1464u;
bogdanm 20:4263a77256ae 95 break;
bogdanm 20:4263a77256ae 96 case 0xC0u:
bogdanm 20:4263a77256ae 97 MCGOUTClock *= 2197u;
bogdanm 20:4263a77256ae 98 break;
bogdanm 20:4263a77256ae 99 case 0xE0u:
bogdanm 20:4263a77256ae 100 MCGOUTClock *= 2929u;
bogdanm 20:4263a77256ae 101 break;
bogdanm 20:4263a77256ae 102 default:
bogdanm 20:4263a77256ae 103 break;
bogdanm 20:4263a77256ae 104 }
bogdanm 20:4263a77256ae 105 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
bogdanm 20:4263a77256ae 106 /* Internal reference clock is selected */
bogdanm 20:4263a77256ae 107 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
bogdanm 20:4263a77256ae 108 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
bogdanm 20:4263a77256ae 109 } else {
bogdanm 20:4263a77256ae 110 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
bogdanm 20:4263a77256ae 111 }
bogdanm 20:4263a77256ae 112 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
bogdanm 20:4263a77256ae 113 /* External reference clock is selected */
bogdanm 20:4263a77256ae 114 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 20:4263a77256ae 115 } else {
bogdanm 20:4263a77256ae 116 /* Reserved value */
bogdanm 20:4263a77256ae 117 return;
bogdanm 20:4263a77256ae 118 }
bogdanm 20:4263a77256ae 119
bogdanm 20:4263a77256ae 120 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
bogdanm 20:4263a77256ae 121
bogdanm 20:4263a77256ae 122 }