david dicarlo / mbed-src-FLL48

mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).

Fork of mbed-src by mbed official

The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h

targets/cmsis/TARGET_Freescale/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.s@20:4263a77256ae, 2013-09-10 (annotated)

Committer:
bogdanm
Date:
Tue Sep 10 15:14:19 2013 +0300
Revision:
20:4263a77256ae
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 20:4263a77256ae 1 ;/*****************************************************************************
bogdanm 20:4263a77256ae 2 ; * @file: startup_MKL25Z4.s
bogdanm 20:4263a77256ae 3 ; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
bogdanm 20:4263a77256ae 4 ; * MKL05Z4
bogdanm 20:4263a77256ae 5 ; * @version: 1.1
bogdanm 20:4263a77256ae 6 ; * @date: 2012-6-21
bogdanm 20:4263a77256ae 7 ; *
bogdanm 20:4263a77256ae 8 ; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
bogdanm 20:4263a77256ae 9 ;*
bogdanm 20:4263a77256ae 10 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
bogdanm 20:4263a77256ae 11 ; *
bogdanm 20:4263a77256ae 12 ; *****************************************************************************/
bogdanm 20:4263a77256ae 13
bogdanm 20:4263a77256ae 14
bogdanm 20:4263a77256ae 15 __initial_sp EQU 0x20000C00 ; Top of RAM
bogdanm 20:4263a77256ae 16
bogdanm 20:4263a77256ae 17 PRESERVE8
bogdanm 20:4263a77256ae 18 THUMB
bogdanm 20:4263a77256ae 19
bogdanm 20:4263a77256ae 20
bogdanm 20:4263a77256ae 21 ; Vector Table Mapped to Address 0 at Reset
bogdanm 20:4263a77256ae 22
bogdanm 20:4263a77256ae 23 AREA RESET, DATA, READONLY
bogdanm 20:4263a77256ae 24 EXPORT __Vectors
bogdanm 20:4263a77256ae 25 EXPORT __Vectors_End
bogdanm 20:4263a77256ae 26 EXPORT __Vectors_Size
bogdanm 20:4263a77256ae 27
bogdanm 20:4263a77256ae 28 __Vectors DCD __initial_sp ; Top of Stack
bogdanm 20:4263a77256ae 29 DCD Reset_Handler ; Reset Handler
bogdanm 20:4263a77256ae 30 DCD NMI_Handler ; NMI Handler
bogdanm 20:4263a77256ae 31 DCD HardFault_Handler ; Hard Fault Handler
bogdanm 20:4263a77256ae 32 DCD 0 ; Reserved
bogdanm 20:4263a77256ae 33 DCD 0 ; Reserved
bogdanm 20:4263a77256ae 34 DCD 0 ; Reserved
bogdanm 20:4263a77256ae 35 DCD 0 ; Reserved
bogdanm 20:4263a77256ae 36 DCD 0 ; Reserved
bogdanm 20:4263a77256ae 37 DCD 0 ; Reserved
bogdanm 20:4263a77256ae 38 DCD 0 ; Reserved
bogdanm 20:4263a77256ae 39 DCD SVC_Handler ; SVCall Handler
bogdanm 20:4263a77256ae 40 DCD 0 ; Reserved
bogdanm 20:4263a77256ae 41 DCD 0 ; Reserved
bogdanm 20:4263a77256ae 42 DCD PendSV_Handler ; PendSV Handler
bogdanm 20:4263a77256ae 43 DCD SysTick_Handler ; SysTick Handler
bogdanm 20:4263a77256ae 44
bogdanm 20:4263a77256ae 45 ; External Interrupts
bogdanm 20:4263a77256ae 46 DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
bogdanm 20:4263a77256ae 47 DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
bogdanm 20:4263a77256ae 48 DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
bogdanm 20:4263a77256ae 49 DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
bogdanm 20:4263a77256ae 50 DCD Reserved20_IRQHandler ; Reserved interrupt 20
bogdanm 20:4263a77256ae 51 DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
bogdanm 20:4263a77256ae 52 DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
bogdanm 20:4263a77256ae 53 DCD LLW_IRQHandler ; Low Leakage Wakeup
bogdanm 20:4263a77256ae 54 DCD I2C0_IRQHandler ; I2C0 interrupt
bogdanm 20:4263a77256ae 55 DCD Reserved_25_IRQHandler ; Reserved interrupt 25
bogdanm 20:4263a77256ae 56 DCD SPI0_IRQHandler ; SPI0 interrupt
bogdanm 20:4263a77256ae 57 DCD Reserved_27_IRQHandler ; Reserved interrupt 27
bogdanm 20:4263a77256ae 58 DCD UART0_IRQHandler ; UART0 status and error interrupt
bogdanm 20:4263a77256ae 59 DCD Reserved_29_IRQHandler ; Reserved interrupt 29
bogdanm 20:4263a77256ae 60 DCD Reserved_30_IRQHandler ; Reserved interrupt 30
bogdanm 20:4263a77256ae 61 DCD ADC0_IRQHandler ; ADC0 interrupt
bogdanm 20:4263a77256ae 62 DCD CMP0_IRQHandler ; CMP0 interrupt
bogdanm 20:4263a77256ae 63 DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
bogdanm 20:4263a77256ae 64 DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
bogdanm 20:4263a77256ae 65 DCD Reserved_35_IRQHandler ; Reserved interrupt 35
bogdanm 20:4263a77256ae 66 DCD RTC_IRQHandler ; RTC interrupt
bogdanm 20:4263a77256ae 67 DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
bogdanm 20:4263a77256ae 68 DCD PIT_IRQHandler ; PIT timer channel 0 interrupt
bogdanm 20:4263a77256ae 69 DCD Reserved_39_IRQHandler ; Reserved interrupt 39
bogdanm 20:4263a77256ae 70 DCD Reserved_40_IRQHandler ; Reserved interrupt 40
bogdanm 20:4263a77256ae 71 DCD DAC0_IRQHandler ; DAC0 interrupt
bogdanm 20:4263a77256ae 72 DCD TSI0_IRQHandler ; TSI0 interrupt
bogdanm 20:4263a77256ae 73 DCD MCG_IRQHandler ; MCG interrupt
bogdanm 20:4263a77256ae 74 DCD LPTimer_IRQHandler ; LPTimer interrupt
bogdanm 20:4263a77256ae 75 DCD Reserved_45_IRQHandler ; Reserved interrupt 45
bogdanm 20:4263a77256ae 76 DCD PORTA_IRQHandler ; Port A interrupt
bogdanm 20:4263a77256ae 77 DCD PORTB_IRQHandler ; Port B interrupt
bogdanm 20:4263a77256ae 78 __Vectors_End
bogdanm 20:4263a77256ae 79
bogdanm 20:4263a77256ae 80 __Vectors_Size EQU __Vectors_End - __Vectors
bogdanm 20:4263a77256ae 81
bogdanm 20:4263a77256ae 82 ; <h> Flash Configuration
bogdanm 20:4263a77256ae 83 ; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
bogdanm 20:4263a77256ae 84 ; <i> and security information that allows the MCU to restrict acces to the FTFL module.
bogdanm 20:4263a77256ae 85 ; <h> Backdoor Comparison Key
bogdanm 20:4263a77256ae 86 ; <o0> Backdoor Key 0 <0x0-0xFF:2>
bogdanm 20:4263a77256ae 87 ; <o1> Backdoor Key 1 <0x0-0xFF:2>
bogdanm 20:4263a77256ae 88 ; <o2> Backdoor Key 2 <0x0-0xFF:2>
bogdanm 20:4263a77256ae 89 ; <o3> Backdoor Key 3 <0x0-0xFF:2>
bogdanm 20:4263a77256ae 90 ; <o4> Backdoor Key 4 <0x0-0xFF:2>
bogdanm 20:4263a77256ae 91 ; <o5> Backdoor Key 5 <0x0-0xFF:2>
bogdanm 20:4263a77256ae 92 ; <o6> Backdoor Key 6 <0x0-0xFF:2>
bogdanm 20:4263a77256ae 93 ; <o7> Backdoor Key 7 <0x0-0xFF:2>
bogdanm 20:4263a77256ae 94 BackDoorK0 EQU 0xFF
bogdanm 20:4263a77256ae 95 BackDoorK1 EQU 0xFF
bogdanm 20:4263a77256ae 96 BackDoorK2 EQU 0xFF
bogdanm 20:4263a77256ae 97 BackDoorK3 EQU 0xFF
bogdanm 20:4263a77256ae 98 BackDoorK4 EQU 0xFF
bogdanm 20:4263a77256ae 99 BackDoorK5 EQU 0xFF
bogdanm 20:4263a77256ae 100 BackDoorK6 EQU 0xFF
bogdanm 20:4263a77256ae 101 BackDoorK7 EQU 0xFF
bogdanm 20:4263a77256ae 102 ; </h>
bogdanm 20:4263a77256ae 103 ; <h> Program flash protection bytes (FPROT)
bogdanm 20:4263a77256ae 104 ; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
bogdanm 20:4263a77256ae 105 ; <i> Each bit protects a 1/32 region of the program flash memory.
bogdanm 20:4263a77256ae 106 ; <h> FPROT0
bogdanm 20:4263a77256ae 107 ; <i> Program flash protection bytes
bogdanm 20:4263a77256ae 108 ; <i> 1/32 - 8/32 region
bogdanm 20:4263a77256ae 109 ; <o.0> FPROT0.0
bogdanm 20:4263a77256ae 110 ; <o.1> FPROT0.1
bogdanm 20:4263a77256ae 111 ; <o.2> FPROT0.2
bogdanm 20:4263a77256ae 112 ; <o.3> FPROT0.3
bogdanm 20:4263a77256ae 113 ; <o.4> FPROT0.4
bogdanm 20:4263a77256ae 114 ; <o.5> FPROT0.5
bogdanm 20:4263a77256ae 115 ; <o.6> FPROT0.6
bogdanm 20:4263a77256ae 116 ; <o.7> FPROT0.7
bogdanm 20:4263a77256ae 117 nFPROT0 EQU 0x00
bogdanm 20:4263a77256ae 118 FPROT0 EQU nFPROT0:EOR:0xFF
bogdanm 20:4263a77256ae 119 ; </h>
bogdanm 20:4263a77256ae 120 ; <h> FPROT1
bogdanm 20:4263a77256ae 121 ; <i> Program Flash Region Protect Register 1
bogdanm 20:4263a77256ae 122 ; <i> 9/32 - 16/32 region
bogdanm 20:4263a77256ae 123 ; <o.0> FPROT1.0
bogdanm 20:4263a77256ae 124 ; <o.1> FPROT1.1
bogdanm 20:4263a77256ae 125 ; <o.2> FPROT1.2
bogdanm 20:4263a77256ae 126 ; <o.3> FPROT1.3
bogdanm 20:4263a77256ae 127 ; <o.4> FPROT1.4
bogdanm 20:4263a77256ae 128 ; <o.5> FPROT1.5
bogdanm 20:4263a77256ae 129 ; <o.6> FPROT1.6
bogdanm 20:4263a77256ae 130 ; <o.7> FPROT1.7
bogdanm 20:4263a77256ae 131 nFPROT1 EQU 0x00
bogdanm 20:4263a77256ae 132 FPROT1 EQU nFPROT1:EOR:0xFF
bogdanm 20:4263a77256ae 133 ; </h>
bogdanm 20:4263a77256ae 134 ; <h> FPROT2
bogdanm 20:4263a77256ae 135 ; <i> Program Flash Region Protect Register 2
bogdanm 20:4263a77256ae 136 ; <i> 17/32 - 24/32 region
bogdanm 20:4263a77256ae 137 ; <o.0> FPROT2.0
bogdanm 20:4263a77256ae 138 ; <o.1> FPROT2.1
bogdanm 20:4263a77256ae 139 ; <o.2> FPROT2.2
bogdanm 20:4263a77256ae 140 ; <o.3> FPROT2.3
bogdanm 20:4263a77256ae 141 ; <o.4> FPROT2.4
bogdanm 20:4263a77256ae 142 ; <o.5> FPROT2.5
bogdanm 20:4263a77256ae 143 ; <o.6> FPROT2.6
bogdanm 20:4263a77256ae 144 ; <o.7> FPROT2.7
bogdanm 20:4263a77256ae 145 nFPROT2 EQU 0x00
bogdanm 20:4263a77256ae 146 FPROT2 EQU nFPROT2:EOR:0xFF
bogdanm 20:4263a77256ae 147 ; </h>
bogdanm 20:4263a77256ae 148 ; <h> FPROT3
bogdanm 20:4263a77256ae 149 ; <i> Program Flash Region Protect Register 3
bogdanm 20:4263a77256ae 150 ; <i> 25/32 - 32/32 region
bogdanm 20:4263a77256ae 151 ; <o.0> FPROT3.0
bogdanm 20:4263a77256ae 152 ; <o.1> FPROT3.1
bogdanm 20:4263a77256ae 153 ; <o.2> FPROT3.2
bogdanm 20:4263a77256ae 154 ; <o.3> FPROT3.3
bogdanm 20:4263a77256ae 155 ; <o.4> FPROT3.4
bogdanm 20:4263a77256ae 156 ; <o.5> FPROT3.5
bogdanm 20:4263a77256ae 157 ; <o.6> FPROT3.6
bogdanm 20:4263a77256ae 158 ; <o.7> FPROT3.7
bogdanm 20:4263a77256ae 159 nFPROT3 EQU 0x00
bogdanm 20:4263a77256ae 160 FPROT3 EQU nFPROT3:EOR:0xFF
bogdanm 20:4263a77256ae 161 ; </h>
bogdanm 20:4263a77256ae 162 ; </h>
bogdanm 20:4263a77256ae 163 ; </h>
bogdanm 20:4263a77256ae 164 ; <h> Flash nonvolatile option byte (FOPT)
bogdanm 20:4263a77256ae 165 ; <i> Allows the user to customize the operation of the MCU at boot time.
bogdanm 20:4263a77256ae 166 ; <o.0> LPBOOT0
bogdanm 20:4263a77256ae 167 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
bogdanm 20:4263a77256ae 168 ; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
bogdanm 20:4263a77256ae 169 ; <o.4> LPBOOT1
bogdanm 20:4263a77256ae 170 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
bogdanm 20:4263a77256ae 171 ; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
bogdanm 20:4263a77256ae 172 ; <o.2> NMI_DIS
bogdanm 20:4263a77256ae 173 ; <0=> NMI interrupts are always blocked
bogdanm 20:4263a77256ae 174 ; <1=> NMI pin/interrupts reset default to enabled
bogdanm 20:4263a77256ae 175 ; <o.3> RESET_PIN_CFG
bogdanm 20:4263a77256ae 176 ; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
bogdanm 20:4263a77256ae 177 ; <1=> RESET pin is dedicated
bogdanm 20:4263a77256ae 178 ; <o.3> FAST_INIT
bogdanm 20:4263a77256ae 179 ; <0=> Slower initialization
bogdanm 20:4263a77256ae 180 ; <1=> Fast Initialization
bogdanm 20:4263a77256ae 181 FOPT EQU 0xFF
bogdanm 20:4263a77256ae 182 ; </h>
bogdanm 20:4263a77256ae 183 ; <h> Flash security byte (FSEC)
bogdanm 20:4263a77256ae 184 ; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
bogdanm 20:4263a77256ae 185 ; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
bogdanm 20:4263a77256ae 186 ; <o.0..1> SEC
bogdanm 20:4263a77256ae 187 ; <2=> MCU security status is unsecure
bogdanm 20:4263a77256ae 188 ; <3=> MCU security status is secure
bogdanm 20:4263a77256ae 189 ; <i> Flash Security
bogdanm 20:4263a77256ae 190 ; <i> This bits define the security state of the MCU.
bogdanm 20:4263a77256ae 191 ; <o.2..3> FSLACC
bogdanm 20:4263a77256ae 192 ; <2=> Freescale factory access denied
bogdanm 20:4263a77256ae 193 ; <3=> Freescale factory access granted
bogdanm 20:4263a77256ae 194 ; <i> Freescale Failure Analysis Access Code
bogdanm 20:4263a77256ae 195 ; <i> This bits define the security state of the MCU.
bogdanm 20:4263a77256ae 196 ; <o.4..5> MEEN
bogdanm 20:4263a77256ae 197 ; <2=> Mass erase is disabled
bogdanm 20:4263a77256ae 198 ; <3=> Mass erase is enabled
bogdanm 20:4263a77256ae 199 ; <i> Mass Erase Enable Bits
bogdanm 20:4263a77256ae 200 ; <i> Enables and disables mass erase capability of the FTFL module
bogdanm 20:4263a77256ae 201 ; <o.6..7> KEYEN
bogdanm 20:4263a77256ae 202 ; <2=> Backdoor key access enabled
bogdanm 20:4263a77256ae 203 ; <3=> Backdoor key access disabled
bogdanm 20:4263a77256ae 204 ; <i> Backdoor key Security Enable
bogdanm 20:4263a77256ae 205 ; <i> These bits enable and disable backdoor key access to the FTFL module.
bogdanm 20:4263a77256ae 206 FSEC EQU 0xFE
bogdanm 20:4263a77256ae 207 ; </h>
bogdanm 20:4263a77256ae 208
bogdanm 20:4263a77256ae 209 IF :LNOT::DEF:RAM_TARGET
bogdanm 20:4263a77256ae 210 AREA |.ARM.__at_0x400|, CODE, READONLY
bogdanm 20:4263a77256ae 211 DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
bogdanm 20:4263a77256ae 212 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
bogdanm 20:4263a77256ae 213 DCB FPROT0, FPROT1, FPROT2, FPROT3
bogdanm 20:4263a77256ae 214 DCB FSEC, FOPT, 0xFF, 0xFF
bogdanm 20:4263a77256ae 215 ENDIF
bogdanm 20:4263a77256ae 216
bogdanm 20:4263a77256ae 217 AREA |.text|, CODE, READONLY
bogdanm 20:4263a77256ae 218
bogdanm 20:4263a77256ae 219
bogdanm 20:4263a77256ae 220 ; Reset Handler
bogdanm 20:4263a77256ae 221
bogdanm 20:4263a77256ae 222 Reset_Handler PROC
bogdanm 20:4263a77256ae 223 EXPORT Reset_Handler [WEAK]
bogdanm 20:4263a77256ae 224 IMPORT SystemInit
bogdanm 20:4263a77256ae 225 IMPORT __main
bogdanm 20:4263a77256ae 226 LDR R0, =SystemInit
bogdanm 20:4263a77256ae 227 BLX R0
bogdanm 20:4263a77256ae 228 LDR R0, =__main
bogdanm 20:4263a77256ae 229 BX R0
bogdanm 20:4263a77256ae 230 ENDP
bogdanm 20:4263a77256ae 231
bogdanm 20:4263a77256ae 232
bogdanm 20:4263a77256ae 233 ; Dummy Exception Handlers (infinite loops which can be modified)
bogdanm 20:4263a77256ae 234
bogdanm 20:4263a77256ae 235 NMI_Handler PROC
bogdanm 20:4263a77256ae 236 EXPORT NMI_Handler [WEAK]
bogdanm 20:4263a77256ae 237 B .
bogdanm 20:4263a77256ae 238 ENDP
bogdanm 20:4263a77256ae 239 HardFault_Handler\
bogdanm 20:4263a77256ae 240 PROC
bogdanm 20:4263a77256ae 241 EXPORT HardFault_Handler [WEAK]
bogdanm 20:4263a77256ae 242 B .
bogdanm 20:4263a77256ae 243 ENDP
bogdanm 20:4263a77256ae 244 SVC_Handler PROC
bogdanm 20:4263a77256ae 245 EXPORT SVC_Handler [WEAK]
bogdanm 20:4263a77256ae 246 B .
bogdanm 20:4263a77256ae 247 ENDP
bogdanm 20:4263a77256ae 248 PendSV_Handler PROC
bogdanm 20:4263a77256ae 249 EXPORT PendSV_Handler [WEAK]
bogdanm 20:4263a77256ae 250 B .
bogdanm 20:4263a77256ae 251 ENDP
bogdanm 20:4263a77256ae 252 SysTick_Handler PROC
bogdanm 20:4263a77256ae 253 EXPORT SysTick_Handler [WEAK]
bogdanm 20:4263a77256ae 254 B .
bogdanm 20:4263a77256ae 255 ENDP
bogdanm 20:4263a77256ae 256
bogdanm 20:4263a77256ae 257 Default_Handler PROC
bogdanm 20:4263a77256ae 258 EXPORT DMA0_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 259 EXPORT DMA1_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 260 EXPORT DMA2_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 261 EXPORT DMA3_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 262 EXPORT Reserved20_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 263 EXPORT FTFA_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 264 EXPORT LVD_LVW_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 265 EXPORT LLW_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 266 EXPORT I2C0_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 267 EXPORT Reserved_25_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 268 EXPORT SPI0_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 269 EXPORT Reserved_27_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 270 EXPORT UART0_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 271 EXPORT Reserved_29_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 272 EXPORT Reserved_30_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 273 EXPORT ADC0_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 274 EXPORT CMP0_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 275 EXPORT TPM0_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 276 EXPORT TPM1_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 277 EXPORT Reserved_35_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 278 EXPORT RTC_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 279 EXPORT RTC_Seconds_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 280 EXPORT PIT_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 281 EXPORT Reserved_39_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 282 EXPORT Reserved_40_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 283 EXPORT DAC0_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 284 EXPORT TSI0_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 285 EXPORT MCG_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 286 EXPORT LPTimer_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 287 EXPORT Reserved_45_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 288 EXPORT PORTA_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 289 EXPORT PORTB_IRQHandler [WEAK]
bogdanm 20:4263a77256ae 290 EXPORT DefaultISR [WEAK]
bogdanm 20:4263a77256ae 291
bogdanm 20:4263a77256ae 292 DMA0_IRQHandler
bogdanm 20:4263a77256ae 293 DMA1_IRQHandler
bogdanm 20:4263a77256ae 294 DMA2_IRQHandler
bogdanm 20:4263a77256ae 295 DMA3_IRQHandler
bogdanm 20:4263a77256ae 296 Reserved20_IRQHandler
bogdanm 20:4263a77256ae 297 FTFA_IRQHandler
bogdanm 20:4263a77256ae 298 LVD_LVW_IRQHandler
bogdanm 20:4263a77256ae 299 LLW_IRQHandler
bogdanm 20:4263a77256ae 300 I2C0_IRQHandler
bogdanm 20:4263a77256ae 301 Reserved_25_IRQHandler
bogdanm 20:4263a77256ae 302 SPI0_IRQHandler
bogdanm 20:4263a77256ae 303 Reserved_27_IRQHandler
bogdanm 20:4263a77256ae 304 UART0_IRQHandler
bogdanm 20:4263a77256ae 305 Reserved_29_IRQHandler
bogdanm 20:4263a77256ae 306 Reserved_30_IRQHandler
bogdanm 20:4263a77256ae 307 ADC0_IRQHandler
bogdanm 20:4263a77256ae 308 CMP0_IRQHandler
bogdanm 20:4263a77256ae 309 TPM0_IRQHandler
bogdanm 20:4263a77256ae 310 TPM1_IRQHandler
bogdanm 20:4263a77256ae 311 Reserved_35_IRQHandler
bogdanm 20:4263a77256ae 312 RTC_IRQHandler
bogdanm 20:4263a77256ae 313 RTC_Seconds_IRQHandler
bogdanm 20:4263a77256ae 314 PIT_IRQHandler
bogdanm 20:4263a77256ae 315 Reserved_39_IRQHandler
bogdanm 20:4263a77256ae 316 Reserved_40_IRQHandler
bogdanm 20:4263a77256ae 317 DAC0_IRQHandler
bogdanm 20:4263a77256ae 318 TSI0_IRQHandler
bogdanm 20:4263a77256ae 319 MCG_IRQHandler
bogdanm 20:4263a77256ae 320 LPTimer_IRQHandler
bogdanm 20:4263a77256ae 321 Reserved_45_IRQHandler
bogdanm 20:4263a77256ae 322 PORTA_IRQHandler
bogdanm 20:4263a77256ae 323 PORTB_IRQHandler
bogdanm 20:4263a77256ae 324 DefaultISR
bogdanm 20:4263a77256ae 325
bogdanm 20:4263a77256ae 326 B .
bogdanm 20:4263a77256ae 327
bogdanm 20:4263a77256ae 328 ENDP
bogdanm 20:4263a77256ae 329
bogdanm 20:4263a77256ae 330
bogdanm 20:4263a77256ae 331 ALIGN
bogdanm 20:4263a77256ae 332 END