mbed library sources: Modified to operate FRDM-KL25Z at 48MHz from internal 32kHz oscillator (nothing else changed).

Fork of mbed-src by mbed official

The only file that changed is: mbed-src-FLL48/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h

Committer:
bogdanm
Date:
Tue Sep 10 15:14:19 2013 +0300
Revision:
20:4263a77256ae
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 20:4263a77256ae 1 /*
bogdanm 20:4263a77256ae 2 ** ###################################################################
bogdanm 20:4263a77256ae 3 ** Processors: MKL05Z32FK4
bogdanm 20:4263a77256ae 4 ** MKL05Z32LC4
bogdanm 20:4263a77256ae 5 ** MKL05Z32VLF4
bogdanm 20:4263a77256ae 6 **
bogdanm 20:4263a77256ae 7 ** Compilers: ARM Compiler
bogdanm 20:4263a77256ae 8 ** Freescale C/C++ for Embedded ARM
bogdanm 20:4263a77256ae 9 ** GNU C Compiler
bogdanm 20:4263a77256ae 10 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 20:4263a77256ae 11 **
bogdanm 20:4263a77256ae 12 ** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
bogdanm 20:4263a77256ae 13 ** Version: rev. 1.3, 2012-10-04
bogdanm 20:4263a77256ae 14 **
bogdanm 20:4263a77256ae 15 ** Abstract:
bogdanm 20:4263a77256ae 16 ** CMSIS Peripheral Access Layer for MKL05Z4
bogdanm 20:4263a77256ae 17 **
bogdanm 20:4263a77256ae 18 ** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
bogdanm 20:4263a77256ae 19 **
bogdanm 20:4263a77256ae 20 ** http: www.freescale.com
bogdanm 20:4263a77256ae 21 ** mail: support@freescale.com
bogdanm 20:4263a77256ae 22 **
bogdanm 20:4263a77256ae 23 ** Revisions:
bogdanm 20:4263a77256ae 24 ** - rev. 1.0 (2012-06-08)
bogdanm 20:4263a77256ae 25 ** Initial version.
bogdanm 20:4263a77256ae 26 ** - rev. 1.1 (2012-06-21)
bogdanm 20:4263a77256ae 27 ** Update according to reference manual rev. 1.
bogdanm 20:4263a77256ae 28 ** - rev. 1.2 (2012-08-01)
bogdanm 20:4263a77256ae 29 ** Device type UARTLP changed to UART0.
bogdanm 20:4263a77256ae 30 ** Missing PORTB_IRQn interrupt number definition added.
bogdanm 20:4263a77256ae 31 ** - rev. 1.3 (2012-10-04)
bogdanm 20:4263a77256ae 32 ** Update according to reference manual rev. 3.
bogdanm 20:4263a77256ae 33 **
bogdanm 20:4263a77256ae 34 ** ###################################################################
bogdanm 20:4263a77256ae 35 */
bogdanm 20:4263a77256ae 36
bogdanm 20:4263a77256ae 37 /**
bogdanm 20:4263a77256ae 38 * @file MKL05Z4.h
bogdanm 20:4263a77256ae 39 * @version 1.3
bogdanm 20:4263a77256ae 40 * @date 2012-10-04
bogdanm 20:4263a77256ae 41 * @brief CMSIS Peripheral Access Layer for MKL05Z4
bogdanm 20:4263a77256ae 42 *
bogdanm 20:4263a77256ae 43 * CMSIS Peripheral Access Layer for MKL05Z4
bogdanm 20:4263a77256ae 44 */
bogdanm 20:4263a77256ae 45
bogdanm 20:4263a77256ae 46 #if !defined(MKL05Z4_H_)
bogdanm 20:4263a77256ae 47 #define MKL05Z4_H_ /**< Symbol preventing repeated inclusion */
bogdanm 20:4263a77256ae 48
bogdanm 20:4263a77256ae 49 /** Memory map major version (memory maps with equal major version number are
bogdanm 20:4263a77256ae 50 * compatible) */
bogdanm 20:4263a77256ae 51 #define MCU_MEM_MAP_VERSION 0x0100u
bogdanm 20:4263a77256ae 52 /** Memory map minor version */
bogdanm 20:4263a77256ae 53 #define MCU_MEM_MAP_VERSION_MINOR 0x0003u
bogdanm 20:4263a77256ae 54
bogdanm 20:4263a77256ae 55
bogdanm 20:4263a77256ae 56 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 57 -- Interrupt vector numbers
bogdanm 20:4263a77256ae 58 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 59
bogdanm 20:4263a77256ae 60 /**
bogdanm 20:4263a77256ae 61 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
bogdanm 20:4263a77256ae 62 * @{
bogdanm 20:4263a77256ae 63 */
bogdanm 20:4263a77256ae 64
bogdanm 20:4263a77256ae 65 /** Interrupt Number Definitions */
bogdanm 20:4263a77256ae 66 typedef enum IRQn {
bogdanm 20:4263a77256ae 67 /* Core interrupts */
bogdanm 20:4263a77256ae 68 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
bogdanm 20:4263a77256ae 69 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
bogdanm 20:4263a77256ae 70 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
bogdanm 20:4263a77256ae 71 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
bogdanm 20:4263a77256ae 72 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
bogdanm 20:4263a77256ae 73
bogdanm 20:4263a77256ae 74 /* Device specific interrupts */
bogdanm 20:4263a77256ae 75 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
bogdanm 20:4263a77256ae 76 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
bogdanm 20:4263a77256ae 77 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
bogdanm 20:4263a77256ae 78 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
bogdanm 20:4263a77256ae 79 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
bogdanm 20:4263a77256ae 80 FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
bogdanm 20:4263a77256ae 81 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
bogdanm 20:4263a77256ae 82 LLW_IRQn = 7, /**< Low Leakage Wakeup */
bogdanm 20:4263a77256ae 83 I2C0_IRQn = 8, /**< I2C0 interrupt */
bogdanm 20:4263a77256ae 84 Reserved25_IRQn = 9, /**< Reserved interrupt 25 */
bogdanm 20:4263a77256ae 85 SPI0_IRQn = 10, /**< SPI0 interrupt */
bogdanm 20:4263a77256ae 86 Reserved27_IRQn = 11, /**< Reserved interrupt 27 */
bogdanm 20:4263a77256ae 87 UART0_IRQn = 12, /**< UART0 status/error interrupt */
bogdanm 20:4263a77256ae 88 Reserved29_IRQn = 13, /**< Reserved interrupt 29 */
bogdanm 20:4263a77256ae 89 Reserved30_IRQn = 14, /**< Reserved interrupt 30 */
bogdanm 20:4263a77256ae 90 ADC0_IRQn = 15, /**< ADC0 interrupt */
bogdanm 20:4263a77256ae 91 CMP0_IRQn = 16, /**< CMP0 interrupt */
bogdanm 20:4263a77256ae 92 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
bogdanm 20:4263a77256ae 93 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
bogdanm 20:4263a77256ae 94 Reserved35_IRQn = 19, /**< Reserved interrupt 35 */
bogdanm 20:4263a77256ae 95 RTC_IRQn = 20, /**< RTC interrupt */
bogdanm 20:4263a77256ae 96 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
bogdanm 20:4263a77256ae 97 PIT_IRQn = 22, /**< PIT timer interrupt */
bogdanm 20:4263a77256ae 98 Reserved39_IRQn = 23, /**< Reserved interrupt 39 */
bogdanm 20:4263a77256ae 99 Reserved40_IRQn = 24, /**< Reserved interrupt 40 */
bogdanm 20:4263a77256ae 100 DAC0_IRQn = 25, /**< DAC0 interrupt */
bogdanm 20:4263a77256ae 101 TSI0_IRQn = 26, /**< TSI0 interrupt */
bogdanm 20:4263a77256ae 102 MCG_IRQn = 27, /**< MCG interrupt */
bogdanm 20:4263a77256ae 103 LPTimer_IRQn = 28, /**< LPTimer interrupt */
bogdanm 20:4263a77256ae 104 Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
bogdanm 20:4263a77256ae 105 PORTA_IRQn = 30, /**< Port A interrupt */
bogdanm 20:4263a77256ae 106 PORTB_IRQn = 31 /**< Port B interrupt */
bogdanm 20:4263a77256ae 107 } IRQn_Type;
bogdanm 20:4263a77256ae 108
bogdanm 20:4263a77256ae 109 /**
bogdanm 20:4263a77256ae 110 * @}
bogdanm 20:4263a77256ae 111 */ /* end of group Interrupt_vector_numbers */
bogdanm 20:4263a77256ae 112
bogdanm 20:4263a77256ae 113
bogdanm 20:4263a77256ae 114 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 115 -- Cortex M0 Core Configuration
bogdanm 20:4263a77256ae 116 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 117
bogdanm 20:4263a77256ae 118 /**
bogdanm 20:4263a77256ae 119 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
bogdanm 20:4263a77256ae 120 * @{
bogdanm 20:4263a77256ae 121 */
bogdanm 20:4263a77256ae 122
bogdanm 20:4263a77256ae 123 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
bogdanm 20:4263a77256ae 124 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
bogdanm 20:4263a77256ae 125 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
bogdanm 20:4263a77256ae 126 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
bogdanm 20:4263a77256ae 127 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
bogdanm 20:4263a77256ae 128
bogdanm 20:4263a77256ae 129 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
bogdanm 20:4263a77256ae 130 #include "system_MKL05Z4.h" /* Device specific configuration file */
bogdanm 20:4263a77256ae 131
bogdanm 20:4263a77256ae 132 /**
bogdanm 20:4263a77256ae 133 * @}
bogdanm 20:4263a77256ae 134 */ /* end of group Cortex_Core_Configuration */
bogdanm 20:4263a77256ae 135
bogdanm 20:4263a77256ae 136
bogdanm 20:4263a77256ae 137 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 138 -- Device Peripheral Access Layer
bogdanm 20:4263a77256ae 139 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 140
bogdanm 20:4263a77256ae 141 /**
bogdanm 20:4263a77256ae 142 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
bogdanm 20:4263a77256ae 143 * @{
bogdanm 20:4263a77256ae 144 */
bogdanm 20:4263a77256ae 145
bogdanm 20:4263a77256ae 146
bogdanm 20:4263a77256ae 147 /*
bogdanm 20:4263a77256ae 148 ** Start of section using anonymous unions
bogdanm 20:4263a77256ae 149 */
bogdanm 20:4263a77256ae 150
bogdanm 20:4263a77256ae 151 #if defined(__ARMCC_VERSION)
bogdanm 20:4263a77256ae 152 #pragma push
bogdanm 20:4263a77256ae 153 #pragma anon_unions
bogdanm 20:4263a77256ae 154 #elif defined(__CWCC__)
bogdanm 20:4263a77256ae 155 #pragma push
bogdanm 20:4263a77256ae 156 #pragma cpp_extensions on
bogdanm 20:4263a77256ae 157 #elif defined(__GNUC__)
bogdanm 20:4263a77256ae 158 /* anonymous unions are enabled by default */
bogdanm 20:4263a77256ae 159 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 20:4263a77256ae 160 #pragma language=extended
bogdanm 20:4263a77256ae 161 #else
bogdanm 20:4263a77256ae 162 #error Not supported compiler type
bogdanm 20:4263a77256ae 163 #endif
bogdanm 20:4263a77256ae 164
bogdanm 20:4263a77256ae 165 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 166 -- ADC Peripheral Access Layer
bogdanm 20:4263a77256ae 167 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 168
bogdanm 20:4263a77256ae 169 /**
bogdanm 20:4263a77256ae 170 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
bogdanm 20:4263a77256ae 171 * @{
bogdanm 20:4263a77256ae 172 */
bogdanm 20:4263a77256ae 173
bogdanm 20:4263a77256ae 174 /** ADC - Register Layout Typedef */
bogdanm 20:4263a77256ae 175 typedef struct {
bogdanm 20:4263a77256ae 176 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
bogdanm 20:4263a77256ae 177 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
bogdanm 20:4263a77256ae 178 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
bogdanm 20:4263a77256ae 179 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
bogdanm 20:4263a77256ae 180 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
bogdanm 20:4263a77256ae 181 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
bogdanm 20:4263a77256ae 182 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
bogdanm 20:4263a77256ae 183 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
bogdanm 20:4263a77256ae 184 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
bogdanm 20:4263a77256ae 185 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
bogdanm 20:4263a77256ae 186 uint8_t RESERVED_0[4];
bogdanm 20:4263a77256ae 187 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
bogdanm 20:4263a77256ae 188 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
bogdanm 20:4263a77256ae 189 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
bogdanm 20:4263a77256ae 190 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
bogdanm 20:4263a77256ae 191 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
bogdanm 20:4263a77256ae 192 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
bogdanm 20:4263a77256ae 193 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
bogdanm 20:4263a77256ae 194 } ADC_Type;
bogdanm 20:4263a77256ae 195
bogdanm 20:4263a77256ae 196 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 197 -- ADC Register Masks
bogdanm 20:4263a77256ae 198 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 199
bogdanm 20:4263a77256ae 200 /**
bogdanm 20:4263a77256ae 201 * @addtogroup ADC_Register_Masks ADC Register Masks
bogdanm 20:4263a77256ae 202 * @{
bogdanm 20:4263a77256ae 203 */
bogdanm 20:4263a77256ae 204
bogdanm 20:4263a77256ae 205 /* SC1 Bit Fields */
bogdanm 20:4263a77256ae 206 #define ADC_SC1_ADCH_MASK 0x1Fu
bogdanm 20:4263a77256ae 207 #define ADC_SC1_ADCH_SHIFT 0
bogdanm 20:4263a77256ae 208 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
bogdanm 20:4263a77256ae 209 #define ADC_SC1_AIEN_MASK 0x40u
bogdanm 20:4263a77256ae 210 #define ADC_SC1_AIEN_SHIFT 6
bogdanm 20:4263a77256ae 211 #define ADC_SC1_COCO_MASK 0x80u
bogdanm 20:4263a77256ae 212 #define ADC_SC1_COCO_SHIFT 7
bogdanm 20:4263a77256ae 213 /* CFG1 Bit Fields */
bogdanm 20:4263a77256ae 214 #define ADC_CFG1_ADICLK_MASK 0x3u
bogdanm 20:4263a77256ae 215 #define ADC_CFG1_ADICLK_SHIFT 0
bogdanm 20:4263a77256ae 216 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
bogdanm 20:4263a77256ae 217 #define ADC_CFG1_MODE_MASK 0xCu
bogdanm 20:4263a77256ae 218 #define ADC_CFG1_MODE_SHIFT 2
bogdanm 20:4263a77256ae 219 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
bogdanm 20:4263a77256ae 220 #define ADC_CFG1_ADLSMP_MASK 0x10u
bogdanm 20:4263a77256ae 221 #define ADC_CFG1_ADLSMP_SHIFT 4
bogdanm 20:4263a77256ae 222 #define ADC_CFG1_ADIV_MASK 0x60u
bogdanm 20:4263a77256ae 223 #define ADC_CFG1_ADIV_SHIFT 5
bogdanm 20:4263a77256ae 224 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
bogdanm 20:4263a77256ae 225 #define ADC_CFG1_ADLPC_MASK 0x80u
bogdanm 20:4263a77256ae 226 #define ADC_CFG1_ADLPC_SHIFT 7
bogdanm 20:4263a77256ae 227 /* CFG2 Bit Fields */
bogdanm 20:4263a77256ae 228 #define ADC_CFG2_ADLSTS_MASK 0x3u
bogdanm 20:4263a77256ae 229 #define ADC_CFG2_ADLSTS_SHIFT 0
bogdanm 20:4263a77256ae 230 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
bogdanm 20:4263a77256ae 231 #define ADC_CFG2_ADHSC_MASK 0x4u
bogdanm 20:4263a77256ae 232 #define ADC_CFG2_ADHSC_SHIFT 2
bogdanm 20:4263a77256ae 233 #define ADC_CFG2_ADACKEN_MASK 0x8u
bogdanm 20:4263a77256ae 234 #define ADC_CFG2_ADACKEN_SHIFT 3
bogdanm 20:4263a77256ae 235 #define ADC_CFG2_MUXSEL_MASK 0x10u
bogdanm 20:4263a77256ae 236 #define ADC_CFG2_MUXSEL_SHIFT 4
bogdanm 20:4263a77256ae 237 /* R Bit Fields */
bogdanm 20:4263a77256ae 238 #define ADC_R_D_MASK 0xFFFFu
bogdanm 20:4263a77256ae 239 #define ADC_R_D_SHIFT 0
bogdanm 20:4263a77256ae 240 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
bogdanm 20:4263a77256ae 241 /* CV1 Bit Fields */
bogdanm 20:4263a77256ae 242 #define ADC_CV1_CV_MASK 0xFFFFu
bogdanm 20:4263a77256ae 243 #define ADC_CV1_CV_SHIFT 0
bogdanm 20:4263a77256ae 244 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
bogdanm 20:4263a77256ae 245 /* CV2 Bit Fields */
bogdanm 20:4263a77256ae 246 #define ADC_CV2_CV_MASK 0xFFFFu
bogdanm 20:4263a77256ae 247 #define ADC_CV2_CV_SHIFT 0
bogdanm 20:4263a77256ae 248 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
bogdanm 20:4263a77256ae 249 /* SC2 Bit Fields */
bogdanm 20:4263a77256ae 250 #define ADC_SC2_REFSEL_MASK 0x3u
bogdanm 20:4263a77256ae 251 #define ADC_SC2_REFSEL_SHIFT 0
bogdanm 20:4263a77256ae 252 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
bogdanm 20:4263a77256ae 253 #define ADC_SC2_DMAEN_MASK 0x4u
bogdanm 20:4263a77256ae 254 #define ADC_SC2_DMAEN_SHIFT 2
bogdanm 20:4263a77256ae 255 #define ADC_SC2_ACREN_MASK 0x8u
bogdanm 20:4263a77256ae 256 #define ADC_SC2_ACREN_SHIFT 3
bogdanm 20:4263a77256ae 257 #define ADC_SC2_ACFGT_MASK 0x10u
bogdanm 20:4263a77256ae 258 #define ADC_SC2_ACFGT_SHIFT 4
bogdanm 20:4263a77256ae 259 #define ADC_SC2_ACFE_MASK 0x20u
bogdanm 20:4263a77256ae 260 #define ADC_SC2_ACFE_SHIFT 5
bogdanm 20:4263a77256ae 261 #define ADC_SC2_ADTRG_MASK 0x40u
bogdanm 20:4263a77256ae 262 #define ADC_SC2_ADTRG_SHIFT 6
bogdanm 20:4263a77256ae 263 #define ADC_SC2_ADACT_MASK 0x80u
bogdanm 20:4263a77256ae 264 #define ADC_SC2_ADACT_SHIFT 7
bogdanm 20:4263a77256ae 265 /* SC3 Bit Fields */
bogdanm 20:4263a77256ae 266 #define ADC_SC3_AVGS_MASK 0x3u
bogdanm 20:4263a77256ae 267 #define ADC_SC3_AVGS_SHIFT 0
bogdanm 20:4263a77256ae 268 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
bogdanm 20:4263a77256ae 269 #define ADC_SC3_AVGE_MASK 0x4u
bogdanm 20:4263a77256ae 270 #define ADC_SC3_AVGE_SHIFT 2
bogdanm 20:4263a77256ae 271 #define ADC_SC3_ADCO_MASK 0x8u
bogdanm 20:4263a77256ae 272 #define ADC_SC3_ADCO_SHIFT 3
bogdanm 20:4263a77256ae 273 #define ADC_SC3_CALF_MASK 0x40u
bogdanm 20:4263a77256ae 274 #define ADC_SC3_CALF_SHIFT 6
bogdanm 20:4263a77256ae 275 #define ADC_SC3_CAL_MASK 0x80u
bogdanm 20:4263a77256ae 276 #define ADC_SC3_CAL_SHIFT 7
bogdanm 20:4263a77256ae 277 /* OFS Bit Fields */
bogdanm 20:4263a77256ae 278 #define ADC_OFS_OFS_MASK 0xFFFFu
bogdanm 20:4263a77256ae 279 #define ADC_OFS_OFS_SHIFT 0
bogdanm 20:4263a77256ae 280 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
bogdanm 20:4263a77256ae 281 /* PG Bit Fields */
bogdanm 20:4263a77256ae 282 #define ADC_PG_PG_MASK 0xFFFFu
bogdanm 20:4263a77256ae 283 #define ADC_PG_PG_SHIFT 0
bogdanm 20:4263a77256ae 284 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
bogdanm 20:4263a77256ae 285 /* CLPD Bit Fields */
bogdanm 20:4263a77256ae 286 #define ADC_CLPD_CLPD_MASK 0x3Fu
bogdanm 20:4263a77256ae 287 #define ADC_CLPD_CLPD_SHIFT 0
bogdanm 20:4263a77256ae 288 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
bogdanm 20:4263a77256ae 289 /* CLPS Bit Fields */
bogdanm 20:4263a77256ae 290 #define ADC_CLPS_CLPS_MASK 0x3Fu
bogdanm 20:4263a77256ae 291 #define ADC_CLPS_CLPS_SHIFT 0
bogdanm 20:4263a77256ae 292 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
bogdanm 20:4263a77256ae 293 /* CLP4 Bit Fields */
bogdanm 20:4263a77256ae 294 #define ADC_CLP4_CLP4_MASK 0x3FFu
bogdanm 20:4263a77256ae 295 #define ADC_CLP4_CLP4_SHIFT 0
bogdanm 20:4263a77256ae 296 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
bogdanm 20:4263a77256ae 297 /* CLP3 Bit Fields */
bogdanm 20:4263a77256ae 298 #define ADC_CLP3_CLP3_MASK 0x1FFu
bogdanm 20:4263a77256ae 299 #define ADC_CLP3_CLP3_SHIFT 0
bogdanm 20:4263a77256ae 300 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
bogdanm 20:4263a77256ae 301 /* CLP2 Bit Fields */
bogdanm 20:4263a77256ae 302 #define ADC_CLP2_CLP2_MASK 0xFFu
bogdanm 20:4263a77256ae 303 #define ADC_CLP2_CLP2_SHIFT 0
bogdanm 20:4263a77256ae 304 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
bogdanm 20:4263a77256ae 305 /* CLP1 Bit Fields */
bogdanm 20:4263a77256ae 306 #define ADC_CLP1_CLP1_MASK 0x7Fu
bogdanm 20:4263a77256ae 307 #define ADC_CLP1_CLP1_SHIFT 0
bogdanm 20:4263a77256ae 308 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
bogdanm 20:4263a77256ae 309 /* CLP0 Bit Fields */
bogdanm 20:4263a77256ae 310 #define ADC_CLP0_CLP0_MASK 0x3Fu
bogdanm 20:4263a77256ae 311 #define ADC_CLP0_CLP0_SHIFT 0
bogdanm 20:4263a77256ae 312 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
bogdanm 20:4263a77256ae 313
bogdanm 20:4263a77256ae 314 /**
bogdanm 20:4263a77256ae 315 * @}
bogdanm 20:4263a77256ae 316 */ /* end of group ADC_Register_Masks */
bogdanm 20:4263a77256ae 317
bogdanm 20:4263a77256ae 318
bogdanm 20:4263a77256ae 319 /* ADC - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 320 /** Peripheral ADC0 base address */
bogdanm 20:4263a77256ae 321 #define ADC0_BASE (0x4003B000u)
bogdanm 20:4263a77256ae 322 /** Peripheral ADC0 base pointer */
bogdanm 20:4263a77256ae 323 #define ADC0 ((ADC_Type *)ADC0_BASE)
bogdanm 20:4263a77256ae 324 /** Array initializer of ADC peripheral base pointers */
bogdanm 20:4263a77256ae 325 #define ADC_BASES { ADC0 }
bogdanm 20:4263a77256ae 326
bogdanm 20:4263a77256ae 327 /**
bogdanm 20:4263a77256ae 328 * @}
bogdanm 20:4263a77256ae 329 */ /* end of group ADC_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 330
bogdanm 20:4263a77256ae 331
bogdanm 20:4263a77256ae 332 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 333 -- CMP Peripheral Access Layer
bogdanm 20:4263a77256ae 334 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 335
bogdanm 20:4263a77256ae 336 /**
bogdanm 20:4263a77256ae 337 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
bogdanm 20:4263a77256ae 338 * @{
bogdanm 20:4263a77256ae 339 */
bogdanm 20:4263a77256ae 340
bogdanm 20:4263a77256ae 341 /** CMP - Register Layout Typedef */
bogdanm 20:4263a77256ae 342 typedef struct {
bogdanm 20:4263a77256ae 343 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
bogdanm 20:4263a77256ae 344 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
bogdanm 20:4263a77256ae 345 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
bogdanm 20:4263a77256ae 346 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
bogdanm 20:4263a77256ae 347 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
bogdanm 20:4263a77256ae 348 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
bogdanm 20:4263a77256ae 349 } CMP_Type;
bogdanm 20:4263a77256ae 350
bogdanm 20:4263a77256ae 351 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 352 -- CMP Register Masks
bogdanm 20:4263a77256ae 353 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 354
bogdanm 20:4263a77256ae 355 /**
bogdanm 20:4263a77256ae 356 * @addtogroup CMP_Register_Masks CMP Register Masks
bogdanm 20:4263a77256ae 357 * @{
bogdanm 20:4263a77256ae 358 */
bogdanm 20:4263a77256ae 359
bogdanm 20:4263a77256ae 360 /* CR0 Bit Fields */
bogdanm 20:4263a77256ae 361 #define CMP_CR0_HYSTCTR_MASK 0x3u
bogdanm 20:4263a77256ae 362 #define CMP_CR0_HYSTCTR_SHIFT 0
bogdanm 20:4263a77256ae 363 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
bogdanm 20:4263a77256ae 364 #define CMP_CR0_FILTER_CNT_MASK 0x70u
bogdanm 20:4263a77256ae 365 #define CMP_CR0_FILTER_CNT_SHIFT 4
bogdanm 20:4263a77256ae 366 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
bogdanm 20:4263a77256ae 367 /* CR1 Bit Fields */
bogdanm 20:4263a77256ae 368 #define CMP_CR1_EN_MASK 0x1u
bogdanm 20:4263a77256ae 369 #define CMP_CR1_EN_SHIFT 0
bogdanm 20:4263a77256ae 370 #define CMP_CR1_OPE_MASK 0x2u
bogdanm 20:4263a77256ae 371 #define CMP_CR1_OPE_SHIFT 1
bogdanm 20:4263a77256ae 372 #define CMP_CR1_COS_MASK 0x4u
bogdanm 20:4263a77256ae 373 #define CMP_CR1_COS_SHIFT 2
bogdanm 20:4263a77256ae 374 #define CMP_CR1_INV_MASK 0x8u
bogdanm 20:4263a77256ae 375 #define CMP_CR1_INV_SHIFT 3
bogdanm 20:4263a77256ae 376 #define CMP_CR1_PMODE_MASK 0x10u
bogdanm 20:4263a77256ae 377 #define CMP_CR1_PMODE_SHIFT 4
bogdanm 20:4263a77256ae 378 #define CMP_CR1_TRIGM_MASK 0x20u
bogdanm 20:4263a77256ae 379 #define CMP_CR1_TRIGM_SHIFT 5
bogdanm 20:4263a77256ae 380 #define CMP_CR1_WE_MASK 0x40u
bogdanm 20:4263a77256ae 381 #define CMP_CR1_WE_SHIFT 6
bogdanm 20:4263a77256ae 382 #define CMP_CR1_SE_MASK 0x80u
bogdanm 20:4263a77256ae 383 #define CMP_CR1_SE_SHIFT 7
bogdanm 20:4263a77256ae 384 /* FPR Bit Fields */
bogdanm 20:4263a77256ae 385 #define CMP_FPR_FILT_PER_MASK 0xFFu
bogdanm 20:4263a77256ae 386 #define CMP_FPR_FILT_PER_SHIFT 0
bogdanm 20:4263a77256ae 387 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
bogdanm 20:4263a77256ae 388 /* SCR Bit Fields */
bogdanm 20:4263a77256ae 389 #define CMP_SCR_COUT_MASK 0x1u
bogdanm 20:4263a77256ae 390 #define CMP_SCR_COUT_SHIFT 0
bogdanm 20:4263a77256ae 391 #define CMP_SCR_CFF_MASK 0x2u
bogdanm 20:4263a77256ae 392 #define CMP_SCR_CFF_SHIFT 1
bogdanm 20:4263a77256ae 393 #define CMP_SCR_CFR_MASK 0x4u
bogdanm 20:4263a77256ae 394 #define CMP_SCR_CFR_SHIFT 2
bogdanm 20:4263a77256ae 395 #define CMP_SCR_IEF_MASK 0x8u
bogdanm 20:4263a77256ae 396 #define CMP_SCR_IEF_SHIFT 3
bogdanm 20:4263a77256ae 397 #define CMP_SCR_IER_MASK 0x10u
bogdanm 20:4263a77256ae 398 #define CMP_SCR_IER_SHIFT 4
bogdanm 20:4263a77256ae 399 #define CMP_SCR_DMAEN_MASK 0x40u
bogdanm 20:4263a77256ae 400 #define CMP_SCR_DMAEN_SHIFT 6
bogdanm 20:4263a77256ae 401 /* DACCR Bit Fields */
bogdanm 20:4263a77256ae 402 #define CMP_DACCR_VOSEL_MASK 0x3Fu
bogdanm 20:4263a77256ae 403 #define CMP_DACCR_VOSEL_SHIFT 0
bogdanm 20:4263a77256ae 404 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
bogdanm 20:4263a77256ae 405 #define CMP_DACCR_VRSEL_MASK 0x40u
bogdanm 20:4263a77256ae 406 #define CMP_DACCR_VRSEL_SHIFT 6
bogdanm 20:4263a77256ae 407 #define CMP_DACCR_DACEN_MASK 0x80u
bogdanm 20:4263a77256ae 408 #define CMP_DACCR_DACEN_SHIFT 7
bogdanm 20:4263a77256ae 409 /* MUXCR Bit Fields */
bogdanm 20:4263a77256ae 410 #define CMP_MUXCR_MSEL_MASK 0x7u
bogdanm 20:4263a77256ae 411 #define CMP_MUXCR_MSEL_SHIFT 0
bogdanm 20:4263a77256ae 412 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
bogdanm 20:4263a77256ae 413 #define CMP_MUXCR_PSEL_MASK 0x38u
bogdanm 20:4263a77256ae 414 #define CMP_MUXCR_PSEL_SHIFT 3
bogdanm 20:4263a77256ae 415 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
bogdanm 20:4263a77256ae 416 #define CMP_MUXCR_PSTM_MASK 0x80u
bogdanm 20:4263a77256ae 417 #define CMP_MUXCR_PSTM_SHIFT 7
bogdanm 20:4263a77256ae 418
bogdanm 20:4263a77256ae 419 /**
bogdanm 20:4263a77256ae 420 * @}
bogdanm 20:4263a77256ae 421 */ /* end of group CMP_Register_Masks */
bogdanm 20:4263a77256ae 422
bogdanm 20:4263a77256ae 423
bogdanm 20:4263a77256ae 424 /* CMP - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 425 /** Peripheral CMP0 base address */
bogdanm 20:4263a77256ae 426 #define CMP0_BASE (0x40073000u)
bogdanm 20:4263a77256ae 427 /** Peripheral CMP0 base pointer */
bogdanm 20:4263a77256ae 428 #define CMP0 ((CMP_Type *)CMP0_BASE)
bogdanm 20:4263a77256ae 429 /** Array initializer of CMP peripheral base pointers */
bogdanm 20:4263a77256ae 430 #define CMP_BASES { CMP0 }
bogdanm 20:4263a77256ae 431
bogdanm 20:4263a77256ae 432 /**
bogdanm 20:4263a77256ae 433 * @}
bogdanm 20:4263a77256ae 434 */ /* end of group CMP_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 435
bogdanm 20:4263a77256ae 436
bogdanm 20:4263a77256ae 437 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 438 -- DAC Peripheral Access Layer
bogdanm 20:4263a77256ae 439 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 440
bogdanm 20:4263a77256ae 441 /**
bogdanm 20:4263a77256ae 442 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
bogdanm 20:4263a77256ae 443 * @{
bogdanm 20:4263a77256ae 444 */
bogdanm 20:4263a77256ae 445
bogdanm 20:4263a77256ae 446 /** DAC - Register Layout Typedef */
bogdanm 20:4263a77256ae 447 typedef struct {
bogdanm 20:4263a77256ae 448 struct { /* offset: 0x0, array step: 0x2 */
bogdanm 20:4263a77256ae 449 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
bogdanm 20:4263a77256ae 450 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
bogdanm 20:4263a77256ae 451 } DAT[2];
bogdanm 20:4263a77256ae 452 uint8_t RESERVED_0[28];
bogdanm 20:4263a77256ae 453 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
bogdanm 20:4263a77256ae 454 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
bogdanm 20:4263a77256ae 455 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
bogdanm 20:4263a77256ae 456 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
bogdanm 20:4263a77256ae 457 } DAC_Type;
bogdanm 20:4263a77256ae 458
bogdanm 20:4263a77256ae 459 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 460 -- DAC Register Masks
bogdanm 20:4263a77256ae 461 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 462
bogdanm 20:4263a77256ae 463 /**
bogdanm 20:4263a77256ae 464 * @addtogroup DAC_Register_Masks DAC Register Masks
bogdanm 20:4263a77256ae 465 * @{
bogdanm 20:4263a77256ae 466 */
bogdanm 20:4263a77256ae 467
bogdanm 20:4263a77256ae 468 /* DATL Bit Fields */
bogdanm 20:4263a77256ae 469 #define DAC_DATL_DATA0_MASK 0xFFu
bogdanm 20:4263a77256ae 470 #define DAC_DATL_DATA0_SHIFT 0
bogdanm 20:4263a77256ae 471 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
bogdanm 20:4263a77256ae 472 /* DATH Bit Fields */
bogdanm 20:4263a77256ae 473 #define DAC_DATH_DATA1_MASK 0xFu
bogdanm 20:4263a77256ae 474 #define DAC_DATH_DATA1_SHIFT 0
bogdanm 20:4263a77256ae 475 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
bogdanm 20:4263a77256ae 476 /* SR Bit Fields */
bogdanm 20:4263a77256ae 477 #define DAC_SR_DACBFRPBF_MASK 0x1u
bogdanm 20:4263a77256ae 478 #define DAC_SR_DACBFRPBF_SHIFT 0
bogdanm 20:4263a77256ae 479 #define DAC_SR_DACBFRPTF_MASK 0x2u
bogdanm 20:4263a77256ae 480 #define DAC_SR_DACBFRPTF_SHIFT 1
bogdanm 20:4263a77256ae 481 /* C0 Bit Fields */
bogdanm 20:4263a77256ae 482 #define DAC_C0_DACBBIEN_MASK 0x1u
bogdanm 20:4263a77256ae 483 #define DAC_C0_DACBBIEN_SHIFT 0
bogdanm 20:4263a77256ae 484 #define DAC_C0_DACBTIEN_MASK 0x2u
bogdanm 20:4263a77256ae 485 #define DAC_C0_DACBTIEN_SHIFT 1
bogdanm 20:4263a77256ae 486 #define DAC_C0_LPEN_MASK 0x8u
bogdanm 20:4263a77256ae 487 #define DAC_C0_LPEN_SHIFT 3
bogdanm 20:4263a77256ae 488 #define DAC_C0_DACSWTRG_MASK 0x10u
bogdanm 20:4263a77256ae 489 #define DAC_C0_DACSWTRG_SHIFT 4
bogdanm 20:4263a77256ae 490 #define DAC_C0_DACTRGSEL_MASK 0x20u
bogdanm 20:4263a77256ae 491 #define DAC_C0_DACTRGSEL_SHIFT 5
bogdanm 20:4263a77256ae 492 #define DAC_C0_DACRFS_MASK 0x40u
bogdanm 20:4263a77256ae 493 #define DAC_C0_DACRFS_SHIFT 6
bogdanm 20:4263a77256ae 494 #define DAC_C0_DACEN_MASK 0x80u
bogdanm 20:4263a77256ae 495 #define DAC_C0_DACEN_SHIFT 7
bogdanm 20:4263a77256ae 496 /* C1 Bit Fields */
bogdanm 20:4263a77256ae 497 #define DAC_C1_DACBFEN_MASK 0x1u
bogdanm 20:4263a77256ae 498 #define DAC_C1_DACBFEN_SHIFT 0
bogdanm 20:4263a77256ae 499 #define DAC_C1_DACBFMD_MASK 0x4u
bogdanm 20:4263a77256ae 500 #define DAC_C1_DACBFMD_SHIFT 2
bogdanm 20:4263a77256ae 501 #define DAC_C1_DMAEN_MASK 0x80u
bogdanm 20:4263a77256ae 502 #define DAC_C1_DMAEN_SHIFT 7
bogdanm 20:4263a77256ae 503 /* C2 Bit Fields */
bogdanm 20:4263a77256ae 504 #define DAC_C2_DACBFUP_MASK 0x1u
bogdanm 20:4263a77256ae 505 #define DAC_C2_DACBFUP_SHIFT 0
bogdanm 20:4263a77256ae 506 #define DAC_C2_DACBFRP_MASK 0x10u
bogdanm 20:4263a77256ae 507 #define DAC_C2_DACBFRP_SHIFT 4
bogdanm 20:4263a77256ae 508
bogdanm 20:4263a77256ae 509 /**
bogdanm 20:4263a77256ae 510 * @}
bogdanm 20:4263a77256ae 511 */ /* end of group DAC_Register_Masks */
bogdanm 20:4263a77256ae 512
bogdanm 20:4263a77256ae 513
bogdanm 20:4263a77256ae 514 /* DAC - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 515 /** Peripheral DAC0 base address */
bogdanm 20:4263a77256ae 516 #define DAC0_BASE (0x4003F000u)
bogdanm 20:4263a77256ae 517 /** Peripheral DAC0 base pointer */
bogdanm 20:4263a77256ae 518 #define DAC0 ((DAC_Type *)DAC0_BASE)
bogdanm 20:4263a77256ae 519 /** Array initializer of DAC peripheral base pointers */
bogdanm 20:4263a77256ae 520 #define DAC_BASES { DAC0 }
bogdanm 20:4263a77256ae 521
bogdanm 20:4263a77256ae 522 /**
bogdanm 20:4263a77256ae 523 * @}
bogdanm 20:4263a77256ae 524 */ /* end of group DAC_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 525
bogdanm 20:4263a77256ae 526
bogdanm 20:4263a77256ae 527 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 528 -- DMA Peripheral Access Layer
bogdanm 20:4263a77256ae 529 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 530
bogdanm 20:4263a77256ae 531 /**
bogdanm 20:4263a77256ae 532 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
bogdanm 20:4263a77256ae 533 * @{
bogdanm 20:4263a77256ae 534 */
bogdanm 20:4263a77256ae 535
bogdanm 20:4263a77256ae 536 /** DMA - Register Layout Typedef */
bogdanm 20:4263a77256ae 537 typedef struct {
bogdanm 20:4263a77256ae 538 uint8_t RESERVED_0[256];
bogdanm 20:4263a77256ae 539 struct { /* offset: 0x100, array step: 0x10 */
bogdanm 20:4263a77256ae 540 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
bogdanm 20:4263a77256ae 541 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
bogdanm 20:4263a77256ae 542 union { /* offset: 0x108, array step: 0x10 */
bogdanm 20:4263a77256ae 543 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
bogdanm 20:4263a77256ae 544 struct { /* offset: 0x108, array step: 0x10 */
bogdanm 20:4263a77256ae 545 uint8_t RESERVED_0[3];
bogdanm 20:4263a77256ae 546 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
bogdanm 20:4263a77256ae 547 } DMA_DSR_ACCESS8BIT;
bogdanm 20:4263a77256ae 548 };
bogdanm 20:4263a77256ae 549 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
bogdanm 20:4263a77256ae 550 } DMA[4];
bogdanm 20:4263a77256ae 551 } DMA_Type;
bogdanm 20:4263a77256ae 552
bogdanm 20:4263a77256ae 553 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 554 -- DMA Register Masks
bogdanm 20:4263a77256ae 555 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 556
bogdanm 20:4263a77256ae 557 /**
bogdanm 20:4263a77256ae 558 * @addtogroup DMA_Register_Masks DMA Register Masks
bogdanm 20:4263a77256ae 559 * @{
bogdanm 20:4263a77256ae 560 */
bogdanm 20:4263a77256ae 561
bogdanm 20:4263a77256ae 562 /* SAR Bit Fields */
bogdanm 20:4263a77256ae 563 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 564 #define DMA_SAR_SAR_SHIFT 0
bogdanm 20:4263a77256ae 565 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
bogdanm 20:4263a77256ae 566 /* DAR Bit Fields */
bogdanm 20:4263a77256ae 567 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 568 #define DMA_DAR_DAR_SHIFT 0
bogdanm 20:4263a77256ae 569 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
bogdanm 20:4263a77256ae 570 /* DSR_BCR Bit Fields */
bogdanm 20:4263a77256ae 571 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
bogdanm 20:4263a77256ae 572 #define DMA_DSR_BCR_BCR_SHIFT 0
bogdanm 20:4263a77256ae 573 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
bogdanm 20:4263a77256ae 574 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
bogdanm 20:4263a77256ae 575 #define DMA_DSR_BCR_DONE_SHIFT 24
bogdanm 20:4263a77256ae 576 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
bogdanm 20:4263a77256ae 577 #define DMA_DSR_BCR_BSY_SHIFT 25
bogdanm 20:4263a77256ae 578 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
bogdanm 20:4263a77256ae 579 #define DMA_DSR_BCR_REQ_SHIFT 26
bogdanm 20:4263a77256ae 580 #define DMA_DSR_BCR_BED_MASK 0x10000000u
bogdanm 20:4263a77256ae 581 #define DMA_DSR_BCR_BED_SHIFT 28
bogdanm 20:4263a77256ae 582 #define DMA_DSR_BCR_BES_MASK 0x20000000u
bogdanm 20:4263a77256ae 583 #define DMA_DSR_BCR_BES_SHIFT 29
bogdanm 20:4263a77256ae 584 #define DMA_DSR_BCR_CE_MASK 0x40000000u
bogdanm 20:4263a77256ae 585 #define DMA_DSR_BCR_CE_SHIFT 30
bogdanm 20:4263a77256ae 586 /* DCR Bit Fields */
bogdanm 20:4263a77256ae 587 #define DMA_DCR_LCH2_MASK 0x3u
bogdanm 20:4263a77256ae 588 #define DMA_DCR_LCH2_SHIFT 0
bogdanm 20:4263a77256ae 589 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
bogdanm 20:4263a77256ae 590 #define DMA_DCR_LCH1_MASK 0xCu
bogdanm 20:4263a77256ae 591 #define DMA_DCR_LCH1_SHIFT 2
bogdanm 20:4263a77256ae 592 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
bogdanm 20:4263a77256ae 593 #define DMA_DCR_LINKCC_MASK 0x30u
bogdanm 20:4263a77256ae 594 #define DMA_DCR_LINKCC_SHIFT 4
bogdanm 20:4263a77256ae 595 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
bogdanm 20:4263a77256ae 596 #define DMA_DCR_D_REQ_MASK 0x80u
bogdanm 20:4263a77256ae 597 #define DMA_DCR_D_REQ_SHIFT 7
bogdanm 20:4263a77256ae 598 #define DMA_DCR_DMOD_MASK 0xF00u
bogdanm 20:4263a77256ae 599 #define DMA_DCR_DMOD_SHIFT 8
bogdanm 20:4263a77256ae 600 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
bogdanm 20:4263a77256ae 601 #define DMA_DCR_SMOD_MASK 0xF000u
bogdanm 20:4263a77256ae 602 #define DMA_DCR_SMOD_SHIFT 12
bogdanm 20:4263a77256ae 603 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
bogdanm 20:4263a77256ae 604 #define DMA_DCR_START_MASK 0x10000u
bogdanm 20:4263a77256ae 605 #define DMA_DCR_START_SHIFT 16
bogdanm 20:4263a77256ae 606 #define DMA_DCR_DSIZE_MASK 0x60000u
bogdanm 20:4263a77256ae 607 #define DMA_DCR_DSIZE_SHIFT 17
bogdanm 20:4263a77256ae 608 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
bogdanm 20:4263a77256ae 609 #define DMA_DCR_DINC_MASK 0x80000u
bogdanm 20:4263a77256ae 610 #define DMA_DCR_DINC_SHIFT 19
bogdanm 20:4263a77256ae 611 #define DMA_DCR_SSIZE_MASK 0x300000u
bogdanm 20:4263a77256ae 612 #define DMA_DCR_SSIZE_SHIFT 20
bogdanm 20:4263a77256ae 613 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
bogdanm 20:4263a77256ae 614 #define DMA_DCR_SINC_MASK 0x400000u
bogdanm 20:4263a77256ae 615 #define DMA_DCR_SINC_SHIFT 22
bogdanm 20:4263a77256ae 616 #define DMA_DCR_EADREQ_MASK 0x800000u
bogdanm 20:4263a77256ae 617 #define DMA_DCR_EADREQ_SHIFT 23
bogdanm 20:4263a77256ae 618 #define DMA_DCR_AA_MASK 0x10000000u
bogdanm 20:4263a77256ae 619 #define DMA_DCR_AA_SHIFT 28
bogdanm 20:4263a77256ae 620 #define DMA_DCR_CS_MASK 0x20000000u
bogdanm 20:4263a77256ae 621 #define DMA_DCR_CS_SHIFT 29
bogdanm 20:4263a77256ae 622 #define DMA_DCR_ERQ_MASK 0x40000000u
bogdanm 20:4263a77256ae 623 #define DMA_DCR_ERQ_SHIFT 30
bogdanm 20:4263a77256ae 624 #define DMA_DCR_EINT_MASK 0x80000000u
bogdanm 20:4263a77256ae 625 #define DMA_DCR_EINT_SHIFT 31
bogdanm 20:4263a77256ae 626
bogdanm 20:4263a77256ae 627 /**
bogdanm 20:4263a77256ae 628 * @}
bogdanm 20:4263a77256ae 629 */ /* end of group DMA_Register_Masks */
bogdanm 20:4263a77256ae 630
bogdanm 20:4263a77256ae 631
bogdanm 20:4263a77256ae 632 /* DMA - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 633 /** Peripheral DMA base address */
bogdanm 20:4263a77256ae 634 #define DMA_BASE (0x40008000u)
bogdanm 20:4263a77256ae 635 /** Peripheral DMA base pointer */
bogdanm 20:4263a77256ae 636 #define DMA0 ((DMA_Type *)DMA_BASE)
bogdanm 20:4263a77256ae 637 /** Array initializer of DMA peripheral base pointers */
bogdanm 20:4263a77256ae 638 #define DMA_BASES { DMA0 }
bogdanm 20:4263a77256ae 639
bogdanm 20:4263a77256ae 640 /**
bogdanm 20:4263a77256ae 641 * @}
bogdanm 20:4263a77256ae 642 */ /* end of group DMA_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 643
bogdanm 20:4263a77256ae 644
bogdanm 20:4263a77256ae 645 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 646 -- DMAMUX Peripheral Access Layer
bogdanm 20:4263a77256ae 647 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 648
bogdanm 20:4263a77256ae 649 /**
bogdanm 20:4263a77256ae 650 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
bogdanm 20:4263a77256ae 651 * @{
bogdanm 20:4263a77256ae 652 */
bogdanm 20:4263a77256ae 653
bogdanm 20:4263a77256ae 654 /** DMAMUX - Register Layout Typedef */
bogdanm 20:4263a77256ae 655 typedef struct {
bogdanm 20:4263a77256ae 656 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
bogdanm 20:4263a77256ae 657 } DMAMUX_Type;
bogdanm 20:4263a77256ae 658
bogdanm 20:4263a77256ae 659 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 660 -- DMAMUX Register Masks
bogdanm 20:4263a77256ae 661 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 662
bogdanm 20:4263a77256ae 663 /**
bogdanm 20:4263a77256ae 664 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
bogdanm 20:4263a77256ae 665 * @{
bogdanm 20:4263a77256ae 666 */
bogdanm 20:4263a77256ae 667
bogdanm 20:4263a77256ae 668 /* CHCFG Bit Fields */
bogdanm 20:4263a77256ae 669 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
bogdanm 20:4263a77256ae 670 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
bogdanm 20:4263a77256ae 671 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
bogdanm 20:4263a77256ae 672 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
bogdanm 20:4263a77256ae 673 #define DMAMUX_CHCFG_TRIG_SHIFT 6
bogdanm 20:4263a77256ae 674 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
bogdanm 20:4263a77256ae 675 #define DMAMUX_CHCFG_ENBL_SHIFT 7
bogdanm 20:4263a77256ae 676
bogdanm 20:4263a77256ae 677 /**
bogdanm 20:4263a77256ae 678 * @}
bogdanm 20:4263a77256ae 679 */ /* end of group DMAMUX_Register_Masks */
bogdanm 20:4263a77256ae 680
bogdanm 20:4263a77256ae 681
bogdanm 20:4263a77256ae 682 /* DMAMUX - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 683 /** Peripheral DMAMUX0 base address */
bogdanm 20:4263a77256ae 684 #define DMAMUX0_BASE (0x40021000u)
bogdanm 20:4263a77256ae 685 /** Peripheral DMAMUX0 base pointer */
bogdanm 20:4263a77256ae 686 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
bogdanm 20:4263a77256ae 687 /** Array initializer of DMAMUX peripheral base pointers */
bogdanm 20:4263a77256ae 688 #define DMAMUX_BASES { DMAMUX0 }
bogdanm 20:4263a77256ae 689
bogdanm 20:4263a77256ae 690 /**
bogdanm 20:4263a77256ae 691 * @}
bogdanm 20:4263a77256ae 692 */ /* end of group DMAMUX_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 693
bogdanm 20:4263a77256ae 694
bogdanm 20:4263a77256ae 695 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 696 -- FGPIO Peripheral Access Layer
bogdanm 20:4263a77256ae 697 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 698
bogdanm 20:4263a77256ae 699 /**
bogdanm 20:4263a77256ae 700 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
bogdanm 20:4263a77256ae 701 * @{
bogdanm 20:4263a77256ae 702 */
bogdanm 20:4263a77256ae 703
bogdanm 20:4263a77256ae 704 /** FGPIO - Register Layout Typedef */
bogdanm 20:4263a77256ae 705 typedef struct {
bogdanm 20:4263a77256ae 706 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
bogdanm 20:4263a77256ae 707 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
bogdanm 20:4263a77256ae 708 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
bogdanm 20:4263a77256ae 709 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
bogdanm 20:4263a77256ae 710 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
bogdanm 20:4263a77256ae 711 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
bogdanm 20:4263a77256ae 712 } FGPIO_Type;
bogdanm 20:4263a77256ae 713
bogdanm 20:4263a77256ae 714 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 715 -- FGPIO Register Masks
bogdanm 20:4263a77256ae 716 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 717
bogdanm 20:4263a77256ae 718 /**
bogdanm 20:4263a77256ae 719 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
bogdanm 20:4263a77256ae 720 * @{
bogdanm 20:4263a77256ae 721 */
bogdanm 20:4263a77256ae 722
bogdanm 20:4263a77256ae 723 /* PDOR Bit Fields */
bogdanm 20:4263a77256ae 724 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 725 #define FGPIO_PDOR_PDO_SHIFT 0
bogdanm 20:4263a77256ae 726 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
bogdanm 20:4263a77256ae 727 /* PSOR Bit Fields */
bogdanm 20:4263a77256ae 728 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 729 #define FGPIO_PSOR_PTSO_SHIFT 0
bogdanm 20:4263a77256ae 730 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
bogdanm 20:4263a77256ae 731 /* PCOR Bit Fields */
bogdanm 20:4263a77256ae 732 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 733 #define FGPIO_PCOR_PTCO_SHIFT 0
bogdanm 20:4263a77256ae 734 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
bogdanm 20:4263a77256ae 735 /* PTOR Bit Fields */
bogdanm 20:4263a77256ae 736 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 737 #define FGPIO_PTOR_PTTO_SHIFT 0
bogdanm 20:4263a77256ae 738 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
bogdanm 20:4263a77256ae 739 /* PDIR Bit Fields */
bogdanm 20:4263a77256ae 740 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 741 #define FGPIO_PDIR_PDI_SHIFT 0
bogdanm 20:4263a77256ae 742 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
bogdanm 20:4263a77256ae 743 /* PDDR Bit Fields */
bogdanm 20:4263a77256ae 744 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 745 #define FGPIO_PDDR_PDD_SHIFT 0
bogdanm 20:4263a77256ae 746 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
bogdanm 20:4263a77256ae 747
bogdanm 20:4263a77256ae 748 /**
bogdanm 20:4263a77256ae 749 * @}
bogdanm 20:4263a77256ae 750 */ /* end of group FGPIO_Register_Masks */
bogdanm 20:4263a77256ae 751
bogdanm 20:4263a77256ae 752
bogdanm 20:4263a77256ae 753 /* FGPIO - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 754 /** Peripheral FPTA base address */
bogdanm 20:4263a77256ae 755 #define FPTA_BASE (0xF80FF000u)
bogdanm 20:4263a77256ae 756 /** Peripheral FPTA base pointer */
bogdanm 20:4263a77256ae 757 #define FPTA ((FGPIO_Type *)FPTA_BASE)
bogdanm 20:4263a77256ae 758 /** Peripheral FPTB base address */
bogdanm 20:4263a77256ae 759 #define FPTB_BASE (0xF80FF040u)
bogdanm 20:4263a77256ae 760 /** Peripheral FPTB base pointer */
bogdanm 20:4263a77256ae 761 #define FPTB ((FGPIO_Type *)FPTB_BASE)
bogdanm 20:4263a77256ae 762 /** Array initializer of FGPIO peripheral base pointers */
bogdanm 20:4263a77256ae 763 #define FGPIO_BASES { FPTA, FPTB }
bogdanm 20:4263a77256ae 764
bogdanm 20:4263a77256ae 765 /**
bogdanm 20:4263a77256ae 766 * @}
bogdanm 20:4263a77256ae 767 */ /* end of group FGPIO_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 768
bogdanm 20:4263a77256ae 769
bogdanm 20:4263a77256ae 770 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 771 -- FTFA Peripheral Access Layer
bogdanm 20:4263a77256ae 772 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 773
bogdanm 20:4263a77256ae 774 /**
bogdanm 20:4263a77256ae 775 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
bogdanm 20:4263a77256ae 776 * @{
bogdanm 20:4263a77256ae 777 */
bogdanm 20:4263a77256ae 778
bogdanm 20:4263a77256ae 779 /** FTFA - Register Layout Typedef */
bogdanm 20:4263a77256ae 780 typedef struct {
bogdanm 20:4263a77256ae 781 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
bogdanm 20:4263a77256ae 782 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
bogdanm 20:4263a77256ae 783 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
bogdanm 20:4263a77256ae 784 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
bogdanm 20:4263a77256ae 785 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
bogdanm 20:4263a77256ae 786 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
bogdanm 20:4263a77256ae 787 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
bogdanm 20:4263a77256ae 788 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
bogdanm 20:4263a77256ae 789 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
bogdanm 20:4263a77256ae 790 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
bogdanm 20:4263a77256ae 791 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
bogdanm 20:4263a77256ae 792 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
bogdanm 20:4263a77256ae 793 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
bogdanm 20:4263a77256ae 794 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
bogdanm 20:4263a77256ae 795 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
bogdanm 20:4263a77256ae 796 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
bogdanm 20:4263a77256ae 797 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
bogdanm 20:4263a77256ae 798 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
bogdanm 20:4263a77256ae 799 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
bogdanm 20:4263a77256ae 800 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
bogdanm 20:4263a77256ae 801 } FTFA_Type;
bogdanm 20:4263a77256ae 802
bogdanm 20:4263a77256ae 803 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 804 -- FTFA Register Masks
bogdanm 20:4263a77256ae 805 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 806
bogdanm 20:4263a77256ae 807 /**
bogdanm 20:4263a77256ae 808 * @addtogroup FTFA_Register_Masks FTFA Register Masks
bogdanm 20:4263a77256ae 809 * @{
bogdanm 20:4263a77256ae 810 */
bogdanm 20:4263a77256ae 811
bogdanm 20:4263a77256ae 812 /* FSTAT Bit Fields */
bogdanm 20:4263a77256ae 813 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
bogdanm 20:4263a77256ae 814 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
bogdanm 20:4263a77256ae 815 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
bogdanm 20:4263a77256ae 816 #define FTFA_FSTAT_FPVIOL_SHIFT 4
bogdanm 20:4263a77256ae 817 #define FTFA_FSTAT_ACCERR_MASK 0x20u
bogdanm 20:4263a77256ae 818 #define FTFA_FSTAT_ACCERR_SHIFT 5
bogdanm 20:4263a77256ae 819 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
bogdanm 20:4263a77256ae 820 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
bogdanm 20:4263a77256ae 821 #define FTFA_FSTAT_CCIF_MASK 0x80u
bogdanm 20:4263a77256ae 822 #define FTFA_FSTAT_CCIF_SHIFT 7
bogdanm 20:4263a77256ae 823 /* FCNFG Bit Fields */
bogdanm 20:4263a77256ae 824 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
bogdanm 20:4263a77256ae 825 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
bogdanm 20:4263a77256ae 826 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
bogdanm 20:4263a77256ae 827 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
bogdanm 20:4263a77256ae 828 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
bogdanm 20:4263a77256ae 829 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
bogdanm 20:4263a77256ae 830 #define FTFA_FCNFG_CCIE_MASK 0x80u
bogdanm 20:4263a77256ae 831 #define FTFA_FCNFG_CCIE_SHIFT 7
bogdanm 20:4263a77256ae 832 /* FSEC Bit Fields */
bogdanm 20:4263a77256ae 833 #define FTFA_FSEC_SEC_MASK 0x3u
bogdanm 20:4263a77256ae 834 #define FTFA_FSEC_SEC_SHIFT 0
bogdanm 20:4263a77256ae 835 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
bogdanm 20:4263a77256ae 836 #define FTFA_FSEC_FSLACC_MASK 0xCu
bogdanm 20:4263a77256ae 837 #define FTFA_FSEC_FSLACC_SHIFT 2
bogdanm 20:4263a77256ae 838 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
bogdanm 20:4263a77256ae 839 #define FTFA_FSEC_MEEN_MASK 0x30u
bogdanm 20:4263a77256ae 840 #define FTFA_FSEC_MEEN_SHIFT 4
bogdanm 20:4263a77256ae 841 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
bogdanm 20:4263a77256ae 842 #define FTFA_FSEC_KEYEN_MASK 0xC0u
bogdanm 20:4263a77256ae 843 #define FTFA_FSEC_KEYEN_SHIFT 6
bogdanm 20:4263a77256ae 844 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
bogdanm 20:4263a77256ae 845 /* FOPT Bit Fields */
bogdanm 20:4263a77256ae 846 #define FTFA_FOPT_OPT_MASK 0xFFu
bogdanm 20:4263a77256ae 847 #define FTFA_FOPT_OPT_SHIFT 0
bogdanm 20:4263a77256ae 848 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
bogdanm 20:4263a77256ae 849 /* FCCOB3 Bit Fields */
bogdanm 20:4263a77256ae 850 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
bogdanm 20:4263a77256ae 851 #define FTFA_FCCOB3_CCOBn_SHIFT 0
bogdanm 20:4263a77256ae 852 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
bogdanm 20:4263a77256ae 853 /* FCCOB2 Bit Fields */
bogdanm 20:4263a77256ae 854 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
bogdanm 20:4263a77256ae 855 #define FTFA_FCCOB2_CCOBn_SHIFT 0
bogdanm 20:4263a77256ae 856 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
bogdanm 20:4263a77256ae 857 /* FCCOB1 Bit Fields */
bogdanm 20:4263a77256ae 858 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
bogdanm 20:4263a77256ae 859 #define FTFA_FCCOB1_CCOBn_SHIFT 0
bogdanm 20:4263a77256ae 860 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
bogdanm 20:4263a77256ae 861 /* FCCOB0 Bit Fields */
bogdanm 20:4263a77256ae 862 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
bogdanm 20:4263a77256ae 863 #define FTFA_FCCOB0_CCOBn_SHIFT 0
bogdanm 20:4263a77256ae 864 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
bogdanm 20:4263a77256ae 865 /* FCCOB7 Bit Fields */
bogdanm 20:4263a77256ae 866 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
bogdanm 20:4263a77256ae 867 #define FTFA_FCCOB7_CCOBn_SHIFT 0
bogdanm 20:4263a77256ae 868 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
bogdanm 20:4263a77256ae 869 /* FCCOB6 Bit Fields */
bogdanm 20:4263a77256ae 870 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
bogdanm 20:4263a77256ae 871 #define FTFA_FCCOB6_CCOBn_SHIFT 0
bogdanm 20:4263a77256ae 872 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
bogdanm 20:4263a77256ae 873 /* FCCOB5 Bit Fields */
bogdanm 20:4263a77256ae 874 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
bogdanm 20:4263a77256ae 875 #define FTFA_FCCOB5_CCOBn_SHIFT 0
bogdanm 20:4263a77256ae 876 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
bogdanm 20:4263a77256ae 877 /* FCCOB4 Bit Fields */
bogdanm 20:4263a77256ae 878 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
bogdanm 20:4263a77256ae 879 #define FTFA_FCCOB4_CCOBn_SHIFT 0
bogdanm 20:4263a77256ae 880 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
bogdanm 20:4263a77256ae 881 /* FCCOBB Bit Fields */
bogdanm 20:4263a77256ae 882 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
bogdanm 20:4263a77256ae 883 #define FTFA_FCCOBB_CCOBn_SHIFT 0
bogdanm 20:4263a77256ae 884 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
bogdanm 20:4263a77256ae 885 /* FCCOBA Bit Fields */
bogdanm 20:4263a77256ae 886 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
bogdanm 20:4263a77256ae 887 #define FTFA_FCCOBA_CCOBn_SHIFT 0
bogdanm 20:4263a77256ae 888 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
bogdanm 20:4263a77256ae 889 /* FCCOB9 Bit Fields */
bogdanm 20:4263a77256ae 890 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
bogdanm 20:4263a77256ae 891 #define FTFA_FCCOB9_CCOBn_SHIFT 0
bogdanm 20:4263a77256ae 892 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
bogdanm 20:4263a77256ae 893 /* FCCOB8 Bit Fields */
bogdanm 20:4263a77256ae 894 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
bogdanm 20:4263a77256ae 895 #define FTFA_FCCOB8_CCOBn_SHIFT 0
bogdanm 20:4263a77256ae 896 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
bogdanm 20:4263a77256ae 897 /* FPROT3 Bit Fields */
bogdanm 20:4263a77256ae 898 #define FTFA_FPROT3_PROT_MASK 0xFFu
bogdanm 20:4263a77256ae 899 #define FTFA_FPROT3_PROT_SHIFT 0
bogdanm 20:4263a77256ae 900 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
bogdanm 20:4263a77256ae 901 /* FPROT2 Bit Fields */
bogdanm 20:4263a77256ae 902 #define FTFA_FPROT2_PROT_MASK 0xFFu
bogdanm 20:4263a77256ae 903 #define FTFA_FPROT2_PROT_SHIFT 0
bogdanm 20:4263a77256ae 904 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
bogdanm 20:4263a77256ae 905 /* FPROT1 Bit Fields */
bogdanm 20:4263a77256ae 906 #define FTFA_FPROT1_PROT_MASK 0xFFu
bogdanm 20:4263a77256ae 907 #define FTFA_FPROT1_PROT_SHIFT 0
bogdanm 20:4263a77256ae 908 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
bogdanm 20:4263a77256ae 909 /* FPROT0 Bit Fields */
bogdanm 20:4263a77256ae 910 #define FTFA_FPROT0_PROT_MASK 0xFFu
bogdanm 20:4263a77256ae 911 #define FTFA_FPROT0_PROT_SHIFT 0
bogdanm 20:4263a77256ae 912 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
bogdanm 20:4263a77256ae 913
bogdanm 20:4263a77256ae 914 /**
bogdanm 20:4263a77256ae 915 * @}
bogdanm 20:4263a77256ae 916 */ /* end of group FTFA_Register_Masks */
bogdanm 20:4263a77256ae 917
bogdanm 20:4263a77256ae 918
bogdanm 20:4263a77256ae 919 /* FTFA - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 920 /** Peripheral FTFA base address */
bogdanm 20:4263a77256ae 921 #define FTFA_BASE (0x40020000u)
bogdanm 20:4263a77256ae 922 /** Peripheral FTFA base pointer */
bogdanm 20:4263a77256ae 923 #define FTFA ((FTFA_Type *)FTFA_BASE)
bogdanm 20:4263a77256ae 924 /** Array initializer of FTFA peripheral base pointers */
bogdanm 20:4263a77256ae 925 #define FTFA_BASES { FTFA }
bogdanm 20:4263a77256ae 926
bogdanm 20:4263a77256ae 927 /**
bogdanm 20:4263a77256ae 928 * @}
bogdanm 20:4263a77256ae 929 */ /* end of group FTFA_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 930
bogdanm 20:4263a77256ae 931
bogdanm 20:4263a77256ae 932 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 933 -- GPIO Peripheral Access Layer
bogdanm 20:4263a77256ae 934 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 935
bogdanm 20:4263a77256ae 936 /**
bogdanm 20:4263a77256ae 937 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
bogdanm 20:4263a77256ae 938 * @{
bogdanm 20:4263a77256ae 939 */
bogdanm 20:4263a77256ae 940
bogdanm 20:4263a77256ae 941 /** GPIO - Register Layout Typedef */
bogdanm 20:4263a77256ae 942 typedef struct {
bogdanm 20:4263a77256ae 943 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
bogdanm 20:4263a77256ae 944 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
bogdanm 20:4263a77256ae 945 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
bogdanm 20:4263a77256ae 946 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
bogdanm 20:4263a77256ae 947 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
bogdanm 20:4263a77256ae 948 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
bogdanm 20:4263a77256ae 949 } GPIO_Type;
bogdanm 20:4263a77256ae 950
bogdanm 20:4263a77256ae 951 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 952 -- GPIO Register Masks
bogdanm 20:4263a77256ae 953 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 954
bogdanm 20:4263a77256ae 955 /**
bogdanm 20:4263a77256ae 956 * @addtogroup GPIO_Register_Masks GPIO Register Masks
bogdanm 20:4263a77256ae 957 * @{
bogdanm 20:4263a77256ae 958 */
bogdanm 20:4263a77256ae 959
bogdanm 20:4263a77256ae 960 /* PDOR Bit Fields */
bogdanm 20:4263a77256ae 961 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 962 #define GPIO_PDOR_PDO_SHIFT 0
bogdanm 20:4263a77256ae 963 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
bogdanm 20:4263a77256ae 964 /* PSOR Bit Fields */
bogdanm 20:4263a77256ae 965 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 966 #define GPIO_PSOR_PTSO_SHIFT 0
bogdanm 20:4263a77256ae 967 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
bogdanm 20:4263a77256ae 968 /* PCOR Bit Fields */
bogdanm 20:4263a77256ae 969 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 970 #define GPIO_PCOR_PTCO_SHIFT 0
bogdanm 20:4263a77256ae 971 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
bogdanm 20:4263a77256ae 972 /* PTOR Bit Fields */
bogdanm 20:4263a77256ae 973 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 974 #define GPIO_PTOR_PTTO_SHIFT 0
bogdanm 20:4263a77256ae 975 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
bogdanm 20:4263a77256ae 976 /* PDIR Bit Fields */
bogdanm 20:4263a77256ae 977 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 978 #define GPIO_PDIR_PDI_SHIFT 0
bogdanm 20:4263a77256ae 979 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
bogdanm 20:4263a77256ae 980 /* PDDR Bit Fields */
bogdanm 20:4263a77256ae 981 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 982 #define GPIO_PDDR_PDD_SHIFT 0
bogdanm 20:4263a77256ae 983 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
bogdanm 20:4263a77256ae 984
bogdanm 20:4263a77256ae 985 /**
bogdanm 20:4263a77256ae 986 * @}
bogdanm 20:4263a77256ae 987 */ /* end of group GPIO_Register_Masks */
bogdanm 20:4263a77256ae 988
bogdanm 20:4263a77256ae 989
bogdanm 20:4263a77256ae 990 /* GPIO - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 991 /** Peripheral PTA base address */
bogdanm 20:4263a77256ae 992 #define PTA_BASE (0x400FF000u)
bogdanm 20:4263a77256ae 993 /** Peripheral PTA base pointer */
bogdanm 20:4263a77256ae 994 #define PTA ((GPIO_Type *)PTA_BASE)
bogdanm 20:4263a77256ae 995 /** Peripheral PTB base address */
bogdanm 20:4263a77256ae 996 #define PTB_BASE (0x400FF040u)
bogdanm 20:4263a77256ae 997 /** Peripheral PTB base pointer */
bogdanm 20:4263a77256ae 998 #define PTB ((GPIO_Type *)PTB_BASE)
bogdanm 20:4263a77256ae 999 /** Array initializer of GPIO peripheral base pointers */
bogdanm 20:4263a77256ae 1000 #define GPIO_BASES { PTA, PTB }
bogdanm 20:4263a77256ae 1001
bogdanm 20:4263a77256ae 1002 /**
bogdanm 20:4263a77256ae 1003 * @}
bogdanm 20:4263a77256ae 1004 */ /* end of group GPIO_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 1005
bogdanm 20:4263a77256ae 1006
bogdanm 20:4263a77256ae 1007 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1008 -- I2C Peripheral Access Layer
bogdanm 20:4263a77256ae 1009 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1010
bogdanm 20:4263a77256ae 1011 /**
bogdanm 20:4263a77256ae 1012 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
bogdanm 20:4263a77256ae 1013 * @{
bogdanm 20:4263a77256ae 1014 */
bogdanm 20:4263a77256ae 1015
bogdanm 20:4263a77256ae 1016 /** I2C - Register Layout Typedef */
bogdanm 20:4263a77256ae 1017 typedef struct {
bogdanm 20:4263a77256ae 1018 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
bogdanm 20:4263a77256ae 1019 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
bogdanm 20:4263a77256ae 1020 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
bogdanm 20:4263a77256ae 1021 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
bogdanm 20:4263a77256ae 1022 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
bogdanm 20:4263a77256ae 1023 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
bogdanm 20:4263a77256ae 1024 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
bogdanm 20:4263a77256ae 1025 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
bogdanm 20:4263a77256ae 1026 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
bogdanm 20:4263a77256ae 1027 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
bogdanm 20:4263a77256ae 1028 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
bogdanm 20:4263a77256ae 1029 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
bogdanm 20:4263a77256ae 1030 } I2C_Type;
bogdanm 20:4263a77256ae 1031
bogdanm 20:4263a77256ae 1032 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1033 -- I2C Register Masks
bogdanm 20:4263a77256ae 1034 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1035
bogdanm 20:4263a77256ae 1036 /**
bogdanm 20:4263a77256ae 1037 * @addtogroup I2C_Register_Masks I2C Register Masks
bogdanm 20:4263a77256ae 1038 * @{
bogdanm 20:4263a77256ae 1039 */
bogdanm 20:4263a77256ae 1040
bogdanm 20:4263a77256ae 1041 /* A1 Bit Fields */
bogdanm 20:4263a77256ae 1042 #define I2C_A1_AD_MASK 0xFEu
bogdanm 20:4263a77256ae 1043 #define I2C_A1_AD_SHIFT 1
bogdanm 20:4263a77256ae 1044 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
bogdanm 20:4263a77256ae 1045 /* F Bit Fields */
bogdanm 20:4263a77256ae 1046 #define I2C_F_ICR_MASK 0x3Fu
bogdanm 20:4263a77256ae 1047 #define I2C_F_ICR_SHIFT 0
bogdanm 20:4263a77256ae 1048 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
bogdanm 20:4263a77256ae 1049 #define I2C_F_MULT_MASK 0xC0u
bogdanm 20:4263a77256ae 1050 #define I2C_F_MULT_SHIFT 6
bogdanm 20:4263a77256ae 1051 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
bogdanm 20:4263a77256ae 1052 /* C1 Bit Fields */
bogdanm 20:4263a77256ae 1053 #define I2C_C1_DMAEN_MASK 0x1u
bogdanm 20:4263a77256ae 1054 #define I2C_C1_DMAEN_SHIFT 0
bogdanm 20:4263a77256ae 1055 #define I2C_C1_WUEN_MASK 0x2u
bogdanm 20:4263a77256ae 1056 #define I2C_C1_WUEN_SHIFT 1
bogdanm 20:4263a77256ae 1057 #define I2C_C1_RSTA_MASK 0x4u
bogdanm 20:4263a77256ae 1058 #define I2C_C1_RSTA_SHIFT 2
bogdanm 20:4263a77256ae 1059 #define I2C_C1_TXAK_MASK 0x8u
bogdanm 20:4263a77256ae 1060 #define I2C_C1_TXAK_SHIFT 3
bogdanm 20:4263a77256ae 1061 #define I2C_C1_TX_MASK 0x10u
bogdanm 20:4263a77256ae 1062 #define I2C_C1_TX_SHIFT 4
bogdanm 20:4263a77256ae 1063 #define I2C_C1_MST_MASK 0x20u
bogdanm 20:4263a77256ae 1064 #define I2C_C1_MST_SHIFT 5
bogdanm 20:4263a77256ae 1065 #define I2C_C1_IICIE_MASK 0x40u
bogdanm 20:4263a77256ae 1066 #define I2C_C1_IICIE_SHIFT 6
bogdanm 20:4263a77256ae 1067 #define I2C_C1_IICEN_MASK 0x80u
bogdanm 20:4263a77256ae 1068 #define I2C_C1_IICEN_SHIFT 7
bogdanm 20:4263a77256ae 1069 /* S Bit Fields */
bogdanm 20:4263a77256ae 1070 #define I2C_S_RXAK_MASK 0x1u
bogdanm 20:4263a77256ae 1071 #define I2C_S_RXAK_SHIFT 0
bogdanm 20:4263a77256ae 1072 #define I2C_S_IICIF_MASK 0x2u
bogdanm 20:4263a77256ae 1073 #define I2C_S_IICIF_SHIFT 1
bogdanm 20:4263a77256ae 1074 #define I2C_S_SRW_MASK 0x4u
bogdanm 20:4263a77256ae 1075 #define I2C_S_SRW_SHIFT 2
bogdanm 20:4263a77256ae 1076 #define I2C_S_RAM_MASK 0x8u
bogdanm 20:4263a77256ae 1077 #define I2C_S_RAM_SHIFT 3
bogdanm 20:4263a77256ae 1078 #define I2C_S_ARBL_MASK 0x10u
bogdanm 20:4263a77256ae 1079 #define I2C_S_ARBL_SHIFT 4
bogdanm 20:4263a77256ae 1080 #define I2C_S_BUSY_MASK 0x20u
bogdanm 20:4263a77256ae 1081 #define I2C_S_BUSY_SHIFT 5
bogdanm 20:4263a77256ae 1082 #define I2C_S_IAAS_MASK 0x40u
bogdanm 20:4263a77256ae 1083 #define I2C_S_IAAS_SHIFT 6
bogdanm 20:4263a77256ae 1084 #define I2C_S_TCF_MASK 0x80u
bogdanm 20:4263a77256ae 1085 #define I2C_S_TCF_SHIFT 7
bogdanm 20:4263a77256ae 1086 /* D Bit Fields */
bogdanm 20:4263a77256ae 1087 #define I2C_D_DATA_MASK 0xFFu
bogdanm 20:4263a77256ae 1088 #define I2C_D_DATA_SHIFT 0
bogdanm 20:4263a77256ae 1089 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
bogdanm 20:4263a77256ae 1090 /* C2 Bit Fields */
bogdanm 20:4263a77256ae 1091 #define I2C_C2_AD_MASK 0x7u
bogdanm 20:4263a77256ae 1092 #define I2C_C2_AD_SHIFT 0
bogdanm 20:4263a77256ae 1093 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
bogdanm 20:4263a77256ae 1094 #define I2C_C2_RMEN_MASK 0x8u
bogdanm 20:4263a77256ae 1095 #define I2C_C2_RMEN_SHIFT 3
bogdanm 20:4263a77256ae 1096 #define I2C_C2_SBRC_MASK 0x10u
bogdanm 20:4263a77256ae 1097 #define I2C_C2_SBRC_SHIFT 4
bogdanm 20:4263a77256ae 1098 #define I2C_C2_HDRS_MASK 0x20u
bogdanm 20:4263a77256ae 1099 #define I2C_C2_HDRS_SHIFT 5
bogdanm 20:4263a77256ae 1100 #define I2C_C2_ADEXT_MASK 0x40u
bogdanm 20:4263a77256ae 1101 #define I2C_C2_ADEXT_SHIFT 6
bogdanm 20:4263a77256ae 1102 #define I2C_C2_GCAEN_MASK 0x80u
bogdanm 20:4263a77256ae 1103 #define I2C_C2_GCAEN_SHIFT 7
bogdanm 20:4263a77256ae 1104 /* FLT Bit Fields */
bogdanm 20:4263a77256ae 1105 #define I2C_FLT_FLT_MASK 0x1Fu
bogdanm 20:4263a77256ae 1106 #define I2C_FLT_FLT_SHIFT 0
bogdanm 20:4263a77256ae 1107 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
bogdanm 20:4263a77256ae 1108 #define I2C_FLT_STOPIE_MASK 0x20u
bogdanm 20:4263a77256ae 1109 #define I2C_FLT_STOPIE_SHIFT 5
bogdanm 20:4263a77256ae 1110 #define I2C_FLT_STOPF_MASK 0x40u
bogdanm 20:4263a77256ae 1111 #define I2C_FLT_STOPF_SHIFT 6
bogdanm 20:4263a77256ae 1112 #define I2C_FLT_SHEN_MASK 0x80u
bogdanm 20:4263a77256ae 1113 #define I2C_FLT_SHEN_SHIFT 7
bogdanm 20:4263a77256ae 1114 /* RA Bit Fields */
bogdanm 20:4263a77256ae 1115 #define I2C_RA_RAD_MASK 0xFEu
bogdanm 20:4263a77256ae 1116 #define I2C_RA_RAD_SHIFT 1
bogdanm 20:4263a77256ae 1117 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
bogdanm 20:4263a77256ae 1118 /* SMB Bit Fields */
bogdanm 20:4263a77256ae 1119 #define I2C_SMB_SHTF2IE_MASK 0x1u
bogdanm 20:4263a77256ae 1120 #define I2C_SMB_SHTF2IE_SHIFT 0
bogdanm 20:4263a77256ae 1121 #define I2C_SMB_SHTF2_MASK 0x2u
bogdanm 20:4263a77256ae 1122 #define I2C_SMB_SHTF2_SHIFT 1
bogdanm 20:4263a77256ae 1123 #define I2C_SMB_SHTF1_MASK 0x4u
bogdanm 20:4263a77256ae 1124 #define I2C_SMB_SHTF1_SHIFT 2
bogdanm 20:4263a77256ae 1125 #define I2C_SMB_SLTF_MASK 0x8u
bogdanm 20:4263a77256ae 1126 #define I2C_SMB_SLTF_SHIFT 3
bogdanm 20:4263a77256ae 1127 #define I2C_SMB_TCKSEL_MASK 0x10u
bogdanm 20:4263a77256ae 1128 #define I2C_SMB_TCKSEL_SHIFT 4
bogdanm 20:4263a77256ae 1129 #define I2C_SMB_SIICAEN_MASK 0x20u
bogdanm 20:4263a77256ae 1130 #define I2C_SMB_SIICAEN_SHIFT 5
bogdanm 20:4263a77256ae 1131 #define I2C_SMB_ALERTEN_MASK 0x40u
bogdanm 20:4263a77256ae 1132 #define I2C_SMB_ALERTEN_SHIFT 6
bogdanm 20:4263a77256ae 1133 #define I2C_SMB_FACK_MASK 0x80u
bogdanm 20:4263a77256ae 1134 #define I2C_SMB_FACK_SHIFT 7
bogdanm 20:4263a77256ae 1135 /* A2 Bit Fields */
bogdanm 20:4263a77256ae 1136 #define I2C_A2_SAD_MASK 0xFEu
bogdanm 20:4263a77256ae 1137 #define I2C_A2_SAD_SHIFT 1
bogdanm 20:4263a77256ae 1138 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
bogdanm 20:4263a77256ae 1139 /* SLTH Bit Fields */
bogdanm 20:4263a77256ae 1140 #define I2C_SLTH_SSLT_MASK 0xFFu
bogdanm 20:4263a77256ae 1141 #define I2C_SLTH_SSLT_SHIFT 0
bogdanm 20:4263a77256ae 1142 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
bogdanm 20:4263a77256ae 1143 /* SLTL Bit Fields */
bogdanm 20:4263a77256ae 1144 #define I2C_SLTL_SSLT_MASK 0xFFu
bogdanm 20:4263a77256ae 1145 #define I2C_SLTL_SSLT_SHIFT 0
bogdanm 20:4263a77256ae 1146 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
bogdanm 20:4263a77256ae 1147
bogdanm 20:4263a77256ae 1148 /**
bogdanm 20:4263a77256ae 1149 * @}
bogdanm 20:4263a77256ae 1150 */ /* end of group I2C_Register_Masks */
bogdanm 20:4263a77256ae 1151
bogdanm 20:4263a77256ae 1152
bogdanm 20:4263a77256ae 1153 /* I2C - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 1154 /** Peripheral I2C0 base address */
bogdanm 20:4263a77256ae 1155 #define I2C0_BASE (0x40066000u)
bogdanm 20:4263a77256ae 1156 /** Peripheral I2C0 base pointer */
bogdanm 20:4263a77256ae 1157 #define I2C0 ((I2C_Type *)I2C0_BASE)
bogdanm 20:4263a77256ae 1158 /** Array initializer of I2C peripheral base pointers */
bogdanm 20:4263a77256ae 1159 #define I2C_BASES { I2C0 }
bogdanm 20:4263a77256ae 1160
bogdanm 20:4263a77256ae 1161 /**
bogdanm 20:4263a77256ae 1162 * @}
bogdanm 20:4263a77256ae 1163 */ /* end of group I2C_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 1164
bogdanm 20:4263a77256ae 1165
bogdanm 20:4263a77256ae 1166 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1167 -- LLWU Peripheral Access Layer
bogdanm 20:4263a77256ae 1168 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1169
bogdanm 20:4263a77256ae 1170 /**
bogdanm 20:4263a77256ae 1171 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
bogdanm 20:4263a77256ae 1172 * @{
bogdanm 20:4263a77256ae 1173 */
bogdanm 20:4263a77256ae 1174
bogdanm 20:4263a77256ae 1175 /** LLWU - Register Layout Typedef */
bogdanm 20:4263a77256ae 1176 typedef struct {
bogdanm 20:4263a77256ae 1177 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
bogdanm 20:4263a77256ae 1178 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
bogdanm 20:4263a77256ae 1179 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x2 */
bogdanm 20:4263a77256ae 1180 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x3 */
bogdanm 20:4263a77256ae 1181 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x4 */
bogdanm 20:4263a77256ae 1182 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x5 */
bogdanm 20:4263a77256ae 1183 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x6 */
bogdanm 20:4263a77256ae 1184 } LLWU_Type;
bogdanm 20:4263a77256ae 1185
bogdanm 20:4263a77256ae 1186 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1187 -- LLWU Register Masks
bogdanm 20:4263a77256ae 1188 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1189
bogdanm 20:4263a77256ae 1190 /**
bogdanm 20:4263a77256ae 1191 * @addtogroup LLWU_Register_Masks LLWU Register Masks
bogdanm 20:4263a77256ae 1192 * @{
bogdanm 20:4263a77256ae 1193 */
bogdanm 20:4263a77256ae 1194
bogdanm 20:4263a77256ae 1195 /* PE1 Bit Fields */
bogdanm 20:4263a77256ae 1196 #define LLWU_PE1_WUPE0_MASK 0x3u
bogdanm 20:4263a77256ae 1197 #define LLWU_PE1_WUPE0_SHIFT 0
bogdanm 20:4263a77256ae 1198 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
bogdanm 20:4263a77256ae 1199 #define LLWU_PE1_WUPE1_MASK 0xCu
bogdanm 20:4263a77256ae 1200 #define LLWU_PE1_WUPE1_SHIFT 2
bogdanm 20:4263a77256ae 1201 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
bogdanm 20:4263a77256ae 1202 #define LLWU_PE1_WUPE2_MASK 0x30u
bogdanm 20:4263a77256ae 1203 #define LLWU_PE1_WUPE2_SHIFT 4
bogdanm 20:4263a77256ae 1204 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
bogdanm 20:4263a77256ae 1205 #define LLWU_PE1_WUPE3_MASK 0xC0u
bogdanm 20:4263a77256ae 1206 #define LLWU_PE1_WUPE3_SHIFT 6
bogdanm 20:4263a77256ae 1207 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
bogdanm 20:4263a77256ae 1208 /* PE2 Bit Fields */
bogdanm 20:4263a77256ae 1209 #define LLWU_PE2_WUPE4_MASK 0x3u
bogdanm 20:4263a77256ae 1210 #define LLWU_PE2_WUPE4_SHIFT 0
bogdanm 20:4263a77256ae 1211 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
bogdanm 20:4263a77256ae 1212 #define LLWU_PE2_WUPE5_MASK 0xCu
bogdanm 20:4263a77256ae 1213 #define LLWU_PE2_WUPE5_SHIFT 2
bogdanm 20:4263a77256ae 1214 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
bogdanm 20:4263a77256ae 1215 #define LLWU_PE2_WUPE6_MASK 0x30u
bogdanm 20:4263a77256ae 1216 #define LLWU_PE2_WUPE6_SHIFT 4
bogdanm 20:4263a77256ae 1217 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
bogdanm 20:4263a77256ae 1218 #define LLWU_PE2_WUPE7_MASK 0xC0u
bogdanm 20:4263a77256ae 1219 #define LLWU_PE2_WUPE7_SHIFT 6
bogdanm 20:4263a77256ae 1220 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
bogdanm 20:4263a77256ae 1221 /* ME Bit Fields */
bogdanm 20:4263a77256ae 1222 #define LLWU_ME_WUME0_MASK 0x1u
bogdanm 20:4263a77256ae 1223 #define LLWU_ME_WUME0_SHIFT 0
bogdanm 20:4263a77256ae 1224 #define LLWU_ME_WUME1_MASK 0x2u
bogdanm 20:4263a77256ae 1225 #define LLWU_ME_WUME1_SHIFT 1
bogdanm 20:4263a77256ae 1226 #define LLWU_ME_WUME2_MASK 0x4u
bogdanm 20:4263a77256ae 1227 #define LLWU_ME_WUME2_SHIFT 2
bogdanm 20:4263a77256ae 1228 #define LLWU_ME_WUME3_MASK 0x8u
bogdanm 20:4263a77256ae 1229 #define LLWU_ME_WUME3_SHIFT 3
bogdanm 20:4263a77256ae 1230 #define LLWU_ME_WUME4_MASK 0x10u
bogdanm 20:4263a77256ae 1231 #define LLWU_ME_WUME4_SHIFT 4
bogdanm 20:4263a77256ae 1232 #define LLWU_ME_WUME5_MASK 0x20u
bogdanm 20:4263a77256ae 1233 #define LLWU_ME_WUME5_SHIFT 5
bogdanm 20:4263a77256ae 1234 #define LLWU_ME_WUME6_MASK 0x40u
bogdanm 20:4263a77256ae 1235 #define LLWU_ME_WUME6_SHIFT 6
bogdanm 20:4263a77256ae 1236 #define LLWU_ME_WUME7_MASK 0x80u
bogdanm 20:4263a77256ae 1237 #define LLWU_ME_WUME7_SHIFT 7
bogdanm 20:4263a77256ae 1238 /* F1 Bit Fields */
bogdanm 20:4263a77256ae 1239 #define LLWU_F1_WUF0_MASK 0x1u
bogdanm 20:4263a77256ae 1240 #define LLWU_F1_WUF0_SHIFT 0
bogdanm 20:4263a77256ae 1241 #define LLWU_F1_WUF1_MASK 0x2u
bogdanm 20:4263a77256ae 1242 #define LLWU_F1_WUF1_SHIFT 1
bogdanm 20:4263a77256ae 1243 #define LLWU_F1_WUF2_MASK 0x4u
bogdanm 20:4263a77256ae 1244 #define LLWU_F1_WUF2_SHIFT 2
bogdanm 20:4263a77256ae 1245 #define LLWU_F1_WUF3_MASK 0x8u
bogdanm 20:4263a77256ae 1246 #define LLWU_F1_WUF3_SHIFT 3
bogdanm 20:4263a77256ae 1247 #define LLWU_F1_WUF4_MASK 0x10u
bogdanm 20:4263a77256ae 1248 #define LLWU_F1_WUF4_SHIFT 4
bogdanm 20:4263a77256ae 1249 #define LLWU_F1_WUF5_MASK 0x20u
bogdanm 20:4263a77256ae 1250 #define LLWU_F1_WUF5_SHIFT 5
bogdanm 20:4263a77256ae 1251 #define LLWU_F1_WUF6_MASK 0x40u
bogdanm 20:4263a77256ae 1252 #define LLWU_F1_WUF6_SHIFT 6
bogdanm 20:4263a77256ae 1253 #define LLWU_F1_WUF7_MASK 0x80u
bogdanm 20:4263a77256ae 1254 #define LLWU_F1_WUF7_SHIFT 7
bogdanm 20:4263a77256ae 1255 /* F3 Bit Fields */
bogdanm 20:4263a77256ae 1256 #define LLWU_F3_MWUF0_MASK 0x1u
bogdanm 20:4263a77256ae 1257 #define LLWU_F3_MWUF0_SHIFT 0
bogdanm 20:4263a77256ae 1258 #define LLWU_F3_MWUF1_MASK 0x2u
bogdanm 20:4263a77256ae 1259 #define LLWU_F3_MWUF1_SHIFT 1
bogdanm 20:4263a77256ae 1260 #define LLWU_F3_MWUF2_MASK 0x4u
bogdanm 20:4263a77256ae 1261 #define LLWU_F3_MWUF2_SHIFT 2
bogdanm 20:4263a77256ae 1262 #define LLWU_F3_MWUF3_MASK 0x8u
bogdanm 20:4263a77256ae 1263 #define LLWU_F3_MWUF3_SHIFT 3
bogdanm 20:4263a77256ae 1264 #define LLWU_F3_MWUF4_MASK 0x10u
bogdanm 20:4263a77256ae 1265 #define LLWU_F3_MWUF4_SHIFT 4
bogdanm 20:4263a77256ae 1266 #define LLWU_F3_MWUF5_MASK 0x20u
bogdanm 20:4263a77256ae 1267 #define LLWU_F3_MWUF5_SHIFT 5
bogdanm 20:4263a77256ae 1268 #define LLWU_F3_MWUF6_MASK 0x40u
bogdanm 20:4263a77256ae 1269 #define LLWU_F3_MWUF6_SHIFT 6
bogdanm 20:4263a77256ae 1270 #define LLWU_F3_MWUF7_MASK 0x80u
bogdanm 20:4263a77256ae 1271 #define LLWU_F3_MWUF7_SHIFT 7
bogdanm 20:4263a77256ae 1272 /* FILT1 Bit Fields */
bogdanm 20:4263a77256ae 1273 #define LLWU_FILT1_FILTSEL_MASK 0xFu
bogdanm 20:4263a77256ae 1274 #define LLWU_FILT1_FILTSEL_SHIFT 0
bogdanm 20:4263a77256ae 1275 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
bogdanm 20:4263a77256ae 1276 #define LLWU_FILT1_FILTE_MASK 0x60u
bogdanm 20:4263a77256ae 1277 #define LLWU_FILT1_FILTE_SHIFT 5
bogdanm 20:4263a77256ae 1278 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
bogdanm 20:4263a77256ae 1279 #define LLWU_FILT1_FILTF_MASK 0x80u
bogdanm 20:4263a77256ae 1280 #define LLWU_FILT1_FILTF_SHIFT 7
bogdanm 20:4263a77256ae 1281 /* FILT2 Bit Fields */
bogdanm 20:4263a77256ae 1282 #define LLWU_FILT2_FILTSEL_MASK 0xFu
bogdanm 20:4263a77256ae 1283 #define LLWU_FILT2_FILTSEL_SHIFT 0
bogdanm 20:4263a77256ae 1284 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
bogdanm 20:4263a77256ae 1285 #define LLWU_FILT2_FILTE_MASK 0x60u
bogdanm 20:4263a77256ae 1286 #define LLWU_FILT2_FILTE_SHIFT 5
bogdanm 20:4263a77256ae 1287 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
bogdanm 20:4263a77256ae 1288 #define LLWU_FILT2_FILTF_MASK 0x80u
bogdanm 20:4263a77256ae 1289 #define LLWU_FILT2_FILTF_SHIFT 7
bogdanm 20:4263a77256ae 1290
bogdanm 20:4263a77256ae 1291 /**
bogdanm 20:4263a77256ae 1292 * @}
bogdanm 20:4263a77256ae 1293 */ /* end of group LLWU_Register_Masks */
bogdanm 20:4263a77256ae 1294
bogdanm 20:4263a77256ae 1295
bogdanm 20:4263a77256ae 1296 /* LLWU - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 1297 /** Peripheral LLWU base address */
bogdanm 20:4263a77256ae 1298 #define LLWU_BASE (0x4007C000u)
bogdanm 20:4263a77256ae 1299 /** Peripheral LLWU base pointer */
bogdanm 20:4263a77256ae 1300 #define LLWU ((LLWU_Type *)LLWU_BASE)
bogdanm 20:4263a77256ae 1301 /** Array initializer of LLWU peripheral base pointers */
bogdanm 20:4263a77256ae 1302 #define LLWU_BASES { LLWU }
bogdanm 20:4263a77256ae 1303
bogdanm 20:4263a77256ae 1304 /**
bogdanm 20:4263a77256ae 1305 * @}
bogdanm 20:4263a77256ae 1306 */ /* end of group LLWU_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 1307
bogdanm 20:4263a77256ae 1308
bogdanm 20:4263a77256ae 1309 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1310 -- LPTMR Peripheral Access Layer
bogdanm 20:4263a77256ae 1311 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1312
bogdanm 20:4263a77256ae 1313 /**
bogdanm 20:4263a77256ae 1314 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
bogdanm 20:4263a77256ae 1315 * @{
bogdanm 20:4263a77256ae 1316 */
bogdanm 20:4263a77256ae 1317
bogdanm 20:4263a77256ae 1318 /** LPTMR - Register Layout Typedef */
bogdanm 20:4263a77256ae 1319 typedef struct {
bogdanm 20:4263a77256ae 1320 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
bogdanm 20:4263a77256ae 1321 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
bogdanm 20:4263a77256ae 1322 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
bogdanm 20:4263a77256ae 1323 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
bogdanm 20:4263a77256ae 1324 } LPTMR_Type;
bogdanm 20:4263a77256ae 1325
bogdanm 20:4263a77256ae 1326 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1327 -- LPTMR Register Masks
bogdanm 20:4263a77256ae 1328 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1329
bogdanm 20:4263a77256ae 1330 /**
bogdanm 20:4263a77256ae 1331 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
bogdanm 20:4263a77256ae 1332 * @{
bogdanm 20:4263a77256ae 1333 */
bogdanm 20:4263a77256ae 1334
bogdanm 20:4263a77256ae 1335 /* CSR Bit Fields */
bogdanm 20:4263a77256ae 1336 #define LPTMR_CSR_TEN_MASK 0x1u
bogdanm 20:4263a77256ae 1337 #define LPTMR_CSR_TEN_SHIFT 0
bogdanm 20:4263a77256ae 1338 #define LPTMR_CSR_TMS_MASK 0x2u
bogdanm 20:4263a77256ae 1339 #define LPTMR_CSR_TMS_SHIFT 1
bogdanm 20:4263a77256ae 1340 #define LPTMR_CSR_TFC_MASK 0x4u
bogdanm 20:4263a77256ae 1341 #define LPTMR_CSR_TFC_SHIFT 2
bogdanm 20:4263a77256ae 1342 #define LPTMR_CSR_TPP_MASK 0x8u
bogdanm 20:4263a77256ae 1343 #define LPTMR_CSR_TPP_SHIFT 3
bogdanm 20:4263a77256ae 1344 #define LPTMR_CSR_TPS_MASK 0x30u
bogdanm 20:4263a77256ae 1345 #define LPTMR_CSR_TPS_SHIFT 4
bogdanm 20:4263a77256ae 1346 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
bogdanm 20:4263a77256ae 1347 #define LPTMR_CSR_TIE_MASK 0x40u
bogdanm 20:4263a77256ae 1348 #define LPTMR_CSR_TIE_SHIFT 6
bogdanm 20:4263a77256ae 1349 #define LPTMR_CSR_TCF_MASK 0x80u
bogdanm 20:4263a77256ae 1350 #define LPTMR_CSR_TCF_SHIFT 7
bogdanm 20:4263a77256ae 1351 /* PSR Bit Fields */
bogdanm 20:4263a77256ae 1352 #define LPTMR_PSR_PCS_MASK 0x3u
bogdanm 20:4263a77256ae 1353 #define LPTMR_PSR_PCS_SHIFT 0
bogdanm 20:4263a77256ae 1354 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
bogdanm 20:4263a77256ae 1355 #define LPTMR_PSR_PBYP_MASK 0x4u
bogdanm 20:4263a77256ae 1356 #define LPTMR_PSR_PBYP_SHIFT 2
bogdanm 20:4263a77256ae 1357 #define LPTMR_PSR_PRESCALE_MASK 0x78u
bogdanm 20:4263a77256ae 1358 #define LPTMR_PSR_PRESCALE_SHIFT 3
bogdanm 20:4263a77256ae 1359 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
bogdanm 20:4263a77256ae 1360 /* CMR Bit Fields */
bogdanm 20:4263a77256ae 1361 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
bogdanm 20:4263a77256ae 1362 #define LPTMR_CMR_COMPARE_SHIFT 0
bogdanm 20:4263a77256ae 1363 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
bogdanm 20:4263a77256ae 1364 /* CNR Bit Fields */
bogdanm 20:4263a77256ae 1365 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
bogdanm 20:4263a77256ae 1366 #define LPTMR_CNR_COUNTER_SHIFT 0
bogdanm 20:4263a77256ae 1367 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
bogdanm 20:4263a77256ae 1368
bogdanm 20:4263a77256ae 1369 /**
bogdanm 20:4263a77256ae 1370 * @}
bogdanm 20:4263a77256ae 1371 */ /* end of group LPTMR_Register_Masks */
bogdanm 20:4263a77256ae 1372
bogdanm 20:4263a77256ae 1373
bogdanm 20:4263a77256ae 1374 /* LPTMR - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 1375 /** Peripheral LPTMR0 base address */
bogdanm 20:4263a77256ae 1376 #define LPTMR0_BASE (0x40040000u)
bogdanm 20:4263a77256ae 1377 /** Peripheral LPTMR0 base pointer */
bogdanm 20:4263a77256ae 1378 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
bogdanm 20:4263a77256ae 1379 /** Array initializer of LPTMR peripheral base pointers */
bogdanm 20:4263a77256ae 1380 #define LPTMR_BASES { LPTMR0 }
bogdanm 20:4263a77256ae 1381
bogdanm 20:4263a77256ae 1382 /**
bogdanm 20:4263a77256ae 1383 * @}
bogdanm 20:4263a77256ae 1384 */ /* end of group LPTMR_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 1385
bogdanm 20:4263a77256ae 1386
bogdanm 20:4263a77256ae 1387 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1388 -- MCG Peripheral Access Layer
bogdanm 20:4263a77256ae 1389 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1390
bogdanm 20:4263a77256ae 1391 /**
bogdanm 20:4263a77256ae 1392 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
bogdanm 20:4263a77256ae 1393 * @{
bogdanm 20:4263a77256ae 1394 */
bogdanm 20:4263a77256ae 1395
bogdanm 20:4263a77256ae 1396 /** MCG - Register Layout Typedef */
bogdanm 20:4263a77256ae 1397 typedef struct {
bogdanm 20:4263a77256ae 1398 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
bogdanm 20:4263a77256ae 1399 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
bogdanm 20:4263a77256ae 1400 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
bogdanm 20:4263a77256ae 1401 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
bogdanm 20:4263a77256ae 1402 __I uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
bogdanm 20:4263a77256ae 1403 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
bogdanm 20:4263a77256ae 1404 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
bogdanm 20:4263a77256ae 1405 uint8_t RESERVED_0[1];
bogdanm 20:4263a77256ae 1406 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
bogdanm 20:4263a77256ae 1407 uint8_t RESERVED_1[1];
bogdanm 20:4263a77256ae 1408 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
bogdanm 20:4263a77256ae 1409 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
bogdanm 20:4263a77256ae 1410 } MCG_Type;
bogdanm 20:4263a77256ae 1411
bogdanm 20:4263a77256ae 1412 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1413 -- MCG Register Masks
bogdanm 20:4263a77256ae 1414 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1415
bogdanm 20:4263a77256ae 1416 /**
bogdanm 20:4263a77256ae 1417 * @addtogroup MCG_Register_Masks MCG Register Masks
bogdanm 20:4263a77256ae 1418 * @{
bogdanm 20:4263a77256ae 1419 */
bogdanm 20:4263a77256ae 1420
bogdanm 20:4263a77256ae 1421 /* C1 Bit Fields */
bogdanm 20:4263a77256ae 1422 #define MCG_C1_IREFSTEN_MASK 0x1u
bogdanm 20:4263a77256ae 1423 #define MCG_C1_IREFSTEN_SHIFT 0
bogdanm 20:4263a77256ae 1424 #define MCG_C1_IRCLKEN_MASK 0x2u
bogdanm 20:4263a77256ae 1425 #define MCG_C1_IRCLKEN_SHIFT 1
bogdanm 20:4263a77256ae 1426 #define MCG_C1_IREFS_MASK 0x4u
bogdanm 20:4263a77256ae 1427 #define MCG_C1_IREFS_SHIFT 2
bogdanm 20:4263a77256ae 1428 #define MCG_C1_FRDIV_MASK 0x38u
bogdanm 20:4263a77256ae 1429 #define MCG_C1_FRDIV_SHIFT 3
bogdanm 20:4263a77256ae 1430 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
bogdanm 20:4263a77256ae 1431 #define MCG_C1_CLKS_MASK 0xC0u
bogdanm 20:4263a77256ae 1432 #define MCG_C1_CLKS_SHIFT 6
bogdanm 20:4263a77256ae 1433 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
bogdanm 20:4263a77256ae 1434 /* C2 Bit Fields */
bogdanm 20:4263a77256ae 1435 #define MCG_C2_IRCS_MASK 0x1u
bogdanm 20:4263a77256ae 1436 #define MCG_C2_IRCS_SHIFT 0
bogdanm 20:4263a77256ae 1437 #define MCG_C2_LP_MASK 0x2u
bogdanm 20:4263a77256ae 1438 #define MCG_C2_LP_SHIFT 1
bogdanm 20:4263a77256ae 1439 #define MCG_C2_EREFS0_MASK 0x4u
bogdanm 20:4263a77256ae 1440 #define MCG_C2_EREFS0_SHIFT 2
bogdanm 20:4263a77256ae 1441 #define MCG_C2_HGO0_MASK 0x8u
bogdanm 20:4263a77256ae 1442 #define MCG_C2_HGO0_SHIFT 3
bogdanm 20:4263a77256ae 1443 #define MCG_C2_RANGE0_MASK 0x30u
bogdanm 20:4263a77256ae 1444 #define MCG_C2_RANGE0_SHIFT 4
bogdanm 20:4263a77256ae 1445 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
bogdanm 20:4263a77256ae 1446 #define MCG_C2_LOCRE0_MASK 0x80u
bogdanm 20:4263a77256ae 1447 #define MCG_C2_LOCRE0_SHIFT 7
bogdanm 20:4263a77256ae 1448 /* C3 Bit Fields */
bogdanm 20:4263a77256ae 1449 #define MCG_C3_SCTRIM_MASK 0xFFu
bogdanm 20:4263a77256ae 1450 #define MCG_C3_SCTRIM_SHIFT 0
bogdanm 20:4263a77256ae 1451 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
bogdanm 20:4263a77256ae 1452 /* C4 Bit Fields */
bogdanm 20:4263a77256ae 1453 #define MCG_C4_SCFTRIM_MASK 0x1u
bogdanm 20:4263a77256ae 1454 #define MCG_C4_SCFTRIM_SHIFT 0
bogdanm 20:4263a77256ae 1455 #define MCG_C4_FCTRIM_MASK 0x1Eu
bogdanm 20:4263a77256ae 1456 #define MCG_C4_FCTRIM_SHIFT 1
bogdanm 20:4263a77256ae 1457 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
bogdanm 20:4263a77256ae 1458 #define MCG_C4_DRST_DRS_MASK 0x60u
bogdanm 20:4263a77256ae 1459 #define MCG_C4_DRST_DRS_SHIFT 5
bogdanm 20:4263a77256ae 1460 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
bogdanm 20:4263a77256ae 1461 #define MCG_C4_DMX32_MASK 0x80u
bogdanm 20:4263a77256ae 1462 #define MCG_C4_DMX32_SHIFT 7
bogdanm 20:4263a77256ae 1463 /* C6 Bit Fields */
bogdanm 20:4263a77256ae 1464 #define MCG_C6_CME_MASK 0x20u
bogdanm 20:4263a77256ae 1465 #define MCG_C6_CME_SHIFT 5
bogdanm 20:4263a77256ae 1466 /* S Bit Fields */
bogdanm 20:4263a77256ae 1467 #define MCG_S_IRCST_MASK 0x1u
bogdanm 20:4263a77256ae 1468 #define MCG_S_IRCST_SHIFT 0
bogdanm 20:4263a77256ae 1469 #define MCG_S_OSCINIT0_MASK 0x2u
bogdanm 20:4263a77256ae 1470 #define MCG_S_OSCINIT0_SHIFT 1
bogdanm 20:4263a77256ae 1471 #define MCG_S_CLKST_MASK 0xCu
bogdanm 20:4263a77256ae 1472 #define MCG_S_CLKST_SHIFT 2
bogdanm 20:4263a77256ae 1473 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
bogdanm 20:4263a77256ae 1474 #define MCG_S_IREFST_MASK 0x10u
bogdanm 20:4263a77256ae 1475 #define MCG_S_IREFST_SHIFT 4
bogdanm 20:4263a77256ae 1476 /* SC Bit Fields */
bogdanm 20:4263a77256ae 1477 #define MCG_SC_LOCS0_MASK 0x1u
bogdanm 20:4263a77256ae 1478 #define MCG_SC_LOCS0_SHIFT 0
bogdanm 20:4263a77256ae 1479 #define MCG_SC_FCRDIV_MASK 0xEu
bogdanm 20:4263a77256ae 1480 #define MCG_SC_FCRDIV_SHIFT 1
bogdanm 20:4263a77256ae 1481 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
bogdanm 20:4263a77256ae 1482 #define MCG_SC_FLTPRSRV_MASK 0x10u
bogdanm 20:4263a77256ae 1483 #define MCG_SC_FLTPRSRV_SHIFT 4
bogdanm 20:4263a77256ae 1484 #define MCG_SC_ATMF_MASK 0x20u
bogdanm 20:4263a77256ae 1485 #define MCG_SC_ATMF_SHIFT 5
bogdanm 20:4263a77256ae 1486 #define MCG_SC_ATMS_MASK 0x40u
bogdanm 20:4263a77256ae 1487 #define MCG_SC_ATMS_SHIFT 6
bogdanm 20:4263a77256ae 1488 #define MCG_SC_ATME_MASK 0x80u
bogdanm 20:4263a77256ae 1489 #define MCG_SC_ATME_SHIFT 7
bogdanm 20:4263a77256ae 1490 /* ATCVH Bit Fields */
bogdanm 20:4263a77256ae 1491 #define MCG_ATCVH_ATCVH_MASK 0xFFu
bogdanm 20:4263a77256ae 1492 #define MCG_ATCVH_ATCVH_SHIFT 0
bogdanm 20:4263a77256ae 1493 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
bogdanm 20:4263a77256ae 1494 /* ATCVL Bit Fields */
bogdanm 20:4263a77256ae 1495 #define MCG_ATCVL_ATCVL_MASK 0xFFu
bogdanm 20:4263a77256ae 1496 #define MCG_ATCVL_ATCVL_SHIFT 0
bogdanm 20:4263a77256ae 1497 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
bogdanm 20:4263a77256ae 1498
bogdanm 20:4263a77256ae 1499 /**
bogdanm 20:4263a77256ae 1500 * @}
bogdanm 20:4263a77256ae 1501 */ /* end of group MCG_Register_Masks */
bogdanm 20:4263a77256ae 1502
bogdanm 20:4263a77256ae 1503
bogdanm 20:4263a77256ae 1504 /* MCG - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 1505 /** Peripheral MCG base address */
bogdanm 20:4263a77256ae 1506 #define MCG_BASE (0x40064000u)
bogdanm 20:4263a77256ae 1507 /** Peripheral MCG base pointer */
bogdanm 20:4263a77256ae 1508 #define MCG ((MCG_Type *)MCG_BASE)
bogdanm 20:4263a77256ae 1509 /** Array initializer of MCG peripheral base pointers */
bogdanm 20:4263a77256ae 1510 #define MCG_BASES { MCG }
bogdanm 20:4263a77256ae 1511
bogdanm 20:4263a77256ae 1512 /**
bogdanm 20:4263a77256ae 1513 * @}
bogdanm 20:4263a77256ae 1514 */ /* end of group MCG_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 1515
bogdanm 20:4263a77256ae 1516
bogdanm 20:4263a77256ae 1517 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1518 -- MCM Peripheral Access Layer
bogdanm 20:4263a77256ae 1519 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1520
bogdanm 20:4263a77256ae 1521 /**
bogdanm 20:4263a77256ae 1522 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
bogdanm 20:4263a77256ae 1523 * @{
bogdanm 20:4263a77256ae 1524 */
bogdanm 20:4263a77256ae 1525
bogdanm 20:4263a77256ae 1526 /** MCM - Register Layout Typedef */
bogdanm 20:4263a77256ae 1527 typedef struct {
bogdanm 20:4263a77256ae 1528 uint8_t RESERVED_0[8];
bogdanm 20:4263a77256ae 1529 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
bogdanm 20:4263a77256ae 1530 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
bogdanm 20:4263a77256ae 1531 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
bogdanm 20:4263a77256ae 1532 uint8_t RESERVED_1[48];
bogdanm 20:4263a77256ae 1533 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
bogdanm 20:4263a77256ae 1534 } MCM_Type;
bogdanm 20:4263a77256ae 1535
bogdanm 20:4263a77256ae 1536 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1537 -- MCM Register Masks
bogdanm 20:4263a77256ae 1538 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1539
bogdanm 20:4263a77256ae 1540 /**
bogdanm 20:4263a77256ae 1541 * @addtogroup MCM_Register_Masks MCM Register Masks
bogdanm 20:4263a77256ae 1542 * @{
bogdanm 20:4263a77256ae 1543 */
bogdanm 20:4263a77256ae 1544
bogdanm 20:4263a77256ae 1545 /* PLASC Bit Fields */
bogdanm 20:4263a77256ae 1546 #define MCM_PLASC_ASC_MASK 0xFFu
bogdanm 20:4263a77256ae 1547 #define MCM_PLASC_ASC_SHIFT 0
bogdanm 20:4263a77256ae 1548 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
bogdanm 20:4263a77256ae 1549 /* PLAMC Bit Fields */
bogdanm 20:4263a77256ae 1550 #define MCM_PLAMC_AMC_MASK 0xFFu
bogdanm 20:4263a77256ae 1551 #define MCM_PLAMC_AMC_SHIFT 0
bogdanm 20:4263a77256ae 1552 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
bogdanm 20:4263a77256ae 1553 /* PLACR Bit Fields */
bogdanm 20:4263a77256ae 1554 #define MCM_PLACR_ARB_MASK 0x200u
bogdanm 20:4263a77256ae 1555 #define MCM_PLACR_ARB_SHIFT 9
bogdanm 20:4263a77256ae 1556 #define MCM_PLACR_CFCC_MASK 0x400u
bogdanm 20:4263a77256ae 1557 #define MCM_PLACR_CFCC_SHIFT 10
bogdanm 20:4263a77256ae 1558 #define MCM_PLACR_DFCDA_MASK 0x800u
bogdanm 20:4263a77256ae 1559 #define MCM_PLACR_DFCDA_SHIFT 11
bogdanm 20:4263a77256ae 1560 #define MCM_PLACR_DFCIC_MASK 0x1000u
bogdanm 20:4263a77256ae 1561 #define MCM_PLACR_DFCIC_SHIFT 12
bogdanm 20:4263a77256ae 1562 #define MCM_PLACR_DFCC_MASK 0x2000u
bogdanm 20:4263a77256ae 1563 #define MCM_PLACR_DFCC_SHIFT 13
bogdanm 20:4263a77256ae 1564 #define MCM_PLACR_EFDS_MASK 0x4000u
bogdanm 20:4263a77256ae 1565 #define MCM_PLACR_EFDS_SHIFT 14
bogdanm 20:4263a77256ae 1566 #define MCM_PLACR_DFCS_MASK 0x8000u
bogdanm 20:4263a77256ae 1567 #define MCM_PLACR_DFCS_SHIFT 15
bogdanm 20:4263a77256ae 1568 #define MCM_PLACR_ESFC_MASK 0x10000u
bogdanm 20:4263a77256ae 1569 #define MCM_PLACR_ESFC_SHIFT 16
bogdanm 20:4263a77256ae 1570 /* CPO Bit Fields */
bogdanm 20:4263a77256ae 1571 #define MCM_CPO_CPOREQ_MASK 0x1u
bogdanm 20:4263a77256ae 1572 #define MCM_CPO_CPOREQ_SHIFT 0
bogdanm 20:4263a77256ae 1573 #define MCM_CPO_CPOACK_MASK 0x2u
bogdanm 20:4263a77256ae 1574 #define MCM_CPO_CPOACK_SHIFT 1
bogdanm 20:4263a77256ae 1575 #define MCM_CPO_CPOWOI_MASK 0x4u
bogdanm 20:4263a77256ae 1576 #define MCM_CPO_CPOWOI_SHIFT 2
bogdanm 20:4263a77256ae 1577
bogdanm 20:4263a77256ae 1578 /**
bogdanm 20:4263a77256ae 1579 * @}
bogdanm 20:4263a77256ae 1580 */ /* end of group MCM_Register_Masks */
bogdanm 20:4263a77256ae 1581
bogdanm 20:4263a77256ae 1582
bogdanm 20:4263a77256ae 1583 /* MCM - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 1584 /** Peripheral MCM base address */
bogdanm 20:4263a77256ae 1585 #define MCM_BASE (0xF0003000u)
bogdanm 20:4263a77256ae 1586 /** Peripheral MCM base pointer */
bogdanm 20:4263a77256ae 1587 #define MCM ((MCM_Type *)MCM_BASE)
bogdanm 20:4263a77256ae 1588 /** Array initializer of MCM peripheral base pointers */
bogdanm 20:4263a77256ae 1589 #define MCM_BASES { MCM }
bogdanm 20:4263a77256ae 1590
bogdanm 20:4263a77256ae 1591 /**
bogdanm 20:4263a77256ae 1592 * @}
bogdanm 20:4263a77256ae 1593 */ /* end of group MCM_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 1594
bogdanm 20:4263a77256ae 1595
bogdanm 20:4263a77256ae 1596 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1597 -- MTB Peripheral Access Layer
bogdanm 20:4263a77256ae 1598 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1599
bogdanm 20:4263a77256ae 1600 /**
bogdanm 20:4263a77256ae 1601 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
bogdanm 20:4263a77256ae 1602 * @{
bogdanm 20:4263a77256ae 1603 */
bogdanm 20:4263a77256ae 1604
bogdanm 20:4263a77256ae 1605 /** MTB - Register Layout Typedef */
bogdanm 20:4263a77256ae 1606 typedef struct {
bogdanm 20:4263a77256ae 1607 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
bogdanm 20:4263a77256ae 1608 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
bogdanm 20:4263a77256ae 1609 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
bogdanm 20:4263a77256ae 1610 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
bogdanm 20:4263a77256ae 1611 uint8_t RESERVED_0[3824];
bogdanm 20:4263a77256ae 1612 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
bogdanm 20:4263a77256ae 1613 uint8_t RESERVED_1[156];
bogdanm 20:4263a77256ae 1614 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
bogdanm 20:4263a77256ae 1615 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
bogdanm 20:4263a77256ae 1616 uint8_t RESERVED_2[8];
bogdanm 20:4263a77256ae 1617 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
bogdanm 20:4263a77256ae 1618 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
bogdanm 20:4263a77256ae 1619 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
bogdanm 20:4263a77256ae 1620 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
bogdanm 20:4263a77256ae 1621 uint8_t RESERVED_3[8];
bogdanm 20:4263a77256ae 1622 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
bogdanm 20:4263a77256ae 1623 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
bogdanm 20:4263a77256ae 1624 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
bogdanm 20:4263a77256ae 1625 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
bogdanm 20:4263a77256ae 1626 } MTB_Type;
bogdanm 20:4263a77256ae 1627
bogdanm 20:4263a77256ae 1628 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1629 -- MTB Register Masks
bogdanm 20:4263a77256ae 1630 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1631
bogdanm 20:4263a77256ae 1632 /**
bogdanm 20:4263a77256ae 1633 * @addtogroup MTB_Register_Masks MTB Register Masks
bogdanm 20:4263a77256ae 1634 * @{
bogdanm 20:4263a77256ae 1635 */
bogdanm 20:4263a77256ae 1636
bogdanm 20:4263a77256ae 1637 /* POSITION Bit Fields */
bogdanm 20:4263a77256ae 1638 #define MTB_POSITION_WRAP_MASK 0x4u
bogdanm 20:4263a77256ae 1639 #define MTB_POSITION_WRAP_SHIFT 2
bogdanm 20:4263a77256ae 1640 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
bogdanm 20:4263a77256ae 1641 #define MTB_POSITION_POINTER_SHIFT 3
bogdanm 20:4263a77256ae 1642 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
bogdanm 20:4263a77256ae 1643 /* MASTER Bit Fields */
bogdanm 20:4263a77256ae 1644 #define MTB_MASTER_MASK_MASK 0x1Fu
bogdanm 20:4263a77256ae 1645 #define MTB_MASTER_MASK_SHIFT 0
bogdanm 20:4263a77256ae 1646 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
bogdanm 20:4263a77256ae 1647 #define MTB_MASTER_TSTARTEN_MASK 0x20u
bogdanm 20:4263a77256ae 1648 #define MTB_MASTER_TSTARTEN_SHIFT 5
bogdanm 20:4263a77256ae 1649 #define MTB_MASTER_TSTOPEN_MASK 0x40u
bogdanm 20:4263a77256ae 1650 #define MTB_MASTER_TSTOPEN_SHIFT 6
bogdanm 20:4263a77256ae 1651 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
bogdanm 20:4263a77256ae 1652 #define MTB_MASTER_SFRWPRIV_SHIFT 7
bogdanm 20:4263a77256ae 1653 #define MTB_MASTER_RAMPRIV_MASK 0x100u
bogdanm 20:4263a77256ae 1654 #define MTB_MASTER_RAMPRIV_SHIFT 8
bogdanm 20:4263a77256ae 1655 #define MTB_MASTER_HALTREQ_MASK 0x200u
bogdanm 20:4263a77256ae 1656 #define MTB_MASTER_HALTREQ_SHIFT 9
bogdanm 20:4263a77256ae 1657 #define MTB_MASTER_EN_MASK 0x80000000u
bogdanm 20:4263a77256ae 1658 #define MTB_MASTER_EN_SHIFT 31
bogdanm 20:4263a77256ae 1659 /* FLOW Bit Fields */
bogdanm 20:4263a77256ae 1660 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
bogdanm 20:4263a77256ae 1661 #define MTB_FLOW_AUTOSTOP_SHIFT 0
bogdanm 20:4263a77256ae 1662 #define MTB_FLOW_AUTOHALT_MASK 0x2u
bogdanm 20:4263a77256ae 1663 #define MTB_FLOW_AUTOHALT_SHIFT 1
bogdanm 20:4263a77256ae 1664 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
bogdanm 20:4263a77256ae 1665 #define MTB_FLOW_WATERMARK_SHIFT 3
bogdanm 20:4263a77256ae 1666 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
bogdanm 20:4263a77256ae 1667 /* BASE Bit Fields */
bogdanm 20:4263a77256ae 1668 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1669 #define MTB_BASE_BASEADDR_SHIFT 0
bogdanm 20:4263a77256ae 1670 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
bogdanm 20:4263a77256ae 1671 /* MODECTRL Bit Fields */
bogdanm 20:4263a77256ae 1672 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1673 #define MTB_MODECTRL_MODECTRL_SHIFT 0
bogdanm 20:4263a77256ae 1674 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
bogdanm 20:4263a77256ae 1675 /* TAGSET Bit Fields */
bogdanm 20:4263a77256ae 1676 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1677 #define MTB_TAGSET_TAGSET_SHIFT 0
bogdanm 20:4263a77256ae 1678 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
bogdanm 20:4263a77256ae 1679 /* TAGCLEAR Bit Fields */
bogdanm 20:4263a77256ae 1680 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1681 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
bogdanm 20:4263a77256ae 1682 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
bogdanm 20:4263a77256ae 1683 /* LOCKACCESS Bit Fields */
bogdanm 20:4263a77256ae 1684 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1685 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
bogdanm 20:4263a77256ae 1686 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
bogdanm 20:4263a77256ae 1687 /* LOCKSTAT Bit Fields */
bogdanm 20:4263a77256ae 1688 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1689 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
bogdanm 20:4263a77256ae 1690 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
bogdanm 20:4263a77256ae 1691 /* AUTHSTAT Bit Fields */
bogdanm 20:4263a77256ae 1692 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
bogdanm 20:4263a77256ae 1693 #define MTB_AUTHSTAT_BIT0_SHIFT 0
bogdanm 20:4263a77256ae 1694 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
bogdanm 20:4263a77256ae 1695 #define MTB_AUTHSTAT_BIT1_SHIFT 1
bogdanm 20:4263a77256ae 1696 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
bogdanm 20:4263a77256ae 1697 #define MTB_AUTHSTAT_BIT2_SHIFT 2
bogdanm 20:4263a77256ae 1698 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
bogdanm 20:4263a77256ae 1699 #define MTB_AUTHSTAT_BIT3_SHIFT 3
bogdanm 20:4263a77256ae 1700 /* DEVICEARCH Bit Fields */
bogdanm 20:4263a77256ae 1701 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1702 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
bogdanm 20:4263a77256ae 1703 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
bogdanm 20:4263a77256ae 1704 /* DEVICECFG Bit Fields */
bogdanm 20:4263a77256ae 1705 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1706 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
bogdanm 20:4263a77256ae 1707 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
bogdanm 20:4263a77256ae 1708 /* DEVICETYPID Bit Fields */
bogdanm 20:4263a77256ae 1709 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1710 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
bogdanm 20:4263a77256ae 1711 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
bogdanm 20:4263a77256ae 1712 /* PERIPHID Bit Fields */
bogdanm 20:4263a77256ae 1713 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1714 #define MTB_PERIPHID_PERIPHID_SHIFT 0
bogdanm 20:4263a77256ae 1715 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
bogdanm 20:4263a77256ae 1716 /* COMPID Bit Fields */
bogdanm 20:4263a77256ae 1717 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1718 #define MTB_COMPID_COMPID_SHIFT 0
bogdanm 20:4263a77256ae 1719 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
bogdanm 20:4263a77256ae 1720
bogdanm 20:4263a77256ae 1721 /**
bogdanm 20:4263a77256ae 1722 * @}
bogdanm 20:4263a77256ae 1723 */ /* end of group MTB_Register_Masks */
bogdanm 20:4263a77256ae 1724
bogdanm 20:4263a77256ae 1725
bogdanm 20:4263a77256ae 1726 /* MTB - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 1727 /** Peripheral MTB base address */
bogdanm 20:4263a77256ae 1728 #define MTB_BASE (0xF0000000u)
bogdanm 20:4263a77256ae 1729 /** Peripheral MTB base pointer */
bogdanm 20:4263a77256ae 1730 #define MTB ((MTB_Type *)MTB_BASE)
bogdanm 20:4263a77256ae 1731 /** Array initializer of MTB peripheral base pointers */
bogdanm 20:4263a77256ae 1732 #define MTB_BASES { MTB }
bogdanm 20:4263a77256ae 1733
bogdanm 20:4263a77256ae 1734 /**
bogdanm 20:4263a77256ae 1735 * @}
bogdanm 20:4263a77256ae 1736 */ /* end of group MTB_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 1737
bogdanm 20:4263a77256ae 1738
bogdanm 20:4263a77256ae 1739 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1740 -- MTBDWT Peripheral Access Layer
bogdanm 20:4263a77256ae 1741 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1742
bogdanm 20:4263a77256ae 1743 /**
bogdanm 20:4263a77256ae 1744 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
bogdanm 20:4263a77256ae 1745 * @{
bogdanm 20:4263a77256ae 1746 */
bogdanm 20:4263a77256ae 1747
bogdanm 20:4263a77256ae 1748 /** MTBDWT - Register Layout Typedef */
bogdanm 20:4263a77256ae 1749 typedef struct {
bogdanm 20:4263a77256ae 1750 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
bogdanm 20:4263a77256ae 1751 uint8_t RESERVED_0[28];
bogdanm 20:4263a77256ae 1752 struct { /* offset: 0x20, array step: 0x10 */
bogdanm 20:4263a77256ae 1753 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
bogdanm 20:4263a77256ae 1754 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
bogdanm 20:4263a77256ae 1755 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
bogdanm 20:4263a77256ae 1756 uint8_t RESERVED_0[4];
bogdanm 20:4263a77256ae 1757 } COMPARATOR[2];
bogdanm 20:4263a77256ae 1758 uint8_t RESERVED_1[448];
bogdanm 20:4263a77256ae 1759 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
bogdanm 20:4263a77256ae 1760 uint8_t RESERVED_2[3524];
bogdanm 20:4263a77256ae 1761 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
bogdanm 20:4263a77256ae 1762 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
bogdanm 20:4263a77256ae 1763 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
bogdanm 20:4263a77256ae 1764 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
bogdanm 20:4263a77256ae 1765 } MTBDWT_Type;
bogdanm 20:4263a77256ae 1766
bogdanm 20:4263a77256ae 1767 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1768 -- MTBDWT Register Masks
bogdanm 20:4263a77256ae 1769 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1770
bogdanm 20:4263a77256ae 1771 /**
bogdanm 20:4263a77256ae 1772 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
bogdanm 20:4263a77256ae 1773 * @{
bogdanm 20:4263a77256ae 1774 */
bogdanm 20:4263a77256ae 1775
bogdanm 20:4263a77256ae 1776 /* CTRL Bit Fields */
bogdanm 20:4263a77256ae 1777 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
bogdanm 20:4263a77256ae 1778 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
bogdanm 20:4263a77256ae 1779 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
bogdanm 20:4263a77256ae 1780 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
bogdanm 20:4263a77256ae 1781 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
bogdanm 20:4263a77256ae 1782 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
bogdanm 20:4263a77256ae 1783 /* COMP Bit Fields */
bogdanm 20:4263a77256ae 1784 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1785 #define MTBDWT_COMP_COMP_SHIFT 0
bogdanm 20:4263a77256ae 1786 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
bogdanm 20:4263a77256ae 1787 /* MASK Bit Fields */
bogdanm 20:4263a77256ae 1788 #define MTBDWT_MASK_MASK_MASK 0x1Fu
bogdanm 20:4263a77256ae 1789 #define MTBDWT_MASK_MASK_SHIFT 0
bogdanm 20:4263a77256ae 1790 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
bogdanm 20:4263a77256ae 1791 /* FCT Bit Fields */
bogdanm 20:4263a77256ae 1792 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
bogdanm 20:4263a77256ae 1793 #define MTBDWT_FCT_FUNCTION_SHIFT 0
bogdanm 20:4263a77256ae 1794 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
bogdanm 20:4263a77256ae 1795 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
bogdanm 20:4263a77256ae 1796 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
bogdanm 20:4263a77256ae 1797 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
bogdanm 20:4263a77256ae 1798 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
bogdanm 20:4263a77256ae 1799 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
bogdanm 20:4263a77256ae 1800 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
bogdanm 20:4263a77256ae 1801 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
bogdanm 20:4263a77256ae 1802 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
bogdanm 20:4263a77256ae 1803 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
bogdanm 20:4263a77256ae 1804 #define MTBDWT_FCT_MATCHED_SHIFT 24
bogdanm 20:4263a77256ae 1805 /* TBCTRL Bit Fields */
bogdanm 20:4263a77256ae 1806 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
bogdanm 20:4263a77256ae 1807 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
bogdanm 20:4263a77256ae 1808 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
bogdanm 20:4263a77256ae 1809 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
bogdanm 20:4263a77256ae 1810 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
bogdanm 20:4263a77256ae 1811 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
bogdanm 20:4263a77256ae 1812 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
bogdanm 20:4263a77256ae 1813 /* DEVICECFG Bit Fields */
bogdanm 20:4263a77256ae 1814 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1815 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
bogdanm 20:4263a77256ae 1816 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
bogdanm 20:4263a77256ae 1817 /* DEVICETYPID Bit Fields */
bogdanm 20:4263a77256ae 1818 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1819 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
bogdanm 20:4263a77256ae 1820 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
bogdanm 20:4263a77256ae 1821 /* PERIPHID Bit Fields */
bogdanm 20:4263a77256ae 1822 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1823 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
bogdanm 20:4263a77256ae 1824 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
bogdanm 20:4263a77256ae 1825 /* COMPID Bit Fields */
bogdanm 20:4263a77256ae 1826 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 1827 #define MTBDWT_COMPID_COMPID_SHIFT 0
bogdanm 20:4263a77256ae 1828 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
bogdanm 20:4263a77256ae 1829
bogdanm 20:4263a77256ae 1830 /**
bogdanm 20:4263a77256ae 1831 * @}
bogdanm 20:4263a77256ae 1832 */ /* end of group MTBDWT_Register_Masks */
bogdanm 20:4263a77256ae 1833
bogdanm 20:4263a77256ae 1834
bogdanm 20:4263a77256ae 1835 /* MTBDWT - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 1836 /** Peripheral MTBDWT base address */
bogdanm 20:4263a77256ae 1837 #define MTBDWT_BASE (0xF0001000u)
bogdanm 20:4263a77256ae 1838 /** Peripheral MTBDWT base pointer */
bogdanm 20:4263a77256ae 1839 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
bogdanm 20:4263a77256ae 1840 /** Array initializer of MTBDWT peripheral base pointers */
bogdanm 20:4263a77256ae 1841 #define MTBDWT_BASES { MTBDWT }
bogdanm 20:4263a77256ae 1842
bogdanm 20:4263a77256ae 1843 /**
bogdanm 20:4263a77256ae 1844 * @}
bogdanm 20:4263a77256ae 1845 */ /* end of group MTBDWT_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 1846
bogdanm 20:4263a77256ae 1847
bogdanm 20:4263a77256ae 1848 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1849 -- NV Peripheral Access Layer
bogdanm 20:4263a77256ae 1850 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1851
bogdanm 20:4263a77256ae 1852 /**
bogdanm 20:4263a77256ae 1853 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
bogdanm 20:4263a77256ae 1854 * @{
bogdanm 20:4263a77256ae 1855 */
bogdanm 20:4263a77256ae 1856
bogdanm 20:4263a77256ae 1857 /** NV - Register Layout Typedef */
bogdanm 20:4263a77256ae 1858 typedef struct {
bogdanm 20:4263a77256ae 1859 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
bogdanm 20:4263a77256ae 1860 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
bogdanm 20:4263a77256ae 1861 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
bogdanm 20:4263a77256ae 1862 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
bogdanm 20:4263a77256ae 1863 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
bogdanm 20:4263a77256ae 1864 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
bogdanm 20:4263a77256ae 1865 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
bogdanm 20:4263a77256ae 1866 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
bogdanm 20:4263a77256ae 1867 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
bogdanm 20:4263a77256ae 1868 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
bogdanm 20:4263a77256ae 1869 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
bogdanm 20:4263a77256ae 1870 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
bogdanm 20:4263a77256ae 1871 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
bogdanm 20:4263a77256ae 1872 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
bogdanm 20:4263a77256ae 1873 } NV_Type;
bogdanm 20:4263a77256ae 1874
bogdanm 20:4263a77256ae 1875 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1876 -- NV Register Masks
bogdanm 20:4263a77256ae 1877 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1878
bogdanm 20:4263a77256ae 1879 /**
bogdanm 20:4263a77256ae 1880 * @addtogroup NV_Register_Masks NV Register Masks
bogdanm 20:4263a77256ae 1881 * @{
bogdanm 20:4263a77256ae 1882 */
bogdanm 20:4263a77256ae 1883
bogdanm 20:4263a77256ae 1884 /* BACKKEY3 Bit Fields */
bogdanm 20:4263a77256ae 1885 #define NV_BACKKEY3_KEY_MASK 0xFFu
bogdanm 20:4263a77256ae 1886 #define NV_BACKKEY3_KEY_SHIFT 0
bogdanm 20:4263a77256ae 1887 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
bogdanm 20:4263a77256ae 1888 /* BACKKEY2 Bit Fields */
bogdanm 20:4263a77256ae 1889 #define NV_BACKKEY2_KEY_MASK 0xFFu
bogdanm 20:4263a77256ae 1890 #define NV_BACKKEY2_KEY_SHIFT 0
bogdanm 20:4263a77256ae 1891 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
bogdanm 20:4263a77256ae 1892 /* BACKKEY1 Bit Fields */
bogdanm 20:4263a77256ae 1893 #define NV_BACKKEY1_KEY_MASK 0xFFu
bogdanm 20:4263a77256ae 1894 #define NV_BACKKEY1_KEY_SHIFT 0
bogdanm 20:4263a77256ae 1895 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
bogdanm 20:4263a77256ae 1896 /* BACKKEY0 Bit Fields */
bogdanm 20:4263a77256ae 1897 #define NV_BACKKEY0_KEY_MASK 0xFFu
bogdanm 20:4263a77256ae 1898 #define NV_BACKKEY0_KEY_SHIFT 0
bogdanm 20:4263a77256ae 1899 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
bogdanm 20:4263a77256ae 1900 /* BACKKEY7 Bit Fields */
bogdanm 20:4263a77256ae 1901 #define NV_BACKKEY7_KEY_MASK 0xFFu
bogdanm 20:4263a77256ae 1902 #define NV_BACKKEY7_KEY_SHIFT 0
bogdanm 20:4263a77256ae 1903 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
bogdanm 20:4263a77256ae 1904 /* BACKKEY6 Bit Fields */
bogdanm 20:4263a77256ae 1905 #define NV_BACKKEY6_KEY_MASK 0xFFu
bogdanm 20:4263a77256ae 1906 #define NV_BACKKEY6_KEY_SHIFT 0
bogdanm 20:4263a77256ae 1907 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
bogdanm 20:4263a77256ae 1908 /* BACKKEY5 Bit Fields */
bogdanm 20:4263a77256ae 1909 #define NV_BACKKEY5_KEY_MASK 0xFFu
bogdanm 20:4263a77256ae 1910 #define NV_BACKKEY5_KEY_SHIFT 0
bogdanm 20:4263a77256ae 1911 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
bogdanm 20:4263a77256ae 1912 /* BACKKEY4 Bit Fields */
bogdanm 20:4263a77256ae 1913 #define NV_BACKKEY4_KEY_MASK 0xFFu
bogdanm 20:4263a77256ae 1914 #define NV_BACKKEY4_KEY_SHIFT 0
bogdanm 20:4263a77256ae 1915 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
bogdanm 20:4263a77256ae 1916 /* FPROT3 Bit Fields */
bogdanm 20:4263a77256ae 1917 #define NV_FPROT3_PROT_MASK 0xFFu
bogdanm 20:4263a77256ae 1918 #define NV_FPROT3_PROT_SHIFT 0
bogdanm 20:4263a77256ae 1919 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
bogdanm 20:4263a77256ae 1920 /* FPROT2 Bit Fields */
bogdanm 20:4263a77256ae 1921 #define NV_FPROT2_PROT_MASK 0xFFu
bogdanm 20:4263a77256ae 1922 #define NV_FPROT2_PROT_SHIFT 0
bogdanm 20:4263a77256ae 1923 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
bogdanm 20:4263a77256ae 1924 /* FPROT1 Bit Fields */
bogdanm 20:4263a77256ae 1925 #define NV_FPROT1_PROT_MASK 0xFFu
bogdanm 20:4263a77256ae 1926 #define NV_FPROT1_PROT_SHIFT 0
bogdanm 20:4263a77256ae 1927 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
bogdanm 20:4263a77256ae 1928 /* FPROT0 Bit Fields */
bogdanm 20:4263a77256ae 1929 #define NV_FPROT0_PROT_MASK 0xFFu
bogdanm 20:4263a77256ae 1930 #define NV_FPROT0_PROT_SHIFT 0
bogdanm 20:4263a77256ae 1931 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
bogdanm 20:4263a77256ae 1932 /* FSEC Bit Fields */
bogdanm 20:4263a77256ae 1933 #define NV_FSEC_SEC_MASK 0x3u
bogdanm 20:4263a77256ae 1934 #define NV_FSEC_SEC_SHIFT 0
bogdanm 20:4263a77256ae 1935 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
bogdanm 20:4263a77256ae 1936 #define NV_FSEC_FSLACC_MASK 0xCu
bogdanm 20:4263a77256ae 1937 #define NV_FSEC_FSLACC_SHIFT 2
bogdanm 20:4263a77256ae 1938 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
bogdanm 20:4263a77256ae 1939 #define NV_FSEC_MEEN_MASK 0x30u
bogdanm 20:4263a77256ae 1940 #define NV_FSEC_MEEN_SHIFT 4
bogdanm 20:4263a77256ae 1941 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
bogdanm 20:4263a77256ae 1942 #define NV_FSEC_KEYEN_MASK 0xC0u
bogdanm 20:4263a77256ae 1943 #define NV_FSEC_KEYEN_SHIFT 6
bogdanm 20:4263a77256ae 1944 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
bogdanm 20:4263a77256ae 1945 /* FOPT Bit Fields */
bogdanm 20:4263a77256ae 1946 #define NV_FOPT_LPBOOT0_MASK 0x1u
bogdanm 20:4263a77256ae 1947 #define NV_FOPT_LPBOOT0_SHIFT 0
bogdanm 20:4263a77256ae 1948 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
bogdanm 20:4263a77256ae 1949 #define NV_FOPT_EZPORT_DIS_SHIFT 1
bogdanm 20:4263a77256ae 1950 #define NV_FOPT_NMI_DIS_MASK 0x4u
bogdanm 20:4263a77256ae 1951 #define NV_FOPT_NMI_DIS_SHIFT 2
bogdanm 20:4263a77256ae 1952 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
bogdanm 20:4263a77256ae 1953 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
bogdanm 20:4263a77256ae 1954 #define NV_FOPT_LPBOOT1_MASK 0x10u
bogdanm 20:4263a77256ae 1955 #define NV_FOPT_LPBOOT1_SHIFT 4
bogdanm 20:4263a77256ae 1956 #define NV_FOPT_FAST_INIT_MASK 0x20u
bogdanm 20:4263a77256ae 1957 #define NV_FOPT_FAST_INIT_SHIFT 5
bogdanm 20:4263a77256ae 1958
bogdanm 20:4263a77256ae 1959 /**
bogdanm 20:4263a77256ae 1960 * @}
bogdanm 20:4263a77256ae 1961 */ /* end of group NV_Register_Masks */
bogdanm 20:4263a77256ae 1962
bogdanm 20:4263a77256ae 1963
bogdanm 20:4263a77256ae 1964 /* NV - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 1965 /** Peripheral FTFA_FlashConfig base address */
bogdanm 20:4263a77256ae 1966 #define FTFA_FlashConfig_BASE (0x400u)
bogdanm 20:4263a77256ae 1967 /** Peripheral FTFA_FlashConfig base pointer */
bogdanm 20:4263a77256ae 1968 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
bogdanm 20:4263a77256ae 1969 /** Array initializer of NV peripheral base pointers */
bogdanm 20:4263a77256ae 1970 #define NV_BASES { FTFA_FlashConfig }
bogdanm 20:4263a77256ae 1971
bogdanm 20:4263a77256ae 1972 /**
bogdanm 20:4263a77256ae 1973 * @}
bogdanm 20:4263a77256ae 1974 */ /* end of group NV_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 1975
bogdanm 20:4263a77256ae 1976
bogdanm 20:4263a77256ae 1977 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1978 -- OSC Peripheral Access Layer
bogdanm 20:4263a77256ae 1979 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1980
bogdanm 20:4263a77256ae 1981 /**
bogdanm 20:4263a77256ae 1982 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
bogdanm 20:4263a77256ae 1983 * @{
bogdanm 20:4263a77256ae 1984 */
bogdanm 20:4263a77256ae 1985
bogdanm 20:4263a77256ae 1986 /** OSC - Register Layout Typedef */
bogdanm 20:4263a77256ae 1987 typedef struct {
bogdanm 20:4263a77256ae 1988 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
bogdanm 20:4263a77256ae 1989 } OSC_Type;
bogdanm 20:4263a77256ae 1990
bogdanm 20:4263a77256ae 1991 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 1992 -- OSC Register Masks
bogdanm 20:4263a77256ae 1993 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 1994
bogdanm 20:4263a77256ae 1995 /**
bogdanm 20:4263a77256ae 1996 * @addtogroup OSC_Register_Masks OSC Register Masks
bogdanm 20:4263a77256ae 1997 * @{
bogdanm 20:4263a77256ae 1998 */
bogdanm 20:4263a77256ae 1999
bogdanm 20:4263a77256ae 2000 /* CR Bit Fields */
bogdanm 20:4263a77256ae 2001 #define OSC_CR_SC16P_MASK 0x1u
bogdanm 20:4263a77256ae 2002 #define OSC_CR_SC16P_SHIFT 0
bogdanm 20:4263a77256ae 2003 #define OSC_CR_SC8P_MASK 0x2u
bogdanm 20:4263a77256ae 2004 #define OSC_CR_SC8P_SHIFT 1
bogdanm 20:4263a77256ae 2005 #define OSC_CR_SC4P_MASK 0x4u
bogdanm 20:4263a77256ae 2006 #define OSC_CR_SC4P_SHIFT 2
bogdanm 20:4263a77256ae 2007 #define OSC_CR_SC2P_MASK 0x8u
bogdanm 20:4263a77256ae 2008 #define OSC_CR_SC2P_SHIFT 3
bogdanm 20:4263a77256ae 2009 #define OSC_CR_EREFSTEN_MASK 0x20u
bogdanm 20:4263a77256ae 2010 #define OSC_CR_EREFSTEN_SHIFT 5
bogdanm 20:4263a77256ae 2011 #define OSC_CR_ERCLKEN_MASK 0x80u
bogdanm 20:4263a77256ae 2012 #define OSC_CR_ERCLKEN_SHIFT 7
bogdanm 20:4263a77256ae 2013
bogdanm 20:4263a77256ae 2014 /**
bogdanm 20:4263a77256ae 2015 * @}
bogdanm 20:4263a77256ae 2016 */ /* end of group OSC_Register_Masks */
bogdanm 20:4263a77256ae 2017
bogdanm 20:4263a77256ae 2018
bogdanm 20:4263a77256ae 2019 /* OSC - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 2020 /** Peripheral OSC0 base address */
bogdanm 20:4263a77256ae 2021 #define OSC0_BASE (0x40065000u)
bogdanm 20:4263a77256ae 2022 /** Peripheral OSC0 base pointer */
bogdanm 20:4263a77256ae 2023 #define OSC0 ((OSC_Type *)OSC0_BASE)
bogdanm 20:4263a77256ae 2024 /** Array initializer of OSC peripheral base pointers */
bogdanm 20:4263a77256ae 2025 #define OSC_BASES { OSC0 }
bogdanm 20:4263a77256ae 2026
bogdanm 20:4263a77256ae 2027 /**
bogdanm 20:4263a77256ae 2028 * @}
bogdanm 20:4263a77256ae 2029 */ /* end of group OSC_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 2030
bogdanm 20:4263a77256ae 2031
bogdanm 20:4263a77256ae 2032 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2033 -- PIT Peripheral Access Layer
bogdanm 20:4263a77256ae 2034 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2035
bogdanm 20:4263a77256ae 2036 /**
bogdanm 20:4263a77256ae 2037 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
bogdanm 20:4263a77256ae 2038 * @{
bogdanm 20:4263a77256ae 2039 */
bogdanm 20:4263a77256ae 2040
bogdanm 20:4263a77256ae 2041 /** PIT - Register Layout Typedef */
bogdanm 20:4263a77256ae 2042 typedef struct {
bogdanm 20:4263a77256ae 2043 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
bogdanm 20:4263a77256ae 2044 uint8_t RESERVED_0[220];
bogdanm 20:4263a77256ae 2045 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
bogdanm 20:4263a77256ae 2046 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
bogdanm 20:4263a77256ae 2047 uint8_t RESERVED_1[24];
bogdanm 20:4263a77256ae 2048 struct { /* offset: 0x100, array step: 0x10 */
bogdanm 20:4263a77256ae 2049 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
bogdanm 20:4263a77256ae 2050 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
bogdanm 20:4263a77256ae 2051 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
bogdanm 20:4263a77256ae 2052 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
bogdanm 20:4263a77256ae 2053 } CHANNEL[2];
bogdanm 20:4263a77256ae 2054 } PIT_Type;
bogdanm 20:4263a77256ae 2055
bogdanm 20:4263a77256ae 2056 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2057 -- PIT Register Masks
bogdanm 20:4263a77256ae 2058 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2059
bogdanm 20:4263a77256ae 2060 /**
bogdanm 20:4263a77256ae 2061 * @addtogroup PIT_Register_Masks PIT Register Masks
bogdanm 20:4263a77256ae 2062 * @{
bogdanm 20:4263a77256ae 2063 */
bogdanm 20:4263a77256ae 2064
bogdanm 20:4263a77256ae 2065 /* MCR Bit Fields */
bogdanm 20:4263a77256ae 2066 #define PIT_MCR_FRZ_MASK 0x1u
bogdanm 20:4263a77256ae 2067 #define PIT_MCR_FRZ_SHIFT 0
bogdanm 20:4263a77256ae 2068 #define PIT_MCR_MDIS_MASK 0x2u
bogdanm 20:4263a77256ae 2069 #define PIT_MCR_MDIS_SHIFT 1
bogdanm 20:4263a77256ae 2070 /* LTMR64H Bit Fields */
bogdanm 20:4263a77256ae 2071 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2072 #define PIT_LTMR64H_LTH_SHIFT 0
bogdanm 20:4263a77256ae 2073 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
bogdanm 20:4263a77256ae 2074 /* LTMR64L Bit Fields */
bogdanm 20:4263a77256ae 2075 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2076 #define PIT_LTMR64L_LTL_SHIFT 0
bogdanm 20:4263a77256ae 2077 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
bogdanm 20:4263a77256ae 2078 /* LDVAL Bit Fields */
bogdanm 20:4263a77256ae 2079 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2080 #define PIT_LDVAL_TSV_SHIFT 0
bogdanm 20:4263a77256ae 2081 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
bogdanm 20:4263a77256ae 2082 /* CVAL Bit Fields */
bogdanm 20:4263a77256ae 2083 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2084 #define PIT_CVAL_TVL_SHIFT 0
bogdanm 20:4263a77256ae 2085 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
bogdanm 20:4263a77256ae 2086 /* TCTRL Bit Fields */
bogdanm 20:4263a77256ae 2087 #define PIT_TCTRL_TEN_MASK 0x1u
bogdanm 20:4263a77256ae 2088 #define PIT_TCTRL_TEN_SHIFT 0
bogdanm 20:4263a77256ae 2089 #define PIT_TCTRL_TIE_MASK 0x2u
bogdanm 20:4263a77256ae 2090 #define PIT_TCTRL_TIE_SHIFT 1
bogdanm 20:4263a77256ae 2091 #define PIT_TCTRL_CHN_MASK 0x4u
bogdanm 20:4263a77256ae 2092 #define PIT_TCTRL_CHN_SHIFT 2
bogdanm 20:4263a77256ae 2093 /* TFLG Bit Fields */
bogdanm 20:4263a77256ae 2094 #define PIT_TFLG_TIF_MASK 0x1u
bogdanm 20:4263a77256ae 2095 #define PIT_TFLG_TIF_SHIFT 0
bogdanm 20:4263a77256ae 2096
bogdanm 20:4263a77256ae 2097 /**
bogdanm 20:4263a77256ae 2098 * @}
bogdanm 20:4263a77256ae 2099 */ /* end of group PIT_Register_Masks */
bogdanm 20:4263a77256ae 2100
bogdanm 20:4263a77256ae 2101
bogdanm 20:4263a77256ae 2102 /* PIT - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 2103 /** Peripheral PIT base address */
bogdanm 20:4263a77256ae 2104 #define PIT_BASE (0x40037000u)
bogdanm 20:4263a77256ae 2105 /** Peripheral PIT base pointer */
bogdanm 20:4263a77256ae 2106 #define PIT ((PIT_Type *)PIT_BASE)
bogdanm 20:4263a77256ae 2107 /** Array initializer of PIT peripheral base pointers */
bogdanm 20:4263a77256ae 2108 #define PIT_BASES { PIT }
bogdanm 20:4263a77256ae 2109
bogdanm 20:4263a77256ae 2110 /**
bogdanm 20:4263a77256ae 2111 * @}
bogdanm 20:4263a77256ae 2112 */ /* end of group PIT_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 2113
bogdanm 20:4263a77256ae 2114
bogdanm 20:4263a77256ae 2115 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2116 -- PMC Peripheral Access Layer
bogdanm 20:4263a77256ae 2117 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2118
bogdanm 20:4263a77256ae 2119 /**
bogdanm 20:4263a77256ae 2120 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
bogdanm 20:4263a77256ae 2121 * @{
bogdanm 20:4263a77256ae 2122 */
bogdanm 20:4263a77256ae 2123
bogdanm 20:4263a77256ae 2124 /** PMC - Register Layout Typedef */
bogdanm 20:4263a77256ae 2125 typedef struct {
bogdanm 20:4263a77256ae 2126 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
bogdanm 20:4263a77256ae 2127 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
bogdanm 20:4263a77256ae 2128 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
bogdanm 20:4263a77256ae 2129 } PMC_Type;
bogdanm 20:4263a77256ae 2130
bogdanm 20:4263a77256ae 2131 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2132 -- PMC Register Masks
bogdanm 20:4263a77256ae 2133 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2134
bogdanm 20:4263a77256ae 2135 /**
bogdanm 20:4263a77256ae 2136 * @addtogroup PMC_Register_Masks PMC Register Masks
bogdanm 20:4263a77256ae 2137 * @{
bogdanm 20:4263a77256ae 2138 */
bogdanm 20:4263a77256ae 2139
bogdanm 20:4263a77256ae 2140 /* LVDSC1 Bit Fields */
bogdanm 20:4263a77256ae 2141 #define PMC_LVDSC1_LVDV_MASK 0x3u
bogdanm 20:4263a77256ae 2142 #define PMC_LVDSC1_LVDV_SHIFT 0
bogdanm 20:4263a77256ae 2143 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
bogdanm 20:4263a77256ae 2144 #define PMC_LVDSC1_LVDRE_MASK 0x10u
bogdanm 20:4263a77256ae 2145 #define PMC_LVDSC1_LVDRE_SHIFT 4
bogdanm 20:4263a77256ae 2146 #define PMC_LVDSC1_LVDIE_MASK 0x20u
bogdanm 20:4263a77256ae 2147 #define PMC_LVDSC1_LVDIE_SHIFT 5
bogdanm 20:4263a77256ae 2148 #define PMC_LVDSC1_LVDACK_MASK 0x40u
bogdanm 20:4263a77256ae 2149 #define PMC_LVDSC1_LVDACK_SHIFT 6
bogdanm 20:4263a77256ae 2150 #define PMC_LVDSC1_LVDF_MASK 0x80u
bogdanm 20:4263a77256ae 2151 #define PMC_LVDSC1_LVDF_SHIFT 7
bogdanm 20:4263a77256ae 2152 /* LVDSC2 Bit Fields */
bogdanm 20:4263a77256ae 2153 #define PMC_LVDSC2_LVWV_MASK 0x3u
bogdanm 20:4263a77256ae 2154 #define PMC_LVDSC2_LVWV_SHIFT 0
bogdanm 20:4263a77256ae 2155 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
bogdanm 20:4263a77256ae 2156 #define PMC_LVDSC2_LVWIE_MASK 0x20u
bogdanm 20:4263a77256ae 2157 #define PMC_LVDSC2_LVWIE_SHIFT 5
bogdanm 20:4263a77256ae 2158 #define PMC_LVDSC2_LVWACK_MASK 0x40u
bogdanm 20:4263a77256ae 2159 #define PMC_LVDSC2_LVWACK_SHIFT 6
bogdanm 20:4263a77256ae 2160 #define PMC_LVDSC2_LVWF_MASK 0x80u
bogdanm 20:4263a77256ae 2161 #define PMC_LVDSC2_LVWF_SHIFT 7
bogdanm 20:4263a77256ae 2162 /* REGSC Bit Fields */
bogdanm 20:4263a77256ae 2163 #define PMC_REGSC_BGBE_MASK 0x1u
bogdanm 20:4263a77256ae 2164 #define PMC_REGSC_BGBE_SHIFT 0
bogdanm 20:4263a77256ae 2165 #define PMC_REGSC_REGONS_MASK 0x4u
bogdanm 20:4263a77256ae 2166 #define PMC_REGSC_REGONS_SHIFT 2
bogdanm 20:4263a77256ae 2167 #define PMC_REGSC_ACKISO_MASK 0x8u
bogdanm 20:4263a77256ae 2168 #define PMC_REGSC_ACKISO_SHIFT 3
bogdanm 20:4263a77256ae 2169 #define PMC_REGSC_BGEN_MASK 0x10u
bogdanm 20:4263a77256ae 2170 #define PMC_REGSC_BGEN_SHIFT 4
bogdanm 20:4263a77256ae 2171
bogdanm 20:4263a77256ae 2172 /**
bogdanm 20:4263a77256ae 2173 * @}
bogdanm 20:4263a77256ae 2174 */ /* end of group PMC_Register_Masks */
bogdanm 20:4263a77256ae 2175
bogdanm 20:4263a77256ae 2176
bogdanm 20:4263a77256ae 2177 /* PMC - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 2178 /** Peripheral PMC base address */
bogdanm 20:4263a77256ae 2179 #define PMC_BASE (0x4007D000u)
bogdanm 20:4263a77256ae 2180 /** Peripheral PMC base pointer */
bogdanm 20:4263a77256ae 2181 #define PMC ((PMC_Type *)PMC_BASE)
bogdanm 20:4263a77256ae 2182 /** Array initializer of PMC peripheral base pointers */
bogdanm 20:4263a77256ae 2183 #define PMC_BASES { PMC }
bogdanm 20:4263a77256ae 2184
bogdanm 20:4263a77256ae 2185 /**
bogdanm 20:4263a77256ae 2186 * @}
bogdanm 20:4263a77256ae 2187 */ /* end of group PMC_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 2188
bogdanm 20:4263a77256ae 2189
bogdanm 20:4263a77256ae 2190 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2191 -- PORT Peripheral Access Layer
bogdanm 20:4263a77256ae 2192 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2193
bogdanm 20:4263a77256ae 2194 /**
bogdanm 20:4263a77256ae 2195 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
bogdanm 20:4263a77256ae 2196 * @{
bogdanm 20:4263a77256ae 2197 */
bogdanm 20:4263a77256ae 2198
bogdanm 20:4263a77256ae 2199 /** PORT - Register Layout Typedef */
bogdanm 20:4263a77256ae 2200 typedef struct {
bogdanm 20:4263a77256ae 2201 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
bogdanm 20:4263a77256ae 2202 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
bogdanm 20:4263a77256ae 2203 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
bogdanm 20:4263a77256ae 2204 uint8_t RESERVED_0[24];
bogdanm 20:4263a77256ae 2205 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
bogdanm 20:4263a77256ae 2206 } PORT_Type;
bogdanm 20:4263a77256ae 2207
bogdanm 20:4263a77256ae 2208 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2209 -- PORT Register Masks
bogdanm 20:4263a77256ae 2210 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2211
bogdanm 20:4263a77256ae 2212 /**
bogdanm 20:4263a77256ae 2213 * @addtogroup PORT_Register_Masks PORT Register Masks
bogdanm 20:4263a77256ae 2214 * @{
bogdanm 20:4263a77256ae 2215 */
bogdanm 20:4263a77256ae 2216
bogdanm 20:4263a77256ae 2217 /* PCR Bit Fields */
bogdanm 20:4263a77256ae 2218 #define PORT_PCR_PS_MASK 0x1u
bogdanm 20:4263a77256ae 2219 #define PORT_PCR_PS_SHIFT 0
bogdanm 20:4263a77256ae 2220 #define PORT_PCR_PE_MASK 0x2u
bogdanm 20:4263a77256ae 2221 #define PORT_PCR_PE_SHIFT 1
bogdanm 20:4263a77256ae 2222 #define PORT_PCR_SRE_MASK 0x4u
bogdanm 20:4263a77256ae 2223 #define PORT_PCR_SRE_SHIFT 2
bogdanm 20:4263a77256ae 2224 #define PORT_PCR_PFE_MASK 0x10u
bogdanm 20:4263a77256ae 2225 #define PORT_PCR_PFE_SHIFT 4
bogdanm 20:4263a77256ae 2226 #define PORT_PCR_DSE_MASK 0x40u
bogdanm 20:4263a77256ae 2227 #define PORT_PCR_DSE_SHIFT 6
bogdanm 20:4263a77256ae 2228 #define PORT_PCR_MUX_MASK 0x700u
bogdanm 20:4263a77256ae 2229 #define PORT_PCR_MUX_SHIFT 8
bogdanm 20:4263a77256ae 2230 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
bogdanm 20:4263a77256ae 2231 #define PORT_PCR_IRQC_MASK 0xF0000u
bogdanm 20:4263a77256ae 2232 #define PORT_PCR_IRQC_SHIFT 16
bogdanm 20:4263a77256ae 2233 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
bogdanm 20:4263a77256ae 2234 #define PORT_PCR_ISF_MASK 0x1000000u
bogdanm 20:4263a77256ae 2235 #define PORT_PCR_ISF_SHIFT 24
bogdanm 20:4263a77256ae 2236 /* GPCLR Bit Fields */
bogdanm 20:4263a77256ae 2237 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
bogdanm 20:4263a77256ae 2238 #define PORT_GPCLR_GPWD_SHIFT 0
bogdanm 20:4263a77256ae 2239 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
bogdanm 20:4263a77256ae 2240 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
bogdanm 20:4263a77256ae 2241 #define PORT_GPCLR_GPWE_SHIFT 16
bogdanm 20:4263a77256ae 2242 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
bogdanm 20:4263a77256ae 2243 /* GPCHR Bit Fields */
bogdanm 20:4263a77256ae 2244 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
bogdanm 20:4263a77256ae 2245 #define PORT_GPCHR_GPWD_SHIFT 0
bogdanm 20:4263a77256ae 2246 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
bogdanm 20:4263a77256ae 2247 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
bogdanm 20:4263a77256ae 2248 #define PORT_GPCHR_GPWE_SHIFT 16
bogdanm 20:4263a77256ae 2249 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
bogdanm 20:4263a77256ae 2250 /* ISFR Bit Fields */
bogdanm 20:4263a77256ae 2251 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2252 #define PORT_ISFR_ISF_SHIFT 0
bogdanm 20:4263a77256ae 2253 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
bogdanm 20:4263a77256ae 2254
bogdanm 20:4263a77256ae 2255 /**
bogdanm 20:4263a77256ae 2256 * @}
bogdanm 20:4263a77256ae 2257 */ /* end of group PORT_Register_Masks */
bogdanm 20:4263a77256ae 2258
bogdanm 20:4263a77256ae 2259
bogdanm 20:4263a77256ae 2260 /* PORT - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 2261 /** Peripheral PORTA base address */
bogdanm 20:4263a77256ae 2262 #define PORTA_BASE (0x40049000u)
bogdanm 20:4263a77256ae 2263 /** Peripheral PORTA base pointer */
bogdanm 20:4263a77256ae 2264 #define PORTA ((PORT_Type *)PORTA_BASE)
bogdanm 20:4263a77256ae 2265 /** Peripheral PORTB base address */
bogdanm 20:4263a77256ae 2266 #define PORTB_BASE (0x4004A000u)
bogdanm 20:4263a77256ae 2267 /** Peripheral PORTB base pointer */
bogdanm 20:4263a77256ae 2268 #define PORTB ((PORT_Type *)PORTB_BASE)
bogdanm 20:4263a77256ae 2269 /** Array initializer of PORT peripheral base pointers */
bogdanm 20:4263a77256ae 2270 #define PORT_BASES { PORTA, PORTB }
bogdanm 20:4263a77256ae 2271
bogdanm 20:4263a77256ae 2272 /**
bogdanm 20:4263a77256ae 2273 * @}
bogdanm 20:4263a77256ae 2274 */ /* end of group PORT_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 2275
bogdanm 20:4263a77256ae 2276
bogdanm 20:4263a77256ae 2277 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2278 -- RCM Peripheral Access Layer
bogdanm 20:4263a77256ae 2279 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2280
bogdanm 20:4263a77256ae 2281 /**
bogdanm 20:4263a77256ae 2282 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
bogdanm 20:4263a77256ae 2283 * @{
bogdanm 20:4263a77256ae 2284 */
bogdanm 20:4263a77256ae 2285
bogdanm 20:4263a77256ae 2286 /** RCM - Register Layout Typedef */
bogdanm 20:4263a77256ae 2287 typedef struct {
bogdanm 20:4263a77256ae 2288 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
bogdanm 20:4263a77256ae 2289 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
bogdanm 20:4263a77256ae 2290 uint8_t RESERVED_0[2];
bogdanm 20:4263a77256ae 2291 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
bogdanm 20:4263a77256ae 2292 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
bogdanm 20:4263a77256ae 2293 } RCM_Type;
bogdanm 20:4263a77256ae 2294
bogdanm 20:4263a77256ae 2295 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2296 -- RCM Register Masks
bogdanm 20:4263a77256ae 2297 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2298
bogdanm 20:4263a77256ae 2299 /**
bogdanm 20:4263a77256ae 2300 * @addtogroup RCM_Register_Masks RCM Register Masks
bogdanm 20:4263a77256ae 2301 * @{
bogdanm 20:4263a77256ae 2302 */
bogdanm 20:4263a77256ae 2303
bogdanm 20:4263a77256ae 2304 /* SRS0 Bit Fields */
bogdanm 20:4263a77256ae 2305 #define RCM_SRS0_WAKEUP_MASK 0x1u
bogdanm 20:4263a77256ae 2306 #define RCM_SRS0_WAKEUP_SHIFT 0
bogdanm 20:4263a77256ae 2307 #define RCM_SRS0_LVD_MASK 0x2u
bogdanm 20:4263a77256ae 2308 #define RCM_SRS0_LVD_SHIFT 1
bogdanm 20:4263a77256ae 2309 #define RCM_SRS0_LOC_MASK 0x4u
bogdanm 20:4263a77256ae 2310 #define RCM_SRS0_LOC_SHIFT 2
bogdanm 20:4263a77256ae 2311 #define RCM_SRS0_WDOG_MASK 0x20u
bogdanm 20:4263a77256ae 2312 #define RCM_SRS0_WDOG_SHIFT 5
bogdanm 20:4263a77256ae 2313 #define RCM_SRS0_PIN_MASK 0x40u
bogdanm 20:4263a77256ae 2314 #define RCM_SRS0_PIN_SHIFT 6
bogdanm 20:4263a77256ae 2315 #define RCM_SRS0_POR_MASK 0x80u
bogdanm 20:4263a77256ae 2316 #define RCM_SRS0_POR_SHIFT 7
bogdanm 20:4263a77256ae 2317 /* SRS1 Bit Fields */
bogdanm 20:4263a77256ae 2318 #define RCM_SRS1_LOCKUP_MASK 0x2u
bogdanm 20:4263a77256ae 2319 #define RCM_SRS1_LOCKUP_SHIFT 1
bogdanm 20:4263a77256ae 2320 #define RCM_SRS1_SW_MASK 0x4u
bogdanm 20:4263a77256ae 2321 #define RCM_SRS1_SW_SHIFT 2
bogdanm 20:4263a77256ae 2322 #define RCM_SRS1_MDM_AP_MASK 0x8u
bogdanm 20:4263a77256ae 2323 #define RCM_SRS1_MDM_AP_SHIFT 3
bogdanm 20:4263a77256ae 2324 #define RCM_SRS1_SACKERR_MASK 0x20u
bogdanm 20:4263a77256ae 2325 #define RCM_SRS1_SACKERR_SHIFT 5
bogdanm 20:4263a77256ae 2326 /* RPFC Bit Fields */
bogdanm 20:4263a77256ae 2327 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
bogdanm 20:4263a77256ae 2328 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
bogdanm 20:4263a77256ae 2329 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
bogdanm 20:4263a77256ae 2330 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
bogdanm 20:4263a77256ae 2331 #define RCM_RPFC_RSTFLTSS_SHIFT 2
bogdanm 20:4263a77256ae 2332 /* RPFW Bit Fields */
bogdanm 20:4263a77256ae 2333 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
bogdanm 20:4263a77256ae 2334 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
bogdanm 20:4263a77256ae 2335 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
bogdanm 20:4263a77256ae 2336
bogdanm 20:4263a77256ae 2337 /**
bogdanm 20:4263a77256ae 2338 * @}
bogdanm 20:4263a77256ae 2339 */ /* end of group RCM_Register_Masks */
bogdanm 20:4263a77256ae 2340
bogdanm 20:4263a77256ae 2341
bogdanm 20:4263a77256ae 2342 /* RCM - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 2343 /** Peripheral RCM base address */
bogdanm 20:4263a77256ae 2344 #define RCM_BASE (0x4007F000u)
bogdanm 20:4263a77256ae 2345 /** Peripheral RCM base pointer */
bogdanm 20:4263a77256ae 2346 #define RCM ((RCM_Type *)RCM_BASE)
bogdanm 20:4263a77256ae 2347 /** Array initializer of RCM peripheral base pointers */
bogdanm 20:4263a77256ae 2348 #define RCM_BASES { RCM }
bogdanm 20:4263a77256ae 2349
bogdanm 20:4263a77256ae 2350 /**
bogdanm 20:4263a77256ae 2351 * @}
bogdanm 20:4263a77256ae 2352 */ /* end of group RCM_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 2353
bogdanm 20:4263a77256ae 2354
bogdanm 20:4263a77256ae 2355 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2356 -- ROM Peripheral Access Layer
bogdanm 20:4263a77256ae 2357 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2358
bogdanm 20:4263a77256ae 2359 /**
bogdanm 20:4263a77256ae 2360 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
bogdanm 20:4263a77256ae 2361 * @{
bogdanm 20:4263a77256ae 2362 */
bogdanm 20:4263a77256ae 2363
bogdanm 20:4263a77256ae 2364 /** ROM - Register Layout Typedef */
bogdanm 20:4263a77256ae 2365 typedef struct {
bogdanm 20:4263a77256ae 2366 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
bogdanm 20:4263a77256ae 2367 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
bogdanm 20:4263a77256ae 2368 uint8_t RESERVED_0[4028];
bogdanm 20:4263a77256ae 2369 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
bogdanm 20:4263a77256ae 2370 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
bogdanm 20:4263a77256ae 2371 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
bogdanm 20:4263a77256ae 2372 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
bogdanm 20:4263a77256ae 2373 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
bogdanm 20:4263a77256ae 2374 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
bogdanm 20:4263a77256ae 2375 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
bogdanm 20:4263a77256ae 2376 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
bogdanm 20:4263a77256ae 2377 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
bogdanm 20:4263a77256ae 2378 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
bogdanm 20:4263a77256ae 2379 } ROM_Type;
bogdanm 20:4263a77256ae 2380
bogdanm 20:4263a77256ae 2381 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2382 -- ROM Register Masks
bogdanm 20:4263a77256ae 2383 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2384
bogdanm 20:4263a77256ae 2385 /**
bogdanm 20:4263a77256ae 2386 * @addtogroup ROM_Register_Masks ROM Register Masks
bogdanm 20:4263a77256ae 2387 * @{
bogdanm 20:4263a77256ae 2388 */
bogdanm 20:4263a77256ae 2389
bogdanm 20:4263a77256ae 2390 /* ENTRY Bit Fields */
bogdanm 20:4263a77256ae 2391 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2392 #define ROM_ENTRY_ENTRY_SHIFT 0
bogdanm 20:4263a77256ae 2393 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
bogdanm 20:4263a77256ae 2394 /* TABLEMARK Bit Fields */
bogdanm 20:4263a77256ae 2395 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2396 #define ROM_TABLEMARK_MARK_SHIFT 0
bogdanm 20:4263a77256ae 2397 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
bogdanm 20:4263a77256ae 2398 /* SYSACCESS Bit Fields */
bogdanm 20:4263a77256ae 2399 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2400 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
bogdanm 20:4263a77256ae 2401 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
bogdanm 20:4263a77256ae 2402 /* PERIPHID4 Bit Fields */
bogdanm 20:4263a77256ae 2403 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2404 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
bogdanm 20:4263a77256ae 2405 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
bogdanm 20:4263a77256ae 2406 /* PERIPHID5 Bit Fields */
bogdanm 20:4263a77256ae 2407 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2408 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
bogdanm 20:4263a77256ae 2409 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
bogdanm 20:4263a77256ae 2410 /* PERIPHID6 Bit Fields */
bogdanm 20:4263a77256ae 2411 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2412 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
bogdanm 20:4263a77256ae 2413 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
bogdanm 20:4263a77256ae 2414 /* PERIPHID7 Bit Fields */
bogdanm 20:4263a77256ae 2415 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2416 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
bogdanm 20:4263a77256ae 2417 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
bogdanm 20:4263a77256ae 2418 /* PERIPHID0 Bit Fields */
bogdanm 20:4263a77256ae 2419 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2420 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
bogdanm 20:4263a77256ae 2421 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
bogdanm 20:4263a77256ae 2422 /* PERIPHID1 Bit Fields */
bogdanm 20:4263a77256ae 2423 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2424 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
bogdanm 20:4263a77256ae 2425 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
bogdanm 20:4263a77256ae 2426 /* PERIPHID2 Bit Fields */
bogdanm 20:4263a77256ae 2427 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2428 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
bogdanm 20:4263a77256ae 2429 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
bogdanm 20:4263a77256ae 2430 /* PERIPHID3 Bit Fields */
bogdanm 20:4263a77256ae 2431 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2432 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
bogdanm 20:4263a77256ae 2433 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
bogdanm 20:4263a77256ae 2434 /* COMPID Bit Fields */
bogdanm 20:4263a77256ae 2435 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2436 #define ROM_COMPID_COMPID_SHIFT 0
bogdanm 20:4263a77256ae 2437 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
bogdanm 20:4263a77256ae 2438
bogdanm 20:4263a77256ae 2439 /**
bogdanm 20:4263a77256ae 2440 * @}
bogdanm 20:4263a77256ae 2441 */ /* end of group ROM_Register_Masks */
bogdanm 20:4263a77256ae 2442
bogdanm 20:4263a77256ae 2443
bogdanm 20:4263a77256ae 2444 /* ROM - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 2445 /** Peripheral ROM base address */
bogdanm 20:4263a77256ae 2446 #define ROM_BASE (0xF0002000u)
bogdanm 20:4263a77256ae 2447 /** Peripheral ROM base pointer */
bogdanm 20:4263a77256ae 2448 #define ROM ((ROM_Type *)ROM_BASE)
bogdanm 20:4263a77256ae 2449 /** Array initializer of ROM peripheral base pointers */
bogdanm 20:4263a77256ae 2450 #define ROM_BASES { ROM }
bogdanm 20:4263a77256ae 2451
bogdanm 20:4263a77256ae 2452 /**
bogdanm 20:4263a77256ae 2453 * @}
bogdanm 20:4263a77256ae 2454 */ /* end of group ROM_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 2455
bogdanm 20:4263a77256ae 2456
bogdanm 20:4263a77256ae 2457 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2458 -- RTC Peripheral Access Layer
bogdanm 20:4263a77256ae 2459 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2460
bogdanm 20:4263a77256ae 2461 /**
bogdanm 20:4263a77256ae 2462 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
bogdanm 20:4263a77256ae 2463 * @{
bogdanm 20:4263a77256ae 2464 */
bogdanm 20:4263a77256ae 2465
bogdanm 20:4263a77256ae 2466 /** RTC - Register Layout Typedef */
bogdanm 20:4263a77256ae 2467 typedef struct {
bogdanm 20:4263a77256ae 2468 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
bogdanm 20:4263a77256ae 2469 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
bogdanm 20:4263a77256ae 2470 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
bogdanm 20:4263a77256ae 2471 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
bogdanm 20:4263a77256ae 2472 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
bogdanm 20:4263a77256ae 2473 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
bogdanm 20:4263a77256ae 2474 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
bogdanm 20:4263a77256ae 2475 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
bogdanm 20:4263a77256ae 2476 } RTC_Type;
bogdanm 20:4263a77256ae 2477
bogdanm 20:4263a77256ae 2478 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2479 -- RTC Register Masks
bogdanm 20:4263a77256ae 2480 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2481
bogdanm 20:4263a77256ae 2482 /**
bogdanm 20:4263a77256ae 2483 * @addtogroup RTC_Register_Masks RTC Register Masks
bogdanm 20:4263a77256ae 2484 * @{
bogdanm 20:4263a77256ae 2485 */
bogdanm 20:4263a77256ae 2486
bogdanm 20:4263a77256ae 2487 /* TSR Bit Fields */
bogdanm 20:4263a77256ae 2488 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2489 #define RTC_TSR_TSR_SHIFT 0
bogdanm 20:4263a77256ae 2490 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
bogdanm 20:4263a77256ae 2491 /* TPR Bit Fields */
bogdanm 20:4263a77256ae 2492 #define RTC_TPR_TPR_MASK 0xFFFFu
bogdanm 20:4263a77256ae 2493 #define RTC_TPR_TPR_SHIFT 0
bogdanm 20:4263a77256ae 2494 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
bogdanm 20:4263a77256ae 2495 /* TAR Bit Fields */
bogdanm 20:4263a77256ae 2496 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2497 #define RTC_TAR_TAR_SHIFT 0
bogdanm 20:4263a77256ae 2498 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
bogdanm 20:4263a77256ae 2499 /* TCR Bit Fields */
bogdanm 20:4263a77256ae 2500 #define RTC_TCR_TCR_MASK 0xFFu
bogdanm 20:4263a77256ae 2501 #define RTC_TCR_TCR_SHIFT 0
bogdanm 20:4263a77256ae 2502 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
bogdanm 20:4263a77256ae 2503 #define RTC_TCR_CIR_MASK 0xFF00u
bogdanm 20:4263a77256ae 2504 #define RTC_TCR_CIR_SHIFT 8
bogdanm 20:4263a77256ae 2505 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
bogdanm 20:4263a77256ae 2506 #define RTC_TCR_TCV_MASK 0xFF0000u
bogdanm 20:4263a77256ae 2507 #define RTC_TCR_TCV_SHIFT 16
bogdanm 20:4263a77256ae 2508 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
bogdanm 20:4263a77256ae 2509 #define RTC_TCR_CIC_MASK 0xFF000000u
bogdanm 20:4263a77256ae 2510 #define RTC_TCR_CIC_SHIFT 24
bogdanm 20:4263a77256ae 2511 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
bogdanm 20:4263a77256ae 2512 /* CR Bit Fields */
bogdanm 20:4263a77256ae 2513 #define RTC_CR_SWR_MASK 0x1u
bogdanm 20:4263a77256ae 2514 #define RTC_CR_SWR_SHIFT 0
bogdanm 20:4263a77256ae 2515 #define RTC_CR_WPE_MASK 0x2u
bogdanm 20:4263a77256ae 2516 #define RTC_CR_WPE_SHIFT 1
bogdanm 20:4263a77256ae 2517 #define RTC_CR_SUP_MASK 0x4u
bogdanm 20:4263a77256ae 2518 #define RTC_CR_SUP_SHIFT 2
bogdanm 20:4263a77256ae 2519 #define RTC_CR_UM_MASK 0x8u
bogdanm 20:4263a77256ae 2520 #define RTC_CR_UM_SHIFT 3
bogdanm 20:4263a77256ae 2521 #define RTC_CR_OSCE_MASK 0x100u
bogdanm 20:4263a77256ae 2522 #define RTC_CR_OSCE_SHIFT 8
bogdanm 20:4263a77256ae 2523 #define RTC_CR_CLKO_MASK 0x200u
bogdanm 20:4263a77256ae 2524 #define RTC_CR_CLKO_SHIFT 9
bogdanm 20:4263a77256ae 2525 #define RTC_CR_SC16P_MASK 0x400u
bogdanm 20:4263a77256ae 2526 #define RTC_CR_SC16P_SHIFT 10
bogdanm 20:4263a77256ae 2527 #define RTC_CR_SC8P_MASK 0x800u
bogdanm 20:4263a77256ae 2528 #define RTC_CR_SC8P_SHIFT 11
bogdanm 20:4263a77256ae 2529 #define RTC_CR_SC4P_MASK 0x1000u
bogdanm 20:4263a77256ae 2530 #define RTC_CR_SC4P_SHIFT 12
bogdanm 20:4263a77256ae 2531 #define RTC_CR_SC2P_MASK 0x2000u
bogdanm 20:4263a77256ae 2532 #define RTC_CR_SC2P_SHIFT 13
bogdanm 20:4263a77256ae 2533 /* SR Bit Fields */
bogdanm 20:4263a77256ae 2534 #define RTC_SR_TIF_MASK 0x1u
bogdanm 20:4263a77256ae 2535 #define RTC_SR_TIF_SHIFT 0
bogdanm 20:4263a77256ae 2536 #define RTC_SR_TOF_MASK 0x2u
bogdanm 20:4263a77256ae 2537 #define RTC_SR_TOF_SHIFT 1
bogdanm 20:4263a77256ae 2538 #define RTC_SR_TAF_MASK 0x4u
bogdanm 20:4263a77256ae 2539 #define RTC_SR_TAF_SHIFT 2
bogdanm 20:4263a77256ae 2540 #define RTC_SR_TCE_MASK 0x10u
bogdanm 20:4263a77256ae 2541 #define RTC_SR_TCE_SHIFT 4
bogdanm 20:4263a77256ae 2542 /* LR Bit Fields */
bogdanm 20:4263a77256ae 2543 #define RTC_LR_TCL_MASK 0x8u
bogdanm 20:4263a77256ae 2544 #define RTC_LR_TCL_SHIFT 3
bogdanm 20:4263a77256ae 2545 #define RTC_LR_CRL_MASK 0x10u
bogdanm 20:4263a77256ae 2546 #define RTC_LR_CRL_SHIFT 4
bogdanm 20:4263a77256ae 2547 #define RTC_LR_SRL_MASK 0x20u
bogdanm 20:4263a77256ae 2548 #define RTC_LR_SRL_SHIFT 5
bogdanm 20:4263a77256ae 2549 #define RTC_LR_LRL_MASK 0x40u
bogdanm 20:4263a77256ae 2550 #define RTC_LR_LRL_SHIFT 6
bogdanm 20:4263a77256ae 2551 /* IER Bit Fields */
bogdanm 20:4263a77256ae 2552 #define RTC_IER_TIIE_MASK 0x1u
bogdanm 20:4263a77256ae 2553 #define RTC_IER_TIIE_SHIFT 0
bogdanm 20:4263a77256ae 2554 #define RTC_IER_TOIE_MASK 0x2u
bogdanm 20:4263a77256ae 2555 #define RTC_IER_TOIE_SHIFT 1
bogdanm 20:4263a77256ae 2556 #define RTC_IER_TAIE_MASK 0x4u
bogdanm 20:4263a77256ae 2557 #define RTC_IER_TAIE_SHIFT 2
bogdanm 20:4263a77256ae 2558 #define RTC_IER_TSIE_MASK 0x10u
bogdanm 20:4263a77256ae 2559 #define RTC_IER_TSIE_SHIFT 4
bogdanm 20:4263a77256ae 2560 #define RTC_IER_WPON_MASK 0x80u
bogdanm 20:4263a77256ae 2561 #define RTC_IER_WPON_SHIFT 7
bogdanm 20:4263a77256ae 2562
bogdanm 20:4263a77256ae 2563 /**
bogdanm 20:4263a77256ae 2564 * @}
bogdanm 20:4263a77256ae 2565 */ /* end of group RTC_Register_Masks */
bogdanm 20:4263a77256ae 2566
bogdanm 20:4263a77256ae 2567
bogdanm 20:4263a77256ae 2568 /* RTC - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 2569 /** Peripheral RTC base address */
bogdanm 20:4263a77256ae 2570 #define RTC_BASE (0x4003D000u)
bogdanm 20:4263a77256ae 2571 /** Peripheral RTC base pointer */
bogdanm 20:4263a77256ae 2572 #define RTC ((RTC_Type *)RTC_BASE)
bogdanm 20:4263a77256ae 2573 /** Array initializer of RTC peripheral base pointers */
bogdanm 20:4263a77256ae 2574 #define RTC_BASES { RTC }
bogdanm 20:4263a77256ae 2575
bogdanm 20:4263a77256ae 2576 /**
bogdanm 20:4263a77256ae 2577 * @}
bogdanm 20:4263a77256ae 2578 */ /* end of group RTC_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 2579
bogdanm 20:4263a77256ae 2580
bogdanm 20:4263a77256ae 2581 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2582 -- SIM Peripheral Access Layer
bogdanm 20:4263a77256ae 2583 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2584
bogdanm 20:4263a77256ae 2585 /**
bogdanm 20:4263a77256ae 2586 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
bogdanm 20:4263a77256ae 2587 * @{
bogdanm 20:4263a77256ae 2588 */
bogdanm 20:4263a77256ae 2589
bogdanm 20:4263a77256ae 2590 /** SIM - Register Layout Typedef */
bogdanm 20:4263a77256ae 2591 typedef struct {
bogdanm 20:4263a77256ae 2592 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
bogdanm 20:4263a77256ae 2593 __I uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
bogdanm 20:4263a77256ae 2594 uint8_t RESERVED_0[4092];
bogdanm 20:4263a77256ae 2595 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
bogdanm 20:4263a77256ae 2596 uint8_t RESERVED_1[4];
bogdanm 20:4263a77256ae 2597 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
bogdanm 20:4263a77256ae 2598 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
bogdanm 20:4263a77256ae 2599 uint8_t RESERVED_2[4];
bogdanm 20:4263a77256ae 2600 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
bogdanm 20:4263a77256ae 2601 uint8_t RESERVED_3[8];
bogdanm 20:4263a77256ae 2602 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
bogdanm 20:4263a77256ae 2603 uint8_t RESERVED_4[12];
bogdanm 20:4263a77256ae 2604 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
bogdanm 20:4263a77256ae 2605 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
bogdanm 20:4263a77256ae 2606 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
bogdanm 20:4263a77256ae 2607 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
bogdanm 20:4263a77256ae 2608 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
bogdanm 20:4263a77256ae 2609 uint8_t RESERVED_5[4];
bogdanm 20:4263a77256ae 2610 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
bogdanm 20:4263a77256ae 2611 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
bogdanm 20:4263a77256ae 2612 uint8_t RESERVED_6[4];
bogdanm 20:4263a77256ae 2613 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
bogdanm 20:4263a77256ae 2614 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
bogdanm 20:4263a77256ae 2615 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
bogdanm 20:4263a77256ae 2616 uint8_t RESERVED_7[156];
bogdanm 20:4263a77256ae 2617 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
bogdanm 20:4263a77256ae 2618 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
bogdanm 20:4263a77256ae 2619 } SIM_Type;
bogdanm 20:4263a77256ae 2620
bogdanm 20:4263a77256ae 2621 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2622 -- SIM Register Masks
bogdanm 20:4263a77256ae 2623 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2624
bogdanm 20:4263a77256ae 2625 /**
bogdanm 20:4263a77256ae 2626 * @addtogroup SIM_Register_Masks SIM Register Masks
bogdanm 20:4263a77256ae 2627 * @{
bogdanm 20:4263a77256ae 2628 */
bogdanm 20:4263a77256ae 2629
bogdanm 20:4263a77256ae 2630 /* SOPT1 Bit Fields */
bogdanm 20:4263a77256ae 2631 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
bogdanm 20:4263a77256ae 2632 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
bogdanm 20:4263a77256ae 2633 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
bogdanm 20:4263a77256ae 2634 /* SOPT2 Bit Fields */
bogdanm 20:4263a77256ae 2635 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
bogdanm 20:4263a77256ae 2636 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
bogdanm 20:4263a77256ae 2637 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
bogdanm 20:4263a77256ae 2638 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
bogdanm 20:4263a77256ae 2639 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
bogdanm 20:4263a77256ae 2640 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
bogdanm 20:4263a77256ae 2641 #define SIM_SOPT2_TPMSRC_SHIFT 24
bogdanm 20:4263a77256ae 2642 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
bogdanm 20:4263a77256ae 2643 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
bogdanm 20:4263a77256ae 2644 #define SIM_SOPT2_UART0SRC_SHIFT 26
bogdanm 20:4263a77256ae 2645 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
bogdanm 20:4263a77256ae 2646 /* SOPT4 Bit Fields */
bogdanm 20:4263a77256ae 2647 #define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
bogdanm 20:4263a77256ae 2648 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
bogdanm 20:4263a77256ae 2649 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
bogdanm 20:4263a77256ae 2650 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
bogdanm 20:4263a77256ae 2651 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
bogdanm 20:4263a77256ae 2652 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
bogdanm 20:4263a77256ae 2653 /* SOPT5 Bit Fields */
bogdanm 20:4263a77256ae 2654 #define SIM_SOPT5_UART0TXSRC_MASK 0x1u
bogdanm 20:4263a77256ae 2655 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
bogdanm 20:4263a77256ae 2656 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
bogdanm 20:4263a77256ae 2657 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
bogdanm 20:4263a77256ae 2658 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
bogdanm 20:4263a77256ae 2659 #define SIM_SOPT5_UART0ODE_SHIFT 16
bogdanm 20:4263a77256ae 2660 /* SOPT7 Bit Fields */
bogdanm 20:4263a77256ae 2661 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
bogdanm 20:4263a77256ae 2662 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
bogdanm 20:4263a77256ae 2663 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
bogdanm 20:4263a77256ae 2664 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
bogdanm 20:4263a77256ae 2665 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
bogdanm 20:4263a77256ae 2666 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
bogdanm 20:4263a77256ae 2667 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
bogdanm 20:4263a77256ae 2668 /* SDID Bit Fields */
bogdanm 20:4263a77256ae 2669 #define SIM_SDID_PINID_MASK 0xFu
bogdanm 20:4263a77256ae 2670 #define SIM_SDID_PINID_SHIFT 0
bogdanm 20:4263a77256ae 2671 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
bogdanm 20:4263a77256ae 2672 #define SIM_SDID_DIEID_MASK 0xF80u
bogdanm 20:4263a77256ae 2673 #define SIM_SDID_DIEID_SHIFT 7
bogdanm 20:4263a77256ae 2674 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
bogdanm 20:4263a77256ae 2675 #define SIM_SDID_REVID_MASK 0xF000u
bogdanm 20:4263a77256ae 2676 #define SIM_SDID_REVID_SHIFT 12
bogdanm 20:4263a77256ae 2677 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
bogdanm 20:4263a77256ae 2678 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
bogdanm 20:4263a77256ae 2679 #define SIM_SDID_SRAMSIZE_SHIFT 16
bogdanm 20:4263a77256ae 2680 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
bogdanm 20:4263a77256ae 2681 #define SIM_SDID_SERIESID_MASK 0xF00000u
bogdanm 20:4263a77256ae 2682 #define SIM_SDID_SERIESID_SHIFT 20
bogdanm 20:4263a77256ae 2683 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
bogdanm 20:4263a77256ae 2684 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
bogdanm 20:4263a77256ae 2685 #define SIM_SDID_SUBFAMID_SHIFT 24
bogdanm 20:4263a77256ae 2686 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
bogdanm 20:4263a77256ae 2687 #define SIM_SDID_FAMID_MASK 0xF0000000u
bogdanm 20:4263a77256ae 2688 #define SIM_SDID_FAMID_SHIFT 28
bogdanm 20:4263a77256ae 2689 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
bogdanm 20:4263a77256ae 2690 /* SCGC4 Bit Fields */
bogdanm 20:4263a77256ae 2691 #define SIM_SCGC4_I2C0_MASK 0x40u
bogdanm 20:4263a77256ae 2692 #define SIM_SCGC4_I2C0_SHIFT 6
bogdanm 20:4263a77256ae 2693 #define SIM_SCGC4_UART0_MASK 0x400u
bogdanm 20:4263a77256ae 2694 #define SIM_SCGC4_UART0_SHIFT 10
bogdanm 20:4263a77256ae 2695 #define SIM_SCGC4_CMP_MASK 0x80000u
bogdanm 20:4263a77256ae 2696 #define SIM_SCGC4_CMP_SHIFT 19
bogdanm 20:4263a77256ae 2697 #define SIM_SCGC4_SPI0_MASK 0x400000u
bogdanm 20:4263a77256ae 2698 #define SIM_SCGC4_SPI0_SHIFT 22
bogdanm 20:4263a77256ae 2699 /* SCGC5 Bit Fields */
bogdanm 20:4263a77256ae 2700 #define SIM_SCGC5_LPTMR_MASK 0x1u
bogdanm 20:4263a77256ae 2701 #define SIM_SCGC5_LPTMR_SHIFT 0
bogdanm 20:4263a77256ae 2702 #define SIM_SCGC5_TSI_MASK 0x20u
bogdanm 20:4263a77256ae 2703 #define SIM_SCGC5_TSI_SHIFT 5
bogdanm 20:4263a77256ae 2704 #define SIM_SCGC5_PORTA_MASK 0x200u
bogdanm 20:4263a77256ae 2705 #define SIM_SCGC5_PORTA_SHIFT 9
bogdanm 20:4263a77256ae 2706 #define SIM_SCGC5_PORTB_MASK 0x400u
bogdanm 20:4263a77256ae 2707 #define SIM_SCGC5_PORTB_SHIFT 10
bogdanm 20:4263a77256ae 2708 /* SCGC6 Bit Fields */
bogdanm 20:4263a77256ae 2709 #define SIM_SCGC6_FTF_MASK 0x1u
bogdanm 20:4263a77256ae 2710 #define SIM_SCGC6_FTF_SHIFT 0
bogdanm 20:4263a77256ae 2711 #define SIM_SCGC6_DMAMUX_MASK 0x2u
bogdanm 20:4263a77256ae 2712 #define SIM_SCGC6_DMAMUX_SHIFT 1
bogdanm 20:4263a77256ae 2713 #define SIM_SCGC6_PIT_MASK 0x800000u
bogdanm 20:4263a77256ae 2714 #define SIM_SCGC6_PIT_SHIFT 23
bogdanm 20:4263a77256ae 2715 #define SIM_SCGC6_TPM0_MASK 0x1000000u
bogdanm 20:4263a77256ae 2716 #define SIM_SCGC6_TPM0_SHIFT 24
bogdanm 20:4263a77256ae 2717 #define SIM_SCGC6_TPM1_MASK 0x2000000u
bogdanm 20:4263a77256ae 2718 #define SIM_SCGC6_TPM1_SHIFT 25
bogdanm 20:4263a77256ae 2719 #define SIM_SCGC6_ADC0_MASK 0x8000000u
bogdanm 20:4263a77256ae 2720 #define SIM_SCGC6_ADC0_SHIFT 27
bogdanm 20:4263a77256ae 2721 #define SIM_SCGC6_RTC_MASK 0x20000000u
bogdanm 20:4263a77256ae 2722 #define SIM_SCGC6_RTC_SHIFT 29
bogdanm 20:4263a77256ae 2723 #define SIM_SCGC6_DAC0_MASK 0x80000000u
bogdanm 20:4263a77256ae 2724 #define SIM_SCGC6_DAC0_SHIFT 31
bogdanm 20:4263a77256ae 2725 /* SCGC7 Bit Fields */
bogdanm 20:4263a77256ae 2726 #define SIM_SCGC7_DMA_MASK 0x100u
bogdanm 20:4263a77256ae 2727 #define SIM_SCGC7_DMA_SHIFT 8
bogdanm 20:4263a77256ae 2728 /* CLKDIV1 Bit Fields */
bogdanm 20:4263a77256ae 2729 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
bogdanm 20:4263a77256ae 2730 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
bogdanm 20:4263a77256ae 2731 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
bogdanm 20:4263a77256ae 2732 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
bogdanm 20:4263a77256ae 2733 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
bogdanm 20:4263a77256ae 2734 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
bogdanm 20:4263a77256ae 2735 /* FCFG1 Bit Fields */
bogdanm 20:4263a77256ae 2736 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
bogdanm 20:4263a77256ae 2737 #define SIM_FCFG1_FLASHDIS_SHIFT 0
bogdanm 20:4263a77256ae 2738 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
bogdanm 20:4263a77256ae 2739 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
bogdanm 20:4263a77256ae 2740 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
bogdanm 20:4263a77256ae 2741 #define SIM_FCFG1_PFSIZE_SHIFT 24
bogdanm 20:4263a77256ae 2742 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
bogdanm 20:4263a77256ae 2743 /* FCFG2 Bit Fields */
bogdanm 20:4263a77256ae 2744 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
bogdanm 20:4263a77256ae 2745 #define SIM_FCFG2_MAXADDR0_SHIFT 24
bogdanm 20:4263a77256ae 2746 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
bogdanm 20:4263a77256ae 2747 /* UIDMH Bit Fields */
bogdanm 20:4263a77256ae 2748 #define SIM_UIDMH_UID_MASK 0xFFFFu
bogdanm 20:4263a77256ae 2749 #define SIM_UIDMH_UID_SHIFT 0
bogdanm 20:4263a77256ae 2750 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
bogdanm 20:4263a77256ae 2751 /* UIDML Bit Fields */
bogdanm 20:4263a77256ae 2752 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2753 #define SIM_UIDML_UID_SHIFT 0
bogdanm 20:4263a77256ae 2754 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
bogdanm 20:4263a77256ae 2755 /* UIDL Bit Fields */
bogdanm 20:4263a77256ae 2756 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
bogdanm 20:4263a77256ae 2757 #define SIM_UIDL_UID_SHIFT 0
bogdanm 20:4263a77256ae 2758 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
bogdanm 20:4263a77256ae 2759 /* COPC Bit Fields */
bogdanm 20:4263a77256ae 2760 #define SIM_COPC_COPW_MASK 0x1u
bogdanm 20:4263a77256ae 2761 #define SIM_COPC_COPW_SHIFT 0
bogdanm 20:4263a77256ae 2762 #define SIM_COPC_COPCLKS_MASK 0x2u
bogdanm 20:4263a77256ae 2763 #define SIM_COPC_COPCLKS_SHIFT 1
bogdanm 20:4263a77256ae 2764 #define SIM_COPC_COPT_MASK 0xCu
bogdanm 20:4263a77256ae 2765 #define SIM_COPC_COPT_SHIFT 2
bogdanm 20:4263a77256ae 2766 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
bogdanm 20:4263a77256ae 2767 /* SRVCOP Bit Fields */
bogdanm 20:4263a77256ae 2768 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
bogdanm 20:4263a77256ae 2769 #define SIM_SRVCOP_SRVCOP_SHIFT 0
bogdanm 20:4263a77256ae 2770 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
bogdanm 20:4263a77256ae 2771
bogdanm 20:4263a77256ae 2772 /**
bogdanm 20:4263a77256ae 2773 * @}
bogdanm 20:4263a77256ae 2774 */ /* end of group SIM_Register_Masks */
bogdanm 20:4263a77256ae 2775
bogdanm 20:4263a77256ae 2776
bogdanm 20:4263a77256ae 2777 /* SIM - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 2778 /** Peripheral SIM base address */
bogdanm 20:4263a77256ae 2779 #define SIM_BASE (0x40047000u)
bogdanm 20:4263a77256ae 2780 /** Peripheral SIM base pointer */
bogdanm 20:4263a77256ae 2781 #define SIM ((SIM_Type *)SIM_BASE)
bogdanm 20:4263a77256ae 2782 /** Array initializer of SIM peripheral base pointers */
bogdanm 20:4263a77256ae 2783 #define SIM_BASES { SIM }
bogdanm 20:4263a77256ae 2784
bogdanm 20:4263a77256ae 2785 /**
bogdanm 20:4263a77256ae 2786 * @}
bogdanm 20:4263a77256ae 2787 */ /* end of group SIM_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 2788
bogdanm 20:4263a77256ae 2789
bogdanm 20:4263a77256ae 2790 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2791 -- SMC Peripheral Access Layer
bogdanm 20:4263a77256ae 2792 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2793
bogdanm 20:4263a77256ae 2794 /**
bogdanm 20:4263a77256ae 2795 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
bogdanm 20:4263a77256ae 2796 * @{
bogdanm 20:4263a77256ae 2797 */
bogdanm 20:4263a77256ae 2798
bogdanm 20:4263a77256ae 2799 /** SMC - Register Layout Typedef */
bogdanm 20:4263a77256ae 2800 typedef struct {
bogdanm 20:4263a77256ae 2801 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
bogdanm 20:4263a77256ae 2802 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
bogdanm 20:4263a77256ae 2803 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
bogdanm 20:4263a77256ae 2804 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
bogdanm 20:4263a77256ae 2805 } SMC_Type;
bogdanm 20:4263a77256ae 2806
bogdanm 20:4263a77256ae 2807 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2808 -- SMC Register Masks
bogdanm 20:4263a77256ae 2809 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2810
bogdanm 20:4263a77256ae 2811 /**
bogdanm 20:4263a77256ae 2812 * @addtogroup SMC_Register_Masks SMC Register Masks
bogdanm 20:4263a77256ae 2813 * @{
bogdanm 20:4263a77256ae 2814 */
bogdanm 20:4263a77256ae 2815
bogdanm 20:4263a77256ae 2816 /* PMPROT Bit Fields */
bogdanm 20:4263a77256ae 2817 #define SMC_PMPROT_AVLLS_MASK 0x2u
bogdanm 20:4263a77256ae 2818 #define SMC_PMPROT_AVLLS_SHIFT 1
bogdanm 20:4263a77256ae 2819 #define SMC_PMPROT_ALLS_MASK 0x8u
bogdanm 20:4263a77256ae 2820 #define SMC_PMPROT_ALLS_SHIFT 3
bogdanm 20:4263a77256ae 2821 #define SMC_PMPROT_AVLP_MASK 0x20u
bogdanm 20:4263a77256ae 2822 #define SMC_PMPROT_AVLP_SHIFT 5
bogdanm 20:4263a77256ae 2823 /* PMCTRL Bit Fields */
bogdanm 20:4263a77256ae 2824 #define SMC_PMCTRL_STOPM_MASK 0x7u
bogdanm 20:4263a77256ae 2825 #define SMC_PMCTRL_STOPM_SHIFT 0
bogdanm 20:4263a77256ae 2826 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
bogdanm 20:4263a77256ae 2827 #define SMC_PMCTRL_STOPA_MASK 0x8u
bogdanm 20:4263a77256ae 2828 #define SMC_PMCTRL_STOPA_SHIFT 3
bogdanm 20:4263a77256ae 2829 #define SMC_PMCTRL_RUNM_MASK 0x60u
bogdanm 20:4263a77256ae 2830 #define SMC_PMCTRL_RUNM_SHIFT 5
bogdanm 20:4263a77256ae 2831 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
bogdanm 20:4263a77256ae 2832 /* STOPCTRL Bit Fields */
bogdanm 20:4263a77256ae 2833 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
bogdanm 20:4263a77256ae 2834 #define SMC_STOPCTRL_VLLSM_SHIFT 0
bogdanm 20:4263a77256ae 2835 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
bogdanm 20:4263a77256ae 2836 #define SMC_STOPCTRL_PORPO_MASK 0x20u
bogdanm 20:4263a77256ae 2837 #define SMC_STOPCTRL_PORPO_SHIFT 5
bogdanm 20:4263a77256ae 2838 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
bogdanm 20:4263a77256ae 2839 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
bogdanm 20:4263a77256ae 2840 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
bogdanm 20:4263a77256ae 2841 /* PMSTAT Bit Fields */
bogdanm 20:4263a77256ae 2842 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
bogdanm 20:4263a77256ae 2843 #define SMC_PMSTAT_PMSTAT_SHIFT 0
bogdanm 20:4263a77256ae 2844 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
bogdanm 20:4263a77256ae 2845
bogdanm 20:4263a77256ae 2846 /**
bogdanm 20:4263a77256ae 2847 * @}
bogdanm 20:4263a77256ae 2848 */ /* end of group SMC_Register_Masks */
bogdanm 20:4263a77256ae 2849
bogdanm 20:4263a77256ae 2850
bogdanm 20:4263a77256ae 2851 /* SMC - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 2852 /** Peripheral SMC base address */
bogdanm 20:4263a77256ae 2853 #define SMC_BASE (0x4007E000u)
bogdanm 20:4263a77256ae 2854 /** Peripheral SMC base pointer */
bogdanm 20:4263a77256ae 2855 #define SMC ((SMC_Type *)SMC_BASE)
bogdanm 20:4263a77256ae 2856 /** Array initializer of SMC peripheral base pointers */
bogdanm 20:4263a77256ae 2857 #define SMC_BASES { SMC }
bogdanm 20:4263a77256ae 2858
bogdanm 20:4263a77256ae 2859 /**
bogdanm 20:4263a77256ae 2860 * @}
bogdanm 20:4263a77256ae 2861 */ /* end of group SMC_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 2862
bogdanm 20:4263a77256ae 2863
bogdanm 20:4263a77256ae 2864 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2865 -- SPI Peripheral Access Layer
bogdanm 20:4263a77256ae 2866 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2867
bogdanm 20:4263a77256ae 2868 /**
bogdanm 20:4263a77256ae 2869 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
bogdanm 20:4263a77256ae 2870 * @{
bogdanm 20:4263a77256ae 2871 */
bogdanm 20:4263a77256ae 2872
bogdanm 20:4263a77256ae 2873 /** SPI - Register Layout Typedef */
bogdanm 20:4263a77256ae 2874 typedef struct {
bogdanm 20:4263a77256ae 2875 __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
bogdanm 20:4263a77256ae 2876 __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
bogdanm 20:4263a77256ae 2877 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
bogdanm 20:4263a77256ae 2878 __I uint8_t S; /**< SPI status register, offset: 0x3 */
bogdanm 20:4263a77256ae 2879 uint8_t RESERVED_0[1];
bogdanm 20:4263a77256ae 2880 __IO uint8_t D; /**< SPI data register, offset: 0x5 */
bogdanm 20:4263a77256ae 2881 uint8_t RESERVED_1[1];
bogdanm 20:4263a77256ae 2882 __IO uint8_t M; /**< SPI match register, offset: 0x7 */
bogdanm 20:4263a77256ae 2883 } SPI_Type;
bogdanm 20:4263a77256ae 2884
bogdanm 20:4263a77256ae 2885 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2886 -- SPI Register Masks
bogdanm 20:4263a77256ae 2887 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2888
bogdanm 20:4263a77256ae 2889 /**
bogdanm 20:4263a77256ae 2890 * @addtogroup SPI_Register_Masks SPI Register Masks
bogdanm 20:4263a77256ae 2891 * @{
bogdanm 20:4263a77256ae 2892 */
bogdanm 20:4263a77256ae 2893
bogdanm 20:4263a77256ae 2894 /* C1 Bit Fields */
bogdanm 20:4263a77256ae 2895 #define SPI_C1_LSBFE_MASK 0x1u
bogdanm 20:4263a77256ae 2896 #define SPI_C1_LSBFE_SHIFT 0
bogdanm 20:4263a77256ae 2897 #define SPI_C1_SSOE_MASK 0x2u
bogdanm 20:4263a77256ae 2898 #define SPI_C1_SSOE_SHIFT 1
bogdanm 20:4263a77256ae 2899 #define SPI_C1_CPHA_MASK 0x4u
bogdanm 20:4263a77256ae 2900 #define SPI_C1_CPHA_SHIFT 2
bogdanm 20:4263a77256ae 2901 #define SPI_C1_CPOL_MASK 0x8u
bogdanm 20:4263a77256ae 2902 #define SPI_C1_CPOL_SHIFT 3
bogdanm 20:4263a77256ae 2903 #define SPI_C1_MSTR_MASK 0x10u
bogdanm 20:4263a77256ae 2904 #define SPI_C1_MSTR_SHIFT 4
bogdanm 20:4263a77256ae 2905 #define SPI_C1_SPTIE_MASK 0x20u
bogdanm 20:4263a77256ae 2906 #define SPI_C1_SPTIE_SHIFT 5
bogdanm 20:4263a77256ae 2907 #define SPI_C1_SPE_MASK 0x40u
bogdanm 20:4263a77256ae 2908 #define SPI_C1_SPE_SHIFT 6
bogdanm 20:4263a77256ae 2909 #define SPI_C1_SPIE_MASK 0x80u
bogdanm 20:4263a77256ae 2910 #define SPI_C1_SPIE_SHIFT 7
bogdanm 20:4263a77256ae 2911 /* C2 Bit Fields */
bogdanm 20:4263a77256ae 2912 #define SPI_C2_SPC0_MASK 0x1u
bogdanm 20:4263a77256ae 2913 #define SPI_C2_SPC0_SHIFT 0
bogdanm 20:4263a77256ae 2914 #define SPI_C2_SPISWAI_MASK 0x2u
bogdanm 20:4263a77256ae 2915 #define SPI_C2_SPISWAI_SHIFT 1
bogdanm 20:4263a77256ae 2916 #define SPI_C2_RXDMAE_MASK 0x4u
bogdanm 20:4263a77256ae 2917 #define SPI_C2_RXDMAE_SHIFT 2
bogdanm 20:4263a77256ae 2918 #define SPI_C2_BIDIROE_MASK 0x8u
bogdanm 20:4263a77256ae 2919 #define SPI_C2_BIDIROE_SHIFT 3
bogdanm 20:4263a77256ae 2920 #define SPI_C2_MODFEN_MASK 0x10u
bogdanm 20:4263a77256ae 2921 #define SPI_C2_MODFEN_SHIFT 4
bogdanm 20:4263a77256ae 2922 #define SPI_C2_TXDMAE_MASK 0x20u
bogdanm 20:4263a77256ae 2923 #define SPI_C2_TXDMAE_SHIFT 5
bogdanm 20:4263a77256ae 2924 #define SPI_C2_SPMIE_MASK 0x80u
bogdanm 20:4263a77256ae 2925 #define SPI_C2_SPMIE_SHIFT 7
bogdanm 20:4263a77256ae 2926 /* BR Bit Fields */
bogdanm 20:4263a77256ae 2927 #define SPI_BR_SPR_MASK 0xFu
bogdanm 20:4263a77256ae 2928 #define SPI_BR_SPR_SHIFT 0
bogdanm 20:4263a77256ae 2929 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
bogdanm 20:4263a77256ae 2930 #define SPI_BR_SPPR_MASK 0x70u
bogdanm 20:4263a77256ae 2931 #define SPI_BR_SPPR_SHIFT 4
bogdanm 20:4263a77256ae 2932 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
bogdanm 20:4263a77256ae 2933 /* S Bit Fields */
bogdanm 20:4263a77256ae 2934 #define SPI_S_MODF_MASK 0x10u
bogdanm 20:4263a77256ae 2935 #define SPI_S_MODF_SHIFT 4
bogdanm 20:4263a77256ae 2936 #define SPI_S_SPTEF_MASK 0x20u
bogdanm 20:4263a77256ae 2937 #define SPI_S_SPTEF_SHIFT 5
bogdanm 20:4263a77256ae 2938 #define SPI_S_SPMF_MASK 0x40u
bogdanm 20:4263a77256ae 2939 #define SPI_S_SPMF_SHIFT 6
bogdanm 20:4263a77256ae 2940 #define SPI_S_SPRF_MASK 0x80u
bogdanm 20:4263a77256ae 2941 #define SPI_S_SPRF_SHIFT 7
bogdanm 20:4263a77256ae 2942 /* D Bit Fields */
bogdanm 20:4263a77256ae 2943 #define SPI_D_Bits_MASK 0xFFu
bogdanm 20:4263a77256ae 2944 #define SPI_D_Bits_SHIFT 0
bogdanm 20:4263a77256ae 2945 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
bogdanm 20:4263a77256ae 2946 /* M Bit Fields */
bogdanm 20:4263a77256ae 2947 #define SPI_M_Bits_MASK 0xFFu
bogdanm 20:4263a77256ae 2948 #define SPI_M_Bits_SHIFT 0
bogdanm 20:4263a77256ae 2949 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
bogdanm 20:4263a77256ae 2950
bogdanm 20:4263a77256ae 2951 /**
bogdanm 20:4263a77256ae 2952 * @}
bogdanm 20:4263a77256ae 2953 */ /* end of group SPI_Register_Masks */
bogdanm 20:4263a77256ae 2954
bogdanm 20:4263a77256ae 2955
bogdanm 20:4263a77256ae 2956 /* SPI - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 2957 /** Peripheral SPI0 base address */
bogdanm 20:4263a77256ae 2958 #define SPI0_BASE (0x40076000u)
bogdanm 20:4263a77256ae 2959 /** Peripheral SPI0 base pointer */
bogdanm 20:4263a77256ae 2960 #define SPI0 ((SPI_Type *)SPI0_BASE)
bogdanm 20:4263a77256ae 2961 /** Array initializer of SPI peripheral base pointers */
bogdanm 20:4263a77256ae 2962 #define SPI_BASES { SPI0 }
bogdanm 20:4263a77256ae 2963
bogdanm 20:4263a77256ae 2964 /**
bogdanm 20:4263a77256ae 2965 * @}
bogdanm 20:4263a77256ae 2966 */ /* end of group SPI_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 2967
bogdanm 20:4263a77256ae 2968
bogdanm 20:4263a77256ae 2969 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2970 -- TPM Peripheral Access Layer
bogdanm 20:4263a77256ae 2971 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2972
bogdanm 20:4263a77256ae 2973 /**
bogdanm 20:4263a77256ae 2974 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
bogdanm 20:4263a77256ae 2975 * @{
bogdanm 20:4263a77256ae 2976 */
bogdanm 20:4263a77256ae 2977
bogdanm 20:4263a77256ae 2978 /** TPM - Register Layout Typedef */
bogdanm 20:4263a77256ae 2979 typedef struct {
bogdanm 20:4263a77256ae 2980 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
bogdanm 20:4263a77256ae 2981 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
bogdanm 20:4263a77256ae 2982 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
bogdanm 20:4263a77256ae 2983 struct { /* offset: 0xC, array step: 0x8 */
bogdanm 20:4263a77256ae 2984 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
bogdanm 20:4263a77256ae 2985 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
bogdanm 20:4263a77256ae 2986 } CONTROLS[6];
bogdanm 20:4263a77256ae 2987 uint8_t RESERVED_0[20];
bogdanm 20:4263a77256ae 2988 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
bogdanm 20:4263a77256ae 2989 uint8_t RESERVED_1[48];
bogdanm 20:4263a77256ae 2990 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
bogdanm 20:4263a77256ae 2991 } TPM_Type;
bogdanm 20:4263a77256ae 2992
bogdanm 20:4263a77256ae 2993 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 2994 -- TPM Register Masks
bogdanm 20:4263a77256ae 2995 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 2996
bogdanm 20:4263a77256ae 2997 /**
bogdanm 20:4263a77256ae 2998 * @addtogroup TPM_Register_Masks TPM Register Masks
bogdanm 20:4263a77256ae 2999 * @{
bogdanm 20:4263a77256ae 3000 */
bogdanm 20:4263a77256ae 3001
bogdanm 20:4263a77256ae 3002 /* SC Bit Fields */
bogdanm 20:4263a77256ae 3003 #define TPM_SC_PS_MASK 0x7u
bogdanm 20:4263a77256ae 3004 #define TPM_SC_PS_SHIFT 0
bogdanm 20:4263a77256ae 3005 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
bogdanm 20:4263a77256ae 3006 #define TPM_SC_CMOD_MASK 0x18u
bogdanm 20:4263a77256ae 3007 #define TPM_SC_CMOD_SHIFT 3
bogdanm 20:4263a77256ae 3008 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
bogdanm 20:4263a77256ae 3009 #define TPM_SC_CPWMS_MASK 0x20u
bogdanm 20:4263a77256ae 3010 #define TPM_SC_CPWMS_SHIFT 5
bogdanm 20:4263a77256ae 3011 #define TPM_SC_TOIE_MASK 0x40u
bogdanm 20:4263a77256ae 3012 #define TPM_SC_TOIE_SHIFT 6
bogdanm 20:4263a77256ae 3013 #define TPM_SC_TOF_MASK 0x80u
bogdanm 20:4263a77256ae 3014 #define TPM_SC_TOF_SHIFT 7
bogdanm 20:4263a77256ae 3015 #define TPM_SC_DMA_MASK 0x100u
bogdanm 20:4263a77256ae 3016 #define TPM_SC_DMA_SHIFT 8
bogdanm 20:4263a77256ae 3017 /* CNT Bit Fields */
bogdanm 20:4263a77256ae 3018 #define TPM_CNT_COUNT_MASK 0xFFFFu
bogdanm 20:4263a77256ae 3019 #define TPM_CNT_COUNT_SHIFT 0
bogdanm 20:4263a77256ae 3020 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
bogdanm 20:4263a77256ae 3021 /* MOD Bit Fields */
bogdanm 20:4263a77256ae 3022 #define TPM_MOD_MOD_MASK 0xFFFFu
bogdanm 20:4263a77256ae 3023 #define TPM_MOD_MOD_SHIFT 0
bogdanm 20:4263a77256ae 3024 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
bogdanm 20:4263a77256ae 3025 /* CnSC Bit Fields */
bogdanm 20:4263a77256ae 3026 #define TPM_CnSC_DMA_MASK 0x1u
bogdanm 20:4263a77256ae 3027 #define TPM_CnSC_DMA_SHIFT 0
bogdanm 20:4263a77256ae 3028 #define TPM_CnSC_ELSA_MASK 0x4u
bogdanm 20:4263a77256ae 3029 #define TPM_CnSC_ELSA_SHIFT 2
bogdanm 20:4263a77256ae 3030 #define TPM_CnSC_ELSB_MASK 0x8u
bogdanm 20:4263a77256ae 3031 #define TPM_CnSC_ELSB_SHIFT 3
bogdanm 20:4263a77256ae 3032 #define TPM_CnSC_MSA_MASK 0x10u
bogdanm 20:4263a77256ae 3033 #define TPM_CnSC_MSA_SHIFT 4
bogdanm 20:4263a77256ae 3034 #define TPM_CnSC_MSB_MASK 0x20u
bogdanm 20:4263a77256ae 3035 #define TPM_CnSC_MSB_SHIFT 5
bogdanm 20:4263a77256ae 3036 #define TPM_CnSC_CHIE_MASK 0x40u
bogdanm 20:4263a77256ae 3037 #define TPM_CnSC_CHIE_SHIFT 6
bogdanm 20:4263a77256ae 3038 #define TPM_CnSC_CHF_MASK 0x80u
bogdanm 20:4263a77256ae 3039 #define TPM_CnSC_CHF_SHIFT 7
bogdanm 20:4263a77256ae 3040 /* CnV Bit Fields */
bogdanm 20:4263a77256ae 3041 #define TPM_CnV_VAL_MASK 0xFFFFu
bogdanm 20:4263a77256ae 3042 #define TPM_CnV_VAL_SHIFT 0
bogdanm 20:4263a77256ae 3043 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
bogdanm 20:4263a77256ae 3044 /* STATUS Bit Fields */
bogdanm 20:4263a77256ae 3045 #define TPM_STATUS_CH0F_MASK 0x1u
bogdanm 20:4263a77256ae 3046 #define TPM_STATUS_CH0F_SHIFT 0
bogdanm 20:4263a77256ae 3047 #define TPM_STATUS_CH1F_MASK 0x2u
bogdanm 20:4263a77256ae 3048 #define TPM_STATUS_CH1F_SHIFT 1
bogdanm 20:4263a77256ae 3049 #define TPM_STATUS_CH2F_MASK 0x4u
bogdanm 20:4263a77256ae 3050 #define TPM_STATUS_CH2F_SHIFT 2
bogdanm 20:4263a77256ae 3051 #define TPM_STATUS_CH3F_MASK 0x8u
bogdanm 20:4263a77256ae 3052 #define TPM_STATUS_CH3F_SHIFT 3
bogdanm 20:4263a77256ae 3053 #define TPM_STATUS_CH4F_MASK 0x10u
bogdanm 20:4263a77256ae 3054 #define TPM_STATUS_CH4F_SHIFT 4
bogdanm 20:4263a77256ae 3055 #define TPM_STATUS_CH5F_MASK 0x20u
bogdanm 20:4263a77256ae 3056 #define TPM_STATUS_CH5F_SHIFT 5
bogdanm 20:4263a77256ae 3057 #define TPM_STATUS_TOF_MASK 0x100u
bogdanm 20:4263a77256ae 3058 #define TPM_STATUS_TOF_SHIFT 8
bogdanm 20:4263a77256ae 3059 /* CONF Bit Fields */
bogdanm 20:4263a77256ae 3060 #define TPM_CONF_DOZEEN_MASK 0x20u
bogdanm 20:4263a77256ae 3061 #define TPM_CONF_DOZEEN_SHIFT 5
bogdanm 20:4263a77256ae 3062 #define TPM_CONF_DBGMODE_MASK 0xC0u
bogdanm 20:4263a77256ae 3063 #define TPM_CONF_DBGMODE_SHIFT 6
bogdanm 20:4263a77256ae 3064 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
bogdanm 20:4263a77256ae 3065 #define TPM_CONF_GTBEEN_MASK 0x200u
bogdanm 20:4263a77256ae 3066 #define TPM_CONF_GTBEEN_SHIFT 9
bogdanm 20:4263a77256ae 3067 #define TPM_CONF_CSOT_MASK 0x10000u
bogdanm 20:4263a77256ae 3068 #define TPM_CONF_CSOT_SHIFT 16
bogdanm 20:4263a77256ae 3069 #define TPM_CONF_CSOO_MASK 0x20000u
bogdanm 20:4263a77256ae 3070 #define TPM_CONF_CSOO_SHIFT 17
bogdanm 20:4263a77256ae 3071 #define TPM_CONF_CROT_MASK 0x40000u
bogdanm 20:4263a77256ae 3072 #define TPM_CONF_CROT_SHIFT 18
bogdanm 20:4263a77256ae 3073 #define TPM_CONF_TRGSEL_MASK 0xF000000u
bogdanm 20:4263a77256ae 3074 #define TPM_CONF_TRGSEL_SHIFT 24
bogdanm 20:4263a77256ae 3075 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
bogdanm 20:4263a77256ae 3076
bogdanm 20:4263a77256ae 3077 /**
bogdanm 20:4263a77256ae 3078 * @}
bogdanm 20:4263a77256ae 3079 */ /* end of group TPM_Register_Masks */
bogdanm 20:4263a77256ae 3080
bogdanm 20:4263a77256ae 3081
bogdanm 20:4263a77256ae 3082 /* TPM - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 3083 /** Peripheral TPM0 base address */
bogdanm 20:4263a77256ae 3084 #define TPM0_BASE (0x40038000u)
bogdanm 20:4263a77256ae 3085 /** Peripheral TPM0 base pointer */
bogdanm 20:4263a77256ae 3086 #define TPM0 ((TPM_Type *)TPM0_BASE)
bogdanm 20:4263a77256ae 3087 /** Peripheral TPM1 base address */
bogdanm 20:4263a77256ae 3088 #define TPM1_BASE (0x40039000u)
bogdanm 20:4263a77256ae 3089 /** Peripheral TPM1 base pointer */
bogdanm 20:4263a77256ae 3090 #define TPM1 ((TPM_Type *)TPM1_BASE)
bogdanm 20:4263a77256ae 3091 /** Array initializer of TPM peripheral base pointers */
bogdanm 20:4263a77256ae 3092 #define TPM_BASES { TPM0, TPM1 }
bogdanm 20:4263a77256ae 3093
bogdanm 20:4263a77256ae 3094 /**
bogdanm 20:4263a77256ae 3095 * @}
bogdanm 20:4263a77256ae 3096 */ /* end of group TPM_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 3097
bogdanm 20:4263a77256ae 3098
bogdanm 20:4263a77256ae 3099 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 3100 -- TSI Peripheral Access Layer
bogdanm 20:4263a77256ae 3101 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 3102
bogdanm 20:4263a77256ae 3103 /**
bogdanm 20:4263a77256ae 3104 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
bogdanm 20:4263a77256ae 3105 * @{
bogdanm 20:4263a77256ae 3106 */
bogdanm 20:4263a77256ae 3107
bogdanm 20:4263a77256ae 3108 /** TSI - Register Layout Typedef */
bogdanm 20:4263a77256ae 3109 typedef struct {
bogdanm 20:4263a77256ae 3110 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
bogdanm 20:4263a77256ae 3111 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
bogdanm 20:4263a77256ae 3112 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
bogdanm 20:4263a77256ae 3113 } TSI_Type;
bogdanm 20:4263a77256ae 3114
bogdanm 20:4263a77256ae 3115 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 3116 -- TSI Register Masks
bogdanm 20:4263a77256ae 3117 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 3118
bogdanm 20:4263a77256ae 3119 /**
bogdanm 20:4263a77256ae 3120 * @addtogroup TSI_Register_Masks TSI Register Masks
bogdanm 20:4263a77256ae 3121 * @{
bogdanm 20:4263a77256ae 3122 */
bogdanm 20:4263a77256ae 3123
bogdanm 20:4263a77256ae 3124 /* GENCS Bit Fields */
bogdanm 20:4263a77256ae 3125 #define TSI_GENCS_CURSW_MASK 0x2u
bogdanm 20:4263a77256ae 3126 #define TSI_GENCS_CURSW_SHIFT 1
bogdanm 20:4263a77256ae 3127 #define TSI_GENCS_EOSF_MASK 0x4u
bogdanm 20:4263a77256ae 3128 #define TSI_GENCS_EOSF_SHIFT 2
bogdanm 20:4263a77256ae 3129 #define TSI_GENCS_SCNIP_MASK 0x8u
bogdanm 20:4263a77256ae 3130 #define TSI_GENCS_SCNIP_SHIFT 3
bogdanm 20:4263a77256ae 3131 #define TSI_GENCS_STM_MASK 0x10u
bogdanm 20:4263a77256ae 3132 #define TSI_GENCS_STM_SHIFT 4
bogdanm 20:4263a77256ae 3133 #define TSI_GENCS_STPE_MASK 0x20u
bogdanm 20:4263a77256ae 3134 #define TSI_GENCS_STPE_SHIFT 5
bogdanm 20:4263a77256ae 3135 #define TSI_GENCS_TSIIEN_MASK 0x40u
bogdanm 20:4263a77256ae 3136 #define TSI_GENCS_TSIIEN_SHIFT 6
bogdanm 20:4263a77256ae 3137 #define TSI_GENCS_TSIEN_MASK 0x80u
bogdanm 20:4263a77256ae 3138 #define TSI_GENCS_TSIEN_SHIFT 7
bogdanm 20:4263a77256ae 3139 #define TSI_GENCS_NSCN_MASK 0x1F00u
bogdanm 20:4263a77256ae 3140 #define TSI_GENCS_NSCN_SHIFT 8
bogdanm 20:4263a77256ae 3141 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
bogdanm 20:4263a77256ae 3142 #define TSI_GENCS_PS_MASK 0xE000u
bogdanm 20:4263a77256ae 3143 #define TSI_GENCS_PS_SHIFT 13
bogdanm 20:4263a77256ae 3144 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
bogdanm 20:4263a77256ae 3145 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
bogdanm 20:4263a77256ae 3146 #define TSI_GENCS_EXTCHRG_SHIFT 16
bogdanm 20:4263a77256ae 3147 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
bogdanm 20:4263a77256ae 3148 #define TSI_GENCS_DVOLT_MASK 0x180000u
bogdanm 20:4263a77256ae 3149 #define TSI_GENCS_DVOLT_SHIFT 19
bogdanm 20:4263a77256ae 3150 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
bogdanm 20:4263a77256ae 3151 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
bogdanm 20:4263a77256ae 3152 #define TSI_GENCS_REFCHRG_SHIFT 21
bogdanm 20:4263a77256ae 3153 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
bogdanm 20:4263a77256ae 3154 #define TSI_GENCS_MODE_MASK 0xF000000u
bogdanm 20:4263a77256ae 3155 #define TSI_GENCS_MODE_SHIFT 24
bogdanm 20:4263a77256ae 3156 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
bogdanm 20:4263a77256ae 3157 #define TSI_GENCS_ESOR_MASK 0x10000000u
bogdanm 20:4263a77256ae 3158 #define TSI_GENCS_ESOR_SHIFT 28
bogdanm 20:4263a77256ae 3159 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
bogdanm 20:4263a77256ae 3160 #define TSI_GENCS_OUTRGF_SHIFT 31
bogdanm 20:4263a77256ae 3161 /* DATA Bit Fields */
bogdanm 20:4263a77256ae 3162 #define TSI_DATA_TSICNT_MASK 0xFFFFu
bogdanm 20:4263a77256ae 3163 #define TSI_DATA_TSICNT_SHIFT 0
bogdanm 20:4263a77256ae 3164 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
bogdanm 20:4263a77256ae 3165 #define TSI_DATA_SWTS_MASK 0x400000u
bogdanm 20:4263a77256ae 3166 #define TSI_DATA_SWTS_SHIFT 22
bogdanm 20:4263a77256ae 3167 #define TSI_DATA_DMAEN_MASK 0x800000u
bogdanm 20:4263a77256ae 3168 #define TSI_DATA_DMAEN_SHIFT 23
bogdanm 20:4263a77256ae 3169 #define TSI_DATA_TSICH_MASK 0xF0000000u
bogdanm 20:4263a77256ae 3170 #define TSI_DATA_TSICH_SHIFT 28
bogdanm 20:4263a77256ae 3171 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
bogdanm 20:4263a77256ae 3172 /* TSHD Bit Fields */
bogdanm 20:4263a77256ae 3173 #define TSI_TSHD_THRESL_MASK 0xFFFFu
bogdanm 20:4263a77256ae 3174 #define TSI_TSHD_THRESL_SHIFT 0
bogdanm 20:4263a77256ae 3175 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
bogdanm 20:4263a77256ae 3176 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
bogdanm 20:4263a77256ae 3177 #define TSI_TSHD_THRESH_SHIFT 16
bogdanm 20:4263a77256ae 3178 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
bogdanm 20:4263a77256ae 3179
bogdanm 20:4263a77256ae 3180 /**
bogdanm 20:4263a77256ae 3181 * @}
bogdanm 20:4263a77256ae 3182 */ /* end of group TSI_Register_Masks */
bogdanm 20:4263a77256ae 3183
bogdanm 20:4263a77256ae 3184
bogdanm 20:4263a77256ae 3185 /* TSI - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 3186 /** Peripheral TSI0 base address */
bogdanm 20:4263a77256ae 3187 #define TSI0_BASE (0x40045000u)
bogdanm 20:4263a77256ae 3188 /** Peripheral TSI0 base pointer */
bogdanm 20:4263a77256ae 3189 #define TSI0 ((TSI_Type *)TSI0_BASE)
bogdanm 20:4263a77256ae 3190 /** Array initializer of TSI peripheral base pointers */
bogdanm 20:4263a77256ae 3191 #define TSI_BASES { TSI0 }
bogdanm 20:4263a77256ae 3192
bogdanm 20:4263a77256ae 3193 /**
bogdanm 20:4263a77256ae 3194 * @}
bogdanm 20:4263a77256ae 3195 */ /* end of group TSI_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 3196
bogdanm 20:4263a77256ae 3197
bogdanm 20:4263a77256ae 3198 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 3199 -- UART0 Peripheral Access Layer
bogdanm 20:4263a77256ae 3200 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 3201
bogdanm 20:4263a77256ae 3202 /**
bogdanm 20:4263a77256ae 3203 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
bogdanm 20:4263a77256ae 3204 * @{
bogdanm 20:4263a77256ae 3205 */
bogdanm 20:4263a77256ae 3206
bogdanm 20:4263a77256ae 3207 /** UART0 - Register Layout Typedef */
bogdanm 20:4263a77256ae 3208 typedef struct {
bogdanm 20:4263a77256ae 3209 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
bogdanm 20:4263a77256ae 3210 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
bogdanm 20:4263a77256ae 3211 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
bogdanm 20:4263a77256ae 3212 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
bogdanm 20:4263a77256ae 3213 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
bogdanm 20:4263a77256ae 3214 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
bogdanm 20:4263a77256ae 3215 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
bogdanm 20:4263a77256ae 3216 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
bogdanm 20:4263a77256ae 3217 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
bogdanm 20:4263a77256ae 3218 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
bogdanm 20:4263a77256ae 3219 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
bogdanm 20:4263a77256ae 3220 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
bogdanm 20:4263a77256ae 3221 } UART0_Type;
bogdanm 20:4263a77256ae 3222
bogdanm 20:4263a77256ae 3223 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 3224 -- UART0 Register Masks
bogdanm 20:4263a77256ae 3225 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 3226
bogdanm 20:4263a77256ae 3227 /**
bogdanm 20:4263a77256ae 3228 * @addtogroup UART0_Register_Masks UART0 Register Masks
bogdanm 20:4263a77256ae 3229 * @{
bogdanm 20:4263a77256ae 3230 */
bogdanm 20:4263a77256ae 3231
bogdanm 20:4263a77256ae 3232 /* BDH Bit Fields */
bogdanm 20:4263a77256ae 3233 #define UART0_BDH_SBR_MASK 0x1Fu
bogdanm 20:4263a77256ae 3234 #define UART0_BDH_SBR_SHIFT 0
bogdanm 20:4263a77256ae 3235 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
bogdanm 20:4263a77256ae 3236 #define UART0_BDH_SBNS_MASK 0x20u
bogdanm 20:4263a77256ae 3237 #define UART0_BDH_SBNS_SHIFT 5
bogdanm 20:4263a77256ae 3238 #define UART0_BDH_RXEDGIE_MASK 0x40u
bogdanm 20:4263a77256ae 3239 #define UART0_BDH_RXEDGIE_SHIFT 6
bogdanm 20:4263a77256ae 3240 #define UART0_BDH_LBKDIE_MASK 0x80u
bogdanm 20:4263a77256ae 3241 #define UART0_BDH_LBKDIE_SHIFT 7
bogdanm 20:4263a77256ae 3242 /* BDL Bit Fields */
bogdanm 20:4263a77256ae 3243 #define UART0_BDL_SBR_MASK 0xFFu
bogdanm 20:4263a77256ae 3244 #define UART0_BDL_SBR_SHIFT 0
bogdanm 20:4263a77256ae 3245 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
bogdanm 20:4263a77256ae 3246 /* C1 Bit Fields */
bogdanm 20:4263a77256ae 3247 #define UART0_C1_PT_MASK 0x1u
bogdanm 20:4263a77256ae 3248 #define UART0_C1_PT_SHIFT 0
bogdanm 20:4263a77256ae 3249 #define UART0_C1_PE_MASK 0x2u
bogdanm 20:4263a77256ae 3250 #define UART0_C1_PE_SHIFT 1
bogdanm 20:4263a77256ae 3251 #define UART0_C1_ILT_MASK 0x4u
bogdanm 20:4263a77256ae 3252 #define UART0_C1_ILT_SHIFT 2
bogdanm 20:4263a77256ae 3253 #define UART0_C1_WAKE_MASK 0x8u
bogdanm 20:4263a77256ae 3254 #define UART0_C1_WAKE_SHIFT 3
bogdanm 20:4263a77256ae 3255 #define UART0_C1_M_MASK 0x10u
bogdanm 20:4263a77256ae 3256 #define UART0_C1_M_SHIFT 4
bogdanm 20:4263a77256ae 3257 #define UART0_C1_RSRC_MASK 0x20u
bogdanm 20:4263a77256ae 3258 #define UART0_C1_RSRC_SHIFT 5
bogdanm 20:4263a77256ae 3259 #define UART0_C1_DOZEEN_MASK 0x40u
bogdanm 20:4263a77256ae 3260 #define UART0_C1_DOZEEN_SHIFT 6
bogdanm 20:4263a77256ae 3261 #define UART0_C1_LOOPS_MASK 0x80u
bogdanm 20:4263a77256ae 3262 #define UART0_C1_LOOPS_SHIFT 7
bogdanm 20:4263a77256ae 3263 /* C2 Bit Fields */
bogdanm 20:4263a77256ae 3264 #define UART0_C2_SBK_MASK 0x1u
bogdanm 20:4263a77256ae 3265 #define UART0_C2_SBK_SHIFT 0
bogdanm 20:4263a77256ae 3266 #define UART0_C2_RWU_MASK 0x2u
bogdanm 20:4263a77256ae 3267 #define UART0_C2_RWU_SHIFT 1
bogdanm 20:4263a77256ae 3268 #define UART0_C2_RE_MASK 0x4u
bogdanm 20:4263a77256ae 3269 #define UART0_C2_RE_SHIFT 2
bogdanm 20:4263a77256ae 3270 #define UART0_C2_TE_MASK 0x8u
bogdanm 20:4263a77256ae 3271 #define UART0_C2_TE_SHIFT 3
bogdanm 20:4263a77256ae 3272 #define UART0_C2_ILIE_MASK 0x10u
bogdanm 20:4263a77256ae 3273 #define UART0_C2_ILIE_SHIFT 4
bogdanm 20:4263a77256ae 3274 #define UART0_C2_RIE_MASK 0x20u
bogdanm 20:4263a77256ae 3275 #define UART0_C2_RIE_SHIFT 5
bogdanm 20:4263a77256ae 3276 #define UART0_C2_TCIE_MASK 0x40u
bogdanm 20:4263a77256ae 3277 #define UART0_C2_TCIE_SHIFT 6
bogdanm 20:4263a77256ae 3278 #define UART0_C2_TIE_MASK 0x80u
bogdanm 20:4263a77256ae 3279 #define UART0_C2_TIE_SHIFT 7
bogdanm 20:4263a77256ae 3280 /* S1 Bit Fields */
bogdanm 20:4263a77256ae 3281 #define UART0_S1_PF_MASK 0x1u
bogdanm 20:4263a77256ae 3282 #define UART0_S1_PF_SHIFT 0
bogdanm 20:4263a77256ae 3283 #define UART0_S1_FE_MASK 0x2u
bogdanm 20:4263a77256ae 3284 #define UART0_S1_FE_SHIFT 1
bogdanm 20:4263a77256ae 3285 #define UART0_S1_NF_MASK 0x4u
bogdanm 20:4263a77256ae 3286 #define UART0_S1_NF_SHIFT 2
bogdanm 20:4263a77256ae 3287 #define UART0_S1_OR_MASK 0x8u
bogdanm 20:4263a77256ae 3288 #define UART0_S1_OR_SHIFT 3
bogdanm 20:4263a77256ae 3289 #define UART0_S1_IDLE_MASK 0x10u
bogdanm 20:4263a77256ae 3290 #define UART0_S1_IDLE_SHIFT 4
bogdanm 20:4263a77256ae 3291 #define UART0_S1_RDRF_MASK 0x20u
bogdanm 20:4263a77256ae 3292 #define UART0_S1_RDRF_SHIFT 5
bogdanm 20:4263a77256ae 3293 #define UART0_S1_TC_MASK 0x40u
bogdanm 20:4263a77256ae 3294 #define UART0_S1_TC_SHIFT 6
bogdanm 20:4263a77256ae 3295 #define UART0_S1_TDRE_MASK 0x80u
bogdanm 20:4263a77256ae 3296 #define UART0_S1_TDRE_SHIFT 7
bogdanm 20:4263a77256ae 3297 /* S2 Bit Fields */
bogdanm 20:4263a77256ae 3298 #define UART0_S2_RAF_MASK 0x1u
bogdanm 20:4263a77256ae 3299 #define UART0_S2_RAF_SHIFT 0
bogdanm 20:4263a77256ae 3300 #define UART0_S2_LBKDE_MASK 0x2u
bogdanm 20:4263a77256ae 3301 #define UART0_S2_LBKDE_SHIFT 1
bogdanm 20:4263a77256ae 3302 #define UART0_S2_BRK13_MASK 0x4u
bogdanm 20:4263a77256ae 3303 #define UART0_S2_BRK13_SHIFT 2
bogdanm 20:4263a77256ae 3304 #define UART0_S2_RWUID_MASK 0x8u
bogdanm 20:4263a77256ae 3305 #define UART0_S2_RWUID_SHIFT 3
bogdanm 20:4263a77256ae 3306 #define UART0_S2_RXINV_MASK 0x10u
bogdanm 20:4263a77256ae 3307 #define UART0_S2_RXINV_SHIFT 4
bogdanm 20:4263a77256ae 3308 #define UART0_S2_MSBF_MASK 0x20u
bogdanm 20:4263a77256ae 3309 #define UART0_S2_MSBF_SHIFT 5
bogdanm 20:4263a77256ae 3310 #define UART0_S2_RXEDGIF_MASK 0x40u
bogdanm 20:4263a77256ae 3311 #define UART0_S2_RXEDGIF_SHIFT 6
bogdanm 20:4263a77256ae 3312 #define UART0_S2_LBKDIF_MASK 0x80u
bogdanm 20:4263a77256ae 3313 #define UART0_S2_LBKDIF_SHIFT 7
bogdanm 20:4263a77256ae 3314 /* C3 Bit Fields */
bogdanm 20:4263a77256ae 3315 #define UART0_C3_PEIE_MASK 0x1u
bogdanm 20:4263a77256ae 3316 #define UART0_C3_PEIE_SHIFT 0
bogdanm 20:4263a77256ae 3317 #define UART0_C3_FEIE_MASK 0x2u
bogdanm 20:4263a77256ae 3318 #define UART0_C3_FEIE_SHIFT 1
bogdanm 20:4263a77256ae 3319 #define UART0_C3_NEIE_MASK 0x4u
bogdanm 20:4263a77256ae 3320 #define UART0_C3_NEIE_SHIFT 2
bogdanm 20:4263a77256ae 3321 #define UART0_C3_ORIE_MASK 0x8u
bogdanm 20:4263a77256ae 3322 #define UART0_C3_ORIE_SHIFT 3
bogdanm 20:4263a77256ae 3323 #define UART0_C3_TXINV_MASK 0x10u
bogdanm 20:4263a77256ae 3324 #define UART0_C3_TXINV_SHIFT 4
bogdanm 20:4263a77256ae 3325 #define UART0_C3_TXDIR_MASK 0x20u
bogdanm 20:4263a77256ae 3326 #define UART0_C3_TXDIR_SHIFT 5
bogdanm 20:4263a77256ae 3327 #define UART0_C3_R9T8_MASK 0x40u
bogdanm 20:4263a77256ae 3328 #define UART0_C3_R9T8_SHIFT 6
bogdanm 20:4263a77256ae 3329 #define UART0_C3_R8T9_MASK 0x80u
bogdanm 20:4263a77256ae 3330 #define UART0_C3_R8T9_SHIFT 7
bogdanm 20:4263a77256ae 3331 /* D Bit Fields */
bogdanm 20:4263a77256ae 3332 #define UART0_D_R0T0_MASK 0x1u
bogdanm 20:4263a77256ae 3333 #define UART0_D_R0T0_SHIFT 0
bogdanm 20:4263a77256ae 3334 #define UART0_D_R1T1_MASK 0x2u
bogdanm 20:4263a77256ae 3335 #define UART0_D_R1T1_SHIFT 1
bogdanm 20:4263a77256ae 3336 #define UART0_D_R2T2_MASK 0x4u
bogdanm 20:4263a77256ae 3337 #define UART0_D_R2T2_SHIFT 2
bogdanm 20:4263a77256ae 3338 #define UART0_D_R3T3_MASK 0x8u
bogdanm 20:4263a77256ae 3339 #define UART0_D_R3T3_SHIFT 3
bogdanm 20:4263a77256ae 3340 #define UART0_D_R4T4_MASK 0x10u
bogdanm 20:4263a77256ae 3341 #define UART0_D_R4T4_SHIFT 4
bogdanm 20:4263a77256ae 3342 #define UART0_D_R5T5_MASK 0x20u
bogdanm 20:4263a77256ae 3343 #define UART0_D_R5T5_SHIFT 5
bogdanm 20:4263a77256ae 3344 #define UART0_D_R6T6_MASK 0x40u
bogdanm 20:4263a77256ae 3345 #define UART0_D_R6T6_SHIFT 6
bogdanm 20:4263a77256ae 3346 #define UART0_D_R7T7_MASK 0x80u
bogdanm 20:4263a77256ae 3347 #define UART0_D_R7T7_SHIFT 7
bogdanm 20:4263a77256ae 3348 /* MA1 Bit Fields */
bogdanm 20:4263a77256ae 3349 #define UART0_MA1_MA_MASK 0xFFu
bogdanm 20:4263a77256ae 3350 #define UART0_MA1_MA_SHIFT 0
bogdanm 20:4263a77256ae 3351 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
bogdanm 20:4263a77256ae 3352 /* MA2 Bit Fields */
bogdanm 20:4263a77256ae 3353 #define UART0_MA2_MA_MASK 0xFFu
bogdanm 20:4263a77256ae 3354 #define UART0_MA2_MA_SHIFT 0
bogdanm 20:4263a77256ae 3355 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
bogdanm 20:4263a77256ae 3356 /* C4 Bit Fields */
bogdanm 20:4263a77256ae 3357 #define UART0_C4_OSR_MASK 0x1Fu
bogdanm 20:4263a77256ae 3358 #define UART0_C4_OSR_SHIFT 0
bogdanm 20:4263a77256ae 3359 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
bogdanm 20:4263a77256ae 3360 #define UART0_C4_M10_MASK 0x20u
bogdanm 20:4263a77256ae 3361 #define UART0_C4_M10_SHIFT 5
bogdanm 20:4263a77256ae 3362 #define UART0_C4_MAEN2_MASK 0x40u
bogdanm 20:4263a77256ae 3363 #define UART0_C4_MAEN2_SHIFT 6
bogdanm 20:4263a77256ae 3364 #define UART0_C4_MAEN1_MASK 0x80u
bogdanm 20:4263a77256ae 3365 #define UART0_C4_MAEN1_SHIFT 7
bogdanm 20:4263a77256ae 3366 /* C5 Bit Fields */
bogdanm 20:4263a77256ae 3367 #define UART0_C5_RESYNCDIS_MASK 0x1u
bogdanm 20:4263a77256ae 3368 #define UART0_C5_RESYNCDIS_SHIFT 0
bogdanm 20:4263a77256ae 3369 #define UART0_C5_BOTHEDGE_MASK 0x2u
bogdanm 20:4263a77256ae 3370 #define UART0_C5_BOTHEDGE_SHIFT 1
bogdanm 20:4263a77256ae 3371 #define UART0_C5_RDMAE_MASK 0x20u
bogdanm 20:4263a77256ae 3372 #define UART0_C5_RDMAE_SHIFT 5
bogdanm 20:4263a77256ae 3373 #define UART0_C5_TDMAE_MASK 0x80u
bogdanm 20:4263a77256ae 3374 #define UART0_C5_TDMAE_SHIFT 7
bogdanm 20:4263a77256ae 3375
bogdanm 20:4263a77256ae 3376 /**
bogdanm 20:4263a77256ae 3377 * @}
bogdanm 20:4263a77256ae 3378 */ /* end of group UART0_Register_Masks */
bogdanm 20:4263a77256ae 3379
bogdanm 20:4263a77256ae 3380
bogdanm 20:4263a77256ae 3381 /* UART0 - Peripheral instance base addresses */
bogdanm 20:4263a77256ae 3382 /** Peripheral UART0 base address */
bogdanm 20:4263a77256ae 3383 #define UART0_BASE (0x4006A000u)
bogdanm 20:4263a77256ae 3384 /** Peripheral UART0 base pointer */
bogdanm 20:4263a77256ae 3385 #define UART0 ((UART0_Type *)UART0_BASE)
bogdanm 20:4263a77256ae 3386 /** Array initializer of UART0 peripheral base pointers */
bogdanm 20:4263a77256ae 3387 #define UART0_BASES { UART0 }
bogdanm 20:4263a77256ae 3388
bogdanm 20:4263a77256ae 3389 /**
bogdanm 20:4263a77256ae 3390 * @}
bogdanm 20:4263a77256ae 3391 */ /* end of group UART0_Peripheral_Access_Layer */
bogdanm 20:4263a77256ae 3392
bogdanm 20:4263a77256ae 3393
bogdanm 20:4263a77256ae 3394 /*
bogdanm 20:4263a77256ae 3395 ** End of section using anonymous unions
bogdanm 20:4263a77256ae 3396 */
bogdanm 20:4263a77256ae 3397
bogdanm 20:4263a77256ae 3398 #if defined(__ARMCC_VERSION)
bogdanm 20:4263a77256ae 3399 #pragma pop
bogdanm 20:4263a77256ae 3400 #elif defined(__CWCC__)
bogdanm 20:4263a77256ae 3401 #pragma pop
bogdanm 20:4263a77256ae 3402 #elif defined(__GNUC__)
bogdanm 20:4263a77256ae 3403 /* leave anonymous unions enabled */
bogdanm 20:4263a77256ae 3404 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 20:4263a77256ae 3405 #pragma language=default
bogdanm 20:4263a77256ae 3406 #else
bogdanm 20:4263a77256ae 3407 #error Not supported compiler type
bogdanm 20:4263a77256ae 3408 #endif
bogdanm 20:4263a77256ae 3409
bogdanm 20:4263a77256ae 3410 /**
bogdanm 20:4263a77256ae 3411 * @}
bogdanm 20:4263a77256ae 3412 */ /* end of group Peripheral_access_layer */
bogdanm 20:4263a77256ae 3413
bogdanm 20:4263a77256ae 3414
bogdanm 20:4263a77256ae 3415 /* ----------------------------------------------------------------------------
bogdanm 20:4263a77256ae 3416 -- Backward Compatibility
bogdanm 20:4263a77256ae 3417 ---------------------------------------------------------------------------- */
bogdanm 20:4263a77256ae 3418
bogdanm 20:4263a77256ae 3419 /**
bogdanm 20:4263a77256ae 3420 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
bogdanm 20:4263a77256ae 3421 * @{
bogdanm 20:4263a77256ae 3422 */
bogdanm 20:4263a77256ae 3423
bogdanm 20:4263a77256ae 3424 #define DMA_REQC_ARR_DMAC_MASK This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3425 #define DMA_REQC_ARR_DMAC_SHIFT This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3426 #define DMA_REQC_ARR_DMAC(x) This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3427 #define DMA_REQC_ARR_CFSM_MASK This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3428 #define DMA_REQC_ARR_CFSM_SHIFT This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3429 #define DMA_REQC0 This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3430 #define DMA_REQC1 This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3431 #define DMA_REQC2 This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3432 #define DMA_REQC3 This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3433 #define MCG_C6_CME0_MASK MCG_C6_CME_MASK
bogdanm 20:4263a77256ae 3434 #define MCG_C6_CME0_SHIFT MCG_C6_CME_SHIFT
bogdanm 20:4263a77256ae 3435 #define MCM_MATCR_ATC0_MASK This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3436 #define MCM_MATCR_ATC0_SHIFT This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3437 #define MCM_MATCR_ATC0(x) This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3438 #define MCM_MATCR_RO0_MASK This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3439 #define MCM_MATCR_RO0_SHIFT This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3440 #define MCM_MATCR_ATC1_MASK This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3441 #define MCM_MATCR_ATC1_SHIFT This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3442 #define MCM_MATCR_ATC1(x) This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3443 #define MCM_MATCR_RO1_MASK This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3444 #define MCM_MATCR_RO1_SHIFT This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3445 #define MCM_MATCR_ATC2_MASK This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3446 #define MCM_MATCR_ATC2_SHIFT This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3447 #define MCM_MATCR_ATC2(x) This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3448 #define MCM_MATCR_RO2_MASK This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3449 #define MCM_MATCR_RO2_SHIFT This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3450 #define MCM_MATCR_ATC3_MASK This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3451 #define MCM_MATCR_ATC3_SHIFT This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3452 #define MCM_MATCR_ATC3(x) This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3453 #define MCM_MATCR_RO3_MASK This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3454 #define MCM_MATCR_RO3_SHIFT This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3455 #define SIM_FCFG2_MAXADDR_MASK SIM_FCFG2_MAXADDR0_MASK
bogdanm 20:4263a77256ae 3456 #define SIM_FCFG2_MAXADDR_SHIFT SIM_FCFG2_MAXADDR0_SHIFT
bogdanm 20:4263a77256ae 3457 #define SIM_FCFG2_MAXADDR SIM_FCFG2_MAXADDR0
bogdanm 20:4263a77256ae 3458 #define SPI_C2_SPLPIE_MASK This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3459 #define SPI_C2_SPLPIE_SHIFT This_symbol_has_been_deprecated
bogdanm 20:4263a77256ae 3460 #define UARTLP_Type UART0_Type
bogdanm 20:4263a77256ae 3461 #define UARTLP_BDH_REG UART0_BDH_REG
bogdanm 20:4263a77256ae 3462 #define UARTLP_BDL_REG UART0_BDL_REG
bogdanm 20:4263a77256ae 3463 #define UARTLP_C1_REG UART0_C1_REG
bogdanm 20:4263a77256ae 3464 #define UARTLP_C2_REG UART0_C2_REG
bogdanm 20:4263a77256ae 3465 #define UARTLP_S1_REG UART0_S1_REG
bogdanm 20:4263a77256ae 3466 #define UARTLP_S2_REG UART0_S2_REG
bogdanm 20:4263a77256ae 3467 #define UARTLP_C3_REG UART0_C3_REG
bogdanm 20:4263a77256ae 3468 #define UARTLP_D_REG UART0_D_REG
bogdanm 20:4263a77256ae 3469 #define UARTLP_MA1_REG UART0_MA1_REG
bogdanm 20:4263a77256ae 3470 #define UARTLP_MA2_REG UART0_MA2_REG
bogdanm 20:4263a77256ae 3471 #define UARTLP_C4_REG UART0_C4_REG
bogdanm 20:4263a77256ae 3472 #define UARTLP_C5_REG UART0_C5_REG
bogdanm 20:4263a77256ae 3473 #define UARTLP_BDH_SBR_MASK UART0_BDH_SBR_MASK
bogdanm 20:4263a77256ae 3474 #define UARTLP_BDH_SBR_SHIFT UART0_BDH_SBR_SHIFT
bogdanm 20:4263a77256ae 3475 #define UARTLP_BDH_SBR(x) UART0_BDH_SBR(x)
bogdanm 20:4263a77256ae 3476 #define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK
bogdanm 20:4263a77256ae 3477 #define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT
bogdanm 20:4263a77256ae 3478 #define UARTLP_BDH_RXEDGIE_MASK UART0_BDH_RXEDGIE_MASK
bogdanm 20:4263a77256ae 3479 #define UARTLP_BDH_RXEDGIE_SHIFT UART0_BDH_RXEDGIE_SHIFT
bogdanm 20:4263a77256ae 3480 #define UARTLP_BDH_LBKDIE_MASK UART0_BDH_LBKDIE_MASK
bogdanm 20:4263a77256ae 3481 #define UARTLP_BDH_LBKDIE_SHIFT UART0_BDH_LBKDIE_SHIFT
bogdanm 20:4263a77256ae 3482 #define UARTLP_BDL_SBR_MASK UART0_BDL_SBR_MASK
bogdanm 20:4263a77256ae 3483 #define UARTLP_BDL_SBR_SHIFT UART0_BDL_SBR_SHIFT
bogdanm 20:4263a77256ae 3484 #define UARTLP_BDL_SBR(x) UART0_BDL_SBR(x)
bogdanm 20:4263a77256ae 3485 #define UARTLP_C1_PT_MASK UART0_C1_PT_MASK
bogdanm 20:4263a77256ae 3486 #define UARTLP_C1_PT_SHIFT UART0_C1_PT_SHIFT
bogdanm 20:4263a77256ae 3487 #define UARTLP_C1_PE_MASK UART0_C1_PE_MASK
bogdanm 20:4263a77256ae 3488 #define UARTLP_C1_PE_SHIFT UART0_C1_PE_SHIFT
bogdanm 20:4263a77256ae 3489 #define UARTLP_C1_ILT_MASK UART0_C1_ILT_MASK
bogdanm 20:4263a77256ae 3490 #define UARTLP_C1_ILT_SHIFT UART0_C1_ILT_SHIFT
bogdanm 20:4263a77256ae 3491 #define UARTLP_C1_WAKE_MASK UART0_C1_WAKE_MASK
bogdanm 20:4263a77256ae 3492 #define UARTLP_C1_WAKE_SHIFT UART0_C1_WAKE_SHIFT
bogdanm 20:4263a77256ae 3493 #define UARTLP_C1_M_MASK UART0_C1_M_MASK
bogdanm 20:4263a77256ae 3494 #define UARTLP_C1_M_SHIFT UART0_C1_M_SHIFT
bogdanm 20:4263a77256ae 3495 #define UARTLP_C1_RSRC_MASK UART0_C1_RSRC_MASK
bogdanm 20:4263a77256ae 3496 #define UARTLP_C1_RSRC_SHIFT UART0_C1_RSRC_SHIFT
bogdanm 20:4263a77256ae 3497 #define UARTLP_C1_DOZEEN_MASK UART0_C1_DOZEEN_MASK
bogdanm 20:4263a77256ae 3498 #define UARTLP_C1_DOZEEN_SHIFT UART0_C1_DOZEEN_SHIFT
bogdanm 20:4263a77256ae 3499 #define UARTLP_C1_LOOPS_MASK UART0_C1_LOOPS_MASK
bogdanm 20:4263a77256ae 3500 #define UARTLP_C1_LOOPS_SHIFT UART0_C1_LOOPS_SHIFT
bogdanm 20:4263a77256ae 3501 #define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK
bogdanm 20:4263a77256ae 3502 #define UARTLP_C2_SBK_SHIFT UART0_C2_SBK_SHIFT
bogdanm 20:4263a77256ae 3503 #define UARTLP_C2_RWU_MASK UART0_C2_RWU_MASK
bogdanm 20:4263a77256ae 3504 #define UARTLP_C2_RWU_SHIFT UART0_C2_RWU_SHIFT
bogdanm 20:4263a77256ae 3505 #define UARTLP_C2_RE_MASK UART0_C2_RE_MASK
bogdanm 20:4263a77256ae 3506 #define UARTLP_C2_RE_SHIFT UART0_C2_RE_SHIFT
bogdanm 20:4263a77256ae 3507 #define UARTLP_C2_TE_MASK UART0_C2_TE_MASK
bogdanm 20:4263a77256ae 3508 #define UARTLP_C2_TE_SHIFT UART0_C2_TE_SHIFT
bogdanm 20:4263a77256ae 3509 #define UARTLP_C2_ILIE_MASK UART0_C2_ILIE_MASK
bogdanm 20:4263a77256ae 3510 #define UARTLP_C2_ILIE_SHIFT UART0_C2_ILIE_SHIFT
bogdanm 20:4263a77256ae 3511 #define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK
bogdanm 20:4263a77256ae 3512 #define UARTLP_C2_RIE_SHIFT UART0_C2_RIE_SHIFT
bogdanm 20:4263a77256ae 3513 #define UARTLP_C2_TCIE_MASK UART0_C2_TCIE_MASK
bogdanm 20:4263a77256ae 3514 #define UARTLP_C2_TCIE_SHIFT UART0_C2_TCIE_SHIFT
bogdanm 20:4263a77256ae 3515 #define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK
bogdanm 20:4263a77256ae 3516 #define UARTLP_C2_TIE_SHIFT UART0_C2_TIE_SHIFT
bogdanm 20:4263a77256ae 3517 #define UARTLP_S1_PF_MASK UART0_S1_PF_MASK
bogdanm 20:4263a77256ae 3518 #define UARTLP_S1_PF_SHIFT UART0_S1_PF_SHIFT
bogdanm 20:4263a77256ae 3519 #define UARTLP_S1_FE_MASK UART0_S1_FE_MASK
bogdanm 20:4263a77256ae 3520 #define UARTLP_S1_FE_SHIFT UART0_S1_FE_SHIFT
bogdanm 20:4263a77256ae 3521 #define UARTLP_S1_NF_MASK UART0_S1_NF_MASK
bogdanm 20:4263a77256ae 3522 #define UARTLP_S1_NF_SHIFT UART0_S1_NF_SHIFT
bogdanm 20:4263a77256ae 3523 #define UARTLP_S1_OR_MASK UART0_S1_OR_MASK
bogdanm 20:4263a77256ae 3524 #define UARTLP_S1_OR_SHIFT UART0_S1_OR_SHIFT
bogdanm 20:4263a77256ae 3525 #define UARTLP_S1_IDLE_MASK UART0_S1_IDLE_MASK
bogdanm 20:4263a77256ae 3526 #define UARTLP_S1_IDLE_SHIFT UART0_S1_IDLE_SHIFT
bogdanm 20:4263a77256ae 3527 #define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK
bogdanm 20:4263a77256ae 3528 #define UARTLP_S1_RDRF_SHIFT UART0_S1_RDRF_SHIFT
bogdanm 20:4263a77256ae 3529 #define UARTLP_S1_TC_MASK UART0_S1_TC_MASK
bogdanm 20:4263a77256ae 3530 #define UARTLP_S1_TC_SHIFT UART0_S1_TC_SHIFT
bogdanm 20:4263a77256ae 3531 #define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK
bogdanm 20:4263a77256ae 3532 #define UARTLP_S1_TDRE_SHIFT UART0_S1_TDRE_SHIFT
bogdanm 20:4263a77256ae 3533 #define UARTLP_S2_RAF_MASK UART0_S2_RAF_MASK
bogdanm 20:4263a77256ae 3534 #define UARTLP_S2_RAF_SHIFT UART0_S2_RAF_SHIFT
bogdanm 20:4263a77256ae 3535 #define UARTLP_S2_LBKDE_MASK UART0_S2_LBKDE_MASK
bogdanm 20:4263a77256ae 3536 #define UARTLP_S2_LBKDE_SHIFT UART0_S2_LBKDE_SHIFT
bogdanm 20:4263a77256ae 3537 #define UARTLP_S2_BRK13_MASK UART0_S2_BRK13_MASK
bogdanm 20:4263a77256ae 3538 #define UARTLP_S2_BRK13_SHIFT UART0_S2_BRK13_SHIFT
bogdanm 20:4263a77256ae 3539 #define UARTLP_S2_RWUID_MASK UART0_S2_RWUID_MASK
bogdanm 20:4263a77256ae 3540 #define UARTLP_S2_RWUID_SHIFT UART0_S2_RWUID_SHIFT
bogdanm 20:4263a77256ae 3541 #define UARTLP_S2_RXINV_MASK UART0_S2_RXINV_MASK
bogdanm 20:4263a77256ae 3542 #define UARTLP_S2_RXINV_SHIFT UART0_S2_RXINV_SHIFT
bogdanm 20:4263a77256ae 3543 #define UARTLP_S2_MSBF_MASK UART0_S2_MSBF_MASK
bogdanm 20:4263a77256ae 3544 #define UARTLP_S2_MSBF_SHIFT UART0_S2_MSBF_SHIFT
bogdanm 20:4263a77256ae 3545 #define UARTLP_S2_RXEDGIF_MASK UART0_S2_RXEDGIF_MASK
bogdanm 20:4263a77256ae 3546 #define UARTLP_S2_RXEDGIF_SHIFT UART0_S2_RXEDGIF_SHIFT
bogdanm 20:4263a77256ae 3547 #define UARTLP_S2_LBKDIF_MASK UART0_S2_LBKDIF_MASK
bogdanm 20:4263a77256ae 3548 #define UARTLP_S2_LBKDIF_SHIFT UART0_S2_LBKDIF_SHIFT
bogdanm 20:4263a77256ae 3549 #define UARTLP_C3_PEIE_MASK UART0_C3_PEIE_MASK
bogdanm 20:4263a77256ae 3550 #define UARTLP_C3_PEIE_SHIFT UART0_C3_PEIE_SHIFT
bogdanm 20:4263a77256ae 3551 #define UARTLP_C3_FEIE_MASK UART0_C3_FEIE_MASK
bogdanm 20:4263a77256ae 3552 #define UARTLP_C3_FEIE_SHIFT UART0_C3_FEIE_SHIFT
bogdanm 20:4263a77256ae 3553 #define UARTLP_C3_NEIE_MASK UART0_C3_NEIE_MASK
bogdanm 20:4263a77256ae 3554 #define UARTLP_C3_NEIE_SHIFT UART0_C3_NEIE_SHIFT
bogdanm 20:4263a77256ae 3555 #define UARTLP_C3_ORIE_MASK UART0_C3_ORIE_MASK
bogdanm 20:4263a77256ae 3556 #define UARTLP_C3_ORIE_SHIFT UART0_C3_ORIE_SHIFT
bogdanm 20:4263a77256ae 3557 #define UARTLP_C3_TXINV_MASK UART0_C3_TXINV_MASK
bogdanm 20:4263a77256ae 3558 #define UARTLP_C3_TXINV_SHIFT UART0_C3_TXINV_SHIFT
bogdanm 20:4263a77256ae 3559 #define UARTLP_C3_TXDIR_MASK UART0_C3_TXDIR_MASK
bogdanm 20:4263a77256ae 3560 #define UARTLP_C3_TXDIR_SHIFT UART0_C3_TXDIR_SHIFT
bogdanm 20:4263a77256ae 3561 #define UARTLP_C3_R9T8_MASK UART0_C3_R9T8_MASK
bogdanm 20:4263a77256ae 3562 #define UARTLP_C3_R9T8_SHIFT UART0_C3_R9T8_SHIFT
bogdanm 20:4263a77256ae 3563 #define UARTLP_C3_R8T9_MASK UART0_C3_R8T9_MASK
bogdanm 20:4263a77256ae 3564 #define UARTLP_C3_R8T9_SHIFT UART0_C3_R8T9_SHIFT
bogdanm 20:4263a77256ae 3565 #define UARTLP_D_R0T0_MASK UART0_D_R0T0_MASK
bogdanm 20:4263a77256ae 3566 #define UARTLP_D_R0T0_SHIFT UART0_D_R0T0_SHIFT
bogdanm 20:4263a77256ae 3567 #define UARTLP_D_R1T1_MASK UART0_D_R1T1_MASK
bogdanm 20:4263a77256ae 3568 #define UARTLP_D_R1T1_SHIFT UART0_D_R1T1_SHIFT
bogdanm 20:4263a77256ae 3569 #define UARTLP_D_R2T2_MASK UART0_D_R2T2_MASK
bogdanm 20:4263a77256ae 3570 #define UARTLP_D_R2T2_SHIFT UART0_D_R2T2_SHIFT
bogdanm 20:4263a77256ae 3571 #define UARTLP_D_R3T3_MASK UART0_D_R3T3_MASK
bogdanm 20:4263a77256ae 3572 #define UARTLP_D_R3T3_SHIFT UART0_D_R3T3_SHIFT
bogdanm 20:4263a77256ae 3573 #define UARTLP_D_R4T4_MASK UART0_D_R4T4_MASK
bogdanm 20:4263a77256ae 3574 #define UARTLP_D_R4T4_SHIFT UART0_D_R4T4_SHIFT
bogdanm 20:4263a77256ae 3575 #define UARTLP_D_R5T5_MASK UART0_D_R5T5_MASK
bogdanm 20:4263a77256ae 3576 #define UARTLP_D_R5T5_SHIFT UART0_D_R5T5_SHIFT
bogdanm 20:4263a77256ae 3577 #define UARTLP_D_R6T6_MASK UART0_D_R6T6_MASK
bogdanm 20:4263a77256ae 3578 #define UARTLP_D_R6T6_SHIFT UART0_D_R6T6_SHIFT
bogdanm 20:4263a77256ae 3579 #define UARTLP_D_R7T7_MASK UART0_D_R7T7_MASK
bogdanm 20:4263a77256ae 3580 #define UARTLP_D_R7T7_SHIFT UART0_D_R7T7_SHIFT
bogdanm 20:4263a77256ae 3581 #define UARTLP_MA1_MA_MASK UART0_MA1_MA_MASK
bogdanm 20:4263a77256ae 3582 #define UARTLP_MA1_MA_SHIFT UART0_MA1_MA_SHIFT
bogdanm 20:4263a77256ae 3583 #define UARTLP_MA1_MA(x) UART0_MA1_MA(x)
bogdanm 20:4263a77256ae 3584 #define UARTLP_MA2_MA_MASK UART0_MA2_MA_MASK
bogdanm 20:4263a77256ae 3585 #define UARTLP_MA2_MA_SHIFT UART0_MA2_MA_SHIFT
bogdanm 20:4263a77256ae 3586 #define UARTLP_MA2_MA(x) UART0_MA2_MA(x)
bogdanm 20:4263a77256ae 3587 #define UARTLP_C4_OSR_MASK UART0_C4_OSR_MASK
bogdanm 20:4263a77256ae 3588 #define UARTLP_C4_OSR_SHIFT UART0_C4_OSR_SHIFT
bogdanm 20:4263a77256ae 3589 #define UARTLP_C4_OSR(x) UART0_C4_OSR(x)
bogdanm 20:4263a77256ae 3590 #define UARTLP_C4_M10_MASK UART0_C4_M10_MASK
bogdanm 20:4263a77256ae 3591 #define UARTLP_C4_M10_SHIFT UART0_C4_M10_SHIFT
bogdanm 20:4263a77256ae 3592 #define UARTLP_C4_MAEN2_MASK UART0_C4_MAEN2_MASK
bogdanm 20:4263a77256ae 3593 #define UARTLP_C4_MAEN2_SHIFT UART0_C4_MAEN2_SHIFT
bogdanm 20:4263a77256ae 3594 #define UARTLP_C4_MAEN1_MASK UART0_C4_MAEN1_MASK
bogdanm 20:4263a77256ae 3595 #define UARTLP_C4_MAEN1_SHIFT UART0_C4_MAEN1_SHIFT
bogdanm 20:4263a77256ae 3596 #define UARTLP_C5_RESYNCDIS_MASK UART0_C5_RESYNCDIS_MASK
bogdanm 20:4263a77256ae 3597 #define UARTLP_C5_RESYNCDIS_SHIFT UART0_C5_RESYNCDIS_SHIFT
bogdanm 20:4263a77256ae 3598 #define UARTLP_C5_BOTHEDGE_MASK UART0_C5_BOTHEDGE_MASK
bogdanm 20:4263a77256ae 3599 #define UARTLP_C5_BOTHEDGE_SHIFT UART0_C5_BOTHEDGE_SHIFT
bogdanm 20:4263a77256ae 3600 #define UARTLP_C5_RDMAE_MASK UART0_C5_RDMAE_MASK
bogdanm 20:4263a77256ae 3601 #define UARTLP_C5_RDMAE_SHIFT UART0_C5_RDMAE_SHIFT
bogdanm 20:4263a77256ae 3602 #define UARTLP_C5_TDMAE_MASK UART0_C5_TDMAE_MASK
bogdanm 20:4263a77256ae 3603 #define UARTLP_C5_TDMAE_SHIFT UART0_C5_TDMAE_SHIFT
bogdanm 20:4263a77256ae 3604 #define UARTLP_BASES UARTLP_BASES
bogdanm 20:4263a77256ae 3605
bogdanm 20:4263a77256ae 3606 /**
bogdanm 20:4263a77256ae 3607 * @}
bogdanm 20:4263a77256ae 3608 */ /* end of group Backward_Compatibility_Symbols */
bogdanm 20:4263a77256ae 3609
bogdanm 20:4263a77256ae 3610
bogdanm 20:4263a77256ae 3611 #endif /* #if !defined(MKL05Z4_H_) */
bogdanm 20:4263a77256ae 3612
bogdanm 20:4263a77256ae 3613 /* MKL05Z4.h, eof. */