PLL0 config script

Page last updated 01 Dec 2010, by Hugo Zijlmans. 2 replies

Here's how to make the LPC1768 board run on 96Mhz:

#include "LPC17xx.h"
#include "core_cm3.h"
#include "cmsis_nvic.h"

  // Define the register names that haven't been defined
#define CLKSRCSEL LPC_SC->CLKSRCSEL
#define PLL0CFG LPC_SC->PLL0CFG
#define PLL0CON LPC_SC->PLL0CON
#define CCLKCFG LPC_SC->CCLKCFG
#define PLL0FEED LPC_SC->PLL0FEED
#define PLL0STAT LPC_SC->PLL0STAT

  // Other defines
#define SYSCLK 96000000
#define EXTCLK 12000000
#define PLLCLK 288000000
#define PLLMULT (PLLCLK/2/EXTCLK)-1

void Sys_init(void) {

    // Set main clk as main oscillator
    CLKSRCSEL = 1;

    // Disconnect the PLL0
    PLL0CON &= ~(1<<1); /* Disconnect the main PLL (PLL0) */

    // Feed the PLL
    PLL0FEED = 0xAA;
    PLL0FEED = 0x55;

    // Wait for main PLL (PLL0) to disconnect
    while ((PLL0STAT & (1<<25)) != 0x00);

    // Turn off the main PLL (PLL0)
    PLL0CON &= ~(1<<0);

    // Feed the PLL
    PLL0FEED = 0xAA;
    PLL0FEED = 0x55;

    // Wait for main PLL (PLL0) to shut down
    while ((PLL0STAT & (1<<24)) != 0x00);

    // Set PLL0 multiplier
    PLL0CFG = PLLMULT;

    // Feed the PLL
    PLL0FEED = 0xAA;
    PLL0FEED = 0x55;

    // Turn on the main PLL (PLL0)
    PLL0CON |= 1<<0;

    // Feed the PLL
    PLL0FEED = 0xAA;
    PLL0FEED = 0x55;

    // Wait for main PLL (PLL0) to come up
    while ((PLL0STAT & (1<<24)) == 0x00);

    // Set CPU clock divider
    CCLKCFG = 2;

    // Wait for PLOCK0 to become 1
    while ((PLL0STAT & (1<<26)) == 0x00);

    // Connect to the main PLL (PLL0)
    PLL0CON |= 1<<1;

    // Feed the PLL
    PLL0FEED = 0xAA;
    PLL0FEED = 0x55;

    // Wait for main PLL (PLL0) to connect
    while ((PLL0STAT & (1<<25)) == 0x00);

}

2 comments

Daniel Ng

# 29 May 2011

Works for me. Thanks!

Manuel Spierenburg

# 21 Nov 2013

Can somebody explain to me this lines:

Why does PLLOCFG = 11 lead to 96Mhz.

Is it possible to down clock the CPU to kHz ?

 // Set PLL0 multiplier
 PLL0CFG = PLLMULT;

 // Set CPU clock divider
 CCLKCFG = 2;

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