BCM2835.h

00001 /* bcm2835.h
00002 
00003     C and C++ support for Broadcom BCM 2835 as used in Raspberry Pi
00004 
00005     Author: Mike McCauley
00006     Copyright (C) 2011-2013 Mike McCauley
00007     $Id: bcm2835.h,v 1.26 2020/01/11 05:07:13 mikem Exp mikem $
00008  */
00009 
00010 #ifndef _BCM2835_H_
00011 #define _BCM2835_H_
00012 
00013 /*$off*/
00014 #include <errno.h>
00015 #include <fcntl.h>
00016 #include <netinet/in.h>
00017 #include <signal.h>
00018 #include <stdlib.h>
00019 #include <stdio.h>
00020 #include <sys/ipc.h>
00021 #include <sys/sem.h>
00022 #include <sys/socket.h>
00023 #include <sys/time.h>
00024 #include <sys/types.h>
00025 #include <sys/wait.h>
00026 #include <sys/mman.h>
00027 #include <string.h>
00028 #include <time.h>
00029 #include <termios.h>
00030 #include <ctype.h>
00031 #include <sys/ioctl.h>
00032 #include <limits.h>
00033 #include <algorithm>
00034 #include <limits.h>
00035 #include <pthread.h>
00036 #include <poll.h>
00037 #include "PinNames.h"
00038 
00039 #define BCM2835_PERI_BASE       0x20000000
00040 #define BCM2835_PERI_SIZE       0x01000000
00041 
00042 #define BCM2835_ST_BASE         0x3000
00043 #define BCM2835_CLOCK_BASE      0x101000
00044 #define BCM2835_GPIO_PWM        0x20C000
00045 #define BCM2835_BSC1_BASE       0x804000
00046 #define BCM2835_SPI0_BASE       0x204000
00047 
00048 /* Defines for ST
00049    GPIO register offsets from BCM2835_ST_BASE.
00050    Offsets into the ST Peripheral block in bytes per 12.1 System Timer Registers
00051    The System Timer peripheral provides four 32-bit timer channels and a single 64-bit free running counter.
00052    BCM2835_ST_CLO is the System Timer Counter Lower bits register.
00053    The system timer free-running counter lower register is a read-only register that returns the current value
00054    of the lower 32-bits of the free running counter.
00055    BCM2835_ST_CHI is the System Timer Counter Upper bits register.
00056    The system timer free-running counter upper register is a read-only register that returns the current value
00057    of the upper 32-bits of the free running counter.
00058 */
00059 #define BCM2835_ST_CS           0x0000 /*!< System Timer Control/Status */
00060 #define BCM2835_ST_CLO          0x0004 /*!< System Timer Counter Lower 32 bits */
00061 #define BCM2835_ST_CHI          0x0008 /*!< System Timer Counter Upper 32 bits */
00062 
00063 // Defines for I2C
00064 // GPIO register offsets from BCM2835_BSC*_BASE.
00065 // Offsets into the BSC Peripheral block in bytes per 3.1 BSC Register Map
00066 #define BCM2835_BSC_C           0x0000     ///< BSC Master Control
00067 #define BCM2835_BSC_S           0x0004     ///< BSC Master Status
00068 #define BCM2835_BSC_DLEN        0x0008     ///< BSC Master Data Length
00069 #define BCM2835_BSC_A           0x000c     ///< BSC Master Slave Address
00070 #define BCM2835_BSC_FIFO        0x0010     ///< BSC Master Data FIFO
00071 #define BCM2835_BSC_DIV         0x0014     ///< BSC Master Clock Divider
00072 #define BCM2835_BSC_DEL         0x0018     ///< BSC Master Data Delay
00073 #define BCM2835_BSC_CLKT        0x001c     ///< BSC Master Clock Stretch Timeout
00074 
00075 // Register masks for BSC_C
00076 #define BCM2835_BSC_C_I2CEN     0x00008000  ///< I2C Enable, 0 = disabled, 1 = enabled
00077 #define BCM2835_BSC_C_INTR      0x00000400  ///< Interrupt on RX
00078 #define BCM2835_BSC_C_INTT      0x00000200  ///< Interrupt on TX
00079 #define BCM2835_BSC_C_INTD      0x00000100  ///< Interrupt on DONE
00080 #define BCM2835_BSC_C_ST        0x00000080  ///< Start transfer, 1 = Start a new transfer
00081 #define BCM2835_BSC_C_CLEAR_1   0x00000020  ///< Clear FIFO Clear
00082 #define BCM2835_BSC_C_CLEAR_2   0x00000010  ///< Clear FIFO Clear
00083 #define BCM2835_BSC_C_READ      0x00000001  ///<    Read transfer
00084 
00085 // Register masks for BSC_S
00086 #define BCM2835_BSC_S_CLKT      0x00000200  ///< Clock stretch timeout
00087 #define BCM2835_BSC_S_ERR       0x00000100  ///< ACK error
00088 #define BCM2835_BSC_S_RXF       0x00000080  ///< RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full
00089 #define BCM2835_BSC_S_TXE       0x00000040  ///< TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full
00090 #define BCM2835_BSC_S_RXD       0x00000020  ///< RXD FIFO contains data
00091 #define BCM2835_BSC_S_TXD       0x00000010  ///< TXD FIFO can accept data
00092 #define BCM2835_BSC_S_RXR       0x00000008  ///< RXR FIFO needs reading (full)
00093 #define BCM2835_BSC_S_TXW       0x00000004  ///< TXW FIFO needs writing (full)
00094 #define BCM2835_BSC_S_DONE      0x00000002  ///< Transfer DONE
00095 #define BCM2835_BSC_S_TA        0x00000001  ///< Transfer Active
00096 #define BCM2835_BSC_FIFO_SIZE   16          ///< BSC FIFO size
00097 #define BCM2835_CORE_CLK_HZ     250000000   ///< 250 MHz
00098 
00099     /// \brief bcm2835I2CClockDivider
00100     /// Specifies the divider used to generate the I2C clock from the system clock.
00101     /// Clock divided is based on nominal base clock rate of 250MHz
00102 typedef enum
00103 {
00104     BCM2835_I2C_CLOCK_DIVIDER_2500  = 2500, ///< 2500 = 10us = 100 kHz
00105     BCM2835_I2C_CLOCK_DIVIDER_626   = 626,  ///< 622 = 2.504us = 399.3610 kHz
00106     BCM2835_I2C_CLOCK_DIVIDER_150   = 150,  ///< 150 = 60ns = 1.666 MHz (default at reset)
00107     BCM2835_I2C_CLOCK_DIVIDER_148   = 148,  ///< 148 = 59ns = 1.689 MHz
00108 } bcm2835I2CClockDivider;
00109 
00110 /// \brief bcm2835I2CReasonCodes
00111 /// Specifies the reason codes for the bcm2835_i2c_write and bcm2835_i2c_read functions.
00112 typedef enum
00113 {
00114     BCM2835_I2C_REASON_OK           = 0x00, ///< Success
00115     BCM2835_I2C_REASON_ERROR_NACK   = 0x01, ///< Received a NACK
00116     BCM2835_I2C_REASON_ERROR_CLKT   = 0x02, ///< Received Clock Stretch Timeout
00117     BCM2835_I2C_REASON_ERROR_DATA   = 0x04, ///< Not all data is sent / received
00118 } bcm2835I2CReasonCodes;
00119 
00120 typedef enum
00121 {
00122     RPI_V2_GPIO_P1_03               = 2,    ///< Version 2, Pin P1-03
00123     RPI_V2_GPIO_P1_05               = 3,    ///< Version 2, Pin P1-05
00124 } RPiGPIOPin;
00125 
00126 #define BSC0_C        *(bsc0.addr + 0x00)
00127 #define BSC0_S        *(bsc0.addr + 0x01)
00128 #define BSC0_DLEN     *(bsc0.addr + 0x02)
00129 #define BSC0_A        *(bsc0.addr + 0x03)
00130 #define BSC0_FIFO     *(bsc0.addr + 0x04)
00131 
00132 #define BSC_C_I2CEN   (1<< 15)
00133 #define BSC_C_INTR    (1<< 10)
00134 #define BSC_C_INTT    (1<< 9)
00135 #define BSC_C_INTD    (1<< 8)
00136 #define BSC_C_ST      (1<< 7)
00137 #define BSC_C_CLEAR   (1<< 4)
00138 #define BSC_C_READ    1
00139 
00140 #define START_READ    BSC_C_I2CEN|BSC_C_ST|BSC_C_CLEAR|BSC_C_READ
00141 #define START_WRITE   BSC_C_I2CEN|BSC_C_ST
00142 
00143 #define BSC_S_CLKT   (1<< 9)
00144 #define BSC_S_ERR    (1<< 8)
00145 #define BSC_S_RXF    (1<< 7)
00146 #define BSC_S_TXE    (1<< 6)
00147 #define BSC_S_RXD    (1<< 5)
00148 #define BSC_S_TXD    (1<< 4)
00149 #define BSC_S_RXR    (1<< 3)
00150 #define BSC_S_TXW    (1<< 2)
00151 #define BSC_S_DONE   (1<< 1)
00152 #define BSC_S_TA     1
00153 
00154 #define CLEAR_STATUS    BSC_S_CLKT|BSC_S_ERR|BSC_S_DONE
00155 
00156 #define GPFSEL0     *(gpio.addr + 0)
00157 #define GPFSEL1     *(gpio.addr + 1)
00158 #define GPFSEL2     *(gpio.addr + 2)
00159 #define GPFSEL3     *(gpio.addr + 3)
00160 #define GPFSEL4     *(gpio.addr + 4)
00161 #define GPFSEL5     *(gpio.addr + 5)
00162 // Reserved @ word offset 6
00163 #define GPSET0      *(gpio.addr + 7)
00164 #define GPSET1      *(gpio.addr + 8)
00165 // Reserved @ word offset 9
00166 #define GPCLR0      *(gpio.addr + 10)
00167 #define GPCLR1      *(gpio.addr + 11)
00168 // Reserved @ word offset 12
00169 #define GPLEV0      *(gpio.addr + 13)
00170 #define GPLEV1      *(gpio.addr + 14)
00171 
00172 #define PAGESIZE    4096
00173 #define BLOCK_SIZE  4096
00174 
00175 /// Defines for SPI
00176 /// GPIO register offsets from BCM2835_SPI0_BASE.
00177 /// Offsets into the SPI Peripheral block in bytes per 10.5 SPI Register Map
00178 #define BCM2835_SPI0_CS                      0x0000 ///< SPI Master Control and Status
00179 #define BCM2835_SPI0_FIFO                    0x0004 ///< SPI Master TX and RX FIFOs
00180 #define BCM2835_SPI0_CLK                     0x0008 ///< SPI Master Clock Divider
00181 #define BCM2835_SPI0_DLEN                    0x000c ///< SPI Master Data Length
00182 #define BCM2835_SPI0_LTOH                    0x0010 ///< SPI LOSSI mode TOH
00183 #define BCM2835_SPI0_DC                      0x0014 ///< SPI DMA DREQ Controls
00184 
00185 // Register masks for SPI0_CS
00186 #define BCM2835_SPI0_CS_LEN_LONG             0x02000000 ///< Enable Long data word in Lossi mode if DMA_LEN is set
00187 #define BCM2835_SPI0_CS_DMA_LEN              0x01000000 ///< Enable DMA mode in Lossi mode
00188 #define BCM2835_SPI0_CS_CSPOL2               0x00800000 ///< Chip Select 2 Polarity
00189 #define BCM2835_SPI0_CS_CSPOL1               0x00400000 ///< Chip Select 1 Polarity
00190 #define BCM2835_SPI0_CS_CSPOL0               0x00200000 ///< Chip Select 0 Polarity
00191 #define BCM2835_SPI0_CS_RXF                  0x00100000 ///< RXF - RX FIFO Full
00192 #define BCM2835_SPI0_CS_RXR                  0x00080000 ///< RXR RX FIFO needs Reading ( full)
00193 #define BCM2835_SPI0_CS_TXD                  0x00040000 ///< TXD TX FIFO can accept Data
00194 #define BCM2835_SPI0_CS_RXD                  0x00020000 ///< RXD RX FIFO contains Data
00195 #define BCM2835_SPI0_CS_DONE                 0x00010000 ///< Done transfer Done
00196 #define BCM2835_SPI0_CS_TE_EN                0x00008000 ///< Unused
00197 #define BCM2835_SPI0_CS_LMONO                0x00004000 ///< Unused
00198 #define BCM2835_SPI0_CS_LEN                  0x00002000 ///< LEN LoSSI enable
00199 #define BCM2835_SPI0_CS_REN                  0x00001000 ///< REN Read Enable
00200 #define BCM2835_SPI0_CS_ADCS                 0x00000800 ///< ADCS Automatically Deassert Chip Select
00201 #define BCM2835_SPI0_CS_INTR                 0x00000400 ///< INTR Interrupt on RXR
00202 #define BCM2835_SPI0_CS_INTD                 0x00000200 ///< INTD Interrupt on Done
00203 #define BCM2835_SPI0_CS_DMAEN                0x00000100 ///< DMAEN DMA Enable
00204 #define BCM2835_SPI0_CS_TA                   0x00000080 ///< Transfer Active
00205 #define BCM2835_SPI0_CS_CSPOL                0x00000040 ///< Chip Select Polarity
00206 #define BCM2835_SPI0_CS_CLEAR                0x00000030 ///< Clear FIFO Clear RX and TX
00207 #define BCM2835_SPI0_CS_CLEAR_RX             0x00000020 ///< Clear FIFO Clear RX
00208 #define BCM2835_SPI0_CS_CLEAR_TX             0x00000010 ///< Clear FIFO Clear TX
00209 #define BCM2835_SPI0_CS_CPOL                 0x00000008 ///< Clock Polarity
00210 #define BCM2835_SPI0_CS_CPHA                 0x00000004 ///< Clock Phase
00211 #define BCM2835_SPI0_CS_CS                   0x00000003 ///< Chip Select
00212 
00213 #define BCM2835_GPFSEL0                      0x0000 ///< GPIO Function Select 0
00214 
00215 #define BCM2835_GPEDS0                       0x0040 ///< GPIO Pin Event Detect Status 0
00216 #define BCM2835_GPREN0                       0x004c ///< GPIO Pin Rising Edge Detect Enable 0
00217 #define BCM2835_GPFEN0                       0x0048 ///< GPIO Pin Falling Edge Detect Enable 0
00218 #define BCM2835_GPHEN0                       0x0064 ///< GPIO Pin High Detect Enable 0
00219 #define BCM2835_GPLEN0                       0x0070 ///< GPIO Pin Low Detect Enable 0
00220 
00221 /* Defines for PWM, word offsets (ie 4 byte multiples) */
00222 #define BCM2835_PWM_CONTROL 0
00223 #define BCM2835_PWM_STATUS  1
00224 #define BCM2835_PWM_DMAC    2
00225 #define BCM2835_PWM0_RANGE  4
00226 #define BCM2835_PWM0_DATA   5
00227 #define BCM2835_PWM_FIF1    6
00228 #define BCM2835_PWM1_RANGE  8
00229 #define BCM2835_PWM1_DATA   9
00230 
00231 /* Defines for PWM Clock, word offsets (ie 4 byte multiples) */
00232 #define BCM2835_PWMCLK_CNTL     40
00233 #define BCM2835_PWMCLK_DIV      41
00234 #define BCM2835_PWM_PASSWRD     (0x5A << 24)  /*!< Password to enable setting PWM clock */
00235 
00236 #define BCM2835_PWM1_MS_MODE    0x8000  /*!< Run in Mark/Space mode */
00237 #define BCM2835_PWM1_USEFIFO    0x2000  /*!< Data from FIFO */
00238 #define BCM2835_PWM1_REVPOLAR   0x1000  /*!< Reverse polarity */
00239 #define BCM2835_PWM1_OFFSTATE   0x0800  /*!< Ouput Off state */
00240 #define BCM2835_PWM1_REPEATFF   0x0400  /*!< Repeat last value if FIFO empty */
00241 #define BCM2835_PWM1_SERIAL     0x0200  /*!< Run in serial mode */
00242 #define BCM2835_PWM1_ENABLE     0x0100  /*!< Channel Enable */
00243 
00244 #define BCM2835_PWM0_MS_MODE    0x0080  /*!< Run in Mark/Space mode */
00245 #define BCM2835_PWM_CLEAR_FIFO  0x0040  /*!< Clear FIFO */
00246 #define BCM2835_PWM0_USEFIFO    0x0020  /*!< Data from FIFO */
00247 #define BCM2835_PWM0_REVPOLAR   0x0010  /*!< Reverse polarity */
00248 #define BCM2835_PWM0_OFFSTATE   0x0008  /*!< Ouput Off state */
00249 #define BCM2835_PWM0_REPEATFF   0x0004  /*!< Repeat last value if FIFO empty */
00250 #define BCM2835_PWM0_SERIAL     0x0002  /*!< Run in serial mode */
00251 #define BCM2835_PWM0_ENABLE     0x0001  /*!< Channel Enable */
00252 
00253 #define PWM_CHANNEL             0
00254 
00255 /// \brief bcm2835SPIBitOrder
00256 /// Specifies the SPI data bit ordering
00257 typedef enum
00258 {
00259     LSBFIRST = 0,  ///< LSB First
00260     MSBFIRST = 1///< MSB First
00261 } bcm2835SPIBitOrder;
00262 
00263 /// \brief bcm2835SPIMode
00264 /// Specify the SPI data mode
00265 typedef enum
00266 {
00267     SPI_MODE0 = 0,  ///< CPOL = 0, CPHA = 0
00268     SPI_MODE1 = 1,  ///< CPOL = 0, CPHA = 1
00269     SPI_MODE2 = 2,  ///< CPOL = 1, CPHA = 0
00270     SPI_MODE3 = 3,  ///< CPOL = 1, CPHA = 1
00271 } bcm2835SPIMode;
00272 
00273 /// \brief bcm2835SPIChipSelect
00274 /// Specify the SPI chip select pin(s)
00275 typedef enum
00276 {
00277     SPI_CS0 = 0,     ///< Chip Select 0
00278     SPI_CS1 = 1,     ///< Chip Select 1
00279     SPI_CS2 = 2,     ///< Chip Select 2 (ie pins CS1 and CS2 are asserted)
00280     SPI_CS_NONE = 3, ///< No CS, control it yourself
00281 } bcm2835SPIChipSelect;
00282 
00283 /// \brief bcm2835SPIClockDivider
00284 /// Specifies the divider used to generate the SPI clock from the system clock.
00285 /// Figures below give the divider, clock period and clock frequency.
00286 typedef enum
00287 {
00288     SPI_CLOCK_DIV65536 = 0,       ///< 65536 = 256us = 4kHz
00289     SPI_CLOCK_DIV32768 = 32768,   ///< 32768 = 126us = 8kHz
00290     SPI_CLOCK_DIV16384 = 16384,   ///< 16384 = 64us = 15.625kHz
00291     SPI_CLOCK_DIV8192  = 8192,    ///< 8192 = 32us = 31.25kHz
00292     SPI_CLOCK_DIV4096  = 4096,    ///< 4096 = 16us = 62.5kHz
00293     SPI_CLOCK_DIV2048  = 2048,    ///< 2048 = 8us = 125kHz
00294     SPI_CLOCK_DIV1024  = 1024,    ///< 1024 = 4us = 250kHz
00295     SPI_CLOCK_DIV512   = 512,     ///< 512 = 2us = 500kHz
00296     SPI_CLOCK_DIV256   = 256,     ///< 256 = 1us = 1MHz
00297     SPI_CLOCK_DIV128   = 128,     ///< 128 = 500ns = = 2MHz
00298     SPI_CLOCK_DIV64    = 64,      ///< 64 = 250ns = 4MHz
00299     SPI_CLOCK_DIV32    = 32,      ///< 32 = 125ns = 8MHz
00300     SPI_CLOCK_DIV16    = 16,      ///< 16 = 50ns = 20MHz
00301     SPI_CLOCK_DIV8     = 8,       ///< 8 = 25ns = 40MHz
00302     SPI_CLOCK_DIV4     = 4,       ///< 4 = 12.5ns 80MHz
00303     SPI_CLOCK_DIV2     = 2,       ///< 2 = 6.25ns = 160MHz
00304     SPI_CLOCK_DIV1     = 1,       ///< 0 = 256us = 4kHz
00305 } bcm2835SPIClockDivider;
00306 
00307 /*! \brief bcm2835PWMClockDivider
00308   Specifies the divider used to generate the PWM clock from the system clock.
00309   Figures below give the divider, clock period and clock frequency.
00310   Clock divided is based on nominal PWM base clock rate of 19.2MHz
00311   The frequencies shown for each divider have been confirmed by measurement
00312 */
00313 typedef enum
00314 {
00315     BCM2835_PWM_CLOCK_DIVIDER_4096  = 4096,    /*!< 4096 = 4.6875kHz */
00316     BCM2835_PWM_CLOCK_DIVIDER_2048  = 2048,    /*!< 2048 = 9.375kHz */
00317     BCM2835_PWM_CLOCK_DIVIDER_1024  = 1024,    /*!< 1024 = 18.75kHz */
00318     BCM2835_PWM_CLOCK_DIVIDER_512   = 512,     /*!< 512 = 37.5kHz */
00319     BCM2835_PWM_CLOCK_DIVIDER_256   = 256,     /*!< 256 = 75kHz */
00320     BCM2835_PWM_CLOCK_DIVIDER_128   = 128,     /*!< 128 = 150kHz */
00321     BCM2835_PWM_CLOCK_DIVIDER_64    = 64,      /*!< 64 = 300kHz */
00322     BCM2835_PWM_CLOCK_DIVIDER_32    = 32,      /*!< 32 = 600.0kHz */
00323     BCM2835_PWM_CLOCK_DIVIDER_16    = 16,      /*!< 16 = 1.2MHz */
00324     BCM2835_PWM_CLOCK_DIVIDER_8     = 8,       /*!< 8 = 2.4MHz */
00325     BCM2835_PWM_CLOCK_DIVIDER_4     = 4,       /*!< 4 = 4.8MHz */
00326     BCM2835_PWM_CLOCK_DIVIDER_2     = 2,       /*!< 2 = 9.6MHz, fastest you can get */
00327     BCM2835_PWM_CLOCK_DIVIDER_1     = 1        /*!< 1 = 4.6875kHz, same as divider 4096 */
00328 } bcm2835PWMClockDivider;
00329 
00330 /*! \brief bcm2835PWMClockDivider
00331   Specifies the divider used to generate the PWM clock from the system clock.
00332   Figures below give the divider, clock period and clock frequency.
00333   Clock divided is based on nominal PWM base clock rate of 19.2MHz
00334   The frequencies shown for each divider have been confirmed by measurement
00335 */
00336 typedef enum
00337 {
00338     BCM2835_PWM_PERIOD_212_US  = 4096,    /*!< 213.33 us  = 4.6875kHz */
00339     BCM2835_PWM_PERIOD_107_US  = 2048,    /*!< 106.66 us  = 9.375kHz  */
00340     BCM2835_PWM_PERIOD_53_US   = 1024,    /*!<  53.33 us  = 18.75kHz  */
00341     BCM2835_PWM_PERIOD_27_US   =  512,    /*!<  26.66 us  = 37.5kHz   */
00342     BCM2835_PWM_PERIOD_13_US   =  256,    /*!<  13.33 us  = 75kHz     */
00343     BCM2835_PWM_PERIOD_6_6_US  =  128,    /*!<   6.66 us  = 150kHz    */
00344     BCM2835_PWM_PERIOD_3_3_US  =   64,    /*!<   3.33 us  = 300kHz    */
00345     BCM2835_PWM_PERIOD_1_7_US  =   32,    /*!<   1.66 us  = 600.0kHz  */
00346     BCM2835_PWM_PERIOD_833_NS  =   16,    /*!< 833.33 ns  = 1.2MHz    */
00347     BCM2835_PWM_PERIOD_417_NS  =    8,    /*!< 416.66 ns  = 2.4MHz    */
00348     BCM2835_PWM_PERIOD_208_NS  =    4,    /*!< 208.33 ns  = 4.8MHz    */
00349     BCM2835_PWM_PERIOD_104_NS  =    2,    /*!< 104.16 ns  = 9.6MHz,   */
00350 } bcm2835_PWM_PulsePeriod;
00351 
00352 typedef enum
00353 {
00354     BCM2835_GPIO_FSEL_INPT  = 0b000,   ///< Input
00355     BCM2835_GPIO_FSEL_OUTP  = 0b001,   ///< Output
00356     BCM2835_GPIO_FSEL_ALT0  = 0b100,   ///< Alternate function 0
00357     BCM2835_GPIO_FSEL_ALT1  = 0b101,   ///< Alternate function 1
00358     BCM2835_GPIO_FSEL_ALT2  = 0b110,   ///< Alternate function 2
00359     BCM2835_GPIO_FSEL_ALT3  = 0b111,   ///< Alternate function 3
00360     BCM2835_GPIO_FSEL_ALT4  = 0b011,   ///< Alternate function 4
00361     BCM2835_GPIO_FSEL_ALT5  = 0b010,   ///< Alternate function 5
00362     BCM2835_GPIO_FSEL_MASK  = 0b111    ///< Function select bits mask
00363 } bcm2835FunctionSelect;
00364 
00365 namespace unistd {
00366     //All functions of unistd.h must be called like this: unistd::the_function()
00367     #include <unistd.h>
00368 }
00369 
00370 enum Representation{
00371     BIN,
00372     OCT,
00373     DEC,
00374     HEX,
00375     BYTE
00376 };
00377 
00378 typedef enum {
00379     LOW     = 0,
00380     HIGH    = 1,
00381     RISING  = 2,
00382     FALLING = 3,
00383     BOTH    = 4
00384 } Digivalue;
00385 //
00386 /*$on*/
00387 //
00388 typedef bool boolean;
00389 typedef unsigned char   byte;
00390 
00391 struct bcm2835_peripheral
00392 {
00393     unsigned long           addr_p;
00394     int                     mem_fd;
00395     void*                   map;
00396     volatile unsigned int*  addr;
00397 };
00398 
00399 
00400 
00401 /* Helper functions */
00402 int         getBoardRev();
00403 uint32_t*   mapmem(const char* msg, size_t size, int fd, off_t off);
00404 void        setBoardRev(int rev);
00405 pthread_t*  getThreadIdFromPin(int pin);
00406 void*       threadFunction(void* args);
00407 uint32_t    bcm2835_peri_read(volatile uint32_t* paddr);
00408 uint32_t    bcm2835_peri_read_nb(volatile uint32_t* paddr);
00409 void        bcm2835_peri_write(volatile uint32_t* paddr, uint32_t value);
00410 void        bcm2835_peri_write_nb(volatile uint32_t* paddr, uint32_t value);
00411 void        bcm2835_peri_set_bits(volatile uint32_t* paddr, uint32_t value, uint32_t mask);
00412 void        bcm2835_gpio_fsel(uint8_t pin, uint8_t mode);
00413 uint64_t    bcm2835_systimer_read(void);
00414 void        bcm2835_delay (unsigned int millis);
00415 void        bcm2835_pwm_set_clock(uint32_t divisor);
00416 void        bcm2835_pwm_set_mode(uint8_t channel, uint8_t markspace, uint8_t enabled);
00417 void        bcm2835_pwm_set_range(uint8_t channel, uint32_t range);
00418 void        bcm2835_pwm_set_data(uint8_t channel, uint32_t data);
00419 void        gpio_dir(PinName pin, PinDirection direction);
00420 void        gpio_mode(PinName pin, PinMode mode);
00421 void        gpio_write(PinName pin, int value);
00422 int         gpio_read(PinName pin);
00423 uint8_t     shiftIn(PinName dPin, PinName cPin, bcm2835SPIBitOrder order);
00424 void        shiftOut(PinName dPin, PinName cPin, bcm2835SPIBitOrder order, uint8_t val);
00425 void        attachInterrupt(PinName p, void (*f) (), Digivalue m);
00426 void        detachInterrupt(PinName p);
00427 
00428 typedef void (*FunctionPointer) ();
00429 
00430 static int REV = 0;
00431 
00432 #endif  // _BCM2835_H_
00433