cdc_XR21B1411.h

00001 /* Copyright (C) 2015 Andrew J. Kroll
00002    and
00003    Circuits At Home, LTD. All rights reserved.
00004 
00005 This software may be distributed and modified under the terms of the GNU
00006 General Public License version 2 (GPL2) as published by the Free Software
00007 Foundation and appearing in the file GPL2.TXT included in the packaging of
00008 this file. Please note that GPL2 Section 2[b] requires that all works based
00009 on this software must also be made publicly available under the terms of
00010 the GPL2 ("Copyleft").
00011 
00012 Contact information
00013 -------------------
00014 
00015 Circuits At Home, LTD
00016 Web      :  http://www.circuitsathome.com
00017 e-mail   :  support@circuitsathome.com
00018  */
00019 #if !defined(__CDC_XR21B1411_H__)
00020 #define __CDC_XR21B1411_H__
00021 
00022 #include "cdcacm.h"
00023 
00024 #define XR_REG_CUSTOM_DRIVER                    (0x020DU) // DRIVER SELECT
00025 #define XR_REG_CUSTOM_DRIVER_ACTIVE             (0x0001U) // 0: CDC 1: CUSTOM
00026 
00027 #define XR_REG_ACM_FLOW_CTL                     (0x0216U) // FLOW CONTROL REGISTER CDCACM MODE
00028 #define XR_REG_FLOW_CTL                         (0x0C06U) // FLOW CONTROL REGISTER CUSTOM MODE
00029 #define XR_REG_FLOW_CTL_HALF_DPLX               (0x0008U) // 0:FULL DUPLEX 1:HALF DUPLEX
00030 #define XR_REG_FLOW_CTL_MODE_MASK               (0x0007U) // MODE BITMASK
00031 #define XR_REG_FLOW_CTL_NONE                    (0x0000U) // NO FLOW CONTROL
00032 #define XR_REG_FLOW_CTL_HW                      (0x0001U) // HARDWARE FLOW CONTROL
00033 #define XR_REG_FLOW_CTL_SW                      (0x0002U) // SOFTWARE FLOW CONTROL
00034 #define XR_REG_FLOW_CTL_MMMRX                   (0x0003U) // MULTIDROP RX UPON ADDRESS MATCH
00035 #define XR_REG_FLOW_CTL_MMMRXTX                 (0x0004U) // MULTIDROP RX/TX UPON ADDRESS MATCH
00036 
00037 #define XR_REG_ACM_GPIO_MODE                    (0x0217U) // GPIO MODE REGISTER IN CDCACM MODE
00038 #define XR_REG_GPIO_MODE                        (0x0C0CU) // GPIO MODE REGISTER IN CUSTOM MODE
00039 #define XR_REG_GPIO_MODE_GPIO                   (0x0000U) // ALL GPIO PINS ACM PROGRAMMABLE
00040 #define XR_REG_GPIO_MODE_FC_RTSCTS              (0x0001U) // AUTO RTSCTS HW FC (GPIO 4/5)
00041 #define XR_REG_GPIO_MODE_FC_DTRDSR              (0x0002U) // AUTO DTRDSR HW FC (GPIO 2/3)
00042 #define XR_REG_GPIO_MODE_ATE                    (0x0003U) // AUTO TRANSCEIVER ENABLE DURING TX (GPIO 5)
00043 #define XR_REG_GPIO_MODE_ATE_ADDRESS            (0x0004U) // AUTO TRANSCEIVER ENABLE ON ADDRESS MATCH (GPIO 5)
00044 
00045 #define XR_REG_ACM_GPIO_DIR                     (0x0218U) // GPIO DIRECTION REGISTER CDCACM MODE, 0:IN 1:OUT
00046 #define XR_REG_GPIO_DIR                         (0x0C0DU) // GPIO DIRECTION REGISTER CUSTOM MODE, 0:IN 1:OUT
00047 
00048 #define XR_REG_ACM_GPIO_INT                     (0x0219U) // GPIO PIN CHANGE INTERRUPT ENABLE CDCACM MODE, 0: ENABLED 1: DISABLED
00049 #define XR_REG_GPIO_INT                         (0x0C11U) // GPIO PIN CHANGE INTERRUPT ENABLE CUSTOM MODE, 0: ENABLED 1: DISABLED
00050 #define XR_REG_GPIO_MASK                        (0x001FU) // GPIO REGISTERS BITMASK
00051 
00052 #define XR_REG_UART_ENABLE                      (0x0C00U) // UART I/O ENABLE REGISTER
00053 #define XR_REG_UART_ENABLE_RX                   (0x0002U) // 0:DISABLED 1:ENABLED
00054 #define XR_REG_UART_ENABLE_TX                   (0x0001U) // 0:DISABLED 1:ENABLED
00055 
00056 #define XR_REG_ERROR_STATUS                     (0x0C09U) // ERROR STATUS REGISTER
00057 #define XR_REG_ERROR_STATUS_MASK                (0x00F8U) // ERROR STATUS BITMASK
00058 #define XR_REG_ERROR_STATUS_ERROR               (0x0070U) // ERROR STATUS ERROR BITMASK
00059 #define XR_REG_ERROR_STATUS_BREAK               (0x0008U) // BREAK HAS BEEN DETECTED
00060 #define XR_REG_ERROR_STATUS_OVERRUN             (0x0010U) // RX OVERRUN ERROR
00061 #define XR_REG_ERROR_STATUS_PARITY              (0x0020U) // PARITY ERROR
00062 #define XR_REG_ERROR_STATUS_FRAME               (0x0040U) // FRAMING ERROR
00063 #define XR_REG_ERROR_STATUS_BREAKING            (0x0080U) // BREAK IS BEING DETECTED
00064 
00065 #define XR_REG_TX_BREAK                         (0x0C0AU) // TRANSMIT BREAK. 0X0001-0XFFE TIME IN MS, 0X0000 STOP, 0X0FFF BREAK ON
00066 
00067 #define XR_REG_XCVR_EN_DELAY                    (0x0C0BU) // TURN-ARROUND DELAY IN BIT-TIMES 0X0000-0X000F
00068 
00069 #define XR_REG_GPIO_SET                         (0x0C0EU) // 1:SET GPIO PIN
00070 
00071 #define XR_REG_GPIO_CLR                         (0x0C0FU) // 1:CLEAR GPIO PIN
00072 
00073 #define XR_REG_GPIO_STATUS                      (0x0C10U) // READ GPIO PINS
00074 
00075 #define XR_REG_CUSTOMISED_INT                   (0x0C12U) // 0:STANDARD 1:CUSTOM SEE DATA SHEET
00076 
00077 #define XR_REG_PIN_PULLUP_ENABLE                (0x0C14U) // 0:DISABLE 1:ENABLE, BITS 0-5:GPIO, 6:RX 7:TX
00078 
00079 #define XR_REG_PIN_PULLDOWN_ENABLE              (0x0C15U) // 0:DISABLE 1:ENABLE, BITS 0-5:GPIO, 6:RX 7:TX
00080 
00081 #define XR_REG_LOOPBACK                         (0x0C16U) // 0:DISABLE 1:ENABLE, SEE DATA SHEET
00082 
00083 #define XR_REG_RX_FIFO_LATENCY                  (0x0CC2U) // FIFO LATENCY REGISTER
00084 #define XR_REG_RX_FIFO_LATENCY_ENABLE           (0x0001U) //
00085 
00086 #define XR_REG_WIDE_MODE                        (0x0D02U)
00087 #define XR_REG_WIDE_MODE_ENABLE                 (0x0001U)
00088 
00089 #define XR_REG_XON_CHAR                         (0x0C07U)
00090 #define XR_REG_XOFF_CHAR                        (0x0C08U)
00091 
00092 #define XR_REG_TX_FIFO_RESET                    (0x0C80U) // 1: RESET, SELF-CLEARING
00093 #define XR_REG_TX_FIFO_COUNT                    (0x0C81U) // READ-ONLY
00094 #define XR_REG_RX_FIFO_RESET                    (0x0CC0U) // 1: RESET, SELF-CLEARING
00095 #define XR_REG_RX_FIFO_COUNT                    (0x0CC1U) // READ-ONLY
00096 
00097 #define XR_WRITE_REQUEST_TYPE                   (0x40U)
00098 
00099 #define XR_READ_REQUEST_TYPE                    (0xC0U)
00100 
00101 #define XR_MAX_ENDPOINTS                        4
00102 
00103 class XR21B1411 : public ACM {
00104 protected:
00105 
00106 public:
00107         XR21B1411(Usb *pusb, CDCAsyncOper *pasync);
00108 
00109         /**
00110          * Used by the USB core to check what this driver support.
00111          * @param  vid The device's VID.
00112          * @param  pid The device's PID.
00113          * @return     Returns true if the device's VID and PID matches this driver.
00114          */
00115         virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
00116                 return (((vid == 0x2890U) && (pid == 0x0201U)) || ((vid == 0x04e2U) && (pid == 0x1411U)));
00117         };
00118 
00119         uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
00120 
00121         virtual tty_features enhanced_features(void) {
00122                 tty_features rv;
00123                 rv.enhanced = true;
00124                 rv.autoflow_RTS = true;
00125                 rv.autoflow_DSR = true;
00126                 rv.autoflow_XON = true;
00127                 rv.half_duplex = true;
00128                 rv.wide = true;
00129                 return rv;
00130         };
00131 
00132         uint8_t read_register(uint16_t reg, uint16_t *val) {
00133                 return (pUsb->ctrlReq(bAddress, 0, XR_READ_REQUEST_TYPE, 1, 0, 0, reg, 2, 2, (uint8_t *)val, NULL));
00134         }
00135 
00136         uint8_t write_register(uint16_t reg, uint16_t val) {
00137                 return (pUsb->ctrlReq(bAddress, 0, XR_WRITE_REQUEST_TYPE, 0, BGRAB0(val), BGRAB1(val), reg, 0, 0, NULL, NULL));
00138         }
00139 
00140 
00141         ////////////////////////////////////////////////////////////////////////
00142         // The following methods set the CDC-ACM defaults.
00143         ////////////////////////////////////////////////////////////////////////
00144 
00145         virtual void autoflowRTS(bool s) {
00146                 uint16_t val;
00147                 uint8_t rval;
00148                 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
00149                 if(!rval) {
00150                         if(s) {
00151                                 val &= XR_REG_FLOW_CTL_HALF_DPLX;
00152                                 val |= XR_REG_FLOW_CTL_HW;
00153                         } else {
00154                                 val &= XR_REG_FLOW_CTL_HALF_DPLX;
00155                         }
00156                         rval = write_register(XR_REG_ACM_FLOW_CTL, val);
00157                         if(!rval) {
00158                                 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
00159                                 if(!rval) {
00160                                         // ACM commands apply the new settings.
00161                                         LINE_CODING LCT;
00162                                         rval = GetLineCoding(&LCT);
00163                                         if(!rval) {
00164                                                 rval = SetLineCoding(&LCT);
00165                                                 if(!rval) {
00166                                                         _enhanced_status.autoflow_XON = false;
00167                                                         _enhanced_status.autoflow_DSR = false;
00168                                                         _enhanced_status.autoflow_RTS = s;
00169                                                 }
00170                                         }
00171                                 }
00172                         }
00173                 }
00174         };
00175 
00176         virtual void autoflowDSR(bool s) {
00177                 uint16_t val;
00178                 uint8_t rval;
00179                 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
00180                 if(!rval) {
00181                         if(s) {
00182                                 val &= XR_REG_FLOW_CTL_HALF_DPLX;
00183                                 val |= XR_REG_FLOW_CTL_HW;
00184                         } else {
00185                                 val &= XR_REG_FLOW_CTL_HALF_DPLX;
00186                         }
00187                         rval = write_register(XR_REG_ACM_FLOW_CTL, val);
00188                         if(!rval) {
00189                                 if(s) {
00190                                         rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_FC_DTRDSR);
00191                                 } else {
00192                                         rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
00193                                 }
00194                                 if(!rval) {
00195                                         // ACM commands apply the new settings.
00196                                         LINE_CODING LCT;
00197                                         rval = GetLineCoding(&LCT);
00198                                         if(!rval) {
00199                                                 rval = SetLineCoding(&LCT);
00200                                                 if(!rval) {
00201                                                         _enhanced_status.autoflow_XON = false;
00202                                                         _enhanced_status.autoflow_RTS = false;
00203                                                         _enhanced_status.autoflow_DSR = s;
00204                                                 }
00205                                         }
00206                                 }
00207                         }
00208                 }
00209         };
00210 
00211         virtual void autoflowXON(bool s) {
00212                 // NOTE: hardware defaults to the normal XON/XOFF
00213                 uint16_t val;
00214                 uint8_t rval;
00215                 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
00216                 if(!rval) {
00217                         if(s) {
00218                                 val &= XR_REG_FLOW_CTL_HALF_DPLX;
00219                                 val |= XR_REG_FLOW_CTL_SW;
00220                         } else {
00221                                 val &= XR_REG_FLOW_CTL_HALF_DPLX;
00222                         }
00223                         rval = write_register(XR_REG_ACM_FLOW_CTL, val);
00224                         if(!rval) {
00225                                 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
00226                                 if(!rval) {
00227                                         // ACM commands apply the new settings.
00228                                         LINE_CODING LCT;
00229                                         rval = GetLineCoding(&LCT);
00230                                         if(!rval) {
00231                                                 rval = SetLineCoding(&LCT);
00232                                                 if(!rval) {
00233                                                         _enhanced_status.autoflow_RTS = false;
00234                                                         _enhanced_status.autoflow_DSR = false;
00235                                                         _enhanced_status.autoflow_XON = s;
00236                                                 }
00237                                         }
00238                                 }
00239                         }
00240                 }
00241         };
00242 
00243         virtual void half_duplex(bool s) {
00244                 uint16_t val;
00245                 uint8_t rval;
00246                 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
00247                 if(!rval) {
00248                         if(s) {
00249                                 val |= XR_REG_FLOW_CTL_HALF_DPLX;
00250                         } else {
00251                                 val &= XR_REG_FLOW_CTL_MODE_MASK;
00252                         }
00253                         rval = write_register(XR_REG_ACM_FLOW_CTL, val);
00254                         if(!rval) {
00255                                 // ACM commands apply the new settings.
00256                                 LINE_CODING LCT;
00257                                 rval = GetLineCoding(&LCT);
00258                                 if(!rval) {
00259                                         rval = SetLineCoding(&LCT);
00260                                         if(!rval) {
00261                                                 _enhanced_status.half_duplex = s;
00262                                         }
00263                                 }
00264                         }
00265                 }
00266         };
00267 
00268 
00269 
00270 };
00271 
00272 #endif // __CDCPROLIFIC_H__