enc28j60_reg.h

00001 /*****************************************************************************
00002 *
00003 * Title         : Microchip ENC28J60 Ethernet Controller Registers
00004 * Author        : Pascal Stang (c)2005
00005 * Modified by   : Tobias Jaster
00006 * Modified by   : Zoltan Hudak
00007 * Copyright     : GPL V2
00008 *
00009 *This driver provides initialization and transmit/receive
00010 *functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY.
00011 *This chip is novel in that it is a full MAC+PHY interface all in a 28-pin
00012 *chip, using an SPI interface to the host processor.
00013 *
00014 *
00015 *****************************************************************************/
00016 #ifndef ENC28J60_REG_H
00017 #define ENC28J60_REG_H
00018 #include <inttypes.h>
00019 #include "enc28j60_emac_config.h"
00020 
00021 // ENC28J60 Control Registers
00022 
00023 // Control register definitions are a combination of address,
00024 // bank number, and Ethernet/MAC/PHY indicator bits.
00025 // - Register address       (bits 0-4)
00026 // - Bank number            (bits 5-6)
00027 // - MAC/PHY indicator      (bit 7)
00028 #define ADDR_MASK   0x1F
00029 #define BANK_MASK   0x60
00030 #define SPRD_MASK   0x80
00031 // All-bank registers
00032 #define EIE     0x1B                        // ETHERNET INTERRUPT ENABLE REGISTER
00033 #define EIR     0x1C                        // ETHERNET INTERRUPT REQUEST (FLAG) REGISTER
00034 #define ESTAT   0x1D                        // ETHERNET STATUS REGISTER
00035 #define ECON2   0x1E                        // ETHERNET CONTROL REGISTER 2
00036 #define ECON1   0x1F                        // ETHERNET CONTROL REGISTER 1
00037 
00038 /*
00039  * Bank 0 registers
00040  */
00041 
00042 // Points to a location in receive/transmit buffer to read from
00043 #define ERDPTL  (0x00 | 0x00)               // Ethernet buffer Read Pointer Low Byte (ERDPT<7:0>)
00044 #define ERDPTH  (0x01 | 0x00)               // Ethernet buffer Read Pointer High Byte (ERDPT<12:8>)
00045 
00046 // Points to a location in receive/transmit buffer to write to
00047 #define EWRPTL  (0x02 | 0x00)               // Ethernet buffer Write Pointer Low Byte (EWRPT<7:0>)
00048 #define EWRPTH  (0x03 | 0x00)               // Ethernet buffer Write Pointer High Byte (EWRPT<12:8>)
00049 
00050 // Pointers to transmit buffer boundaries
00051 #define ETXSTL  (0x04 | 0x00)               // Ethernet Transmit buffer Start Low Byte (ETXST<7:0>)
00052 #define ETXSTH  (0x05 | 0x00)               // Ethernet Transmit buffer Start High Byte (ETXST<12:8>)
00053 #define ETXNDL  (0x06 | 0x00)               // Ethernet Transmit buffer End Low Byte (ETXND<7:0>)
00054 #define ETXNDH  (0x07 | 0x00)               // Ethernet Transmit buffer End High Byte (ETXND<12:8>)
00055 
00056 // Pointers to receive buffer boundaries
00057 #define ERXSTL  (0x08 | 0x00)               // Ethernet Receive buffer Start Low Byte (ERXST<7:0>)
00058 #define ERXSTH  (0x09 | 0x00)               // Ethernet Receive buffer Start High Byte (ERXST<12:8>)
00059 #define ERXNDL  (0x0A | 0x00)               // Ethernet Receive buffer End Low Byte (ERXND<7:0>)
00060 #define ERXNDH  (0x0B | 0x00)               // Ethernet Receive buffer End High Byte (ERXND<12:8>)
00061 
00062 // Receive pointer. Receive hardware will write data up to, but not including the memory pointed to by ERXRDPT
00063 #define ERXRDPTL    (0x0C | 0x00)           // Ethernet Receive buffer RD Pointer Low Byte (ERXRDPT<7:0>)
00064 #define ERXRDPTH    (0x0D | 0x00)           // Ethernet Receive buffer RD Pointer High Byte (ERXRDPT<12:8>)
00065 
00066 // Location within the receive buffer where the hardware will write bytes that it receives.
00067 // The pointer is read-only and is automatically updated by the hardware whenever
00068 // a new packet is successfully received.
00069 #define ERXWRPTL    (0x0E | 0x00)           // Ethernet Receive buffer WR Pointer Low Byte (ERXWRPT<7:0>)   Read-only
00070 #define ERXWRPTH    (0x0F | 0x00)           // Ethernet Receive buffer WR Pointer High Byte (ERXWRPT<12:8>) Read-only
00071 
00072 // Pointers to DMA boundaries
00073 #define EDMASTL (0x10 | 0x00)               // Ethernet buffer DMA Start Low Byte (EDMAST<7:0>)
00074 #define EDMASTH (0x11 | 0x00)               // Ethernet buffer DMA Start High Byte (EDMAST<12:8>)
00075 #define EDMANDL (0x12 | 0x00)               // Ethernet buffer DMA End Low Byte (EDMAND<7:0>)
00076 #define EDMANDH (0x13 | 0x00)               // Ethernet buffer DMA End High Byte (EDMAND<12:8>)
00077 
00078 // Points to the DMA memory copying destination in receive/transmit buffer
00079 #define EDMADSTL    (0x14 | 0x00)           // Ethernet buffer DMA Destination Low Byte (EDMADST<7:0>)
00080 #define EDMADSTH    (0x15 | 0x00)           // Ethernet buffer DMA Destination High Byte (EDMADST<12:8>)
00081 
00082 // Points to the DMA check sum calcularion location in receive/transmit buffer
00083 #define EDMACSL (0x16 | 0x00)               // Ethernet buffer DMA Checksum Low Byte (EDMACS<7:0>)
00084 #define EDMACSH (0x17 | 0x00)               // Ethernet buffer DMA Checksum High Byte (EDMACS<15:8>)
00085 
00086 /*
00087  * Bank 1 registers
00088  */
00089 #define EHT0    (0x00 | 0x20)               //Hash Table Byte 0 (EHT<7:0>)
00090 #define EHT1    (0x01 | 0x20)               //Hash Table Byte 0 (EHT<7:0>)
00091 #define EHT2    (0x02 | 0x20)               //Hash Table Byte 0 (EHT<7:0>)
00092 #define EHT3    (0x03 | 0x20)               //Hash Table Byte 3 (EHT<31:24>)
00093 #define EHT4    (0x04 | 0x20)               //Hash Table Byte 3 (EHT<31:24>)
00094 #define EHT5    (0x05 | 0x20)               //Hash Table Byte 3 (EHT<31:24>)
00095 #define EHT6    (0x06 | 0x20)               //Hash Table Byte 3 (EHT<31:24>)
00096 #define EHT7    (0x07 | 0x20)               //Hash Table Byte 3 (EHT<31:24>)
00097 #define EPMM0   (0x08 | 0x20)               //Pattern Match Mask Byte 0 (EPMM<7:0>)
00098 #define EPMM1   (0x09 | 0x20)               //Pattern Match Mask Byte 1 (EPMM<15:8>)
00099 #define EPMM2   (0x0A | 0x20)               //Pattern Match Mask Byte 2 (EPMM<23:16>)
00100 #define EPMM3   (0x0B | 0x20)               //Pattern Match Mask Byte 3 (EPMM<31:24>)
00101 #define EPMM4   (0x0C | 0x20)               //Pattern Match Mask Byte 4 (EPMM<39:32>)
00102 #define EPMM5   (0x0D | 0x20)               //Pattern Match Mask Byte 5 (EPMM<47:40>)
00103 #define EPMM6   (0x0E | 0x20)               //Pattern Match Mask Byte 6 (EPMM<55:48>)
00104 #define EPMM7   (0x0F | 0x20)               //Pattern Match Mask Byte 7 (EPMM<63:56>)
00105 #define EPMCSL  (0x10 | 0x20)               //Pattern Match Checksum Low Byte (EPMCS<7:0>)
00106 #define EPMCSH  (0x11 | 0x20)               //Pattern Match Checksum High Byte (EPMCS<15:0>)
00107 #define EPMOL   (0x14 | 0x20)               //Pattern Match Offset Low Byte (EPMO<7:0>)
00108 #define EPMOH   (0x15 | 0x20)               //Pattern Match Offset High Byte (EPMO<12:8>)
00109 #define EWOLIE  (0x16 | 0x20)               //Reserved
00110 #define EWOLIR  (0x17 | 0x20)               //Reserved
00111 #define ERXFCON (0x18 | 0x20)               //ETHERNET RECEIVE FILTER CONTROL REGISTER
00112 #define EPKTCNT (0x19 | 0x20)               //Ethernet Packet Count
00113 
00114 /*
00115  * Bank 2 registers
00116  */
00117 #define MACON1      (0x00 | 0x40 | 0x80)    //MAC CONTROL REGISTER 1
00118 #define MACON2      (0x01 | 0x40 | 0x80)    //MAC CONTROL REGISTER 2
00119 #define MACON3      (0x02 | 0x40 | 0x80)    //MAC CONTROL REGISTER 3
00120 #define MACON4      (0x03 | 0x40 | 0x80)    //MAC CONTROL REGISTER 4
00121 #define MABBIPG     (0x04 | 0x40 | 0x80)    //Back-to-Back Inter-Packet Gap (BBIPG<6:0>)
00122 #define MAIPGL      (0x06 | 0x40 | 0x80)    //Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>)
00123 #define MAIPGH      (0x07 | 0x40 | 0x80)    //Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>)
00124 #define MACLCON1    (0x08 | 0x40 | 0x80)    //Retransmission Maximum (RETMAX<3:0>)
00125 #define MACLCON2    (0x09 | 0x40 | 0x80)    //Collision Window (COLWIN<5:0>
00126 #define MAMXFLL     (0x0A | 0x40 | 0x80)    //Maximum Frame Length Low Byte (MAMXFL<7:0>)
00127 #define MAMXFLH     (0x0B | 0x40 | 0x80)    //Maximum Frame Length High Byte (MAMXFL<15:8>)
00128 #define MAPHSUP     (0x0D | 0x40 | 0x80)    //Reserved
00129 #define MICON       (0x11 | 0x40 | 0x80)    //Reserved
00130 #define MICMD       (0x12 | 0x40 | 0x80)    //MII COMMAND REGISTER
00131 #define MIREGADR    (0x14 | 0x40 | 0x80)    //MII Register Address (MIREGADR<4:0>)
00132 #define MIWRL       (0x16 | 0x40 | 0x80)    //MII Write Data Low Byte (MIWR<7:0>)
00133 #define MIWRH       (0x17 | 0x40 | 0x80)    //MII Write Data High Byte (MIWR<15:8>)
00134 #define MIRDL       (0x18 | 0x40 | 0x80)    //MII Read Data Low Byte (MIRD<7:0>)
00135 #define MIRDH       (0x19 | 0x40 | 0x80)    //MII Read Data High Byte(MIRD<15:8>)
00136 
00137 /*
00138  * Bank 3 registers
00139  */
00140 #define MAADR1  (0x00 | 0x60 | 0x80)        //MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1
00141 #define MAADR0  (0x01 | 0x60 | 0x80)        //MAC Address Byte 2 (MAADR<39:32>), OUI Byte 2
00142 #define MAADR3  (0x02 | 0x60 | 0x80)        //MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3
00143 #define MAADR2  (0x03 | 0x60 | 0x80)        //MAC Address Byte 4 (MAADR<23:16>)
00144 #define MAADR5  (0x04 | 0x60 | 0x80)        //MAC Address Byte 5 (MAADR<15:8>)
00145 #define MAADR4  (0x05 | 0x60 | 0x80)        //MAC Address Byte 4 (MAADR<23:16>)
00146 #define EBSTSD  (0x06 | 0x60)               //Built-in Self-Test Fill Seed (EBSTSD<7:0>)
00147 #define EBSTCON (0x07 | 0x60)               //
00148 #define EBSTCSL (0x08 | 0x60)               //Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>)
00149 #define EBSTCSH (0x09 | 0x60)               //Built-in Self-Test Checksum High Byte (EBSTCS<15:8>)
00150 #define MISTAT  (0x0A | 0x60 | 0x80)        //MII STATUS REGISTER
00151 #define EREVID  (0x12 | 0x60)               //Ethernet Revision ID (EREVID<4:0>)
00152 #define ECOCON  (0x15 | 0x60)               //CLOCK OUTPUT CONTROL REGISTER
00153 #define EFLOCON (0x17 | 0x60)               //ETHERNET FLOW CONTROL REGISTER
00154 #define EPAUSL  (0x18 | 0x60)               //Pause Timer Value Low Byte (EPAUS<7:0>)
00155 #define EPAUSH  (0x19 | 0x60)               //Pause Timer Value High Byte (EPAUS<15:8>)
00156 
00157 /*
00158  * PHY registers
00159  */
00160 #define PHCON1  0x00                        //PHY CONTROL REGISTER 1
00161 #define PHSTAT1 0x01                        //PHYSICAL LAYER STATUS REGISTER 1
00162 #define PHHID1  0x02                        //
00163 #define PHHID2  0x03                        //
00164 #define PHCON2  0x10                        //PHY CONTROL REGISTER 2
00165 #define PHSTAT2 0x11                        //PHYSICAL LAYER STATUS REGISTER 2
00166 #define PHIE    0x12                        //PHY INTERRUPT ENABLE REGISTER
00167 #define PHIR    0x13                        //PHY INTERRUPT REQUEST (FLAG) REGISTER
00168 #define PHLCON  0x14                        //PHY MODULE LED CONTROL REGISTER
00169 
00170 /*
00171  * ENC28J60 ERXFCON Register Bit Definitions
00172  */
00173 #define ERXFCON_UCEN    0x80
00174 #define ERXFCON_ANDOR   0x40
00175 #define ERXFCON_CRCEN   0x20
00176 #define ERXFCON_PMEN    0x10
00177 #define ERXFCON_MPEN    0x08
00178 #define ERXFCON_HTEN    0x04
00179 #define ERXFCON_MCEN    0x02
00180 #define ERXFCON_BCEN    0x01
00181 /*
00182  * ENC28J60 EIE Register Bit Definitions
00183  */
00184 #define EIE_INTIE   0x80
00185 #define EIE_PKTIE   0x40
00186 #define EIE_DMAIE   0x20
00187 #define EIE_LINKIE  0x10
00188 #define EIE_TXIE    0x08
00189 #define EIE_WOLIE   0x04
00190 #define EIE_TXERIE  0x02
00191 #define EIE_RXERIE  0x01
00192 /*
00193  * ENC28J60 EIR Register Bit Definitions
00194  */
00195 #define EIR_PKTIF   0x40                    // Receive Packet Pending Interrupt Flag bit
00196 #define EIR_DMAIF   0x20                    // DMA Interrupt Flag bit
00197 #define EIR_LINKIF  0x10                    // Link Change Interrupt Flag bit
00198 #define EIR_TXIF    0x08                    // Transmit Interrupt Flag bit
00199 #define EIR_WOLIF   0x04
00200 #define EIR_TXERIF  0x02                    // Transmit Error Interrupt Flag bit
00201 #define EIR_RXERIF  0x01                    // Receive Error Interrupt Flag bit
00202 
00203 /*
00204  * ENC28J60 ESTAT Register Bit Definitions
00205  */
00206 #define ESTAT_INT       0x80                // INT Interrupt Flag bit (INT interrupt is pending)
00207 #define ESTAT_BUFER     0x40                // Ethernet Buffer Error Status bit
00208 #define ESTAT_LATECOL   0x10                // Late Collision Error bit
00209 #define ESTAT_RXBUSY    0x04                // Receive Busy bit
00210 #define ESTAT_TXABRT    0x02                // Transmit Abort Error bit
00211 #define ESTAT_CLKRDY    0x01                // Clock Ready bit
00212 
00213 /*
00214  * ENC28J60 ECON2 Register Bit Definitions
00215  */
00216 #define ECON2_AUTOINC   0x80
00217 #define ECON2_PKTDEC    0x40
00218 #define ECON2_PWRSV     0x20
00219 #define ECON2_VRPS      0x08
00220 /*
00221  * ENC28J60 ECON1 Register Bit Definitions
00222  */
00223 #define ECON1_TXRST     0x80
00224 #define ECON1_RXRST     0x40
00225 #define ECON1_DMAST     0x20
00226 #define ECON1_CSUMEN    0x10
00227 #define ECON1_TXRTS     0x08
00228 #define ECON1_RXEN      0x04
00229 #define ECON1_BSEL1     0x02
00230 #define ECON1_BSEL0     0x01
00231 /*
00232  * ENC28J60 MACON1 Register Bit Definitions
00233  */
00234 #define MACON1_LOOPBK   0x10
00235 #define MACON1_TXPAUS   0x08
00236 #define MACON1_RXPAUS   0x04
00237 #define MACON1_PASSALL  0x02
00238 #define MACON1_MARXEN   0x01
00239 /*
00240  * ENC28J60 MACON2 Register Bit Definitions
00241  */
00242 #define MACON2_MARST    0x80
00243 #define MACON2_RNDRST   0x40
00244 #define MACON2_MARXRST  0x08
00245 #define MACON2_RFUNRST  0x04
00246 #define MACON2_MATXRST  0x02
00247 #define MACON2_TFUNRST  0x01
00248 /*
00249  * ENC28J60 MACON3 Register Bit Definitions
00250  */
00251 #define MACON3_PADCFG2  0x80
00252 #define MACON3_PADCFG1  0x40
00253 #define MACON3_PADCFG0  0x20
00254 #define MACON3_TXCRCEN  0x10
00255 #define MACON3_PHDRLEN  0x08
00256 #define MACON3_HFRMLEN  0x04
00257 #define MACON3_FRMLNEN  0x02
00258 #define MACON3_FULDPX   0x01
00259 /*
00260  * ENC28J60 MACON4 Register Bit Definitions
00261  */
00262 #define MACON4_DEFER    0x40
00263 #define MACON4_BPEN     0x20
00264 #define MACON4_NOBKOFF  0x10
00265 /*
00266  * ENC28J60 MICMD Register Bit Definitions
00267  */
00268 #define MICMD_MIISCAN   0x02
00269 #define MICMD_MIIRD     0x01
00270 /*
00271  * ENC28J60 MISTAT Register Bit Definitions
00272  */
00273 #define MISTAT_NVALID   0x04
00274 #define MISTAT_SCAN     0x02
00275 #define MISTAT_BUSY     0x01
00276 /*
00277  * ENC28J60 PHY PHCON1 Register Bit Definitions
00278  */
00279 #define PHCON1_PRST     0x8000
00280 #define PHCON1_PLOOPBK  0x4000
00281 #define PHCON1_PPWRSV   0x0800
00282 #define PHCON1_PDPXMD   0x0100
00283 /*
00284  * ENC28J60 PHY PHSTAT1 Register Bit Definitions
00285  */
00286 #define PHSTAT1_PFDPX   0x1000
00287 #define PHSTAT1_PHDPX   0x0800
00288 #define PHSTAT1_LLSTAT  0x0004
00289 #define PHSTAT1_JBSTAT  0x0002
00290 /*
00291  * ENC28J60 PHY PHSTAT2 Register Bit Definitions
00292  */
00293 #define PHSTAT2_TXSTAT  0x2000
00294 #define PHSTAT2_RXSTAT  0x1000
00295 #define PHSTAT2_COLSTAT 0x0800
00296 #define PHSTAT2_LSTAT   0x0400
00297 #define PHSTAT2_DPXSTAT 0x0200
00298 #define PHSTAT2_PLRITY  0x0020
00299 /*
00300  * ENC28J60 PHY PHCON2 Register Bit Definitions
00301  */
00302 #define PHCON2_FRCLINK  0x4000
00303 #define PHCON2_TXDIS    0x2000
00304 #define PHCON2_JABBER   0x0400
00305 #define PHCON2_HDLDIS   0x0100
00306 /*
00307  * ENC28J60 PHY PHIE Register Bit Definitions
00308  */
00309 #define PHIE_PLNKIE 0x0010
00310 #define PHIE_PGEIE  0x0002
00311 /*
00312  * ENC28J60 Packet Control Byte Bit Definitions
00313  */
00314 #define PKTCTRL_PHUGEEN     0x08
00315 #define PKTCTRL_PPADEN      0x04
00316 #define PKTCTRL_PCRCEN      0x02
00317 #define PKTCTRL_POVERRIDE   0x01
00318 /*
00319  * SPI operation codes
00320  */
00321 #define ENC28J60_READ_CTRL_REG  0x00
00322 #define ENC28J60_READ_BUF_MEM   0x3A
00323 #define ENC28J60_WRITE_CTRL_REG 0x40
00324 #define ENC28J60_WRITE_BUF_MEM  0x7A
00325 #define ENC28J60_BIT_FIELD_SET  0x80
00326 #define ENC28J60_BIT_FIELD_CLR  0xA0
00327 #define ENC28J60_SOFT_RESET     0xFF
00328 
00329 // The ERXST_INI should be zero. See Silicon Errata:
00330 
00331 // Sometimes, when ERXST or ERXND is written to, the exact value, 0000h, is stored in the Internal
00332 // Receive Write Pointer instead of the ERXST address.
00333 // Workaround:
00334 // Use the lower segment of the buffer memory for the receive buffer, starting at address 0000h.
00335 // Use the range (0000h to n) for the receive buffer, and ((n + 1) to 8191) for the transmit buffer.
00336 #define ERXST_INI   0x0000U
00337 
00338 // RX buffer end. Make sure this is an odd value ( See Rev. B1,B4,B5,B7 Silicon Errata 'Memory (Ethernet Buffer)')
00339 #define ERXND_INI   (ENC28J60_ETH_RXBUF_SIZE_KB * 1024 - 1)
00340 
00341 // TX buffer start.
00342 #define ETXST_INI   (ERXND_INI + 1)
00343 
00344 // TX buffer end at end of ethernet buffer memory.
00345 #define ETXND_INI   0x1FFF
00346 
00347 // max frame length which the conroller will accept:
00348 #define MAX_FRAMELEN    ENC28J60_ETH_MTU_SIZE   // (note: maximum ethernet frame length would be 1518)
00349 
00350 #define RX_NEXT_LEN 2U  // next packet pointer bytes
00351 #define RX_STAT_LEN 4U  // receive status vector bytes
00352 #define RX_CRC_LEN  4U  // CRC bytes
00353 #define TX_CTRL_LEN 1U  // control byte
00354 #define TX_STAT_LEN 7U  // transmit status vector bytes
00355 
00356 #endif //ENC28J60_REG_H