enc28j60.h

00001 /*
00002  * Copyright (c) 2019 Tobias Jaster
00003  *
00004  * Modified by Zoltan Hudak
00005  *
00006  * Licensed under the Apache License, Version 2.0 (the "License");
00007  * you may not use this file except in compliance with the License.
00008  * You may obtain a copy of the License at
00009  *
00010  *     http://www.apache.org/licenses/LICENSE-2.0
00011  *
00012  * Unless required by applicable law or agreed to in writing, software
00013  * distributed under the License is distributed on an "AS IS" BASIS,
00014  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00015  * See the License for the specific language governing permissions and
00016  * limitations under the License.
00017  */
00018 #ifndef ENC28J60_ETH_DRV_H_
00019 #define ENC28J60_ETH_DRV_H_
00020 
00021 #include "mbed.h"
00022 #include "enc28j60_reg.h"
00023 #include "enc28j60_emac_config.h"
00024 
00025 #define ENC28J60_READWRITE  1
00026 
00027 /**
00028  * \brief Error code definitions
00029  *
00030  */
00031 typedef struct
00032 {
00033     uint8_t*    buf;
00034     uint16_t    len;
00035 } payload_t;
00036 
00037 typedef struct
00038 {
00039     uint32_t    addr;
00040     payload_t   payload;
00041 } packet_t;
00042 
00043 /**
00044  * \brief Error code definitions
00045  *
00046  */
00047 typedef enum
00048 {
00049     ENC28J60_ERROR_OK               = 0U,   /*!< no error */
00050     ENC28J60_ERROR_TIMEOUT          = 1U,   /*!< timeout */
00051     ENC28J60_ERROR_BUSY             = 2U,   /*!< no error */
00052     ENC28J60_ERROR_PARAM            = 3U,   /*!< invalid parameter */
00053     ENC28J60_ERROR_INTERNAL         = 4U,   /*!< internal error */
00054     ENC28J60_ERROR_WRONG_ID         = 5U,   /*!< internal error */
00055     ENC28J60_ERROR_NOPACKET         = 10U,
00056     ENC28J60_ERROR_RECEIVE          = 11U,
00057     ENC28J60_ERROR_LASTPACKET       = 12U,
00058     ENC28J60_ERROR_POSITIONLENGTH   = 13U,  /*!< internal error */
00059     ENC28J60_ERROR_SIZE             = 20U,  /*!< internal error */
00060     ENC28J60_ERROR_FIFOFULL         = 21U,  /*!< internal error */
00061     ENC28J60_ERROR_NEXTPACKET       = 22U,  /*!< internal error */
00062 } enc28j60_error_t;
00063 
00064 /**
00065  * \brief Interrupt source definitions
00066  *
00067  */
00068 typedef enum
00069 {
00070     ENC28J60_INTERRUPT_ENABLE           = EIE_INTIE,
00071     ENC28J60_INTERRUPT_RX_PENDING_ENABLE= EIE_PKTIE,
00072     ENC28J60_INTERRUPT_DMA_ENABLE       = EIE_DMAIE,
00073     ENC28J60_INTERRUPT_LINK_STATE_ENABLE= EIE_LINKIE,
00074     ENC28J60_INTERRUPT_TX_ENABLE        = EIE_TXIE,
00075     ENC28J60_INTERRUPT_TX_ERROR_ENABLE  = EIE_TXERIE,
00076     ENC28J60_INTERRUPT_RX_ERROR_ENABLE  = EIE_RXERIE
00077 } enc28j60_interrupt_source;
00078 
00079 class   ENC28J60
00080 {
00081 public:
00082     ENC28J60(PinName mosi, PinName miso, PinName sclk, PinName cs);
00083 
00084     ENC28J60(mbed::SPI * spi, PinName cs);
00085 
00086     /**
00087      * \brief Initializes ENC28J60 Ethernet controller to a known default state:
00088      *          - device ID is checked
00089      *          - global interrupt is enabled, but all irq sources are disabled
00090      *          - Establish link enabled
00091      *          - Rx enabled
00092      *          - Tx enabled
00093      *        Init should be called prior to any other process and
00094      *        it's the caller's responsibility to follow proper call order.
00095      *
00096      * \return error code /ref enc28j60_error_t
00097      */
00098     void                init(void);
00099 
00100     /** This returns a unique 6-byte MAC address, based on the device UID
00101     *  This function overrides hal/common/mbed_interface.c function
00102     *  @param mac A 6-byte array to write the MAC address
00103     */
00104     void                mbed_mac_address(char* mac);
00105     MBED_WEAK uint8_t   mbed_otp_mac_address(char* mac);
00106     void                mbed_default_mac_address(char* mac);
00107 
00108     /**
00109      * \brief Initiates a soft reset, returns failure or success.
00110      *
00111      * \return error code /ref enc28j60_error_t
00112      */
00113     enc28j60_error_t    softReset(void);
00114 
00115     /**
00116      * \brief Set maximum transition unit by Rx fifo size.
00117      *        Note: The MTU will be smaller by 512 bytes,
00118      *        because the status uses this fixed space.
00119      *
00120      * \param[in] val Size of the fifo in kbytes
00121      */
00122     void                setRxBufSize(uint32_t val);
00123 
00124     /**
00125      * \brief Reset PHY
00126      *
00127      * \return error code /ref enc28j60_error_t
00128      */
00129     enc28j60_error_t    resetPhy(void);
00130 
00131     /**
00132      * \brief Enable receive
00133      */
00134     void                enableMacRecv(void);
00135 
00136     /**
00137      * \brief Disable receive
00138      */
00139     void                disableMacRecv(void);
00140 
00141     /**
00142      * \brief Read MAC address from EEPROM.
00143      *
00144      * \param[in,out] mac array will include the read MAC address in
00145      *                6 bytes hexadecimal format.
00146      *                It should be allocated by the caller to 6 bytes.
00147      *
00148      * \return error code /ref enc28j60_error_t
00149      */
00150     enc28j60_error_t    readMacAddr(char* mac);
00151 
00152     /**
00153      * \brief Write MAC address to EEPROM.
00154      *
00155      * \param[in,out] mac array will include the write MAC address in
00156      *                6 bytes hexadecimal format.
00157      *                It should be allocated by the caller to 6 bytes.
00158      *
00159      * \return error code /ref enc28j60_error_t
00160      */
00161     enc28j60_error_t    writeMacAddr(char* mac);
00162 
00163     /**
00164      * \brief Check device ID.
00165      *
00166      * \return error code /ref enc28j60_error_t
00167      */
00168     bool                check_id(void);
00169 
00170     /**
00171      * \brief Get the data size of the Rx buffer, aka Maximum Transition Unit
00172      *
00173      * \return Fifo data size in bytes
00174      */
00175     enc28j60_error_t    setWritePrt(uint16_t position, uint16_t offset);
00176     enc28j60_error_t    transmitPacket(packet_t* packet);
00177     enc28j60_error_t    loadPacketInTxBuffer(packet_t* packet);
00178 
00179     /**
00180      * \brief Get the free space of Rx fifo in bytes.
00181      *
00182      * \param[in] dev Ethernet device structure \ref enc28j60_eth_dev_t
00183      *
00184      * \return Space available to store received data in bytes
00185      */
00186     uint32_t            getRxBufFreeSpace(void);
00187 
00188     /**
00189      * \brief Get the size of next unread packet in Rx buffer, using the peak
00190      *        register, which is not destructive so can be read asynchronously.
00191      *        Warning: In case of heavy receiving load, it's possible this register
00192      *        is not perfectly in sync.
00193      *
00194      * \param[in] dev Ethernet device structure \ref enc28j60_eth_dev_t
00195      *
00196      * \return Size in bytes of the next packet can be read from Rx fifo, according
00197      *         to the peek register.
00198      */
00199     enc28j60_error_t    setRxBufReadPtr(uint16_t position);
00200     enc28j60_error_t    getPacketInfo(packet_t* packet);
00201     void                readPacket(packet_t* packet);
00202     void                freeRxBuffer(void);
00203     uint16_t            getRecvPointer(void);
00204     uint16_t            getWritePointer(void);
00205     void                readBuf(uint8_t* data, uint16_t len);
00206     void                writeBuf(uint8_t* data, uint16_t len);
00207     uint8_t             readReg(uint8_t address);
00208     uint16_t            readRegPair(uint8_t address);
00209     void                writeReg(uint8_t address, uint8_t data);
00210     void                writeRegPair(uint8_t address, uint16_t data);
00211     enc28j60_error_t    phyRead(uint8_t address, uint16_t* data);
00212     enc28j60_error_t    phyWrite(uint8_t address, uint16_t data);
00213     bool                linkStatus(void);
00214     uint8_t             readOp(uint8_t op, uint8_t address);
00215     void                writeOp(uint8_t op, uint8_t address, uint8_t data);
00216 private:
00217     void        _setBank(uint8_t address);
00218     void        _read(uint8_t cmd, uint8_t* buf, uint16_t len, bool blocking);
00219     void        _write(uint8_t cmd, uint8_t* buf, uint16_t len, bool blocking);
00220 #ifdef ENC28J60_READWRITE
00221     void        _readwrite(uint8_t cmd, uint8_t* readbuf, uint8_t* writebuf, uint16_t len, bool blocking);
00222 #endif
00223     SPI*        _spi;
00224     Mutex       _SPIMutex;
00225     DigitalOut  _cs;
00226     uint8_t     _bank;
00227     bool        _ready;
00228     uint32_t    _next;
00229 };
00230 #endif /* ENC28J60_ETH_DRV_H_ */