Henrique Rosa
/
ILI9341_01_PAR8_Teste_V5
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Revision 1:a5ccd53612ea, committed 2021-04-21
- Comitter:
- silviosz
- Date:
- Wed Apr 21 14:54:37 2021 +0000
- Parent:
- 0:d4d4998d71d5
- Child:
- 2:f603020cd6ec
- Commit message:
- ILI9341 display controller; parallel connection (Arduino Shield); NUCLEO-F103RB tested (2021-04-21) = success!
Changed in this revision
--- a/ADA_GFX_kbv.lib Wed Apr 21 14:47:37 2021 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1 +0,0 @@ -https://os.mbed.com/teams/Sz_Insper/code/ADA_GFX_kbv/#60f1bd43fe2e
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/ADA_GFX_kbv/ADA_GFX_kbv.cpp Wed Apr 21 14:54:37 2021 +0000
@@ -0,0 +1,506 @@
+
+// link:
+// https://os.mbed.com/users/davidprentice/code/Nucleo_dir_L152//file/d88d2ad55fac/ADA_GFX_kbv/ADA_GFX_kbv.cpp/
+// Committer: davidprentice
+// Date: 19 months ago
+// 2021-04-21
+//
+// ADA_GFX_kbv.cpp
+//
+/*
+This is the core graphics library for all our displays, providing a common
+set of graphics primitives (points, lines, circles, etc.). It needs to be
+paired with a hardware-specific library for each display device we carry
+(to handle the lower-level functions).
+
+Adafruit invests time and resources providing this open source code, please
+support Adafruit & open-source hardware by purchasing products from Adafruit!
+
+Copyright (c) 2013 Adafruit Industries. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+- Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+- Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include "ADA_GFX_kbv.h"
+#ifdef __AVR__
+ #include <avr/pgmspace.h>
+#else
+ #define pgm_read_byte(addr) (*(const unsigned char *)(addr))
+ #define PROGMEM
+#endif
+#include "glcdfont.inc"
+
+Adafruit_GFX::Adafruit_GFX(int16_t w, int16_t h):
+ WIDTH(w), HEIGHT(h)
+{
+ _width = WIDTH;
+ _height = HEIGHT;
+ rotation = 0;
+ cursor_y = cursor_x = 0;
+ textsize = 1;
+ textcolor = textbgcolor = 0xFFFF;
+ wrap = true;
+}
+
+// Draw a circle outline
+void Adafruit_GFX::drawCircle(int16_t x0, int16_t y0, int16_t r,
+ uint16_t color) {
+ int16_t f = 1 - r;
+ int16_t ddF_x = 1;
+ int16_t ddF_y = -2 * r;
+ int16_t x = 0;
+ int16_t y = r;
+
+ drawPixel(x0 , y0+r, color);
+ drawPixel(x0 , y0-r, color);
+ drawPixel(x0+r, y0 , color);
+ drawPixel(x0-r, y0 , color);
+
+ while (x<y) {
+ if (f >= 0) {
+ y--;
+ ddF_y += 2;
+ f += ddF_y;
+ }
+ x++;
+ ddF_x += 2;
+ f += ddF_x;
+
+ drawPixel(x0 + x, y0 + y, color);
+ drawPixel(x0 - x, y0 + y, color);
+ drawPixel(x0 + x, y0 - y, color);
+ drawPixel(x0 - x, y0 - y, color);
+ drawPixel(x0 + y, y0 + x, color);
+ drawPixel(x0 - y, y0 + x, color);
+ drawPixel(x0 + y, y0 - x, color);
+ drawPixel(x0 - y, y0 - x, color);
+ }
+}
+
+void Adafruit_GFX::drawCircleHelper( int16_t x0, int16_t y0,
+ int16_t r, uint8_t cornername, uint16_t color) {
+ int16_t f = 1 - r;
+ int16_t ddF_x = 1;
+ int16_t ddF_y = -2 * r;
+ int16_t x = 0;
+ int16_t y = r;
+
+ while (x<y) {
+ if (f >= 0) {
+ y--;
+ ddF_y += 2;
+ f += ddF_y;
+ }
+ x++;
+ ddF_x += 2;
+ f += ddF_x;
+ if (cornername & 0x4) {
+ drawPixel(x0 + x, y0 + y, color);
+ drawPixel(x0 + y, y0 + x, color);
+ }
+ if (cornername & 0x2) {
+ drawPixel(x0 + x, y0 - y, color);
+ drawPixel(x0 + y, y0 - x, color);
+ }
+ if (cornername & 0x8) {
+ drawPixel(x0 - y, y0 + x, color);
+ drawPixel(x0 - x, y0 + y, color);
+ }
+ if (cornername & 0x1) {
+ drawPixel(x0 - y, y0 - x, color);
+ drawPixel(x0 - x, y0 - y, color);
+ }
+ }
+}
+
+void Adafruit_GFX::fillCircle(int16_t x0, int16_t y0, int16_t r,
+ uint16_t color) {
+ drawFastVLine(x0, y0-r, 2*r+1, color);
+ fillCircleHelper(x0, y0, r, 3, 0, color);
+}
+
+// Used to do circles and roundrects
+void Adafruit_GFX::fillCircleHelper(int16_t x0, int16_t y0, int16_t r,
+ uint8_t cornername, int16_t delta, uint16_t color) {
+
+ int16_t f = 1 - r;
+ int16_t ddF_x = 1;
+ int16_t ddF_y = -2 * r;
+ int16_t x = 0;
+ int16_t y = r;
+
+ while (x<y) {
+ if (f >= 0) {
+ y--;
+ ddF_y += 2;
+ f += ddF_y;
+ }
+ x++;
+ ddF_x += 2;
+ f += ddF_x;
+
+ if (cornername & 0x1) {
+ drawFastVLine(x0+x, y0-y, 2*y+1+delta, color);
+ drawFastVLine(x0+y, y0-x, 2*x+1+delta, color);
+ }
+ if (cornername & 0x2) {
+ drawFastVLine(x0-x, y0-y, 2*y+1+delta, color);
+ drawFastVLine(x0-y, y0-x, 2*x+1+delta, color);
+ }
+ }
+}
+
+// Bresenham's algorithm - thx wikpedia
+void Adafruit_GFX::drawLine(int16_t x0, int16_t y0,
+ int16_t x1, int16_t y1,
+ uint16_t color) {
+ int16_t steep = abs(y1 - y0) > abs(x1 - x0);
+ if (steep) {
+ swap(x0, y0);
+ swap(x1, y1);
+ }
+
+ if (x0 > x1) {
+ swap(x0, x1);
+ swap(y0, y1);
+ }
+
+ int16_t dx, dy;
+ dx = x1 - x0;
+ dy = abs(y1 - y0);
+
+ int16_t err = dx / 2;
+ int16_t ystep;
+
+ if (y0 < y1) {
+ ystep = 1;
+ } else {
+ ystep = -1;
+ }
+
+ for (; x0<=x1; x0++) {
+ if (steep) {
+ drawPixel(y0, x0, color);
+ } else {
+ drawPixel(x0, y0, color);
+ }
+ err -= dy;
+ if (err < 0) {
+ y0 += ystep;
+ err += dx;
+ }
+ }
+}
+
+// Draw a rectangle
+void Adafruit_GFX::drawRect(int16_t x, int16_t y,
+ int16_t w, int16_t h,
+ uint16_t color) {
+ drawFastHLine(x, y, w, color);
+ drawFastHLine(x, y+h-1, w, color);
+ drawFastVLine(x, y, h, color);
+ drawFastVLine(x+w-1, y, h, color);
+}
+
+void Adafruit_GFX::drawFastVLine(int16_t x, int16_t y,
+ int16_t h, uint16_t color) {
+ // Update in subclasses if desired!
+ drawLine(x, y, x, y+h-1, color);
+}
+
+void Adafruit_GFX::drawFastHLine(int16_t x, int16_t y,
+ int16_t w, uint16_t color) {
+ // Update in subclasses if desired!
+ drawLine(x, y, x+w-1, y, color);
+}
+
+void Adafruit_GFX::fillRect(int16_t x, int16_t y, int16_t w, int16_t h,
+ uint16_t color) {
+ // Update in subclasses if desired!
+ for (int16_t i=x; i<x+w; i++) {
+ drawFastVLine(i, y, h, color);
+ }
+}
+
+void Adafruit_GFX::fillScreen(uint16_t color) {
+ fillRect(0, 0, _width, _height, color);
+}
+
+// Draw a rounded rectangle
+void Adafruit_GFX::drawRoundRect(int16_t x, int16_t y, int16_t w,
+ int16_t h, int16_t r, uint16_t color) {
+ // smarter version
+ drawFastHLine(x+r , y , w-2*r, color); // Top
+ drawFastHLine(x+r , y+h-1, w-2*r, color); // Bottom
+ drawFastVLine(x , y+r , h-2*r, color); // Left
+ drawFastVLine(x+w-1, y+r , h-2*r, color); // Right
+ // draw four corners
+ drawCircleHelper(x+r , y+r , r, 1, color);
+ drawCircleHelper(x+w-r-1, y+r , r, 2, color);
+ drawCircleHelper(x+w-r-1, y+h-r-1, r, 4, color);
+ drawCircleHelper(x+r , y+h-r-1, r, 8, color);
+}
+
+// Fill a rounded rectangle
+void Adafruit_GFX::fillRoundRect(int16_t x, int16_t y, int16_t w,
+ int16_t h, int16_t r, uint16_t color) {
+ // smarter version
+ fillRect(x+r, y, w-2*r, h, color);
+
+ // draw four corners
+ fillCircleHelper(x+w-r-1, y+r, r, 1, h-2*r-1, color);
+ fillCircleHelper(x+r , y+r, r, 2, h-2*r-1, color);
+}
+
+// Draw a triangle
+void Adafruit_GFX::drawTriangle(int16_t x0, int16_t y0,
+ int16_t x1, int16_t y1,
+ int16_t x2, int16_t y2, uint16_t color) {
+ drawLine(x0, y0, x1, y1, color);
+ drawLine(x1, y1, x2, y2, color);
+ drawLine(x2, y2, x0, y0, color);
+}
+
+// Fill a triangle
+void Adafruit_GFX::fillTriangle ( int16_t x0, int16_t y0,
+ int16_t x1, int16_t y1,
+ int16_t x2, int16_t y2, uint16_t color) {
+
+ int16_t a, b, y, last;
+
+ // Sort coordinates by Y order (y2 >= y1 >= y0)
+ if (y0 > y1) {
+ swap(y0, y1); swap(x0, x1);
+ }
+ if (y1 > y2) {
+ swap(y2, y1); swap(x2, x1);
+ }
+ if (y0 > y1) {
+ swap(y0, y1); swap(x0, x1);
+ }
+
+ if(y0 == y2) { // Handle awkward all-on-same-line case as its own thing
+ a = b = x0;
+ if(x1 < a) a = x1;
+ else if(x1 > b) b = x1;
+ if(x2 < a) a = x2;
+ else if(x2 > b) b = x2;
+ drawFastHLine(a, y0, b-a+1, color);
+ return;
+ }
+
+ int16_t
+ dx01 = x1 - x0,
+ dy01 = y1 - y0,
+ dx02 = x2 - x0,
+ dy02 = y2 - y0,
+ dx12 = x2 - x1,
+ dy12 = y2 - y1;
+ int32_t //.kbv larger triangles overflow with int16_t
+ sa = 0,
+ sb = 0;
+
+ // For upper part of triangle, find scanline crossings for segments
+ // 0-1 and 0-2. If y1=y2 (flat-bottomed triangle), the scanline y1
+ // is included here (and second loop will be skipped, avoiding a /0
+ // error there), otherwise scanline y1 is skipped here and handled
+ // in the second loop...which also avoids a /0 error here if y0=y1
+ // (flat-topped triangle).
+ if(y1 == y2) last = y1; // Include y1 scanline
+ else last = y1-1; // Skip it
+
+ for(y=y0; y<=last; y++) {
+ a = x0 + sa / dy01;
+ b = x0 + sb / dy02;
+ sa += dx01;
+ sb += dx02;
+ /* longhand:
+ a = x0 + (x1 - x0) * (y - y0) / (y1 - y0);
+ b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);
+ */
+ if(a > b) swap(a,b);
+ drawFastHLine(a, y, b-a+1, color);
+ }
+
+ // For lower part of triangle, find scanline crossings for segments
+ // 0-2 and 1-2. This loop is skipped if y1=y2.
+ sa = dx12 * (y - y1);
+ sb = dx02 * (y - y0);
+ for(; y<=y2; y++) {
+ a = x1 + sa / dy12;
+ b = x0 + sb / dy02;
+ sa += dx12;
+ sb += dx02;
+ /* longhand:
+ a = x1 + (x2 - x1) * (y - y1) / (y2 - y1);
+ b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);
+ */
+ if(a > b) swap(a,b);
+ drawFastHLine(a, y, b-a+1, color);
+ }
+}
+
+void Adafruit_GFX::drawBitmap(int16_t x, int16_t y,
+ const uint8_t *bitmap, int16_t w, int16_t h,
+ uint16_t color) {
+
+ int16_t i, j, byteWidth = (w + 7) / 8;
+
+ for(j=0; j<h; j++) {
+ for(i=0; i<w; i++ ) {
+ if(pgm_read_byte(bitmap + j * byteWidth + i / 8) & (128 >> (i & 7))) {
+ drawPixel(x+i, y+j, color);
+ }
+ }
+ }
+}
+
+#if defined(ARDUINO) && ARDUINO < 100
+virtual void Adafruit_GFX::write(uint8_t c) {
+#else
+size_t Adafruit_GFX::write(uint8_t c) {
+#endif
+ if (c == '\n') {
+ cursor_y += textsize*8;
+ cursor_x = 0;
+ } else if (c == '\r') {
+ // skip em
+ } else {
+ drawChar(cursor_x, cursor_y, c, textcolor, textbgcolor, textsize);
+ cursor_x += textsize*6;
+ if (wrap && (cursor_x > (_width - textsize*6))) {
+ cursor_y += textsize*8;
+ cursor_x = 0;
+ }
+ }
+#if !(defined(ARDUINO) && ARDUINO < 100)
+ return 1;
+#endif
+}
+
+// Draw a character
+void Adafruit_GFX::drawChar(int16_t x, int16_t y, unsigned char c,
+ uint16_t color, uint16_t bg, uint8_t size) {
+
+ if((x >= _width) || // Clip right
+ (y >= _height) || // Clip bottom
+ ((x + 6 * size - 1) < 0) || // Clip left
+ ((y + 8 * size - 1) < 0)) // Clip top
+ return;
+
+ for (int8_t i=0; i<6; i++ ) {
+ uint8_t line;
+ if (i == 5)
+ line = 0x0;
+ else
+ line = pgm_read_byte(font+(c*5)+i);
+ for (int8_t j = 0; j<8; j++) {
+ if (line & 0x1) {
+ if (size == 1) // default size
+ drawPixel(x+i, y+j, color);
+ else { // big size
+ fillRect(x+(i*size), y+(j*size), size, size, color);
+ }
+ } else if (bg != color) {
+ if (size == 1) // default size
+ drawPixel(x+i, y+j, bg);
+ else { // big size
+ fillRect(x+i*size, y+j*size, size, size, bg);
+ }
+ }
+ line >>= 1;
+ }
+ }
+}
+
+void Adafruit_GFX::setCursor(int16_t x, int16_t y) {
+ cursor_x = x;
+ cursor_y = y;
+}
+
+void Adafruit_GFX::setTextSize(uint8_t s) {
+ textsize = (s > 0) ? s : 1;
+}
+
+void Adafruit_GFX::setTextColor(uint16_t c) {
+ // For 'transparent' background, we'll set the bg
+ // to the same as fg instead of using a flag
+ textcolor = textbgcolor = c;
+}
+
+void Adafruit_GFX::setTextColor(uint16_t c, uint16_t b) {
+ textcolor = c;
+ textbgcolor = b;
+}
+
+void Adafruit_GFX::setTextWrap(boolean w) {
+ wrap = w;
+}
+
+uint8_t Adafruit_GFX::getRotation(void) {
+ return rotation;
+}
+
+void Adafruit_GFX::setRotation(uint8_t x) {
+ rotation = (x & 3);
+ switch(rotation) {
+ case 0:
+ case 2:
+ _width = WIDTH;
+ _height = HEIGHT;
+ break;
+ case 1:
+ case 3:
+ _width = HEIGHT;
+ _height = WIDTH;
+ break;
+ }
+}
+
+// Return the size of the display (per current rotation)
+int16_t Adafruit_GFX::width(void) {
+ return _width;
+}
+
+int16_t Adafruit_GFX::height(void) {
+ return _height;
+}
+
+void Adafruit_GFX::invertDisplay(boolean i) {
+ // Do nothing, must be subclassed if supported
+}
+
+// this looks the most convenient method of all. i.e. forget about print() and println()
+// and could be part of ADA_GFX_kbv.cpp. possibly overwritten by later classes.
+// possibly use global buffer rather than stack.
+#include <stdarg.h>
+int Adafruit_GFX::printf(const char* format, ...)
+{
+ char buffer[80];
+ va_list args;
+ va_start (args, format);
+ vsnprintf (buffer, 80, format, args);
+ for (char *p = buffer; *p; p++) write(*p);
+ va_end (args);
+ return strlen(buffer);
+}
+
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/ADA_GFX_kbv/ADA_GFX_kbv.h Wed Apr 21 14:54:37 2021 +0000
@@ -0,0 +1,122 @@
+
+// link:
+// https://os.mbed.com/users/davidprentice/code/Nucleo_dir_L152//file/d88d2ad55fac/ADA_GFX_kbv/ADA_GFX_kbv.h/
+// Committer: davidprentice
+// Date: 19 months ago
+// 2021-04-21
+//
+// ADA_GFX_kbv.h
+//
+#ifndef _ADAFRUIT_GFX_H
+#define _ADAFRUIT_GFX_H
+
+//#define USE_VFONTS
+
+#include "Arduino.h"
+#define boolean bool
+
+#ifndef HEX
+#define HEX 1
+#endif
+
+#define swap(a, b) { int16_t t = a; a = b; b = t; }
+
+class Adafruit_GFX { //: public Stream { // requires an interface
+
+ public:
+
+ Adafruit_GFX(int16_t w, int16_t h); // Constructor
+
+ // This MUST be defined by the subclass:
+ virtual void drawPixel(int16_t x, int16_t y, uint16_t color) = 0;
+
+ // These MAY be overridden by the subclass to provide device-specific
+ // optimized code. Otherwise 'generic' versions are used.
+ virtual void
+ drawLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color),
+ drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color),
+ drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color),
+ drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color),
+ fillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color),
+ fillScreen(uint16_t color),
+ invertDisplay(boolean i);
+
+ // These exist only with Adafruit_GFX (no subclass overrides)
+ void
+ drawCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color),
+ drawCircleHelper(int16_t x0, int16_t y0, int16_t r, uint8_t cornername,
+ uint16_t color),
+ fillCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color),
+ fillCircleHelper(int16_t x0, int16_t y0, int16_t r, uint8_t cornername,
+ int16_t delta, uint16_t color),
+ drawTriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1,
+ int16_t x2, int16_t y2, uint16_t color),
+ fillTriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1,
+ int16_t x2, int16_t y2, uint16_t color),
+ drawRoundRect(int16_t x0, int16_t y0, int16_t w, int16_t h,
+ int16_t radius, uint16_t color),
+ fillRoundRect(int16_t x0, int16_t y0, int16_t w, int16_t h,
+ int16_t radius, uint16_t color),
+ drawBitmap(int16_t x, int16_t y, const uint8_t *bitmap,
+ int16_t w, int16_t h, uint16_t color),
+ drawChar(int16_t x, int16_t y, unsigned char c, uint16_t color,
+ uint16_t bg, uint8_t size),
+ setCursor(int16_t x, int16_t y),
+ setTextColor(uint16_t c),
+ setTextColor(uint16_t c, uint16_t bg),
+ setTextSize(uint8_t s),
+ setTextWrap(boolean w),
+ setRotation(uint8_t r);
+
+#if defined(ARDUINO) && ARDUINO < 100
+ virtual void write(uint8_t);
+#else
+ virtual size_t write(uint8_t);
+#endif
+ int printf(const char* format, ...);
+void print(const char *s) { printf("%s", s); }
+void print(char *s) { printf("%s", s); }
+void print(char c) { printf("%c", c); }
+void print(int16_t v) { printf("%d", v); }
+void print(int32_t vl) { printf("%ld", vl); }
+void print(double vd, int =2) { printf("%0.2f", vd); }
+void println(uint8_t u, int fmt=0) { if (fmt == 0) printf("%u\n", u); else printf("%04X\n", u); }
+void println(uint16_t u, int fmt=0) { if (fmt == 0) printf("%u\n", u); else printf("%04X\n", u); }
+void println(uint32_t ul, int fmt=0) { if (fmt == 0) printf("%lu\n", ul); else printf("%04lX\n", ul); }
+void println(const char *s="") { printf("%s\n", s); }
+void println(double vd, int prec=2) { printf("%0.2f\n", vd); }
+
+ int16_t
+ height(void),
+ width(void);
+
+ uint8_t getRotation(void);
+
+ protected:
+ const int16_t
+ WIDTH, HEIGHT; // This is the 'raw' display w/h - never changes
+ int16_t
+ _width, _height, // Display w/h as modified by current rotation
+ cursor_x, cursor_y;
+ uint16_t
+ textcolor, textbgcolor;
+ uint8_t
+ textsize,
+ rotation;
+ boolean
+ wrap; // If set, 'wrap' text at right edge of display
+
+#if defined USE_VFONTS
+ public:
+ void setFont(const PROGMEM uint8_t *ads, uint8_t mode = 0);
+ void drawFontChar(int16_t x, int16_t y, uint8_t c, uint16_t color, uint16_t bg, uint8_t size);
+ int8_t charWidth(uint8_t c);
+ private:
+ uint8_t *vfont_ads, vfont_wid, vfont_ht, vfont_ofs, vfont_siz, vfont_mode, *vfont_letter_ads;
+#endif
+
+};
+
+#endif // _ADAFRUIT_GFX_H
+
+
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ADA_GFX_kbv/Arduino.h Wed Apr 21 14:54:37 2021 +0000 @@ -0,0 +1,30 @@ +// link: +// https://os.mbed.com/users/davidprentice/code/Nucleo_dir_L152//file/d88d2ad55fac/ADA_GFX_kbv/Arduino.h/ +// Committer: davidprentice +// Date: 19 months ago +// 2021-04-21 +// +// Arduino.h +// +#ifndef ARDUINO_H +#define ARDUINO_H + +#include <mbed.h> + +extern uint32_t SystemCoreClock; +#define F_CPU SystemCoreClock + +#define PROGMEM +#define PGM_P const char* +#define PSTR(x) x +#define pgm_read_byte(x) (*(uint8_t *)(x)) +#define pgm_read_word(x) (*(uint16_t *)(x)) +#define delay(ms) wait_ms(ms) + +extern uint32_t micros(void); +extern uint32_t millis(void); +extern void setup(void); +extern void loop(void); + +#endif + \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/ADA_GFX_kbv/glcdfont.inc Wed Apr 21 14:54:37 2021 +0000
@@ -0,0 +1,273 @@
+
+// link:
+// https://os.mbed.com/users/davidprentice/code/Nucleo_dir_L152//file/d88d2ad55fac/main.cpp/
+// Committer: davidprentice
+// Date: 19 months ago
+// 2021-04-21
+//
+// glcdfont.inc
+//
+#ifndef FONT5X7_H
+#define FONT5X7_H
+
+// standard ascii 5x7 font
+
+PROGMEM static unsigned char font[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x3E, 0x5B, 0x4F, 0x5B, 0x3E,
+ 0x3E, 0x6B, 0x4F, 0x6B, 0x3E,
+ 0x1C, 0x3E, 0x7C, 0x3E, 0x1C,
+ 0x18, 0x3C, 0x7E, 0x3C, 0x18,
+ 0x1C, 0x57, 0x7D, 0x57, 0x1C,
+ 0x1C, 0x5E, 0x7F, 0x5E, 0x1C,
+ 0x00, 0x18, 0x3C, 0x18, 0x00,
+ 0xFF, 0xE7, 0xC3, 0xE7, 0xFF,
+ 0x00, 0x18, 0x24, 0x18, 0x00,
+ 0xFF, 0xE7, 0xDB, 0xE7, 0xFF,
+ 0x30, 0x48, 0x3A, 0x06, 0x0E,
+ 0x26, 0x29, 0x79, 0x29, 0x26,
+ 0x40, 0x7F, 0x05, 0x05, 0x07,
+ 0x40, 0x7F, 0x05, 0x25, 0x3F,
+ 0x5A, 0x3C, 0xE7, 0x3C, 0x5A,
+ 0x7F, 0x3E, 0x1C, 0x1C, 0x08,
+ 0x08, 0x1C, 0x1C, 0x3E, 0x7F,
+ 0x14, 0x22, 0x7F, 0x22, 0x14,
+ 0x5F, 0x5F, 0x00, 0x5F, 0x5F,
+ 0x06, 0x09, 0x7F, 0x01, 0x7F,
+ 0x00, 0x66, 0x89, 0x95, 0x6A,
+ 0x60, 0x60, 0x60, 0x60, 0x60,
+ 0x94, 0xA2, 0xFF, 0xA2, 0x94,
+ 0x08, 0x04, 0x7E, 0x04, 0x08,
+ 0x10, 0x20, 0x7E, 0x20, 0x10,
+ 0x08, 0x08, 0x2A, 0x1C, 0x08,
+ 0x08, 0x1C, 0x2A, 0x08, 0x08,
+ 0x1E, 0x10, 0x10, 0x10, 0x10,
+ 0x0C, 0x1E, 0x0C, 0x1E, 0x0C,
+ 0x30, 0x38, 0x3E, 0x38, 0x30,
+ 0x06, 0x0E, 0x3E, 0x0E, 0x06,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x5F, 0x00, 0x00,
+ 0x00, 0x07, 0x00, 0x07, 0x00,
+ 0x14, 0x7F, 0x14, 0x7F, 0x14,
+ 0x24, 0x2A, 0x7F, 0x2A, 0x12,
+ 0x23, 0x13, 0x08, 0x64, 0x62,
+ 0x36, 0x49, 0x56, 0x20, 0x50,
+ 0x00, 0x08, 0x07, 0x03, 0x00,
+ 0x00, 0x1C, 0x22, 0x41, 0x00,
+ 0x00, 0x41, 0x22, 0x1C, 0x00,
+ 0x2A, 0x1C, 0x7F, 0x1C, 0x2A,
+ 0x08, 0x08, 0x3E, 0x08, 0x08,
+ 0x00, 0x80, 0x70, 0x30, 0x00,
+ 0x08, 0x08, 0x08, 0x08, 0x08,
+ 0x00, 0x00, 0x60, 0x60, 0x00,
+ 0x20, 0x10, 0x08, 0x04, 0x02,
+ 0x3E, 0x51, 0x49, 0x45, 0x3E,
+ 0x00, 0x42, 0x7F, 0x40, 0x00,
+ 0x72, 0x49, 0x49, 0x49, 0x46,
+ 0x21, 0x41, 0x49, 0x4D, 0x33,
+ 0x18, 0x14, 0x12, 0x7F, 0x10,
+ 0x27, 0x45, 0x45, 0x45, 0x39,
+ 0x3C, 0x4A, 0x49, 0x49, 0x31,
+ 0x41, 0x21, 0x11, 0x09, 0x07,
+ 0x36, 0x49, 0x49, 0x49, 0x36,
+ 0x46, 0x49, 0x49, 0x29, 0x1E,
+ 0x00, 0x00, 0x14, 0x00, 0x00,
+ 0x00, 0x40, 0x34, 0x00, 0x00,
+ 0x00, 0x08, 0x14, 0x22, 0x41,
+ 0x14, 0x14, 0x14, 0x14, 0x14,
+ 0x00, 0x41, 0x22, 0x14, 0x08,
+ 0x02, 0x01, 0x59, 0x09, 0x06,
+ 0x3E, 0x41, 0x5D, 0x59, 0x4E,
+ 0x7C, 0x12, 0x11, 0x12, 0x7C,
+ 0x7F, 0x49, 0x49, 0x49, 0x36,
+ 0x3E, 0x41, 0x41, 0x41, 0x22,
+ 0x7F, 0x41, 0x41, 0x41, 0x3E,
+ 0x7F, 0x49, 0x49, 0x49, 0x41,
+ 0x7F, 0x09, 0x09, 0x09, 0x01,
+ 0x3E, 0x41, 0x41, 0x51, 0x73,
+ 0x7F, 0x08, 0x08, 0x08, 0x7F,
+ 0x00, 0x41, 0x7F, 0x41, 0x00,
+ 0x20, 0x40, 0x41, 0x3F, 0x01,
+ 0x7F, 0x08, 0x14, 0x22, 0x41,
+ 0x7F, 0x40, 0x40, 0x40, 0x40,
+ 0x7F, 0x02, 0x1C, 0x02, 0x7F,
+ 0x7F, 0x04, 0x08, 0x10, 0x7F,
+ 0x3E, 0x41, 0x41, 0x41, 0x3E,
+ 0x7F, 0x09, 0x09, 0x09, 0x06,
+ 0x3E, 0x41, 0x51, 0x21, 0x5E,
+ 0x7F, 0x09, 0x19, 0x29, 0x46,
+ 0x26, 0x49, 0x49, 0x49, 0x32,
+ 0x03, 0x01, 0x7F, 0x01, 0x03,
+ 0x3F, 0x40, 0x40, 0x40, 0x3F,
+ 0x1F, 0x20, 0x40, 0x20, 0x1F,
+ 0x3F, 0x40, 0x38, 0x40, 0x3F,
+ 0x63, 0x14, 0x08, 0x14, 0x63,
+ 0x03, 0x04, 0x78, 0x04, 0x03,
+ 0x61, 0x59, 0x49, 0x4D, 0x43,
+ 0x00, 0x7F, 0x41, 0x41, 0x41,
+ 0x02, 0x04, 0x08, 0x10, 0x20,
+ 0x00, 0x41, 0x41, 0x41, 0x7F,
+ 0x04, 0x02, 0x01, 0x02, 0x04,
+ 0x40, 0x40, 0x40, 0x40, 0x40,
+ 0x00, 0x03, 0x07, 0x08, 0x00,
+ 0x20, 0x54, 0x54, 0x78, 0x40,
+ 0x7F, 0x28, 0x44, 0x44, 0x38,
+ 0x38, 0x44, 0x44, 0x44, 0x28,
+ 0x38, 0x44, 0x44, 0x28, 0x7F,
+ 0x38, 0x54, 0x54, 0x54, 0x18,
+ 0x00, 0x08, 0x7E, 0x09, 0x02,
+ 0x18, 0xA4, 0xA4, 0x9C, 0x78,
+ 0x7F, 0x08, 0x04, 0x04, 0x78,
+ 0x00, 0x44, 0x7D, 0x40, 0x00,
+ 0x20, 0x40, 0x40, 0x3D, 0x00,
+ 0x7F, 0x10, 0x28, 0x44, 0x00,
+ 0x00, 0x41, 0x7F, 0x40, 0x00,
+ 0x7C, 0x04, 0x78, 0x04, 0x78,
+ 0x7C, 0x08, 0x04, 0x04, 0x78,
+ 0x38, 0x44, 0x44, 0x44, 0x38,
+ 0xFC, 0x18, 0x24, 0x24, 0x18,
+ 0x18, 0x24, 0x24, 0x18, 0xFC,
+ 0x7C, 0x08, 0x04, 0x04, 0x08,
+ 0x48, 0x54, 0x54, 0x54, 0x24,
+ 0x04, 0x04, 0x3F, 0x44, 0x24,
+ 0x3C, 0x40, 0x40, 0x20, 0x7C,
+ 0x1C, 0x20, 0x40, 0x20, 0x1C,
+ 0x3C, 0x40, 0x30, 0x40, 0x3C,
+ 0x44, 0x28, 0x10, 0x28, 0x44,
+ 0x4C, 0x90, 0x90, 0x90, 0x7C,
+ 0x44, 0x64, 0x54, 0x4C, 0x44,
+ 0x00, 0x08, 0x36, 0x41, 0x00,
+ 0x00, 0x00, 0x77, 0x00, 0x00,
+ 0x00, 0x41, 0x36, 0x08, 0x00,
+ 0x02, 0x01, 0x02, 0x04, 0x02,
+ 0x3C, 0x26, 0x23, 0x26, 0x3C,
+ 0x1E, 0xA1, 0xA1, 0x61, 0x12,
+ 0x3A, 0x40, 0x40, 0x20, 0x7A,
+ 0x38, 0x54, 0x54, 0x55, 0x59,
+ 0x21, 0x55, 0x55, 0x79, 0x41,
+ 0x21, 0x54, 0x54, 0x78, 0x41,
+ 0x21, 0x55, 0x54, 0x78, 0x40,
+ 0x20, 0x54, 0x55, 0x79, 0x40,
+ 0x0C, 0x1E, 0x52, 0x72, 0x12,
+ 0x39, 0x55, 0x55, 0x55, 0x59,
+ 0x39, 0x54, 0x54, 0x54, 0x59,
+ 0x39, 0x55, 0x54, 0x54, 0x58,
+ 0x00, 0x00, 0x45, 0x7C, 0x41,
+ 0x00, 0x02, 0x45, 0x7D, 0x42,
+ 0x00, 0x01, 0x45, 0x7C, 0x40,
+ 0xF0, 0x29, 0x24, 0x29, 0xF0,
+ 0xF0, 0x28, 0x25, 0x28, 0xF0,
+ 0x7C, 0x54, 0x55, 0x45, 0x00,
+ 0x20, 0x54, 0x54, 0x7C, 0x54,
+ 0x7C, 0x0A, 0x09, 0x7F, 0x49,
+ 0x32, 0x49, 0x49, 0x49, 0x32,
+ 0x32, 0x48, 0x48, 0x48, 0x32,
+ 0x32, 0x4A, 0x48, 0x48, 0x30,
+ 0x3A, 0x41, 0x41, 0x21, 0x7A,
+ 0x3A, 0x42, 0x40, 0x20, 0x78,
+ 0x00, 0x9D, 0xA0, 0xA0, 0x7D,
+ 0x39, 0x44, 0x44, 0x44, 0x39,
+ 0x3D, 0x40, 0x40, 0x40, 0x3D,
+ 0x3C, 0x24, 0xFF, 0x24, 0x24,
+ 0x48, 0x7E, 0x49, 0x43, 0x66,
+ 0x2B, 0x2F, 0xFC, 0x2F, 0x2B,
+ 0xFF, 0x09, 0x29, 0xF6, 0x20,
+ 0xC0, 0x88, 0x7E, 0x09, 0x03,
+ 0x20, 0x54, 0x54, 0x79, 0x41,
+ 0x00, 0x00, 0x44, 0x7D, 0x41,
+ 0x30, 0x48, 0x48, 0x4A, 0x32,
+ 0x38, 0x40, 0x40, 0x22, 0x7A,
+ 0x00, 0x7A, 0x0A, 0x0A, 0x72,
+ 0x7D, 0x0D, 0x19, 0x31, 0x7D,
+ 0x26, 0x29, 0x29, 0x2F, 0x28,
+ 0x26, 0x29, 0x29, 0x29, 0x26,
+ 0x30, 0x48, 0x4D, 0x40, 0x20,
+ 0x38, 0x08, 0x08, 0x08, 0x08,
+ 0x08, 0x08, 0x08, 0x08, 0x38,
+ 0x2F, 0x10, 0xC8, 0xAC, 0xBA,
+ 0x2F, 0x10, 0x28, 0x34, 0xFA,
+ 0x00, 0x00, 0x7B, 0x00, 0x00,
+ 0x08, 0x14, 0x2A, 0x14, 0x22,
+ 0x22, 0x14, 0x2A, 0x14, 0x08,
+ 0xAA, 0x00, 0x55, 0x00, 0xAA,
+ 0xAA, 0x55, 0xAA, 0x55, 0xAA,
+ 0x00, 0x00, 0x00, 0xFF, 0x00,
+ 0x10, 0x10, 0x10, 0xFF, 0x00,
+ 0x14, 0x14, 0x14, 0xFF, 0x00,
+ 0x10, 0x10, 0xFF, 0x00, 0xFF,
+ 0x10, 0x10, 0xF0, 0x10, 0xF0,
+ 0x14, 0x14, 0x14, 0xFC, 0x00,
+ 0x14, 0x14, 0xF7, 0x00, 0xFF,
+ 0x00, 0x00, 0xFF, 0x00, 0xFF,
+ 0x14, 0x14, 0xF4, 0x04, 0xFC,
+ 0x14, 0x14, 0x17, 0x10, 0x1F,
+ 0x10, 0x10, 0x1F, 0x10, 0x1F,
+ 0x14, 0x14, 0x14, 0x1F, 0x00,
+ 0x10, 0x10, 0x10, 0xF0, 0x00,
+ 0x00, 0x00, 0x00, 0x1F, 0x10,
+ 0x10, 0x10, 0x10, 0x1F, 0x10,
+ 0x10, 0x10, 0x10, 0xF0, 0x10,
+ 0x00, 0x00, 0x00, 0xFF, 0x10,
+ 0x10, 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0xFF, 0x10,
+ 0x00, 0x00, 0x00, 0xFF, 0x14,
+ 0x00, 0x00, 0xFF, 0x00, 0xFF,
+ 0x00, 0x00, 0x1F, 0x10, 0x17,
+ 0x00, 0x00, 0xFC, 0x04, 0xF4,
+ 0x14, 0x14, 0x17, 0x10, 0x17,
+ 0x14, 0x14, 0xF4, 0x04, 0xF4,
+ 0x00, 0x00, 0xFF, 0x00, 0xF7,
+ 0x14, 0x14, 0x14, 0x14, 0x14,
+ 0x14, 0x14, 0xF7, 0x00, 0xF7,
+ 0x14, 0x14, 0x14, 0x17, 0x14,
+ 0x10, 0x10, 0x1F, 0x10, 0x1F,
+ 0x14, 0x14, 0x14, 0xF4, 0x14,
+ 0x10, 0x10, 0xF0, 0x10, 0xF0,
+ 0x00, 0x00, 0x1F, 0x10, 0x1F,
+ 0x00, 0x00, 0x00, 0x1F, 0x14,
+ 0x00, 0x00, 0x00, 0xFC, 0x14,
+ 0x00, 0x00, 0xF0, 0x10, 0xF0,
+ 0x10, 0x10, 0xFF, 0x10, 0xFF,
+ 0x14, 0x14, 0x14, 0xFF, 0x14,
+ 0x10, 0x10, 0x10, 0x1F, 0x00,
+ 0x00, 0x00, 0x00, 0xF0, 0x10,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
+ 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xFF, 0xFF,
+ 0x0F, 0x0F, 0x0F, 0x0F, 0x0F,
+ 0x38, 0x44, 0x44, 0x38, 0x44,
+ 0x7C, 0x2A, 0x2A, 0x3E, 0x14,
+ 0x7E, 0x02, 0x02, 0x06, 0x06,
+ 0x02, 0x7E, 0x02, 0x7E, 0x02,
+ 0x63, 0x55, 0x49, 0x41, 0x63,
+ 0x38, 0x44, 0x44, 0x3C, 0x04,
+ 0x40, 0x7E, 0x20, 0x1E, 0x20,
+ 0x06, 0x02, 0x7E, 0x02, 0x02,
+ 0x99, 0xA5, 0xE7, 0xA5, 0x99,
+ 0x1C, 0x2A, 0x49, 0x2A, 0x1C,
+ 0x4C, 0x72, 0x01, 0x72, 0x4C,
+ 0x30, 0x4A, 0x4D, 0x4D, 0x30,
+ 0x30, 0x48, 0x78, 0x48, 0x30,
+ 0xBC, 0x62, 0x5A, 0x46, 0x3D,
+ 0x3E, 0x49, 0x49, 0x49, 0x00,
+ 0x7E, 0x01, 0x01, 0x01, 0x7E,
+ 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+ 0x44, 0x44, 0x5F, 0x44, 0x44,
+ 0x40, 0x51, 0x4A, 0x44, 0x40,
+ 0x40, 0x44, 0x4A, 0x51, 0x40,
+ 0x00, 0x00, 0xFF, 0x01, 0x03,
+ 0xE0, 0x80, 0xFF, 0x00, 0x00,
+ 0x08, 0x08, 0x6B, 0x6B, 0x08,
+ 0x36, 0x12, 0x36, 0x24, 0x36,
+ 0x06, 0x0F, 0x09, 0x0F, 0x06,
+ 0x00, 0x00, 0x18, 0x18, 0x00,
+ 0x00, 0x00, 0x10, 0x10, 0x00,
+ 0x30, 0x40, 0xFF, 0x01, 0x01,
+ 0x00, 0x1F, 0x01, 0x01, 0x1E,
+ 0x00, 0x19, 0x1D, 0x17, 0x12,
+ 0x00, 0x3C, 0x3C, 0x3C, 0x3C,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+#endif
+
--- a/MCUFRIEND_kbv.lib Wed Apr 21 14:47:37 2021 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1 +0,0 @@ -https://os.mbed.com/teams/Sz_Insper/code/ILI9341_PAR8_Test_01/#b7a40d5d316d
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MCUFRIEND_kbv/MCUFRIEND_kbv.cpp Wed Apr 21 14:54:37 2021 +0000
@@ -0,0 +1,2933 @@
+// link:
+// https://os.mbed.com/users/davidprentice/code/Nucleo_dir_L152//file/d88d2ad55fac/main.cpp/
+// Committer: davidprentice
+// Date: 19 months ago
+// 2021-04-21
+//
+// MCUFRIEND_kbv.cpp
+//
+
+//#define SUPPORT_0139 //S6D0139 +280 bytes
+#define SUPPORT_0154 //S6D0154 +320 bytes
+//#define SUPPORT_1289 //SSD1289,SSD1297 (ID=0x9797) +626 bytes, 0.03s
+//#define SUPPORT_1580 //R61580 Untested
+#define SUPPORT_1963 //only works with 16BIT bus anyway
+//#define SUPPORT_4532 //LGDP4532 +120 bytes. thanks Leodino
+#define SUPPORT_4535 //LGDP4535 +180 bytes
+#define SUPPORT_68140 //RM68140 +52 bytes defaults to PIXFMT=0x55
+//#define SUPPORT_7735
+#define SUPPORT_7781 //ST7781 +172 bytes
+//#define SUPPORT_8230 //UC8230 +118 bytes
+//#define SUPPORT_8347D //HX8347-D, HX8347-G, HX8347-I, HX8367-A +520 bytes, 0.27s
+//#define SUPPORT_8347A //HX8347-A +500 bytes, 0.27s
+//#define SUPPORT_8352A //HX8352A +486 bytes, 0.27s
+//#define SUPPORT_8352B //HX8352B
+//#define SUPPORT_8357D_GAMMA //monster 34 byte
+//#define SUPPORT_9163 //
+//#define SUPPORT_9225 //ILI9225-B, ILI9225-G ID=0x9225, ID=0x9226, ID=0x6813 +380 bytes
+//#define SUPPORT_9326_5420 //ILI9326, SPFD5420 +246 bytes
+//#define SUPPORT_9342 //costs +114 bytes
+//#define SUPPORT_9806 //UNTESTED
+#define SUPPORT_9488_555 //costs +230 bytes, 0.03s / 0.19s
+#define SUPPORT_B509_7793 //R61509, ST7793 +244 bytes
+#define OFFSET_9327 32 //costs about 103 bytes, 0.08s
+
+#include "MCUFRIEND_kbv.h"
+#if defined(USE_SERIAL)
+#include "utility/mcufriend_serial.h"
+ //uint8_t running;
+#elif defined(__MBED__)
+#include "utility/mcufriend_mbed.h"
+#elif defined(__CC_ARM) || defined(__CROSSWORKS_ARM)
+#include "utility/mcufriend_keil.h"
+#else
+#include "utility/mcufriend_shield.h"
+#endif
+
+#define MIPI_DCS_REV1 (1<<0)
+#define AUTO_READINC (1<<1)
+#define READ_BGR (1<<2)
+#define READ_LOWHIGH (1<<3)
+#define READ_24BITS (1<<4)
+#define XSA_XEA_16BIT (1<<5)
+#define READ_NODUMMY (1<<6)
+#define INVERT_GS (1<<8)
+#define INVERT_SS (1<<9)
+#define MV_AXIS (1<<10)
+#define INVERT_RGB (1<<11)
+#define REV_SCREEN (1<<12)
+#define FLIP_VERT (1<<13)
+#define FLIP_HORIZ (1<<14)
+
+#if (defined(USES_16BIT_BUS)) //only comes from SPECIALs
+#define USING_16BIT_BUS 1
+#else
+#define USING_16BIT_BUS 0
+#endif
+
+MCUFRIEND_kbv::MCUFRIEND_kbv(int CS, int RS, int WR, int RD, int _RST):Adafruit_GFX(240, 320)
+{
+ // we can not access GPIO pins until AHB has been enabled.
+}
+
+static uint8_t done_reset, is8347, is555, is9797;
+static uint16_t color565_to_555(uint16_t color) {
+ return (color & 0xFFC0) | ((color & 0x1F) << 1) | ((color & 0x01)); //lose Green LSB, extend Blue LSB
+}
+static uint16_t color555_to_565(uint16_t color) {
+ return (color & 0xFFC0) | ((color & 0x0400) >> 5) | ((color & 0x3F) >> 1); //extend Green LSB
+}
+static uint8_t color565_to_r(uint16_t color) {
+ return ((color & 0xF800) >> 8); // transform to rrrrrxxx
+}
+static uint8_t color565_to_g(uint16_t color) {
+ return ((color & 0x07E0) >> 3); // transform to ggggggxx
+}
+static uint8_t color565_to_b(uint16_t color) {
+ return ((color & 0x001F) << 3); // transform to bbbbbxxx
+}
+static void write24(uint16_t color) {
+ uint8_t r = color565_to_r(color);
+ uint8_t g = color565_to_g(color);
+ uint8_t b = color565_to_b(color);
+ write8(r);
+ write8(g);
+ write8(b);
+}
+
+void MCUFRIEND_kbv::reset(void)
+{
+ done_reset = 1;
+ setWriteDir();
+ CTL_INIT();
+ CS_IDLE;
+ RD_IDLE;
+ WR_IDLE;
+ RESET_IDLE;
+ delay(50);
+ RESET_ACTIVE;
+ delay(100);
+ RESET_IDLE;
+ delay(100);
+ WriteCmdData(0xB0, 0x0000); //R61520 needs this to read ID
+}
+
+static void writecmddata(uint16_t cmd, uint16_t dat)
+{
+ CS_ACTIVE;
+ WriteCmd(cmd);
+ WriteData(dat);
+ CS_IDLE;
+}
+
+void MCUFRIEND_kbv::WriteCmdData(uint16_t cmd, uint16_t dat) { writecmddata(cmd, dat); }
+
+static void WriteCmdParamN(uint16_t cmd, int8_t N, uint8_t * block)
+{
+ CS_ACTIVE;
+ WriteCmd(cmd);
+ while (N-- > 0) {
+ uint8_t u8 = *block++;
+ write8(u8);
+ if (N && is8347) {
+ cmd++;
+ WriteCmd(cmd);
+ }
+ }
+ CS_IDLE;
+}
+
+static inline void WriteCmdParam4(uint8_t cmd, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4)
+{
+ uint8_t d[4];
+ d[0] = d1, d[1] = d2, d[2] = d3, d[3] = d4;
+ WriteCmdParamN(cmd, 4, d);
+}
+
+//#define WriteCmdParam4(cmd, d1, d2, d3, d4) {uint8_t d[4];d[0] = d1, d[1] = d2, d[2] = d3, d[3] = d4;WriteCmdParamN(cmd, 4, d);}
+void MCUFRIEND_kbv::pushCommand(uint16_t cmd, uint8_t * block, int8_t N) { WriteCmdParamN(cmd, N, block); }
+
+static uint16_t read16bits(void)
+{
+ uint16_t ret;
+ uint8_t lo;
+#if USING_16BIT_BUS
+ READ_16(ret); //single strobe to read whole bus
+ if (ret > 255) //ID might say 0x00D3
+ return ret;
+#else
+ READ_8(ret);
+#endif
+ //all MIPI_DCS_REV1 style params are 8-bit
+ READ_8(lo);
+ return (ret << 8) | lo;
+}
+
+uint16_t MCUFRIEND_kbv::readReg(uint16_t reg, int8_t index)
+{
+ uint16_t ret;
+ uint8_t lo;
+ if (!done_reset)
+ reset();
+ CS_ACTIVE;
+ WriteCmd(reg);
+ setReadDir();
+ delay(1); //1us should be adequate
+ // READ_16(ret);
+ do { ret = read16bits(); }while (--index >= 0); //need to test with SSD1963
+ RD_IDLE;
+ CS_IDLE;
+ setWriteDir();
+ return ret;
+}
+
+uint32_t MCUFRIEND_kbv::readReg32(uint16_t reg)
+{
+ uint16_t h = readReg(reg, 0);
+ uint16_t l = readReg(reg, 1);
+ return ((uint32_t) h << 16) | (l);
+}
+
+uint32_t MCUFRIEND_kbv::readReg40(uint16_t reg)
+{
+ uint16_t h = readReg(reg, 0);
+ uint16_t m = readReg(reg, 1);
+ uint16_t l = readReg(reg, 2);
+ return ((uint32_t) h << 24) | (m << 8) | (l >> 8);
+}
+
+uint16_t MCUFRIEND_kbv::readID(void)
+{
+ uint16_t ret, ret2;
+ uint8_t msb;
+ ret = readReg(0); //forces a reset() if called before begin()
+ if (ret == 0x5408) //the SPFD5408 fails the 0xD3D3 test.
+ return 0x5408;
+ if (ret == 0x5420) //the SPFD5420 fails the 0xD3D3 test.
+ return 0x5420;
+ if (ret == 0x8989) //SSD1289 is always 8989
+ return 0x1289;
+ ret = readReg(0x67); //HX8347-A
+ if (ret == 0x4747)
+ return 0x8347;
+//#if defined(SUPPORT_1963) && USING_16BIT_BUS
+ ret = readReg32(0xA1); //SSD1963: [01 57 61 01]
+ if (ret == 0x6101)
+ return 0x1963;
+ if (ret == 0xFFFF) //R61526: [xx FF FF FF]
+ return 0x1526; //subsequent begin() enables Command Access
+// if (ret == 0xFF00) //R61520: [xx FF FF 00]
+// return 0x1520; //subsequent begin() enables Command Access
+//#endif
+ ret = readReg40(0xBF);
+ if (ret == 0x8357) //HX8357B: [xx 01 62 83 57 FF]
+ return 0x8357;
+ if (ret == 0x9481) //ILI9481: [xx 02 04 94 81 FF]
+ return 0x9481;
+ if (ret == 0x1511) //?R61511: [xx 02 04 15 11] not tested yet
+ return 0x1511;
+ if (ret == 0x1520) //?R61520: [xx 01 22 15 20]
+ return 0x1520;
+ if (ret == 0x1526) //?R61526: [xx 01 22 15 26]
+ return 0x1526;
+ if (ret == 0x1581) //R61581: [xx 01 22 15 81]
+ return 0x1581;
+ if (ret == 0x1400) //?RM68140:[xx FF 68 14 00] not tested yet
+ return 0x6814;
+ ret = readReg32(0xD4);
+ if (ret == 0x5310) //NT35310: [xx 01 53 10]
+ return 0x5310;
+ ret = readReg32(0xD7);
+ if (ret == 0x8031) //weird unknown from BangGood [xx 20 80 31] PrinceCharles
+ return 0x8031;
+ ret = readReg40(0xEF); //ILI9327: [xx 02 04 93 27 FF]
+ if (ret == 0x9327)
+ return 0x9327;
+ ret = readReg32(0xFE) >> 8; //weird unknown from BangGood [04 20 53]
+ if (ret == 0x2053)
+ return 0x2053;
+ uint32_t ret32 = readReg32(0x04);
+ msb = ret32 >> 16;
+ ret = ret32;
+// if (msb = 0x38 && ret == 0x8000) //unknown [xx 38 80 00] with D3 = 0x1602
+ if (msb == 0x00 && ret == 0x8000) { //HX8357-D [xx 00 80 00]
+#if 1
+ uint8_t cmds[] = {0xFF, 0x83, 0x57};
+ pushCommand(0xB9, cmds, 3);
+ msb = readReg(0xD0);
+ if (msb == 0x99) return 0x0099; //HX8357-D from datasheet
+ if (msb == 0x90) //HX8357-C undocumented
+#endif
+ return 0x9090; //BIG CHANGE: HX8357-D was 0x8357
+ }
+// if (msb == 0xFF && ret == 0xFFFF) //R61526 [xx FF FF FF]
+// return 0x1526; //subsequent begin() enables Command Access
+ if (ret == 0x1526) //R61526 [xx 06 15 26] if I have written NVM
+ return 0x1526; //subsequent begin() enables Command Access
+ if (ret == 0x89F0) //ST7735S: [xx 7C 89 F0]
+ return 0x7735;
+ if (ret == 0x8552) //ST7789V: [xx 85 85 52]
+ return 0x7789;
+ if (ret == 0xAC11) //?unknown [xx 61 AC 11]
+ return 0xAC11;
+ ret32 = readReg32(0xD3); //[xx 91 63 00]
+ ret = ret32 >> 8;
+ if (ret == 0x9163) return ret;
+ ret = readReg32(0xD3); //for ILI9488, 9486, 9340, 9341
+ msb = ret >> 8;
+ if (msb == 0x93 || msb == 0x94 || msb == 0x98 || msb == 0x77 || msb == 0x16)
+ return ret; //0x9488, 9486, 9340, 9341, 7796
+ if (ret == 0x00D3 || ret == 0xD3D3)
+ return ret; //16-bit write-only bus
+/*
+ msb = 0x12; //read 3rd,4th byte. does not work in parallel
+ pushCommand(0xD9, &msb, 1);
+ ret2 = readReg(0xD3);
+ msb = 0x13;
+ pushCommand(0xD9, &msb, 1);
+ ret = (ret2 << 8) | readReg(0xD3);
+// if (ret2 == 0x93)
+ return ret2;
+*/
+ return readReg(0); //0154, 7783, 9320, 9325, 9335, B505, B509
+}
+
+ // independent cursor and window registers. S6D0154, ST7781 increments. ILI92320/5 do not.
+int16_t MCUFRIEND_kbv::readGRAM(int16_t x, int16_t y, uint16_t * block, int16_t w, int16_t h)
+{
+ uint16_t ret, dummy, _MR = _MW;
+ int16_t n = w * h, row = 0, col = 0;
+ uint8_t r, g, b, tmp;
+ if (!is8347 && _lcd_capable & MIPI_DCS_REV1) // HX8347 uses same register
+ _MR = 0x2E;
+ if (_lcd_ID == 0x1602) _MR = 0x2E;
+ setAddrWindow(x, y, x + w - 1, y + h - 1);
+ while (n > 0) {
+ if (!(_lcd_capable & MIPI_DCS_REV1)) {
+ WriteCmdData(_MC, x + col);
+ WriteCmdData(_MP, y + row);
+ }
+ CS_ACTIVE;
+ WriteCmd(_MR);
+ setReadDir();
+ if (_lcd_capable & READ_NODUMMY) {
+ ;
+ } else if ((_lcd_capable & MIPI_DCS_REV1) || _lcd_ID == 0x1289) {
+ READ_8(r);
+ } else {
+ READ_16(dummy);
+ }
+ if (_lcd_ID == 0x1511) READ_8(r); //extra dummy for R61511
+ while (n) {
+ if (_lcd_capable & READ_24BITS) {
+ READ_8(r);
+ READ_8(g);
+ READ_8(b);
+ if (_lcd_capable & READ_BGR)
+ ret = color565(b, g, r);
+ else
+ ret = color565(r, g, b);
+ } else {
+ READ_16(ret);
+ if (_lcd_capable & READ_LOWHIGH)
+ ret = (ret >> 8) | (ret << 8);
+ if (_lcd_capable & READ_BGR)
+ ret = (ret & 0x07E0) | (ret >> 11) | (ret << 11);
+ }
+#if defined(SUPPORT_9488_555)
+ if (is555) ret = color555_to_565(ret);
+#endif
+ *block++ = ret;
+ n--;
+ if (!(_lcd_capable & AUTO_READINC))
+ break;
+ }
+ if (++col >= w) {
+ col = 0;
+ if (++row >= h)
+ row = 0;
+ }
+ RD_IDLE;
+ CS_IDLE;
+ setWriteDir();
+ }
+ if (!(_lcd_capable & MIPI_DCS_REV1))
+ setAddrWindow(0, 0, width() - 1, height() - 1);
+ return 0;
+}
+
+void MCUFRIEND_kbv::setRotation(uint8_t r)
+{
+ uint16_t GS, SS_v, ORG, REV = _lcd_rev;
+ uint8_t val, d[3];
+ rotation = r & 3; // just perform the operation ourselves on the protected variables
+ _width = (rotation & 1) ? HEIGHT : WIDTH;
+ _height = (rotation & 1) ? WIDTH : HEIGHT;
+ switch (rotation) {
+ case 0: //PORTRAIT:
+ val = 0x48; //MY=0, MX=1, MV=0, ML=0, BGR=1
+ break;
+ case 1: //LANDSCAPE: 90 degrees
+ val = 0x28; //MY=0, MX=0, MV=1, ML=0, BGR=1
+ break;
+ case 2: //PORTRAIT_REV: 180 degrees
+ val = 0x98; //MY=1, MX=0, MV=0, ML=1, BGR=1
+ break;
+ case 3: //LANDSCAPE_REV: 270 degrees
+ val = 0xF8; //MY=1, MX=1, MV=1, ML=1, BGR=1
+ break;
+ }
+ if (_lcd_capable & INVERT_GS)
+ val ^= 0x80;
+ if (_lcd_capable & INVERT_SS)
+ val ^= 0x40;
+ if (_lcd_capable & INVERT_RGB)
+ val ^= 0x08;
+ if (_lcd_capable & MIPI_DCS_REV1) {
+ if (_lcd_ID == 0x6814) { //.kbv my weird 0x9486 might be 68140
+ GS = (val & 0x80) ? (1 << 6) : 0; //MY
+ SS_v = (val & 0x40) ? (1 << 5) : 0; //MX
+ val &= 0x28; //keep MV, BGR, MY=0, MX=0, ML=0
+ d[0] = 0;
+ d[1] = GS | SS_v | 0x02; //MY, MX
+ d[2] = 0x3B;
+ WriteCmdParamN(0xB6, 3, d);
+ goto common_MC;
+ } else if (_lcd_ID == 0x1963 || _lcd_ID == 0x9481 || _lcd_ID == 0x1511) {
+ if (val & 0x80)
+ val |= 0x01; //GS
+ if ((val & 0x40))
+ val |= 0x02; //SS
+ if (_lcd_ID == 0x1963) val &= ~0xC0;
+ if (_lcd_ID == 0x9481) val &= ~0xD0;
+ if (_lcd_ID == 0x1511) {
+ val &= ~0x10; //remove ML
+ val |= 0xC0; //force penguin 180 rotation
+ }
+// val &= (_lcd_ID == 0x1963) ? ~0xC0 : ~0xD0; //MY=0, MX=0 with ML=0 for ILI9481
+ goto common_MC;
+ } else if (is8347) {
+ _MC = 0x02, _MP = 0x06, _MW = 0x22, _SC = 0x02, _EC = 0x04, _SP = 0x06, _EP = 0x08;
+ if (_lcd_ID == 0x0065) { //HX8352-B
+ val |= 0x01; //GS=1
+ if ((val & 0x10)) val ^= 0xD3; //(ML) flip MY, MX, ML, SS, GS
+ if (r & 1) _MC = 0x82, _MP = 0x80;
+ else _MC = 0x80, _MP = 0x82;
+ }
+ if (_lcd_ID == 0x5252) { //HX8352-A
+ val |= 0x02; //VERT_SCROLLON
+ if ((val & 0x10)) val ^= 0xD4; //(ML) flip MY, MX, SS. GS=1
+ }
+ goto common_BGR;
+ }
+ common_MC:
+ _MC = 0x2A, _MP = 0x2B, _MW = 0x2C, _SC = 0x2A, _EC = 0x2A, _SP = 0x2B, _EP = 0x2B;
+ common_BGR:
+ WriteCmdParamN(is8347 ? 0x16 : 0x36, 1, &val);
+ _lcd_madctl = val;
+// if (_lcd_ID == 0x1963) WriteCmdParamN(0x13, 0, NULL); //NORMAL mode
+ }
+ // cope with 9320 variants
+ else {
+ switch (_lcd_ID) {
+#if defined(SUPPORT_9225)
+ case 0x9225:
+ _SC = 0x37, _EC = 0x36, _SP = 0x39, _EP = 0x38;
+ _MC = 0x20, _MP = 0x21, _MW = 0x22;
+ GS = (val & 0x80) ? (1 << 9) : 0;
+ SS_v = (val & 0x40) ? (1 << 8) : 0;
+ WriteCmdData(0x01, GS | SS_v | 0x001C); // set Driver Output Control
+ goto common_ORG;
+#endif
+#if defined(SUPPORT_0139) || defined(SUPPORT_0154)
+#ifdef SUPPORT_0139
+ case 0x0139:
+ _SC = 0x46, _EC = 0x46, _SP = 0x48, _EP = 0x47;
+ goto common_S6D;
+#endif
+#ifdef SUPPORT_0154
+ case 0x0154:
+ _SC = 0x37, _EC = 0x36, _SP = 0x39, _EP = 0x38;
+ goto common_S6D;
+#endif
+ common_S6D:
+ _MC = 0x20, _MP = 0x21, _MW = 0x22;
+ GS = (val & 0x80) ? (1 << 9) : 0;
+ SS_v = (val & 0x40) ? (1 << 8) : 0;
+ // S6D0139 requires NL = 0x27, S6D0154 NL = 0x28
+ WriteCmdData(0x01, GS | SS_v | ((_lcd_ID == 0x0139) ? 0x27 : 0x28));
+ goto common_ORG;
+#endif
+ case 0x5420:
+ case 0x7793:
+ case 0x9326:
+ case 0xB509:
+ _MC = 0x200, _MP = 0x201, _MW = 0x202, _SC = 0x210, _EC = 0x211, _SP = 0x212, _EP = 0x213;
+ GS = (val & 0x80) ? (1 << 15) : 0;
+ uint16_t NL;
+ NL = ((432 / 8) - 1) << 9;
+ if (_lcd_ID == 0x9326 || _lcd_ID == 0x5420) NL >>= 1;
+ WriteCmdData(0x400, GS | NL);
+ goto common_SS;
+ default:
+ _MC = 0x20, _MP = 0x21, _MW = 0x22, _SC = 0x50, _EC = 0x51, _SP = 0x52, _EP = 0x53;
+ GS = (val & 0x80) ? (1 << 15) : 0;
+ WriteCmdData(0x60, GS | 0x2700); // Gate Scan Line (0xA700)
+ common_SS:
+ SS_v = (val & 0x40) ? (1 << 8) : 0;
+ WriteCmdData(0x01, SS_v); // set Driver Output Control
+ common_ORG:
+ ORG = (val & 0x20) ? (1 << 3) : 0;
+#ifdef SUPPORT_8230
+ if (_lcd_ID == 0x8230) { // UC8230 has strange BGR and READ_BGR behaviour
+ if (rotation == 1 || rotation == 2) {
+ val ^= 0x08; // change BGR bit for LANDSCAPE and PORTRAIT_REV
+ }
+ }
+#endif
+ if (val & 0x08)
+ ORG |= 0x1000; //BGR
+ _lcd_madctl = ORG | 0x0030;
+ WriteCmdData(0x03, _lcd_madctl); // set GRAM write direction and BGR=1.
+ break;
+#ifdef SUPPORT_1289
+ case 0x1289:
+ _MC = 0x4E, _MP = 0x4F, _MW = 0x22, _SC = 0x44, _EC = 0x44, _SP = 0x45, _EP = 0x46;
+ if (rotation & 1)
+ val ^= 0xD0; // exchange Landscape modes
+ GS = (val & 0x80) ? (1 << 14) : 0; //called TB (top-bottom), CAD=0
+ SS_v = (val & 0x40) ? (1 << 9) : 0; //called RL (right-left)
+ ORG = (val & 0x20) ? (1 << 3) : 0; //called AM
+ _lcd_drivOut = GS | SS_v | (REV << 13) | 0x013F; //REV=0, BGR=0, MUX=319
+ if (val & 0x08)
+ _lcd_drivOut |= 0x0800; //BGR
+ WriteCmdData(0x01, _lcd_drivOut); // set Driver Output Control
+ if (is9797) WriteCmdData(0x11, ORG | 0x4C30); else // DFM=2, DEN=1, WM=1, TY=0
+ WriteCmdData(0x11, ORG | 0x6070); // DFM=3, EN=0, TY=1
+ break;
+#endif
+ }
+ }
+ if ((rotation & 1) && ((_lcd_capable & MV_AXIS) == 0)) {
+ uint16_t x;
+ x = _MC, _MC = _MP, _MP = x;
+ x = _SC, _SC = _SP, _SP = x; //.kbv check 0139
+ x = _EC, _EC = _EP, _EP = x; //.kbv check 0139
+ }
+ setAddrWindow(0, 0, width() - 1, height() - 1);
+ vertScroll(0, HEIGHT, 0); //reset scrolling after a rotation
+}
+
+void MCUFRIEND_kbv::drawPixel(int16_t x, int16_t y, uint16_t color)
+{
+ // MCUFRIEND just plots at edge if you try to write outside of the box:
+ if (x < 0 || y < 0 || x >= width() || y >= height())
+ return;
+#if defined(SUPPORT_9488_555)
+ if (is555) color = color565_to_555(color);
+#endif
+ setAddrWindow(x, y, x, y);
+// CS_ACTIVE; WriteCmd(_MW); write16(color); CS_IDLE; //-0.01s +98B
+ if (is9797) { CS_ACTIVE; WriteCmd(_MW); write24(color); CS_IDLE;} else
+ WriteCmdData(_MW, color);
+}
+
+void MCUFRIEND_kbv::setAddrWindow(int16_t x, int16_t y, int16_t x1, int16_t y1)
+{
+#if defined(OFFSET_9327)
+ if (_lcd_ID == 0x9327) {
+ if (rotation == 2) y += OFFSET_9327, y1 += OFFSET_9327;
+ if (rotation == 3) x += OFFSET_9327, x1 += OFFSET_9327;
+ }
+#endif
+#if 1
+ if (_lcd_ID == 0x1526 && (rotation & 1)) {
+ int16_t dx = x1 - x, dy = y1 - y;
+ if (dy == 0) { y1++; }
+ else if (dx == 0) { x1 += dy; y1 -= dy; }
+ }
+#endif
+ if (_lcd_capable & MIPI_DCS_REV1) {
+ WriteCmdParam4(_SC, x >> 8, x, x1 >> 8, x1); //Start column instead of _MC
+ WriteCmdParam4(_SP, y >> 8, y, y1 >> 8, y1); //
+ if (is8347 && _lcd_ID == 0x0065) { //HX8352-B has separate _MC, _SC
+ uint8_t d[2];
+ d[0] = x >> 8; d[1] = x;
+ WriteCmdParamN(_MC, 2, d); //allows !MV_AXIS to work
+ d[0] = y >> 8; d[1] = y;
+ WriteCmdParamN(_MP, 2, d);
+ }
+ } else {
+ WriteCmdData(_MC, x);
+ WriteCmdData(_MP, y);
+ if (!(x == x1 && y == y1)) { //only need MC,MP for drawPixel
+ if (_lcd_capable & XSA_XEA_16BIT) {
+ if (rotation & 1)
+ y1 = y = (y1 << 8) | y;
+ else
+ x1 = x = (x1 << 8) | x;
+ }
+ WriteCmdData(_SC, x);
+ WriteCmdData(_SP, y);
+ WriteCmdData(_EC, x1);
+ WriteCmdData(_EP, y1);
+ }
+ }
+}
+
+void MCUFRIEND_kbv::fillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color)
+{
+ int16_t end;
+#if defined(SUPPORT_9488_555)
+ if (is555) color = color565_to_555(color);
+#endif
+ if (w < 0) {
+ w = -w;
+ x -= w;
+ } //+ve w
+ end = x + w;
+ if (x < 0)
+ x = 0;
+ if (end > width())
+ end = width();
+ w = end - x;
+ if (h < 0) {
+ h = -h;
+ y -= h;
+ } //+ve h
+ end = y + h;
+ if (y < 0)
+ y = 0;
+ if (end > height())
+ end = height();
+ h = end - y;
+ setAddrWindow(x, y, x + w - 1, y + h - 1);
+ CS_ACTIVE;
+ WriteCmd(_MW);
+ if (h > w) {
+ end = h;
+ h = w;
+ w = end;
+ }
+ uint8_t hi = color >> 8, lo = color & 0xFF;
+ while (h-- > 0) {
+ end = w;
+#if USING_16BIT_BUS
+#if defined(__MK66FX1M0__) //180MHz M4
+#define STROBE_16BIT {WR_ACTIVE4;WR_ACTIVE;WR_IDLE4;WR_IDLE;} //56ns
+#elif defined(__SAM3X8E__) //84MHz M3
+#define STROBE_16BIT {WR_ACTIVE4;WR_ACTIVE2;WR_IDLE4;WR_IDLE2;} //286ns ?ILI9486
+//#define STROBE_16BIT {WR_ACTIVE4;WR_ACTIVE;WR_IDLE4;WR_IDLE;} //238ns SSD1289
+//#define STROBE_16BIT {WR_ACTIVE2;WR_ACTIVE;WR_IDLE2;} //119ns RM68140
+#else //16MHz AVR
+#define STROBE_16BIT {WR_ACTIVE;WR_ACTIVE;WR_IDLE; } //375ns ?ILI9486
+#endif
+ write_16(color); //we could just do the strobe
+ lo = end & 7;
+ hi = end >> 3;
+ if (hi)
+ do {
+ STROBE_16BIT;
+ STROBE_16BIT;
+ STROBE_16BIT;
+ STROBE_16BIT;
+ STROBE_16BIT;
+ STROBE_16BIT;
+ STROBE_16BIT;
+ STROBE_16BIT;
+ } while (--hi > 0);
+ while (lo-- > 0) {
+ STROBE_16BIT;
+ }
+#else
+#if defined(SUPPORT_1289)
+ if (is9797) {
+ uint8_t r = color565_to_r(color);
+ uint8_t g = color565_to_g(color);
+ uint8_t b = color565_to_b(color);
+ do {
+ write8(r);
+ write8(g);
+ write8(b);
+ } while (--end != 0);
+ } else
+#endif
+ do {
+ write8(hi);
+ write8(lo);
+ } while (--end != 0);
+#endif
+ }
+ CS_IDLE;
+ if (!(_lcd_capable & MIPI_DCS_REV1) || ((_lcd_ID == 0x1526) && (rotation & 1)))
+ setAddrWindow(0, 0, width() - 1, height() - 1);
+}
+
+static void pushColors_any(uint16_t cmd, uint8_t * block, int16_t n, bool first, uint8_t flags)
+{
+ uint16_t color;
+ uint8_t h, l;
+ bool isconst = flags & 1;
+ bool isbigend = (flags & 2) != 0;
+ CS_ACTIVE;
+ if (first) {
+ WriteCmd(cmd);
+ }
+
+ if (!isconst && !isbigend) {
+ uint16_t *block16 = (uint16_t*)block;
+ while (n-- > 0) {
+ color = *block16++;
+ write16(color);
+ }
+ } else
+
+ while (n-- > 0) {
+ if (isconst) {
+ h = pgm_read_byte(block++);
+ l = pgm_read_byte(block++);
+ } else {
+ h = (*block++);
+ l = (*block++);
+ }
+ color = (isbigend) ? (h << 8 | l) : (l << 8 | h);
+#if defined(SUPPORT_9488_555)
+ if (is555) color = color565_to_555(color);
+#endif
+ if (is9797) write24(color); else
+ write16(color);
+ }
+ CS_IDLE;
+}
+
+void MCUFRIEND_kbv::pushColors(uint16_t * block, int16_t n, bool first)
+{
+ pushColors_any(_MW, (uint8_t *)block, n, first, 0);
+}
+void MCUFRIEND_kbv::pushColors(uint8_t * block, int16_t n, bool first)
+{
+ pushColors_any(_MW, (uint8_t *)block, n, first, 2); //regular bigend
+}
+void MCUFRIEND_kbv::pushColors(const uint8_t * block, int16_t n, bool first, bool bigend)
+{
+ pushColors_any(_MW, (uint8_t *)block, n, first, bigend ? 3 : 1);
+}
+
+void MCUFRIEND_kbv::vertScroll(int16_t top, int16_t scrollines, int16_t offset)
+{
+#if defined(OFFSET_9327)
+ if (_lcd_ID == 0x9327) {
+ if (rotation == 2 || rotation == 3) top += OFFSET_9327;
+ }
+#endif
+ int16_t bfa = HEIGHT - top - scrollines; // bottom fixed area
+ int16_t vsp;
+ int16_t sea = top;
+ if (_lcd_ID == 0x9327) bfa += 32;
+ if (offset <= -scrollines || offset >= scrollines) offset = 0; //valid scroll
+ vsp = top + offset; // vertical start position
+ if (offset < 0)
+ vsp += scrollines; //keep in unsigned range
+ sea = top + scrollines - 1;
+ if (_lcd_capable & MIPI_DCS_REV1) {
+ uint8_t d[6]; // for multi-byte parameters
+/*
+ if (_lcd_ID == 0x9327) { //panel is wired for 240x432
+ if (rotation == 2 || rotation == 3) { //180 or 270 degrees
+ if (scrollines == HEIGHT) {
+ scrollines = 432; // we get a glitch but hey-ho
+ vsp -= 432 - HEIGHT;
+ }
+ if (vsp < 0)
+ vsp += 432;
+ }
+ bfa = 432 - top - scrollines;
+ }
+*/
+ d[0] = top >> 8; //TFA
+ d[1] = top;
+ d[2] = scrollines >> 8; //VSA
+ d[3] = scrollines;
+ d[4] = bfa >> 8; //BFA
+ d[5] = bfa;
+ WriteCmdParamN(is8347 ? 0x0E : 0x33, 6, d);
+// if (offset == 0 && rotation > 1) vsp = top + scrollines; //make non-valid
+ d[0] = vsp >> 8; //VSP
+ d[1] = vsp;
+ WriteCmdParamN(is8347 ? 0x14 : 0x37, 2, d);
+ if (is8347) {
+ d[0] = (offset != 0) ? (_lcd_ID == 0x8347 ? 0x02 : 0x08) : 0;
+ WriteCmdParamN(_lcd_ID == 0x8347 ? 0x18 : 0x01, 1, d); //HX8347-D
+ } else if (offset == 0 && (_lcd_capable & MIPI_DCS_REV1)) {
+ WriteCmdParamN(0x13, 0, NULL); //NORMAL i.e. disable scroll
+ }
+ return;
+ }
+ // cope with 9320 style variants:
+ switch (_lcd_ID) {
+ case 0x7783:
+ WriteCmdData(0x61, _lcd_rev); //!NDL, !VLE, REV
+ WriteCmdData(0x6A, vsp); //VL#
+ break;
+#ifdef SUPPORT_0139
+ case 0x0139:
+ WriteCmdData(0x07, 0x0213 | (_lcd_rev << 2)); //VLE1=1, GON=1, REV=x, D=3
+ WriteCmdData(0x41, vsp); //VL# check vsp
+ break;
+#endif
+#if defined(SUPPORT_0154) || defined(SUPPORT_9225) //thanks tongbajiel
+ case 0x9225:
+ case 0x0154:
+ WriteCmdData(0x31, sea); //SEA
+ WriteCmdData(0x32, top); //SSA
+ WriteCmdData(0x33, vsp - top); //SST
+ break;
+#endif
+#ifdef SUPPORT_1289
+ case 0x1289:
+ WriteCmdData(0x41, vsp); //VL#
+ break;
+#endif
+ case 0x5420:
+ case 0x7793:
+ case 0x9326:
+ case 0xB509:
+ WriteCmdData(0x401, (1 << 1) | _lcd_rev); //VLE, REV
+ WriteCmdData(0x404, vsp); //VL#
+ break;
+ default:
+ // 0x6809, 0x9320, 0x9325, 0x9335, 0xB505 can only scroll whole screen
+ WriteCmdData(0x61, (1 << 1) | _lcd_rev); //!NDL, VLE, REV
+ WriteCmdData(0x6A, vsp); //VL#
+ break;
+ }
+}
+
+void MCUFRIEND_kbv::invertDisplay(boolean i)
+{
+ uint8_t val;
+ _lcd_rev = ((_lcd_capable & REV_SCREEN) != 0) ^ i;
+ if (_lcd_capable & MIPI_DCS_REV1) {
+ if (is8347) {
+ // HX8347D: 0x36 Panel Characteristic. REV_Panel
+ // HX8347A: 0x36 is Display Control 10
+ if (_lcd_ID == 0x8347 || _lcd_ID == 0x5252) // HX8347-A, HX5352-A
+ val = _lcd_rev ? 6 : 2; //INVON id bit#2, NORON=bit#1
+ else val = _lcd_rev ? 8 : 10; //HX8347-D, G, I: SCROLLON=bit3, INVON=bit1
+ // HX8347: 0x01 Display Mode has diff bit mapping for A, D
+ WriteCmdParamN(0x01, 1, &val);
+ } else
+ WriteCmdParamN(_lcd_rev ? 0x21 : 0x20, 0, NULL);
+ return;
+ }
+ // cope with 9320 style variants:
+ switch (_lcd_ID) {
+#ifdef SUPPORT_0139
+ case 0x0139:
+#endif
+ case 0x9225: //REV is in reg(0x07) like Samsung
+ case 0x0154:
+ WriteCmdData(0x07, 0x13 | (_lcd_rev << 2)); //.kbv kludge
+ break;
+#ifdef SUPPORT_1289
+ case 0x1289:
+ _lcd_drivOut &= ~(1 << 13);
+ if (_lcd_rev)
+ _lcd_drivOut |= (1 << 13);
+ WriteCmdData(0x01, _lcd_drivOut);
+ break;
+#endif
+ case 0x5420:
+ case 0x7793:
+ case 0x9326:
+ case 0xB509:
+ WriteCmdData(0x401, (1 << 1) | _lcd_rev); //.kbv kludge VLE
+ break;
+ default:
+ WriteCmdData(0x61, _lcd_rev);
+ break;
+ }
+}
+
+#define TFTLCD_DELAY 0xFFFF
+#define TFTLCD_DELAY8 0x7F
+static void init_table(const void *table, int16_t size)
+{
+#ifdef SUPPORT_8357D_GAMMA
+ uint8_t *p = (uint8_t *) table, dat[36]; //HX8357_99 has GAMMA[34]
+#else
+ uint8_t *p = (uint8_t *) table, dat[24]; //R61526 has GAMMA[22]
+#endif
+ while (size > 0) {
+ uint8_t cmd = pgm_read_byte(p++);
+ uint8_t len = pgm_read_byte(p++);
+ if (cmd == TFTLCD_DELAY8) {
+ delay(len);
+ len = 0;
+ } else {
+ for (uint8_t i = 0; i < len; i++)
+ dat[i] = pgm_read_byte(p++);
+ WriteCmdParamN(cmd, len, dat);
+ }
+ size -= len + 2;
+ }
+}
+
+static void init_table16(const void *table, int16_t size)
+{
+ uint16_t *p = (uint16_t *) table;
+ while (size > 0) {
+ uint16_t cmd = pgm_read_word(p++);
+ uint16_t d = pgm_read_word(p++);
+ if (cmd == TFTLCD_DELAY)
+ delay(d);
+ else {
+ writecmddata(cmd, d); //static function
+ }
+ size -= 2 * sizeof(int16_t);
+ }
+}
+
+void MCUFRIEND_kbv::begin(uint16_t ID)
+{
+ int16_t *p16; //so we can "write" to a const protected variable.
+ const uint8_t *table8_ads = NULL;
+ int16_t table_size;
+ reset();
+ _lcd_xor = 0;
+ switch (_lcd_ID = ID) {
+/*
+ static const uint16_t _regValues[] PROGMEM = {
+ 0x0000, 0x0001, // start oscillation
+ 0x0007, 0x0000, // source output control 0 D0
+ 0x0013, 0x0000, // power control 3 off
+ 0x0011, 0x2604, //
+ 0x0014, 0x0015, //
+ 0x0010, 0x3C00, //
+ // 0x0013, 0x0040, //
+ // 0x0013, 0x0060, //
+ // 0x0013, 0x0070, //
+ 0x0013, 0x0070, // power control 3 PON PON1 AON
+
+ 0x0001, 0x0127, // driver output control
+ // 0x0002, 0x0700, // field 0 b/c waveform xor waveform
+ 0x0003, 0x1030, //
+ 0x0007, 0x0000, //
+ 0x0008, 0x0404, //
+ 0x000B, 0x0200, //
+ 0x000C, 0x0000, //
+ 0x00015,0x0000, //
+
+ //gamma setting
+ 0x0030, 0x0000,
+ 0x0031, 0x0606,
+ 0x0032, 0x0006,
+ 0x0033, 0x0403,
+ 0x0034, 0x0107,
+ 0x0035, 0x0101,
+ 0x0036, 0x0707,
+ 0x0037, 0x0304,
+ 0x0038, 0x0A00,
+ 0x0039, 0x0706,
+
+ 0x0040, 0x0000,
+ 0x0041, 0x0000,
+ 0x0042, 0x013F,
+ 0x0043, 0x0000,
+ 0x0044, 0x0000,
+ 0x0045, 0x0000,
+ 0x0046, 0xEF00,
+ 0x0047, 0x013F,
+ 0x0048, 0x0000,
+ 0x0007, 0x0011,
+ 0x0007, 0x0017,
+};
+*/
+#ifdef SUPPORT_0139
+ case 0x0139:
+ _lcd_capable = REV_SCREEN | XSA_XEA_16BIT; //remove AUTO_READINC
+ static const uint16_t S6D0139_regValues[] PROGMEM = {
+ 0x0000, 0x0001, //Start oscillator
+ 0x0011, 0x1a00, //Power Control 2
+ 0x0014, 0x2020, //Power Control 4
+ 0x0010, 0x0900, //Power Control 1
+ 0x0013, 0x0040, //Power Control 3
+ 0x0013, 0x0060, //Power Control 3
+ 0x0013, 0x0070, //Power Control 3
+ 0x0011, 0x1a04, //Power Control 2
+ 0x0010, 0x2f00, //Power Control 1
+ 0x0001, 0x0127, //Driver Control: SM=0, GS=0, SS=1, 240x320
+ 0x0002, 0x0100, //LCD Control: (.kbv was 0700) FLD=0, BC= 0, EOR=1
+ 0x0003, 0x1030, //Entry Mode: TR1=0, DFM=0, BGR=1, I_D=3
+ 0x0007, 0x0000, //Display Control: everything off
+ 0x0008, 0x0303, //Blank Period: FP=3, BP=3
+ 0x0009, 0x0000, //f.k.
+ 0x000b, 0x0000, //Frame Control:
+ 0x000c, 0x0000, //Interface Control: system i/f
+ 0x0040, 0x0000, //Scan Line
+ 0x0041, 0x0000, //Vertical Scroll Control
+ 0x0007, 0x0014, //Display Control: VLE1=0, SPT=0, GON=1, REV=1, D=0 (halt)
+ 0x0007, 0x0016, //Display Control: VLE1=0, SPT=0, GON=1, REV=1, D=2 (blank)
+ 0x0007, 0x0017, //Display Control: VLE1=0, SPT=0, GON=1, REV=1, D=3 (normal)
+// 0x0007, 0x0217, //Display Control: VLE1=1, SPT=0, GON=1, REV=1, D=3
+ };
+ init_table16(S6D0139_regValues, sizeof(S6D0139_regValues));
+ break;
+#endif
+
+#ifdef SUPPORT_0154
+ case 0x0154:
+ _lcd_capable = AUTO_READINC | REV_SCREEN;
+ static const uint16_t S6D0154_regValues[] PROGMEM = {
+ 0x0011, 0x001A,
+ 0x0012, 0x3121, //BT=3, DC1=1, DC2=2, DC3=1
+ 0x0013, 0x006C, //GVD=108
+ 0x0014, 0x4249, //VCM=66, VML=73
+
+ 0x0010, 0x0800, //SAP=8
+ TFTLCD_DELAY, 10,
+ 0x0011, 0x011A, //APON=0, PON=1, AON=0, VCI1_EN=1, VC=10
+ TFTLCD_DELAY, 10,
+ 0x0011, 0x031A, //APON=0, PON=3, AON=0, VCI1_EN=1, VC=10
+ TFTLCD_DELAY, 10,
+ 0x0011, 0x071A, //APON=0, PON=7, AON=0, VCI1_EN=1, VC=10
+ TFTLCD_DELAY, 10,
+ 0x0011, 0x0F1A, //APON=0, PON=15, AON=0, VCI1_EN=1, VC=10
+ TFTLCD_DELAY, 10,
+ 0x0011, 0x0F3A, //APON=0, PON=15, AON=1, VCI1_EN=1, VC=10
+ TFTLCD_DELAY, 30,
+
+ 0x0001, 0x0128,
+ 0x0002, 0x0100,
+ 0x0003, 0x1030,
+ 0x0007, 0x1012,
+ 0x0008, 0x0303,
+ 0x000B, 0x1100,
+ 0x000C, 0x0000,
+ 0x000F, 0x1801,
+ 0x0015, 0x0020,
+
+ 0x0050,0x0101,
+ 0x0051,0x0603,
+ 0x0052,0x0408,
+ 0x0053,0x0000,
+ 0x0054,0x0605,
+ 0x0055,0x0406,
+ 0x0056,0x0303,
+ 0x0057,0x0303,
+ 0x0058,0x0010,
+ 0x0059,0x1000,
+
+ 0x0007, 0x0012, //GON=1, REV=0, D=2
+ TFTLCD_DELAY, 40,
+ 0x0007, 0x0013, //GON=1, REV=0, D=3
+ 0x0007, 0x0017, //GON=1, REV=1, D=3 DISPLAY ON
+ };
+ init_table16(S6D0154_regValues, sizeof(S6D0154_regValues));
+
+ break;
+#endif
+
+#ifdef SUPPORT_1289
+ case 0x9797:
+ is9797 = 1;
+// _lcd_capable = 0 | XSA_XEA_16BIT | REV_SCREEN | AUTO_READINC | READ_24BITS;
+// deliberately set READ_BGR to disable Software Scroll in graphictest_kbv example
+ _lcd_capable = 0 | XSA_XEA_16BIT | REV_SCREEN | AUTO_READINC | READ_24BITS | READ_BGR;
+ _lcd_ID = 0x1289;
+ goto common_1289;
+ case 0x1289:
+ _lcd_capable = 0 | XSA_XEA_16BIT | REV_SCREEN | AUTO_READINC;
+ common_1289:
+ // came from MikroElektronika library http://www.hmsprojects.com/tft_lcd.html
+ static const uint16_t SSD1289_regValues[] PROGMEM = {
+ 0x0000, 0x0001,
+ 0x0003, 0xA8A4,
+ 0x000C, 0x0000,
+ 0x000D, 0x000A, // VRH=10
+ 0x000E, 0x2B00,
+ 0x001E, 0x00B7,
+ 0x0001, 0x2B3F, // setRotation() alters
+ 0x0002, 0x0600, // B_C=1, EOR=1
+ 0x0010, 0x0000,
+ 0x0011, 0x6070, // setRotation() alters
+ 0x0005, 0x0000,
+ 0x0006, 0x0000,
+ 0x0016, 0xEF1C,
+ 0x0017, 0x0003,
+ 0x0007, 0x0233,
+ 0x000B, 0x0000,
+ 0x000F, 0x0000,
+ 0x0030, 0x0707,
+ 0x0031, 0x0204,
+ 0x0032, 0x0204,
+ 0x0033, 0x0502,
+ 0x0034, 0x0507,
+ 0x0035, 0x0204,
+ 0x0036, 0x0204,
+ 0x0037, 0x0502,
+ 0x003A, 0x0302,
+ 0x003B, 0x0302,
+ 0x0023, 0x0000,
+ 0x0024, 0x0000,
+ 0x0025, 0x8000,
+ };
+ init_table16(SSD1289_regValues, sizeof(SSD1289_regValues));
+ break;
+#endif
+
+ case 0x1511: // Unknown from Levy
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1; //extra read_8(dummy)
+ static const uint8_t R61511_regValues[] PROGMEM = {
+ 0xB0, 1, 0x00, //Command Access Protect
+ };
+ table8_ads = R61511_regValues, table_size = sizeof(R61511_regValues);
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 480;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 320;
+ break;
+
+ case 0x1520:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS;
+ static const uint8_t R61520_regValues[] PROGMEM = {
+ 0xB0, 1, 0x00, //Command Access Protect
+ 0xC0, 1, 0x0A, //DM=1, BGR=1
+ };
+ table8_ads = R61520_regValues, table_size = sizeof(R61520_regValues);
+ break;
+
+ case 0x1526:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS;
+ static const uint8_t R61526_regValues[] PROGMEM = {
+ 0xB0, 1, 0x03, //Command Access
+ 0xE2, 1, 0x3F, //Command Write Access
+ 0xC0, 1, 0x22, //REV=0, BGR=1, SS=0
+ 0xE2, 1, 0x00, //Command Write Protect
+ };
+ table8_ads = R61526_regValues, table_size = sizeof(R61526_regValues);
+ break;
+
+#ifdef SUPPORT_1580
+ case 0x1580:
+ _lcd_capable = 0 | REV_SCREEN | READ_BGR | INVERT_GS | READ_NODUMMY; //thanks vanhan123
+ static const uint16_t R61580_regValues[] PROGMEM = { //from MCHIP Graphics Lib drvTFT001.c
+ // Synchronization after reset
+ TFTLCD_DELAY, 2,
+ 0x0000, 0x0000,
+ 0x0000, 0x0000,
+ 0x0000, 0x0000,
+ 0x0000, 0x0000,
+
+ // Setup display
+ 0x00A4, 0x0001, // CALB=1
+ TFTLCD_DELAY, 2,
+ 0x0060, 0xA700, // Driver Output Control
+ 0x0008, 0x0808, // Display Control BP=8, FP=8
+ 0x0030, 0x0111, // y control
+ 0x0031, 0x2410, // y control
+ 0x0032, 0x0501, // y control
+ 0x0033, 0x050C, // y control
+ 0x0034, 0x2211, // y control
+ 0x0035, 0x0C05, // y control
+ 0x0036, 0x2105, // y control
+ 0x0037, 0x1004, // y control
+ 0x0038, 0x1101, // y control
+ 0x0039, 0x1122, // y control
+ 0x0090, 0x0019, // 80Hz
+ 0x0010, 0x0530, // Power Control
+ 0x0011, 0x0237, //DC1=2, DC0=3, VC=7
+// 0x0011, 0x17B0, //DC1=7, DC0=3, VC=0 ?b12 ?b7 vanhan123
+ 0x0012, 0x01BF, //VCMR=1, PSON=1, PON=1, VRH=15
+// 0x0012, 0x013A, //VCMR=1, PSON=1, PON=1, VRH=10 vanhan123
+ 0x0013, 0x1300, //VDV=19
+ TFTLCD_DELAY, 100,
+
+ 0x0001, 0x0100,
+ 0x0002, 0x0200,
+ 0x0003, 0x1030,
+ 0x0009, 0x0001,
+ 0x000A, 0x0008,
+ 0x000C, 0x0001,
+ 0x000D, 0xD000,
+ 0x000E, 0x0030,
+ 0x000F, 0x0000,
+ 0x0020, 0x0000,
+ 0x0021, 0x0000,
+ 0x0029, 0x0077,
+ 0x0050, 0x0000,
+ 0x0051, 0xD0EF,
+ 0x0052, 0x0000,
+ 0x0053, 0x013F,
+ 0x0061, 0x0001,
+ 0x006A, 0x0000,
+ 0x0080, 0x0000,
+ 0x0081, 0x0000,
+ 0x0082, 0x005F,
+ 0x0093, 0x0701,
+ 0x0007, 0x0100,
+ };
+ static const uint16_t R61580_DEM240320C[] PROGMEM = { //from DEM 240320C TMH-PW-N
+ 0x00, 0x0000,
+ 0x00, 0x0000,
+ TFTLCD_DELAY, 100,
+ 0x00, 0x0000,
+ 0x00, 0x0000,
+ 0x00, 0x0000,
+ 0x00, 0x0000,
+ 0xA4, 0x0001,
+ TFTLCD_DELAY, 100,
+ 0x60, 0xA700,
+ 0x08, 0x0808,
+ /******************************************/
+ //Gamma Setting:
+ 0x30, 0x0203,
+ 0x31, 0x080F,
+ 0x32, 0x0401,
+ 0x33, 0x050B,
+ 0x34, 0x3330,
+ 0x35, 0x0B05,
+ 0x36, 0x0005,
+ 0x37, 0x0F08,
+ 0x38, 0x0302,
+ 0x39, 0x3033,
+ /******************************************/
+ //Power Setting:
+ 0x90, 0x0018, //80Hz
+ 0x10, 0x0530, //BT,AP
+ 0x11, 0x0237, //DC1,DC0,VC
+ 0x12, 0x01BF,
+ 0x13, 0x1000, //VCOM
+ TFTLCD_DELAY, 200,
+ /******************************************/
+ 0x01, 0x0100,
+ 0x02, 0x0200,
+ 0x03, 0x1030,
+ 0x09, 0x0001,
+ 0x0A, 0x0008,
+ 0x0C, 0x0000,
+ 0x0D, 0xD000,
+
+ 0x0E, 0x0030,
+ 0x0F, 0x0000,
+ 0x20, 0x0000, //H Start
+ 0x21, 0x0000, //V Start
+ 0x29, 0x002E,
+ 0x50, 0x0000,
+ 0x51, 0x00EF,
+ 0x52, 0x0000,
+ 0x53, 0x013F,
+ 0x61, 0x0001,
+ 0x6A, 0x0000,
+ 0x80, 0x0000,
+ 0x81, 0x0000,
+ 0x82, 0x005F,
+ 0x93, 0x0701,
+ /******************************************/
+ 0x07, 0x0100,
+ TFTLCD_DELAY, 100,
+ };
+ init_table16(R61580_DEM240320C, sizeof(R61580_DEM240320C));
+// init_table16(R61580_regValues, sizeof(R61580_regValues));
+ break;
+#endif
+
+#if defined(SUPPORT_1963) && USING_16BIT_BUS
+ case 0x1963:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | READ_NODUMMY | INVERT_SS | INVERT_RGB;
+ // from NHD 5.0" 8-bit
+ static const uint8_t SSD1963_NHD_50_regValues[] PROGMEM = {
+ (0xE0), 1, 0x01, // PLL enable
+ TFTLCD_DELAY8, 10,
+ (0xE0), 1, 0x03, // Lock PLL
+ (0xB0), 7, 0x08, 0x80, 0x03, 0x1F, 0x01, 0xDF, 0x00, //LCD SPECIFICATION
+ (0xF0), 1, 0x03, //was 00 pixel data interface
+ // (0x3A), 1, 0x60, // SET R G B format = 6 6 6
+ (0xE2), 3, 0x1D, 0x02, 0x54, //PLL multiplier, set PLL clock to 120M
+ (0xE6), 3, 0x02, 0xFF, 0xFF, //PLL setting for PCLK, depends on resolution
+ (0xB4), 8, 0x04, 0x20, 0x00, 0x58, 0x80, 0x00, 0x00, 0x00, //HSYNC
+ (0xB6), 7, 0x02, 0x0D, 0x00, 0x20, 0x01, 0x00, 0x00, //VSYNC
+ (0x13), 0, //Enter Normal mode
+ (0x38), 0, //Exit Idle mode
+ };
+ // from NHD 7.0" 8-bit
+ static const uint8_t SSD1963_NHD_70_regValues[] PROGMEM = {
+ (0xE2), 3, 0x1D, 0x02, 0x04, //PLL multiplier, set PLL clock to 120M
+ (0xE0), 1, 0x01, // PLL enable
+ TFTLCD_DELAY8, 10,
+ (0xE0), 1, 0x03, // Lock PLL
+ 0x01, 0, //Soft Reset
+ TFTLCD_DELAY8, 120,
+ (0xB0), 7, 0x08, 0x80, 0x03, 0x1F, 0x01, 0xDF, 0x00, //LCD SPECIFICATION
+ (0xF0), 1, 0x03, //was 00 pixel data interface
+ // (0x3A), 1, 0x60, // SET R G B format = 6 6 6
+ (0xE6), 3, 0x0F, 0xFF, 0xFF, //PLL setting for PCLK, depends on resolution
+ (0xB4), 8, 0x04, 0x20, 0x00, 0x58, 0x80, 0x00, 0x00, 0x00, //HSYNC
+ (0xB6), 7, 0x02, 0x0D, 0x00, 0x20, 0x01, 0x00, 0x00, //VSYNC
+ (0x13), 0, //Enter Normal mode
+ (0x38), 0, //Exit Idle mode
+ };
+ // from UTFTv2.81 initlcd.h
+ static const uint8_t SSD1963_800_regValues[] PROGMEM = {
+ (0xE2), 3, 0x1E, 0x02, 0x54, //PLL multiplier, set PLL clock to 120M
+ (0xE0), 1, 0x01, // PLL enable
+ TFTLCD_DELAY8, 10,
+ (0xE0), 1, 0x03, //
+ TFTLCD_DELAY8, 10,
+ 0x01, 0, //Soft Reset
+ TFTLCD_DELAY8, 100,
+ (0xE6), 3, 0x03, 0xFF, 0xFF, //PLL setting for PCLK, depends on resolution
+ (0xB0), 7, 0x24, 0x00, 0x03, 0x1F, 0x01, 0xDF, 0x00, //LCD SPECIFICATION
+ // (0xB0), 7, 0x24, 0x00, 0x03, 0x1F, 0x01, 0xDF, 0x2D, //LCD SPECIFICATION
+ (0xB4), 8, 0x03, 0xA0, 0x00, 0x2E, 0x30, 0x00, 0x0F, 0x00, //HSYNC
+ (0xB6), 7, 0x02, 0x0D, 0x00, 0x10, 0x10, 0x00, 0x08, //VSYNC
+ (0xBA), 1, 0x0F, //GPIO[3:0] out 1
+ (0xB8), 2, 0x07, 0x01, //GPIO3=input, GPIO[2:0]=output
+ (0xF0), 1, 0x03, //pixel data interface
+ TFTLCD_DELAY8, 1,
+ 0x28, 0, //Display Off
+ 0x11, 0, //Sleep Out
+ TFTLCD_DELAY8, 100,
+ 0x29, 0, //Display On
+ (0xBE), 6, 0x06, 0xF0, 0x01, 0xF0, 0x00, 0x00, //set PWM for B/L
+ (0xD0), 1, 0x0D,
+ };
+ // from UTFTv2.82 initlcd.h
+ static const uint8_t SSD1963_800NEW_regValues[] PROGMEM = {
+ (0xE2), 3, 0x1E, 0x02, 0x54, //PLL multiplier, set PLL clock to 120M
+ (0xE0), 1, 0x01, // PLL enable
+ TFTLCD_DELAY8, 10,
+ (0xE0), 1, 0x03, //
+ TFTLCD_DELAY8, 10,
+ 0x01, 0, //Soft Reset
+ TFTLCD_DELAY8, 100,
+ (0xE6), 3, 0x03, 0xFF, 0xFF, //PLL setting for PCLK, depends on resolution
+ (0xB0), 7, 0x24, 0x00, 0x03, 0x1F, 0x01, 0xDF, 0x00, //LCD SPECIFICATION
+ (0xB4), 8, 0x03, 0xA0, 0x00, 0x2E, 0x30, 0x00, 0x0F, 0x00, //HSYNC HT=928, HPS=46, HPW=48, LPS=15
+ (0xB6), 7, 0x02, 0x0D, 0x00, 0x10, 0x10, 0x00, 0x08, //VSYNC VT=525, VPS=16, VPW=16, FPS=8
+ (0xBA), 1, 0x0F, //GPIO[3:0] out 1
+ (0xB8), 2, 0x07, 0x01, //GPIO3=input, GPIO[2:0]=output
+ (0xF0), 1, 0x03, //pixel data interface
+ TFTLCD_DELAY8, 1,
+ 0x28, 0, //Display Off
+ 0x11, 0, //Sleep Out
+ TFTLCD_DELAY8, 100,
+ 0x29, 0, //Display On
+ (0xBE), 6, 0x06, 0xF0, 0x01, 0xF0, 0x00, 0x00, //set PWM for B/L
+ (0xD0), 1, 0x0D,
+ };
+ // from UTFTv2.82 initlcd.h
+ static const uint8_t SSD1963_800ALT_regValues[] PROGMEM = {
+ (0xE2), 3, 0x23, 0x02, 0x04, //PLL multiplier, set PLL clock to 120M
+ (0xE0), 1, 0x01, // PLL enable
+ TFTLCD_DELAY8, 10,
+ (0xE0), 1, 0x03, //
+ TFTLCD_DELAY8, 10,
+ 0x01, 0, //Soft Reset
+ TFTLCD_DELAY8, 100,
+ (0xE6), 3, 0x04, 0x93, 0xE0, //PLL setting for PCLK, depends on resolution
+ (0xB0), 7, 0x00, 0x00, 0x03, 0x1F, 0x01, 0xDF, 0x00, //LCD SPECIFICATION
+ (0xB4), 8, 0x03, 0xA0, 0x00, 0x2E, 0x30, 0x00, 0x0F, 0x00, //HSYNC HT=928, HPS=46, HPW=48, LPS=15
+ (0xB6), 7, 0x02, 0x0D, 0x00, 0x10, 0x10, 0x00, 0x08, //VSYNC VT=525, VPS=16, VPW=16, FPS=8
+ (0xBA), 1, 0x0F, //GPIO[3:0] out 1
+ (0xB8), 2, 0x07, 0x01, //GPIO3=input, GPIO[2:0]=output
+ (0xF0), 1, 0x03, //pixel data interface
+ TFTLCD_DELAY8, 1,
+ 0x28, 0, //Display Off
+ 0x11, 0, //Sleep Out
+ TFTLCD_DELAY8, 100,
+ 0x29, 0, //Display On
+ (0xBE), 6, 0x06, 0xF0, 0x01, 0xF0, 0x00, 0x00, //set PWM for B/L
+ (0xD0), 1, 0x0D,
+ };
+ // from UTFTv2.82 initlcd.h
+ static const uint8_t SSD1963_480_regValues[] PROGMEM = {
+ (0xE2), 3, 0x23, 0x02, 0x54, //PLL multiplier, set PLL clock to 120M
+ (0xE0), 1, 0x01, // PLL enable
+ TFTLCD_DELAY8, 10,
+ (0xE0), 1, 0x03, //
+ TFTLCD_DELAY8, 10,
+ 0x01, 0, //Soft Reset
+ TFTLCD_DELAY8, 100,
+ (0xE6), 3, 0x01, 0x1F, 0xFF, //PLL setting for PCLK, depends on resolution
+ (0xB0), 7, 0x20, 0x00, 0x01, 0xDF, 0x01, 0x0F, 0x00, //LCD SPECIFICATION
+ (0xB4), 8, 0x02, 0x13, 0x00, 0x08, 0x2B, 0x00, 0x02, 0x00, //HSYNC
+ (0xB6), 7, 0x01, 0x20, 0x00, 0x04, 0x0C, 0x00, 0x02, //VSYNC
+ (0xBA), 1, 0x0F, //GPIO[3:0] out 1
+ (0xB8), 2, 0x07, 0x01, //GPIO3=input, GPIO[2:0]=output
+ (0xF0), 1, 0x03, //pixel data interface
+ TFTLCD_DELAY8, 1,
+ 0x28, 0, //Display Off
+ 0x11, 0, //Sleep Out
+ TFTLCD_DELAY8, 100,
+ 0x29, 0, //Display On
+ (0xBE), 6, 0x06, 0xF0, 0x01, 0xF0, 0x00, 0x00, //set PWM for B/L
+ (0xD0), 1, 0x0D,
+ };
+// table8_ads = SSD1963_480_regValues, table_size = sizeof(SSD1963_480_regValues);
+ table8_ads = SSD1963_800_regValues, table_size = sizeof(SSD1963_800_regValues);
+// table8_ads = SSD1963_NHD_50_regValues, table_size = sizeof(SSD1963_NHD_50_regValues);
+// table8_ads = SSD1963_NHD_70_regValues, table_size = sizeof(SSD1963_NHD_70_regValues);
+// table8_ads = SSD1963_800NEW_regValues, table_size = sizeof(SSD1963_800NEW_regValues);
+// table8_ads = SSD1963_800ALT_regValues, table_size = sizeof(SSD1963_800ALT_regValues);
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 480;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 800;
+ break;
+#endif
+
+#ifdef SUPPORT_4532
+//Support for LG Electronics LGDP4532 (also 4531 i guess) by Leodino v1.0 2-Nov-2016
+//based on data by waveshare and the datasheet of LG Electronics
+//My approach to get it working: the parameters by waveshare did no make it function allright
+//I started with remming lines to see if this helped. Basically the stuff in range 41-93
+//gives problems.
+//The other lines that are REMmed give no problems, but it seems default values are OK as well.
+case 0x4532: // thanks Leodino
+ _lcd_capable = 0 | REV_SCREEN; // | INVERT_GS;
+ static const uint16_t LGDP4532_regValues[] PROGMEM = {
+ 0x0000,0x0001, //Device code read
+ 0x0010,0x0628, //Power control 1 SAP[2:0] BT[3:0] AP[2:0] DK DSTB SLP
+ 0x0012,0x0006, //Power control 3 PON VRH[3:0]
+ //0x0013,0x0A32, //Power control 4 VCOMG VDV[4:0] VCM[6:0]
+ 0x0011,0x0040, //Power control 2; DC1[2:0] DC0[2:0] VC[2:0]
+ //0x0015,0x0050, //Regulator control RSET RI[2:0] RV[2:0] RCONT[2:0]
+ 0x0012,0x0016, //Power control 3 PON VRH[3:0]
+ TFTLCD_DELAY,50,
+ 0x0010,0x5660, //Power control 1 SAP[2:0] BT[3:0] AP[2:0] DK DSTB SLP
+ TFTLCD_DELAY,50,
+ //0x0013,0x2A4E, //Power control 4 VCOMG VDV[4:0] VCM[6:0]
+ //0x0001,0x0100, //Driver output control SM SS
+ //0x0002,0x0300, //LCD Driving Wave Control
+ //0x0003,0x1030, //Entry mode TRI DFM BGR ORG I/D[1:0] AM
+ //0x0007,0x0202, //Display Control 1 PTDE[1:0] BASEE GON DTE COL D[1:0]
+ TFTLCD_DELAY,50,
+ //0x0008,0x0202, //Display Control 2 FP[3:0] BP[3:0] front and back porch (blank period at begin and end..)
+ //0x000A,0x0000, //Test Register 1 (RA0h)
+ //Gamma adjustment
+ 0x0030,0x0000,
+ 0x0031,0x0402,
+ 0x0032,0x0106,
+ 0x0033,0x0700,
+ 0x0034,0x0104,
+ 0x0035,0x0301,
+ 0x0036,0x0707,
+ 0x0037,0x0305,
+ 0x0038,0x0208,
+ 0x0039,0x0F0B,
+ TFTLCD_DELAY,50,
+ //some of this stuff in range 41-93 really throws things off....
+ //0x0041,0x0002,
+ //0x0060,0x2700, //Driver Output Control (R60h)
+ //0x0061,0x0001, //Base Image Display Control (R61h)
+ //0x0090,0x0119, //Panel Interface Control 1 (R90h) DIVI[1:0] RTNI[4:0]
+ //0x0092,0x010A, //Panel Interface Control 2 (R92h) NOWI[2:0] EQI2[1:0] EQI1[1:0]
+ //0x0093,0x0004, //Panel Interface Control 3 (R93h) MCPI[2:0]
+ //0x00A0,0x0100, //Test Register 1 (RA0h)
+ TFTLCD_DELAY,50,
+ 0x0007,0x0133, //Display Control 1 PTDE[1:0] BASEE GON DTE COL D[1:0]
+ TFTLCD_DELAY,50,
+ //0x00A0,0x0000, //Test Register 1 (RA0h)
+ };
+ init_table16(LGDP4532_regValues, sizeof(LGDP4532_regValues));
+ break;
+#endif
+
+#ifdef SUPPORT_4535
+ case 0x4535:
+ _lcd_capable = 0 | REV_SCREEN; // | INVERT_GS;
+ static const uint16_t LGDP4535_regValues[] PROGMEM = {
+ 0x0015, 0x0030, // Set the internal vcore voltage
+ 0x009A, 0x0010, // Start internal OSC
+ 0x0011, 0x0020, // set SS and SM bit
+ 0x0010, 0x3428, // set 1 line inversion
+ 0x0012, 0x0002, // set GRAM write direction and BGR=1
+ 0x0013, 0x1038, // Resize register
+ TFTLCD_DELAY, 40,
+ 0x0012, 0x0012, // set the back porch and front porch
+ TFTLCD_DELAY, 40,
+ 0x0010, 0x3420, // set non-display area refresh cycle ISC[3:0]
+ 0x0013, 0x3045, // FMARK function
+ TFTLCD_DELAY, 70,
+ 0x0030, 0x0000, // RGB interface setting
+ 0x0031, 0x0402, // Frame marker Position
+ 0x0032, 0x0307, // RGB interface polarity
+ 0x0033, 0x0304, // SAP, BT[3:0], AP, DSTB, SLP, STB
+ 0x0034, 0x0004, // DC1[2:0], DC0[2:0], VC[2:0]
+ 0x0035, 0x0401, // VREG1OUT voltage
+ 0x0036, 0x0707, // VDV[4:0] for VCOM amplitude
+ 0x0037, 0x0305, // SAP, BT[3:0], AP, DSTB, SLP, STB
+ 0x0038, 0x0610, // DC1[2:0], DC0[2:0], VC[2:0]
+ 0x0039, 0x0610, // VREG1OUT voltage
+ 0x0001, 0x0100, // VDV[4:0] for VCOM amplitude
+ 0x0002, 0x0300, // VCM[4:0] for VCOMH
+ 0x0003, 0x1030, // GRAM horizontal Address
+ 0x0008, 0x0808, // GRAM Vertical Address
+ 0x000A, 0x0008,
+ 0x0060, 0x2700, // Gate Scan Line
+ 0x0061, 0x0001, // NDL,VLE, REV
+ 0x0090, 0x013E,
+ 0x0092, 0x0100,
+ 0x0093, 0x0100,
+ 0x00A0, 0x3000,
+ 0x00A3, 0x0010,
+ 0x0007, 0x0001,
+ 0x0007, 0x0021,
+ 0x0007, 0x0023,
+ 0x0007, 0x0033,
+ 0x0007, 0x0133,
+ };
+ init_table16(LGDP4535_regValues, sizeof(LGDP4535_regValues));
+ break;
+#endif
+
+ case 0x5310:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | INVERT_SS | INVERT_RGB | READ_24BITS;
+ static const uint8_t NT35310_regValues[] PROGMEM = { //
+ TFTLCD_DELAY8, 10, //just some dummy
+ };
+ table8_ads = NT35310_regValues, table_size = sizeof(NT35310_regValues);
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 480;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 320;
+ break;
+
+#ifdef SUPPORT_68140
+ case 0x6814:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS;
+ static const uint8_t RM68140_regValues_max[] PROGMEM = { //
+ 0x3A, 1, 0x55, //Pixel format .kbv my Mega Shield
+ };
+ table8_ads = RM68140_regValues_max, table_size = sizeof(RM68140_regValues_max);
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 480;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 320;
+ break;
+#endif
+
+#ifdef SUPPORT_7735
+ case 0x7735: //
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | REV_SCREEN | READ_24BITS;
+ static const uint8_t PROGMEM table7735S[] = {
+ // (COMMAND_BYTE), n, data_bytes....
+ 0xB1, 3, 0x01, 0x2C, 0x2D, // [05 3C 3C] FRMCTR1 if GM==11
+ 0xB2, 3, 0x01, 0x2C, 0x2D, // [05 3C 3C]
+ 0xB3, 6, 0x01, 0x2C, 0x2D, 0x01, 0x2C, 0x2D, // [05 3C 3C 05 3C 3C]
+ 0xB4, 1, 0x07, // [07] INVCTR Column inversion
+ //ST7735XR Power Sequence
+ 0xC0, 3, 0xA2, 0x02, 0x84, // [A8 08 84] PWCTR1
+ 0xC1, 1, 0xC5, // [C0]
+ 0xC2, 2, 0x0A, 0x00, // [0A 00]
+ 0xC3, 2, 0x8A, 0x2A, // [8A 26]
+ 0xC4, 2, 0x8A, 0xEE, // [8A EE]
+ 0xC5, 1, 0x0E, // [05] VMCTR1 VCOM
+ };
+ table8_ads = table7735S, table_size = sizeof(table7735S); //
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 160;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 128;
+ break;
+#endif
+
+#ifdef SUPPORT_7781
+ case 0x7783:
+ _lcd_capable = AUTO_READINC | REV_SCREEN | INVERT_GS;
+ static const uint16_t ST7781_regValues[] PROGMEM = {
+ 0x00FF, 0x0001, //can we do 0xFF
+ 0x00F3, 0x0008,
+ // LCD_Write_COM(0x00F3,
+
+ 0x00, 0x0001,
+ 0x0001, 0x0100, // Driver Output Control Register (R01h)
+ 0x0002, 0x0700, // LCD Driving Waveform Control (R02h)
+ 0x0003, 0x1030, // Entry Mode (R03h)
+ 0x0008, 0x0302,
+ 0x0009, 0x0000,
+ 0x0010, 0x0000, // Power Control 1 (R10h)
+ 0x0011, 0x0007, // Power Control 2 (R11h)
+ 0x0012, 0x0000, // Power Control 3 (R12h)
+ 0x0013, 0x0000, // Power Control 4 (R13h)
+ TFTLCD_DELAY, 50,
+ 0x0010, 0x14B0, // Power Control 1 SAP=1, BT=4, APE=1, AP=3
+ TFTLCD_DELAY, 10,
+ 0x0011, 0x0007, // Power Control 2 VC=7
+ TFTLCD_DELAY, 10,
+ 0x0012, 0x008E, // Power Control 3 VCIRE=1, VRH=14
+ 0x0013, 0x0C00, // Power Control 4 VDV=12
+ 0x0029, 0x0015, // NVM read data 2 VCM=21
+ TFTLCD_DELAY, 10,
+ 0x0030, 0x0000, // Gamma Control 1
+ 0x0031, 0x0107, // Gamma Control 2
+ 0x0032, 0x0000, // Gamma Control 3
+ 0x0035, 0x0203, // Gamma Control 6
+ 0x0036, 0x0402, // Gamma Control 7
+ 0x0037, 0x0000, // Gamma Control 8
+ 0x0038, 0x0207, // Gamma Control 9
+ 0x0039, 0x0000, // Gamma Control 10
+ 0x003C, 0x0203, // Gamma Control 13
+ 0x003D, 0x0403, // Gamma Control 14
+ 0x0060, 0xA700, // Driver Output Control (R60h) .kbv was 0xa700
+ 0x0061, 0x0001, // Driver Output Control (R61h)
+ 0x0090, 0X0029, // Panel Interface Control 1 (R90h)
+
+ // Display On
+ 0x0007, 0x0133, // Display Control (R07h)
+ TFTLCD_DELAY, 50,
+ };
+ init_table16(ST7781_regValues, sizeof(ST7781_regValues));
+ break;
+#endif
+
+ case 0x7789:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS;
+ static const uint8_t ST7789_regValues[] PROGMEM = {
+ (0xB2), 5, 0x0C, 0x0C, 0x00, 0x33, 0x33, //PORCTRK: Porch setting [08 08 00 22 22] PSEN=0 anyway
+ (0xB7), 1, 0x35, //GCTRL: Gate Control [35]
+ (0xBB), 1, 0x2B, //VCOMS: VCOM setting VCOM=1.175 [20] VCOM=0.9
+ (0xC0), 1, 0x04, //LCMCTRL: LCM Control [2C]
+ (0xC2), 2, 0x01, 0xFF, //VDVVRHEN: VDV and VRH Command Enable [01 FF]
+ (0xC3), 1, 0x11, //VRHS: VRH Set VAP=4.4, VAN=-4.4 [0B]
+ (0xC4), 1, 0x20, //VDVS: VDV Set [20]
+ (0xC6), 1, 0x0F, //FRCTRL2: Frame Rate control in normal mode [0F]
+ (0xD0), 2, 0xA4, 0xA1, //PWCTRL1: Power Control 1 [A4 A1]
+ (0xE0), 14, 0xD0, 0x00, 0x05, 0x0E, 0x15, 0x0D, 0x37, 0x43, 0x47, 0x09, 0x15, 0x12, 0x16, 0x19, //PVGAMCTRL: Positive Voltage Gamma control
+ (0xE1), 14, 0xD0, 0x00, 0x05, 0x0D, 0x0C, 0x06, 0x2D, 0x44, 0x40, 0x0E, 0x1C, 0x18, 0x16, 0x19, //NVGAMCTRL: Negative Voltage Gamma control
+ };
+ static const uint8_t ST7789_regValues_arcain6[] PROGMEM = {
+ (0xB2), 5, 0x0C, 0x0C, 0x00, 0x33, 0x33, //PORCTRK: Porch setting [08 08 00 22 22] PSEN=0 anyway
+ (0xB7), 1, 0x35, //GCTRL: Gate Control [35]
+ (0xBB), 1, 0x35, //VCOMS: VCOM setting VCOM=??? [20] VCOM=0.9
+ (0xC0), 1, 0x2C, //LCMCTRL: LCM Control [2C]
+ (0xC2), 2, 0x01, 0xFF, //VDVVRHEN: VDV and VRH Command Enable [01 FF]
+ (0xC3), 1, 0x13, //VRHS: VRH Set VAP=???, VAN=-??? [0B]
+ (0xC4), 1, 0x20, //VDVS: VDV Set [20]
+ (0xC6), 1, 0x0F, //FRCTRL2: Frame Rate control in normal mode [0F]
+ (0xCA), 1, 0x0F, //REGSEL2 [0F]
+ (0xC8), 1, 0x08, //REGSEL1 [08]
+ (0x55), 1, 0x90, //WRCACE [00]
+ (0xD0), 2, 0xA4, 0xA1, //PWCTRL1: Power Control 1 [A4 A1]
+ (0xE0), 14, 0xD0, 0x00, 0x06, 0x09, 0x0B, 0x2A, 0x3C, 0x55, 0x4B, 0x08, 0x16, 0x14, 0x19, 0x20, //PVGAMCTRL: Positive Voltage Gamma control
+ (0xE1), 14, 0xD0, 0x00, 0x06, 0x09, 0x0B, 0x29, 0x36, 0x54, 0x4B, 0x0D, 0x16, 0x14, 0x21, 0x20, //NVGAMCTRL: Negative Voltage Gamma control
+ };
+ table8_ads = ST7789_regValues, table_size = sizeof(ST7789_regValues); //
+ break;
+
+ case 0x8031: //Unknown BangGood thanks PrinceCharles
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS | REV_SCREEN;
+ static const uint8_t FK8031_regValues[] PROGMEM = {
+ // 0xF2:8.2 = SM, 0xF2:8.0 = REV. invertDisplay(), vertScroll() do not work
+ 0xF2,11, 0x16, 0x16, 0x03, 0x08, 0x08, 0x08, 0x08, 0x10, 0x04, 0x16, 0x16, // f.k. 0xF2:8.2 SM=1
+ 0xFD, 3, 0x11, 0x02, 0x35, //f.k 0xFD:1.1 creates contiguous scan lins
+ };
+ table8_ads = FK8031_regValues, table_size = sizeof(FK8031_regValues);
+ break;
+
+#ifdef SUPPORT_8347D
+ case 0x4747: //HX8347-D
+ _lcd_capable = REV_SCREEN | MIPI_DCS_REV1 | MV_AXIS | INVERT_SS | AUTO_READINC | READ_24BITS;
+ goto common_8347DGI;
+ case 0x6767: //HX8367-A
+ case 0x7575: //HX8347-G
+ case 0x9595: //HX8347-I
+ _lcd_capable = REV_SCREEN | MIPI_DCS_REV1 | MV_AXIS;
+ common_8347DGI:
+ is8347 = 1;
+ static const uint8_t HX8347G_2_regValues[] PROGMEM = {
+ 0xEA, 2, 0x00, 0x20, //PTBA[15:0]
+ 0xEC, 2, 0x0C, 0xC4, //STBA[15:0]
+ 0xE8, 1, 0x38, //OPON[7:0]
+ 0xE9, 1, 0x10, //OPON1[7:0]
+ 0xF1, 1, 0x01, //OTPS1B
+ 0xF2, 1, 0x10, //GEN
+ //Gamma 2.2 Setting
+ 0x40, 13, 0x01, 0x00, 0x00, 0x10, 0x0E, 0x24, 0x04, 0x50, 0x02, 0x13, 0x19, 0x19, 0x16,
+ 0x50, 14, 0x1B, 0x31, 0x2F, 0x3F, 0x3F, 0x3E, 0x2F, 0x7B, 0x09, 0x06, 0x06, 0x0C, 0x1D, 0xCC,
+ //Power Voltage Setting
+ 0x1B, 1, 0x1B, //VRH=4.65V
+ 0x1A, 1, 0x01, //BT (VGH~15V,VGL~-10V,DDVDH~5V)
+ 0x24, 1, 0x2F, //VMH(VCOM High voltage ~3.2V)
+ 0x25, 1, 0x57, //VML(VCOM Low voltage -1.2V)
+ //****VCOM offset**///
+ 0x23, 1, 0x88, //for Flicker adjust //can reload from OTP
+ //Power on Setting
+ 0x18, 1, 0x34, //I/P_RADJ,N/P_RADJ, Normal mode 60Hz
+ 0x19, 1, 0x01, //OSC_EN='1', start Osc
+ 0x01, 1, 0x00, //DP_STB='0', out deep sleep
+ 0x1F, 1, 0x88, // GAS=1, VOMG=00, PON=0, DK=1, XDK=0, DVDH_TRI=0, STB=0
+ TFTLCD_DELAY8, 5,
+ 0x1F, 1, 0x80, // GAS=1, VOMG=00, PON=0, DK=0, XDK=0, DVDH_TRI=0, STB=0
+ TFTLCD_DELAY8, 3,
+ 0x1F, 1, 0x90, // GAS=1, VOMG=00, PON=1, DK=0, XDK=0, DVDH_TRI=0, STB=0
+ TFTLCD_DELAY8, 5,
+ 0x1F, 1, 0xD0, // GAS=1, VOMG=10, PON=1, DK=0, XDK=0, DDVDH_TRI=0, STB=0
+ TFTLCD_DELAY8, 5,
+ //262k/65k color selection
+ 0x17, 1, 0x05, //default 0x06 262k color // 0x05 65k color
+ //SET PANEL
+ 0x36, 1, 0x00, //SS_P, GS_P,REV_P,BGR_P
+ //Display ON Setting
+ 0x28, 1, 0x38, //GON=1, DTE=1, D=1000
+ TFTLCD_DELAY8, 40,
+ 0x28, 1, 0x3F, //GON=1, DTE=1, D=1100
+
+ 0x16, 1, 0x18,
+ };
+ init_table(HX8347G_2_regValues, sizeof(HX8347G_2_regValues));
+ break;
+#endif
+
+#ifdef SUPPORT_8352A
+ case 0x5252: //HX8352-A
+ _lcd_capable = MIPI_DCS_REV1 | MV_AXIS;
+ is8347 = 1;
+ static const uint8_t HX8352A_regValues[] PROGMEM = {
+ 0x83, 1, 0x02, //Test Mode: TESTM=1
+ 0x85, 1, 0x03, //VDD ctl : VDC_SEL=3 [05]
+ 0x8B, 1, 0x01, //VGS_RES 1: RES_VGS1=1
+ 0x8C, 1, 0x93, //VGS_RES 2: RES_VGS2=1, anon=0x13 [93]
+ 0x91, 1, 0x01, //PWM control: SYNC=1
+ 0x83, 1, 0x00, //Test Mode: TESTM=0
+ //Gamma Setting
+ 0x3E, 12, 0xB0, 0x03, 0x10, 0x56, 0x13, 0x46, 0x23, 0x76, 0x00, 0x5E, 0x4F, 0x40,
+ //Power Voltage Setting
+ 0x17, 1, 0x91, //OSC 1: RADJ=9, OSC_EN=1 [F0]
+ 0x2B, 1, 0xF9, //Cycle 1: N_DC=F9 [BE]
+ TFTLCD_DELAY8, 10,
+ 0x1B, 1, 0x14, //Power 3: BT=1, ??=1, AP=0 [42]
+ 0x1A, 1, 0x11, //Power 2: VC3=1, VC1=1 [05]
+ 0x1C, 1, 0x06, //Power 4: VRH=6 [0D]
+ 0x1F, 1, 0x42, //VCOM : VCM=42 [55]
+ TFTLCD_DELAY8, 20,
+ 0x19, 1, 0x0A, //Power 1: DK=1, VL_TR1=1 [09]
+ 0x19, 1, 0x1A, //Power 1: PON=1, DK=1, VL_TR1=1 [09]
+ TFTLCD_DELAY8, 40,
+ 0x19, 1, 0x12, //Power 1: PON=1, DK=1, STB=1 [09]
+ TFTLCD_DELAY8, 40,
+ 0x1E, 1, 0x27, //Power 6: VCOMG=1, VDV=7 [10]
+ TFTLCD_DELAY8, 100,
+ //Display ON Setting
+ 0x24, 1, 0x60, //Display 2: PT=1, GON=1 [A0]
+ 0x3D, 1, 0x40, //Source 1: N_SAP=40 [C0]
+ 0x34, 1, 0x38, //Cycle 10: EQS=0x38 [38]
+ 0x35, 1, 0x38, //Cycle 11: EQP=0x38 [38]
+ 0x24, 1, 0x38, //Display 2: GON=1 D=2 [A0]
+ TFTLCD_DELAY8, 40,
+ 0x24, 1, 0x3C, //Display 2: GON=1 D=3 [A0]
+ 0x16, 1, 0x1C, //Memaccess: GS=1, BGR=1, SS=1
+ 0x01, 1, 0x06, //Disp Mode: INVON=1, NORON=1 [02]
+ 0x55, 1, 0x06, //SM_PANEL=0, SS_PANEL=0, GS_PANEL=1, REV_PANEL=1, BGR_PANEL=0
+ };
+ init_table(HX8352A_regValues, sizeof(HX8352A_regValues));
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 400;
+ break;
+#endif
+
+#ifdef SUPPORT_8352B
+ case 0x0065: //HX8352-B
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS | REV_SCREEN;
+ is8347 = 1;
+ static const uint8_t HX8352B_regValues[] PROGMEM = {
+ // Register setting for EQ setting
+ 0xe5, 1, 0x10, //
+ 0xe7, 1, 0x10, //
+ 0xe8, 1, 0x48, //
+ 0xec, 1, 0x09, //
+ 0xed, 1, 0x6c, //
+ // Power on Setting
+ 0x23, 1, 0x6F, //VMF
+ 0x24, 1, 0x57, //VMH
+ 0x25, 1, 0x71, //VML
+ 0xE2, 1, 0x18, //
+ 0x1B, 1, 0x15, //VRH
+ 0x01, 1, 0x00, //
+ 0x1C, 1, 0x03, //AP=3
+ // Power on sequence
+ 0x19, 1, 0x01, //OSCEN=1
+ TFTLCD_DELAY8, 5,
+ 0x1F, 1, 0x8C, //GASEN=1, DK=1, XDK=1
+ 0x1F, 1, 0x84, //GASEN=1, XDK=1
+ TFTLCD_DELAY8, 10,
+ 0x1F, 1, 0x94, //GASEN=1, PON=1, XDK=1
+ TFTLCD_DELAY8, 10,
+ 0x1F, 1, 0xD4, //GASEN=1, VCOMG=1, PON=1, XDK=1
+ TFTLCD_DELAY8, 5,
+ // Gamma Setting
+ 0x40, 13, 0x00, 0x2B, 0x29, 0x3E, 0x3D, 0x3F, 0x24, 0x74, 0x08, 0x06, 0x07, 0x0D, 0x17,
+ 0x50, 13, 0x00, 0x02, 0x01, 0x16, 0x14, 0x3F, 0x0B, 0x5B, 0x08, 0x12, 0x18, 0x19, 0x17,
+ 0x5D, 1, 0xFF, //
+
+ 0x16, 1, 0x08, //MemoryAccess BGR=1
+ 0x28, 1, 0x20, //GON=1
+ TFTLCD_DELAY8, 40,
+ 0x28, 1, 0x38, //GON=1, DTE=1, D=2
+ TFTLCD_DELAY8, 40,
+ 0x28, 1, 0x3C, //GON=1, DTE=1, D=3
+
+ 0x02, 2, 0x00, 0x00, //SC
+ 0x04, 2, 0x00, 0xEF, //EC
+ 0x06, 2, 0x00, 0x00, //SP
+ 0x08, 2, 0x01, 0x8F, //EP
+
+ 0x80, 2, 0x00, 0x00, //CAC
+ 0x82, 2, 0x00, 0x00, //RAC
+ 0x17, 1, 0x05, //COLMOD = 565
+
+ };
+ init_table(HX8352B_regValues, sizeof(HX8352B_regValues));
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 400;
+ break;
+#endif
+
+#ifdef SUPPORT_8347A
+ case 0x8347:
+ _lcd_capable = REV_SCREEN | MIPI_DCS_REV1 | MV_AXIS;
+ // AN.01 The reference setting of CMO 3.2” Panel
+ static const uint8_t HX8347A_CMO32_regValues[] PROGMEM = {
+ // VENDOR Gamma for 3.2"
+ (0x46), 12, 0xA4, 0x53, 0x00, 0x44, 0x04, 0x67, 0x33, 0x77, 0x12, 0x4C, 0x46, 0x44,
+ // Display Setting
+ (0x01), 1, 0x06, // IDMON=0, INVON=1, NORON=1, PTLON=0
+ (0x16), 1, 0x48, // MY=0, MX=0, MV=0, ML=1, BGR=0, TEON=0
+ (0x23), 3, 0x95, 0x95, 0xFF, // N_DC=1001 0101, PI_DC=1001 0101, I_DC=1111 1111
+
+ (0x27), 4, 0x02, 0x02, 0x02, 0x02, // N_BP=2, N_FP=2, PI_BP=2, PI_FP=2
+ (0x2C), 2, 0x02, 0x02, // I_BP=2, I_FP=2
+
+ (0x3a), 4, 0x01, 0x01, 0xF0, 0x00, // N_RTN=0, N_NW=1, P_RTN=0, P_NW=1, I_RTN=15, I_NW=0, DIV=0
+ TFTLCD_DELAY8, 5,
+ (0x35), 2, 0x38, 0x78, // EQS=38h, EQP=78h
+ (0x3E), 1, 0x38, // SON=38h
+ (0x40), 2, 0x0F, 0xF0, // GDON=0Fh, GDOFF
+ // Power Supply Setting
+ (0x19), 1, 0x49, // CADJ=0100, CUADJ=100, OSD_EN=1 ,60Hz
+ (0x93), 1, 0x0F, // RADJ=1111, 100%
+ TFTLCD_DELAY8, 5,
+ (0x20), 1, 0x40, // BT=0100
+ (0x1D), 3, 0x07, 0x00, 0x04, // VC1=7, VC3=0, VRH=??
+ //VCOM SETTING for 3.2"
+ (0x44), 2, 0x4D, 0x11, // VCM=100 1101, VDV=1 0001
+ TFTLCD_DELAY8, 10,
+ (0x1C), 1, 0x04, // AP=100
+ TFTLCD_DELAY8, 20,
+ (0x1B), 1, 0x18, // GASENB=0, PON=0, DK=1, XDK=0, VLCD_TRI=0, STB=0
+ TFTLCD_DELAY8, 40,
+ (0x1B), 1, 0x10, // GASENB=0, PON=1, DK=0, XDK=0, VLCD_TRI=0, STB=0
+ TFTLCD_DELAY8, 40,
+ (0x43), 1, 0x80, //set VCOMG=1
+ TFTLCD_DELAY8, 100,
+ // Display ON Setting
+ (0x90), 1, 0x7F, // SAP=0111 1111
+ (0x26), 1, 0x04, //GON=0, DTE=0, D=01
+ TFTLCD_DELAY8, 40,
+ (0x26), 1, 0x24, //GON=1, DTE=0, D=01
+ (0x26), 1, 0x2C, //GON=1, DTE=0, D=11
+ TFTLCD_DELAY8, 40,
+ (0x26), 1, 0x3C, //GON=1, DTE=1, D=11
+ // INTERNAL REGISTER SETTING
+ (0x57), 1, 0x02, // TEST_Mode=1: into TEST mode
+ (0x55), 1, 0x00, // VDC_SEL=000, VDDD=1.95V
+ (0xFE), 1, 0x5A, // For ESD protection
+ (0x57), 1, 0x00, // TEST_Mode=0: exit TEST mode
+ };
+ // AN.01 The reference setting of CMO 2.4” Panel
+ static const uint8_t HX8347A_CMO24_regValues[] PROGMEM = {
+ // VENDOR Gamma for 2.4"
+ (0x46), 12, 0x94, 0x41, 0x00, 0x33, 0x23, 0x45, 0x44, 0x77, 0x12, 0xCC, 0x46, 0x82,
+ // Display Setting
+ (0x01), 1, 0x06, // IDMON=0, INVON=1, NORON=1, PTLON=0
+ (0x16), 1, 0x48, // MY=0, MX=0, MV=0, ML=1, BGR=0, TEON=0
+ (0x23), 3, 0x95, 0x95, 0xFF, // N_DC=1001 0101, PI_DC=1001 0101, I_DC=1111 1111
+
+ (0x27), 4, 0x02, 0x02, 0x02, 0x02, // N_BP=2, N_FP=2, PI_BP=2, PI_FP=2
+ (0x2C), 2, 0x02, 0x02, // I_BP=2, I_FP=2
+
+ (0x3a), 4, 0x01, 0x01, 0xF0, 0x00, // N_RTN=0, N_NW=1, P_RTN=0, P_NW=1, I_RTN=15, I_NW=0, DIV=0
+ TFTLCD_DELAY8, 5,
+ (0x35), 2, 0x38, 0x78, // EQS=38h, EQP=78h
+ (0x3E), 1, 0x38, // SON=38h
+ (0x40), 2, 0x0F, 0xF0, // GDON=0Fh, GDOFF
+ // Power Supply Setting
+ (0x19), 1, 0x49, // CADJ=0100, CUADJ=100, OSD_EN=1 ,60Hz
+ (0x93), 1, 0x0F, // RADJ=1111, 100%
+ TFTLCD_DELAY8, 5,
+ (0x20), 1, 0x40, // BT=0100
+ (0x1D), 3, 0x07, 0x00, 0x04, // VC1=7, VC3=0, VRH=??
+ //VCOM SETTING for 2.4"
+ (0x44), 2, 0x40, 0x12, // VCM=100 0000, VDV=1 0001
+ TFTLCD_DELAY8, 10,
+ (0x1C), 1, 0x04, // AP=100
+ TFTLCD_DELAY8, 20,
+ (0x1B), 1, 0x18, // GASENB=0, PON=0, DK=1, XDK=0, VLCD_TRI=0, STB=0
+ TFTLCD_DELAY8, 40,
+ (0x1B), 1, 0x10, // GASENB=0, PON=1, DK=0, XDK=0, VLCD_TRI=0, STB=0
+ TFTLCD_DELAY8, 40,
+ (0x43), 1, 0x80, //set VCOMG=1
+ TFTLCD_DELAY8, 100,
+ // Display ON Setting
+ (0x90), 1, 0x7F, // SAP=0111 1111
+ (0x26), 1, 0x04, //GON=0, DTE=0, D=01
+ TFTLCD_DELAY8, 40,
+ (0x26), 1, 0x24, //GON=1, DTE=0, D=01
+ (0x26), 1, 0x2C, //GON=1, DTE=0, D=11
+ TFTLCD_DELAY8, 40,
+ (0x26), 1, 0x3C, //GON=1, DTE=1, D=11
+ // INTERNAL REGISTER SETTING
+ (0x57), 1, 0x02, // TEST_Mode=1: into TEST mode
+ (0x55), 1, 0x00, // VDC_SEL=000, VDDD=1.95V
+ (0xFE), 1, 0x5A, // For ESD protection
+ (0x57), 1, 0x00, // TEST_Mode=0: exit TEST mode
+ };
+ static const uint8_t HX8347A_ITDB02_regValues[] PROGMEM = {
+ // VENDOR Gamma ITDB02 same as CMO32. Delays are shorter than AN01
+ (0x46), 12, 0xA4, 0x53, 0x00, 0x44, 0x04, 0x67, 0x33, 0x77, 0x12, 0x4C, 0x46, 0x44,
+ // Display Setting
+ (0x01), 1, 0x06, // IDMON=0, INVON=1, NORON=1, PTLON=0
+ (0x16), 1, 0xC8, // MY=0, MX=0, MV=0, ML=1, BGR=0, TEON=0 .itead
+ (0x23), 3, 0x95, 0x95, 0xFF, // N_DC=1001 0101, PI_DC=1001 0101, I_DC=1111 1111
+
+ (0x27), 4, 0x02, 0x02, 0x02, 0x02, // N_BP=2, N_FP=2, PI_BP=2, PI_FP=2
+ (0x2C), 2, 0x02, 0x02, // I_BP=2, I_FP=2
+
+ (0x3a), 4, 0x01, 0x00, 0xF0, 0x00, // N_RTN=0, N_NW=1, P_RTN=0, ?? P_NW=1, I_RTN=15, I_NW=0, DIV=0 .itead
+ TFTLCD_DELAY8, 5,
+ (0x35), 2, 0x38, 0x78, // EQS=38h, EQP=78h
+ (0x3E), 1, 0x38, // SON=38h
+ (0x40), 2, 0x0F, 0xF0, // GDON=0Fh, GDOFF
+ // Power Supply Setting
+ (0x19), 1, 0x49, // CADJ=0100, CUADJ=100, OSD_EN=1 ,60Hz
+ (0x93), 1, 0x0F, // RADJ=1111, 100%
+ TFTLCD_DELAY8, 5,
+ (0x20), 1, 0x40, // BT=0100
+ (0x1D), 3, 0x07, 0x00, 0x04, // VC1=7, VC3=0, VRH=??
+ //VCOM SETTING for ITDB02
+ (0x44), 2, 0x4D, 0x0E, // VCM=101 0000 4D, VDV=1 0001 .itead
+ TFTLCD_DELAY8, 5,
+ (0x1C), 1, 0x04, // AP=100
+ TFTLCD_DELAY8, 5,
+ (0x1B), 1, 0x18, // GASENB=0, PON=0, DK=1, XDK=0, VLCD_TRI=0, STB=0
+ TFTLCD_DELAY8, 5,
+ (0x1B), 1, 0x10, // GASENB=0, PON=1, DK=0, XDK=0, VLCD_TRI=0, STB=0
+ TFTLCD_DELAY8, 5,
+ (0x43), 1, 0x80, //set VCOMG=1
+ TFTLCD_DELAY8, 5,
+ // Display ON Setting
+ (0x90), 1, 0x7F, // SAP=0111 1111
+ (0x26), 1, 0x04, //GON=0, DTE=0, D=01
+ TFTLCD_DELAY8, 5,
+ (0x26), 1, 0x24, //GON=1, DTE=0, D=01
+ (0x26), 1, 0x2C, //GON=1, DTE=0, D=11
+ TFTLCD_DELAY8, 5,
+ (0x26), 1, 0x3C, //GON=1, DTE=1, D=11
+ // INTERNAL REGISTER SETTING for ITDB02
+ (0x57), 1, 0x02, // TEST_Mode=1: into TEST mode
+ (0x95), 1, 0x01, // SET DISPLAY CLOCK AND PUMPING CLOCK TO SYNCHRONIZE .itead
+ (0x57), 1, 0x00, // TEST_Mode=0: exit TEST mode
+ };
+ static const uint8_t HX8347A_NHD_regValues[] PROGMEM = {
+ //Gamma Setting NHD
+ (0x46), 12, 0x94, 0x41, 0x00, 0x33, 0x23, 0x45, 0x44, 0x77, 0x12, 0xCC, 0x46, 0x82,
+ (0x01), 1, 0x06, //Display Mode [06]
+ (0x16), 1, 0xC8, //MADCTL [00] MY=1, MX=1, BGR=1
+// (0x70), 1, 0x05, //Panel [06] 16-bit
+ (0x23), 3, 0x95, 0x95, 0xFF, //Cycle Control 1-3 [95 95 FF]
+ (0x27), 4, 0x02, 0x02, 0x02, 0x02, //Display Control 2-5 [02 02 02 02]
+ (0x2C), 2, 0x02, 0x02, //Display Control 6-7 [02 02]
+ (0x3A), 4, 0x01, 0x01, 0xF0, 0x00, //Cycle Control 1-4 [01 01 F0 00]
+ TFTLCD_DELAY8, 80,
+ (0x35), 2, 0x38, 0x78, //Display Control 9-10 [09 09] EQS=56, EQP=120
+ (0x3E), 1, 0x38, //Cycle Control 5 [38]
+ (0x40), 1, 0x0F, //Cycle Control 6 [03] GDON=15
+ (0x41), 1, 0xF0, //Cycle Control 14 [F8] GDOF=248
+
+ (0x19), 1, 0x2D, //OSC Control 1 [86] CADJ=2, CUADJ=6, OSCEN=1
+ (0x93), 1, 0x06, //SAP Idle mode [00] ??? .nhd
+ TFTLCD_DELAY8, 80,
+ (0x20), 1, 0x40, //Power Control 6 [40]
+ (0x1D), 3, 0x07, 0x00, 0x04, //Power Control 3-5 [04 00 06] VC=7
+ (0x44), 2, 0x3C, 0x12, //VCOM Control 2-3 [5A 11] VCM=60, VDV=18
+ TFTLCD_DELAY8, 80,
+ (0x1C), 1, 0x04, //Power Control 2 [04]
+ TFTLCD_DELAY8, 80,
+ (0x43), 1, 0x80, //VCOM Control 1 [80]
+ TFTLCD_DELAY8, 80,
+ (0x1B), 1, 0x08, //Power Control 1 [00] DK=1
+ TFTLCD_DELAY8, 80,
+ (0x1B), 1, 0x10, //Power Control 1 [00] PON=1
+ TFTLCD_DELAY8, 80,
+ (0x90), 1, 0x7F, //Display Control 8 [0A]
+ (0x26), 1, 0x04, //Display Control 1 [A0] D=1
+ TFTLCD_DELAY8, 80,
+ (0x26), 1, 0x24, //Display Control 1 [A0] GON=1, D=1
+ (0x26), 1, 0x2C, //Display Control 1 [A0] GON=1, D=3
+ TFTLCD_DELAY8, 80,
+ (0x26), 1, 0x3C, //Display Control 1 [A0] GON=1, DTE=1, D=3
+ (0x57), 1, 0x02, //?
+ (0x55), 1, 0x00, //?
+ (0x57), 1, 0x00, //?
+ };
+ // Atmel ASF code uses VCOM2-3: 0x38, 0x12. 50ms delays and no TEST mode changes.
+ init_table(HX8347A_NHD_regValues, sizeof(HX8347A_NHD_regValues));
+ // init_table(HX8347A_CMO32_regValues, sizeof(HX8347A_CMO32_regValues));
+ // init_table(HX8347A_CMO24_regValues, sizeof(HX8347A_CMO24_regValues));
+ // init_table(HX8347A_ITDB02_regValues, sizeof(HX8347A_ITDB02_regValues));
+ // init_table(HX8347G_2_regValues, sizeof(HX8347G_2_regValues));
+ break;
+#endif
+
+ case 0x8357: //BIG CHANGE: HX8357-B is now 0x8357
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | REV_SCREEN;
+ goto common_8357;
+ case 0x9090: //BIG CHANGE: HX8357-D was 0x8357
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | REV_SCREEN | READ_24BITS;
+ common_8357:
+ static const uint8_t HX8357C_regValues[] PROGMEM = {
+ TFTLCD_DELAY8, 1, //dummy table
+ };
+ table8_ads = HX8357C_regValues, table_size = sizeof(HX8357C_regValues);
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 480;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 320;
+ break;
+
+ case 0x0099: //HX8357-D matches datasheet
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | REV_SCREEN | READ_24BITS;
+ static const uint8_t HX8357_99_regValues[] PROGMEM = {
+ (0xB9), 3, 0xFF, 0x83, 0x57, // SETEXTC
+ TFTLCD_DELAY8, 150,
+ TFTLCD_DELAY8, 150,
+ (0xB6), 1, 0x25, // SETCOM [4B 00] -2.5V+37*0.02V=-1.76V [-1.00V]
+ (0xC0), 6, 0x50, 0x50, 0x01, 0x3C, 0x1E, 0x08, // SETSTBA [73 50 00 3C C4 08]
+ (0xB4), 7, 0x02, 0x40, 0x00, 0x2A, 0x2A, 0x0D, 0x78, // SETCYC [02 40 00 2A 2A 0D 96]
+#ifdef SUPPORT_8357D_GAMMA
+ // HX8357D_SETGAMMA [0B 0C 11 1D 25 37 43 4B 4E 47 41 39 35 31 2E 21 1C 1D 1D 26 31 44 4E 56 44 3F 39 33 31 2E 28 1D E0 01]
+ (0xE0),34, 0x02, 0x0A, 0x11, 0x1D, 0x23, 0x35, 0x41, 0x4B, 0x4B, 0x42, 0x3A, 0x27, 0x1B, 0x08, 0x09, 0x03, 0x02, 0x0A, 0x11, 0x1D, 0x23, 0x35, 0x41, 0x4B, 0x4B, 0x42, 0x3A, 0x27, 0x1B, 0x08, 0x09, 0x03, 0x00, 0x01,
+#endif
+ };
+ table8_ads = HX8357_99_regValues, table_size = sizeof(HX8357_99_regValues);
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 480;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 320;
+ break;
+
+#ifdef SUPPORT_8230
+ case 0x8230: //thanks Auzman
+ _lcd_capable = 0 | REV_SCREEN | INVERT_GS | INVERT_RGB | READ_BGR;
+ static const uint16_t UC8230_regValues[] PROGMEM = {
+ //After pin Reset wait at least 100ms
+ TFTLCD_DELAY, 100, //at least 100ms
+ 0x0046, 0x0002, //MTP Disable
+ 0x0010, 0x1590, //SAP=1, BT=5, APE=1, AP=1
+ 0x0011, 0x0227, //DC1=2, DC0=2, VC=7
+ 0x0012, 0x80ff, //P5VMD=1, PON=7, VRH=15
+ 0x0013, 0x9c31, //VDV=28, VCM=49
+ TFTLCD_DELAY, 10, //at least 10ms
+ 0x0002, 0x0300, //set N-line = 1
+ 0x0003, 0x1030, //set GRAM writing direction & BGR=1
+ 0x0060, 0xa700, //GS; gate scan: start position & drive line Q'ty
+ 0x0061, 0x0001, //REV, NDL, VLE
+ /*--------------------Gamma control------------------------*/
+ 0x0030, 0x0303,
+ 0x0031, 0x0303,
+ 0x0032, 0x0303,
+ 0x0033, 0x0300,
+ 0x0034, 0x0003,
+ 0x0035, 0x0303,
+ 0x0036, 0x1400,
+ 0x0037, 0x0303,
+ 0x0038, 0x0303,
+ 0x0039, 0x0303,
+ 0x003a, 0x0300,
+ 0x003b, 0x0003,
+ 0x003c, 0x0303,
+ 0x003d, 0x1400,
+ //-----------------------------------------------------------//
+ 0x0020, 0x0000, //GRAM horizontal address
+ 0x0021, 0x0000, //GRAM vertical address
+ //************** Partial Display control*********************//
+ 0x0080, 0x0000,
+ 0x0081, 0x0000,
+ 0x0082, 0x0000,
+ 0x0083, 0x0000,
+ 0x0084, 0x0000,
+ 0x0085, 0x0000,
+ //-----------------------------------------------------------//
+ 0x0092, 0x0200,
+ 0x0093, 0x0303,
+ 0x0090, 0x0010, //set clocks/Line
+ 0x0000, 0x0001,
+ TFTLCD_DELAY, 200, // Delay 200 ms
+ 0x0007, 0x0173, //Display on setting
+ };
+ init_table16(UC8230_regValues, sizeof(UC8230_regValues));
+ break;
+#endif
+
+#ifdef SUPPORT_9163
+ case 0x9163: //
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS;
+ static const uint8_t PROGMEM table9163C[] = {
+ // (COMMAND_BYTE), n, data_bytes....
+ 0x26, 1, 0x02, // [01] GAMMASET use CURVE=1, 2, 4, 8
+ 0xB1, 2, 0x08, 0x02, // [0E 14] FRMCTR1 if GM==011 61.7Hz
+ 0xB4, 1, 0x07, // [02] INVCTR
+ 0xB8, 1, 0x01, // [00] GSCTRL
+ 0xC0, 2, 0x0A, 0x02, // [0A 05] PWCTR1 if LCM==10
+ 0xC1, 1, 0x02, // [07] PWCTR2
+ 0xC5, 2, 0x50, 0x63, // [43 4D] VMCTR1
+ 0xC7, 1, 0, // [40] VCOMOFFS
+ };
+ table8_ads = table9163C, table_size = sizeof(table9163C); //
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 160;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 128;
+ break;
+#endif
+
+#ifdef SUPPORT_9225
+#define ILI9225_DRIVER_OUTPUT_CTRL (0x01u) // Driver Output Control
+#define ILI9225_LCD_AC_DRIVING_CTRL (0x02u) // LCD AC Driving Control
+#define ILI9225_ENTRY_MODE (0x03u) // Entry Mode
+#define ILI9225_DISP_CTRL1 (0x07u) // Display Control 1
+#define ILI9225_BLANK_PERIOD_CTRL1 (0x08u) // Blank Period Control
+#define ILI9225_FRAME_CYCLE_CTRL (0x0Bu) // Frame Cycle Control
+#define ILI9225_INTERFACE_CTRL (0x0Cu) // Interface Control
+#define ILI9225_OSC_CTRL (0x0Fu) // Osc Control
+#define ILI9225_POWER_CTRL1 (0x10u) // Power Control 1
+#define ILI9225_POWER_CTRL2 (0x11u) // Power Control 2
+#define ILI9225_POWER_CTRL3 (0x12u) // Power Control 3
+#define ILI9225_POWER_CTRL4 (0x13u) // Power Control 4
+#define ILI9225_POWER_CTRL5 (0x14u) // Power Control 5
+#define ILI9225_VCI_RECYCLING (0x15u) // VCI Recycling
+#define ILI9225_RAM_ADDR_SET1 (0x20u) // Horizontal GRAM Address Set
+#define ILI9225_RAM_ADDR_SET2 (0x21u) // Vertical GRAM Address Set
+#define ILI9225_GRAM_DATA_REG (0x22u) // GRAM Data Register
+#define ILI9225_GATE_SCAN_CTRL (0x30u) // Gate Scan Control Register
+#define ILI9225_VERTICAL_SCROLL_CTRL1 (0x31u) // Vertical Scroll Control 1 Register
+#define ILI9225_VERTICAL_SCROLL_CTRL2 (0x32u) // Vertical Scroll Control 2 Register
+#define ILI9225_VERTICAL_SCROLL_CTRL3 (0x33u) // Vertical Scroll Control 3 Register
+#define ILI9225_PARTIAL_DRIVING_POS1 (0x34u) // Partial Driving Position 1 Register
+#define ILI9225_PARTIAL_DRIVING_POS2 (0x35u) // Partial Driving Position 2 Register
+#define ILI9225_HORIZONTAL_WINDOW_ADDR1 (0x36u) // Horizontal Address END Position HEA
+#define ILI9225_HORIZONTAL_WINDOW_ADDR2 (0x37u) // Horizontal Address START Position HSA
+#define ILI9225_VERTICAL_WINDOW_ADDR1 (0x38u) // Vertical Address END Position VEA
+#define ILI9225_VERTICAL_WINDOW_ADDR2 (0x39u) // Vertical Address START Position VSA
+#define ILI9225_GAMMA_CTRL1 (0x50u) // Gamma Control 1
+#define ILI9225_GAMMA_CTRL2 (0x51u) // Gamma Control 2
+#define ILI9225_GAMMA_CTRL3 (0x52u) // Gamma Control 3
+#define ILI9225_GAMMA_CTRL4 (0x53u) // Gamma Control 4
+#define ILI9225_GAMMA_CTRL5 (0x54u) // Gamma Control 5
+#define ILI9225_GAMMA_CTRL6 (0x55u) // Gamma Control 6
+#define ILI9225_GAMMA_CTRL7 (0x56u) // Gamma Control 7
+#define ILI9225_GAMMA_CTRL8 (0x57u) // Gamma Control 8
+#define ILI9225_GAMMA_CTRL9 (0x58u) // Gamma Control 9
+#define ILI9225_GAMMA_CTRL10 (0x59u) // Gamma Control 10
+
+#define ILI9225C_INVOFF 0x20
+#define ILI9225C_INVON 0x21
+
+ case 0x6813:
+ case 0x9226:
+ _lcd_ID = 0x9225; //fall through
+ case 0x9225:
+ _lcd_capable = REV_SCREEN | READ_BGR; //thanks tongbajiel
+ static const uint16_t ILI9225_regValues[] PROGMEM = {
+ /* Start Initial Sequence */
+ /* Set SS bit and direction output from S528 to S1 */
+ ILI9225_POWER_CTRL1, 0x0000, // Set SAP,DSTB,STB
+ ILI9225_POWER_CTRL2, 0x0000, // Set APON,PON,AON,VCI1EN,VC
+ ILI9225_POWER_CTRL3, 0x0000, // Set BT,DC1,DC2,DC3
+ ILI9225_POWER_CTRL4, 0x0000, // Set GVDD
+ ILI9225_POWER_CTRL5, 0x0000, // Set VCOMH/VCOML voltage
+ TFTLCD_DELAY, 40,
+
+ // Power-on sequence
+ ILI9225_POWER_CTRL2, 0x0018, // Set APON,PON,AON,VCI1EN,VC
+ ILI9225_POWER_CTRL3, 0x6121, // Set BT,DC1,DC2,DC3
+ ILI9225_POWER_CTRL4, 0x006F, // Set GVDD /*007F 0088 */
+ ILI9225_POWER_CTRL5, 0x495F, // Set VCOMH/VCOML voltage
+ ILI9225_POWER_CTRL1, 0x0800, // Set SAP,DSTB,STB
+ TFTLCD_DELAY, 10,
+ ILI9225_POWER_CTRL2, 0x103B, // Set APON,PON,AON,VCI1EN,VC
+ TFTLCD_DELAY, 50,
+
+ ILI9225_DRIVER_OUTPUT_CTRL, 0x011C, // set the display line number and display direction
+ ILI9225_LCD_AC_DRIVING_CTRL, 0x0100, // set 1 line inversion
+ ILI9225_ENTRY_MODE, 0x1030, // set GRAM write direction and BGR=1.
+ ILI9225_DISP_CTRL1, 0x0000, // Display off
+ ILI9225_BLANK_PERIOD_CTRL1, 0x0808, // set the back porch and front porch
+ ILI9225_FRAME_CYCLE_CTRL, 0x1100, // set the clocks number per line
+ ILI9225_INTERFACE_CTRL, 0x0000, // CPU interface
+ ILI9225_OSC_CTRL, 0x0D01, // Set Osc /*0e01*/
+ ILI9225_VCI_RECYCLING, 0x0020, // Set VCI recycling
+ ILI9225_RAM_ADDR_SET1, 0x0000, // RAM Address
+ ILI9225_RAM_ADDR_SET2, 0x0000, // RAM Address
+
+ /* Set GRAM area */
+ ILI9225_GATE_SCAN_CTRL, 0x0000,
+ ILI9225_VERTICAL_SCROLL_CTRL1, 0x00DB,
+ ILI9225_VERTICAL_SCROLL_CTRL2, 0x0000,
+ ILI9225_VERTICAL_SCROLL_CTRL3, 0x0000,
+ ILI9225_PARTIAL_DRIVING_POS1, 0x00DB,
+ ILI9225_PARTIAL_DRIVING_POS2, 0x0000,
+ ILI9225_HORIZONTAL_WINDOW_ADDR1, 0x00AF,
+ ILI9225_HORIZONTAL_WINDOW_ADDR2, 0x0000,
+ ILI9225_VERTICAL_WINDOW_ADDR1, 0x00DB,
+ ILI9225_VERTICAL_WINDOW_ADDR2, 0x0000,
+
+ /* Set GAMMA curve */
+ ILI9225_GAMMA_CTRL1, 0x0000,
+ ILI9225_GAMMA_CTRL2, 0x0808,
+ ILI9225_GAMMA_CTRL3, 0x080A,
+ ILI9225_GAMMA_CTRL4, 0x000A,
+ ILI9225_GAMMA_CTRL5, 0x0A08,
+ ILI9225_GAMMA_CTRL6, 0x0808,
+ ILI9225_GAMMA_CTRL7, 0x0000,
+ ILI9225_GAMMA_CTRL8, 0x0A00,
+ ILI9225_GAMMA_CTRL9, 0x0710,
+ ILI9225_GAMMA_CTRL10, 0x0710,
+
+ ILI9225_DISP_CTRL1, 0x0012,
+ TFTLCD_DELAY, 50,
+ ILI9225_DISP_CTRL1, 0x1017,
+ };
+ init_table16(ILI9225_regValues, sizeof(ILI9225_regValues));
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 220;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 176;
+ break;
+#endif
+
+ case 0x0001:
+ _lcd_capable = 0 | REV_SCREEN | INVERT_GS; //no RGB bug. thanks Ivo_Deshev
+ goto common_9320;
+ case 0x5408:
+ _lcd_capable = 0 | REV_SCREEN | READ_BGR; //Red 2.4" thanks jorgenv, Ardlab_Gent
+// _lcd_capable = 0 | REV_SCREEN | READ_BGR | INVERT_GS; //Blue 2.8" might be different
+ goto common_9320;
+ case 0x1505: //R61505 thanks Ravi_kanchan2004. R61505V, R61505W different
+ case 0x9320:
+ _lcd_capable = 0 | REV_SCREEN | READ_BGR;
+ common_9320:
+ static const uint16_t ILI9320_regValues[] PROGMEM = {
+ 0x00e5, 0x8000,
+ 0x0000, 0x0001,
+ 0x0001, 0x100,
+ 0x0002, 0x0700,
+ 0x0003, 0x1030,
+ 0x0004, 0x0000,
+ 0x0008, 0x0202,
+ 0x0009, 0x0000,
+ 0x000A, 0x0000,
+ 0x000C, 0x0000,
+ 0x000D, 0x0000,
+ 0x000F, 0x0000,
+ //-----Power On sequence-----------------------
+ 0x0010, 0x0000,
+ 0x0011, 0x0007,
+ 0x0012, 0x0000,
+ 0x0013, 0x0000,
+ TFTLCD_DELAY, 50,
+ 0x0010, 0x17B0, //SAP=1, BT=7, APE=1, AP=3
+ 0x0011, 0x0007, //DC1=0, DC0=0, VC=7
+ TFTLCD_DELAY, 10,
+ 0x0012, 0x013A, //VCMR=1, PON=3, VRH=10
+ TFTLCD_DELAY, 10,
+ 0x0013, 0x1A00, //VDV=26
+ 0x0029, 0x000c, //VCM=12
+ TFTLCD_DELAY, 10,
+ //-----Gamma control-----------------------
+ 0x0030, 0x0000,
+ 0x0031, 0x0505,
+ 0x0032, 0x0004,
+ 0x0035, 0x0006,
+ 0x0036, 0x0707,
+ 0x0037, 0x0105,
+ 0x0038, 0x0002,
+ 0x0039, 0x0707,
+ 0x003C, 0x0704,
+ 0x003D, 0x0807,
+ //-----Set RAM area-----------------------
+ 0x0060, 0xA700, //GS=1
+ 0x0061, 0x0001,
+ 0x006A, 0x0000,
+ 0x0021, 0x0000,
+ 0x0020, 0x0000,
+ //-----Partial Display Control------------
+ 0x0080, 0x0000,
+ 0x0081, 0x0000,
+ 0x0082, 0x0000,
+ 0x0083, 0x0000,
+ 0x0084, 0x0000,
+ 0x0085, 0x0000,
+ //-----Panel Control----------------------
+ 0x0090, 0x0010,
+ 0x0092, 0x0000,
+ 0x0093, 0x0003,
+ 0x0095, 0x0110,
+ 0x0097, 0x0000,
+ 0x0098, 0x0000,
+ //-----Display on-----------------------
+ 0x0007, 0x0173,
+ TFTLCD_DELAY, 50,
+ };
+ init_table16(ILI9320_regValues, sizeof(ILI9320_regValues));
+ break;
+ case 0x6809:
+ _lcd_capable = 0 | REV_SCREEN | INVERT_GS | AUTO_READINC;
+ goto common_93x5;
+ case 0x9328:
+ case 0x9325:
+ _lcd_capable = 0 | REV_SCREEN | INVERT_GS;
+ goto common_93x5;
+ case 0x9331:
+ case 0x9335:
+ _lcd_capable = 0 | REV_SCREEN;
+ common_93x5:
+ static const uint16_t ILI9325_regValues[] PROGMEM = {
+ 0x00E5, 0x78F0, // set SRAM internal timing
+ 0x0001, 0x0100, // set Driver Output Control
+ 0x0002, 0x0200, // set 1 line inversion
+ 0x0003, 0x1030, // set GRAM write direction and BGR=1.
+ 0x0004, 0x0000, // Resize register
+ 0x0005, 0x0000, // .kbv 16bits Data Format Selection
+ 0x0008, 0x0207, // set the back porch and front porch
+ 0x0009, 0x0000, // set non-display area refresh cycle ISC[3:0]
+ 0x000A, 0x0000, // FMARK function
+ 0x000C, 0x0000, // RGB interface setting
+ 0x000D, 0x0000, // Frame marker Position
+ 0x000F, 0x0000, // RGB interface polarity
+ // ----------- Power On sequence ----------- //
+ 0x0010, 0x0000, // SAP, BT[3:0], AP, DSTB, SLP, STB
+ 0x0011, 0x0007, // DC1[2:0], DC0[2:0], VC[2:0]
+ 0x0012, 0x0000, // VREG1OUT voltage
+ 0x0013, 0x0000, // VDV[4:0] for VCOM amplitude
+ 0x0007, 0x0001,
+ TFTLCD_DELAY, 200, // Dis-charge capacitor power voltage
+ 0x0010, 0x1690, // SAP=1, BT=6, APE=1, AP=1, DSTB=0, SLP=0, STB=0
+ 0x0011, 0x0227, // DC1=2, DC0=2, VC=7
+ TFTLCD_DELAY, 50, // wait_ms 50ms
+ 0x0012, 0x000D, // VCIRE=1, PON=0, VRH=5
+ TFTLCD_DELAY, 50, // wait_ms 50ms
+ 0x0013, 0x1200, // VDV=28 for VCOM amplitude
+ 0x0029, 0x000A, // VCM=10 for VCOMH
+ 0x002B, 0x000D, // Set Frame Rate
+ TFTLCD_DELAY, 50, // wait_ms 50ms
+ 0x0020, 0x0000, // GRAM horizontal Address
+ 0x0021, 0x0000, // GRAM Vertical Address
+ // ----------- Adjust the Gamma Curve ----------//
+
+ 0x0030, 0x0000,
+ 0x0031, 0x0404,
+ 0x0032, 0x0003,
+ 0x0035, 0x0405,
+ 0x0036, 0x0808,
+ 0x0037, 0x0407,
+ 0x0038, 0x0303,
+ 0x0039, 0x0707,
+ 0x003C, 0x0504,
+ 0x003D, 0x0808,
+
+ //------------------ Set GRAM area ---------------//
+ 0x0060, 0x2700, // Gate Scan Line GS=0 [0xA700]
+ 0x0061, 0x0001, // NDL,VLE, REV .kbv
+ 0x006A, 0x0000, // set scrolling line
+ //-------------- Partial Display Control ---------//
+ 0x0080, 0x0000,
+ 0x0081, 0x0000,
+ 0x0082, 0x0000,
+ 0x0083, 0x0000,
+ 0x0084, 0x0000,
+ 0x0085, 0x0000,
+ //-------------- Panel Control -------------------//
+ 0x0090, 0x0010,
+ 0x0092, 0x0000,
+ 0x0007, 0x0133, // 262K color and display ON
+ };
+ init_table16(ILI9325_regValues, sizeof(ILI9325_regValues));
+ break;
+
+#if defined(SUPPORT_9326_5420)
+ case 0x5420:
+ case 0x9326:
+ _lcd_capable = REV_SCREEN | READ_BGR;
+ static const uint16_t ILI9326_CPT28_regValues[] PROGMEM = {
+//************* Start Initial Sequence **********//
+ 0x0702, 0x3008, // Set internal timing, don’t change this value
+ 0x0705, 0x0036, // Set internal timing, don’t change this value
+ 0x070B, 0x1213, // Set internal timing, don’t change this value
+ 0x0001, 0x0100, // set SS and SM bit
+ 0x0002, 0x0100, // set 1 line inversion
+ 0x0003, 0x1030, // set GRAM write direction and BGR=1.
+ 0x0008, 0x0202, // set the back porch and front porch
+ 0x0009, 0x0000, // set non-display area refresh cycle ISC[3:0]
+ 0x000C, 0x0000, // RGB interface setting
+ 0x000F, 0x0000, // RGB interface polarity
+//*************Power On sequence ****************//
+ 0x0100, 0x0000, // SAP, BT[3:0], AP, DSTB, SLP, STB
+ 0x0102, 0x0000, // VREG1OUT voltage
+ 0x0103, 0x0000, // VDV[4:0] for VCOM amplitude
+ TFTLCD_DELAY, 200, // Dis-charge capacitor power voltage
+ 0x0100, 0x1190, // SAP, BT[3:0], AP, DSTB, SLP, STB
+ 0x0101, 0x0227, // DC1[2:0], DC0[2:0], VC[2:0]
+ TFTLCD_DELAY, 50, // Delay 50ms
+ 0x0102, 0x01BD, // VREG1OUT voltage
+ TFTLCD_DELAY, 50, // Delay 50ms
+ 0x0103, 0x2D00, // VDV[4:0] for VCOM amplitude
+ 0x0281, 0x000E, // VCM[5:0] for VCOMH
+ TFTLCD_DELAY, 50, //
+ 0x0200, 0x0000, // GRAM horizontal Address
+ 0x0201, 0x0000, // GRAM Vertical Address
+// ----------- Adjust the Gamma Curve ----------//
+ 0x0300, 0x0000, //
+ 0x0301, 0x0707, //
+ 0x0302, 0x0606, //
+ 0x0305, 0x0000, //
+ 0x0306, 0x0D00, //
+ 0x0307, 0x0706, //
+ 0x0308, 0x0005, //
+ 0x0309, 0x0007, //
+ 0x030C, 0x0000, //
+ 0x030D, 0x000A, //
+//------------------ Set GRAM area ---------------//
+ 0x0400, 0x3100, // Gate Scan Line 400 lines
+ 0x0401, 0x0001, // NDL,VLE, REV
+ 0x0404, 0x0000, // set scrolling line
+//-------------- Partial Display Control ---------//
+ 0x0500, 0x0000, // Partial Image 1 Display Position
+ 0x0501, 0x0000, // Partial Image 1 RAM Start/End Address
+ 0x0502, 0x0000, // Partial Image 1 RAM Start/End Address
+ 0x0503, 0x0000, // Partial Image 2 Display Position
+ 0x0504, 0x0000, // Partial Image 2 RAM Start/End Address
+ 0x0505, 0x0000, // Partial Image 2 RAM Start/End Address
+//-------------- Panel Control -------------------//
+ 0x0010, 0x0010, // DIVI[1:0];RTNI[4:0]
+ 0x0011, 0x0600, // NOWI[2:0];SDTI[2:0]
+ 0x0020, 0x0002, // DIVE[1:0];RTNE[5:0]
+ 0x0007, 0x0173, // 262K color and display ON
+ };
+ init_table16(ILI9326_CPT28_regValues, sizeof(ILI9326_CPT28_regValues));
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 400;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 240;
+ break;
+#endif
+
+ case 0x9327:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS;
+ static const uint8_t ILI9327_regValues[] PROGMEM = {
+ 0xB0, 1, 0x00, //Disable Protect for cmds B1-DF, E0-EF, F0-FF
+ // 0xE0, 1, 0x20, //NV Memory Write [00]
+ // 0xD1, 3, 0x00, 0x71, 0x19, //VCOM control [00 40 0F]
+ // 0xD0, 3, 0x07, 0x01, 0x08, //Power Setting [07 04 8C]
+ 0xC1, 4, 0x10, 0x10, 0x02, 0x02, //Display Timing [10 10 02 02]
+ 0xC0, 6, 0x00, 0x35, 0x00, 0x00, 0x01, 0x02, //Panel Drive [00 35 00 00 01 02 REV=0,GS=0,SS=0
+ 0xC5, 1, 0x04, //Frame Rate [04]
+ 0xD2, 2, 0x01, 0x04, //Power Setting [01 44]
+ // 0xC8, 15, 0x04, 0x67, 0x35, 0x04, 0x08, 0x06, 0x24, 0x01, 0x37, 0x40, 0x03, 0x10, 0x08, 0x80, 0x00,
+ // 0xC8, 15, 0x00, 0x77, 0x77, 0x04, 0x04, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+ 0xCA, 1, 0x00, //DGC LUT ???
+ 0xEA, 1, 0x80, //3-Gamma Function Enable
+ // 0xB0, 1, 0x03, //Enable Protect
+ };
+ table8_ads = ILI9327_regValues, table_size = sizeof(ILI9327_regValues);
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 400;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 240;
+ break;
+ case 0x1602:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS; //does not readGRAM
+ static const uint8_t XX1602_regValues[] PROGMEM = {
+ 0xB8, 1, 0x01, //GS [00]
+ 0xC0, 1, 0x0E, //??Power [0A]
+ };
+ table8_ads = XX1602_regValues, table_size = sizeof(XX1602_regValues);
+ break;
+
+ case 0x2053: //weird from BangGood
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS | REV_SCREEN | READ_BGR;
+ goto common_9329;
+ case 0xAC11:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS | REV_SCREEN; //thanks viliam
+ goto common_9329;
+ case 0x9302:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS;
+ goto common_9329;
+ case 0x9338:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS;
+ goto common_9329;
+ case 0x9329:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | INVERT_SS | REV_SCREEN;
+ common_9329:
+ static const uint8_t ILI9329_regValues[] PROGMEM = {
+// 0xF6, 3, 0x01, 0x01, 0x00, //Interface Control needs EXTC=1 MX_EOR=1, TM=0, RIM=0
+// 0xB6, 3, 0x0A, 0x82, 0x27, //Display Function [0A 82 27]
+// 0xB7, 1, 0x06, //Entry Mode Set [06]
+ 0x36, 1, 0x00, //Memory Access [00] pointless but stops an empty array
+ };
+ table8_ads = ILI9329_regValues, table_size = sizeof(ILI9329_regValues);
+ break;
+
+ case 0x9340: //ILI9340 thanks Ravi_kanchan2004.
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS | REV_SCREEN;
+ goto common_9341;
+ case 0x9341:
+ common_9341:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS;
+ static const uint8_t ILI9341_regValues_2_4[] PROGMEM = { // BOE 2.4"
+ 0xF6, 3, 0x01, 0x01, 0x00, //Interface Control needs EXTC=1 MV_EOR=0, TM=0, RIM=0
+ 0xCF, 3, 0x00, 0x81, 0x30, //Power Control B [00 81 30]
+ 0xED, 4, 0x64, 0x03, 0x12, 0x81, //Power On Seq [55 01 23 01]
+ 0xE8, 3, 0x85, 0x10, 0x78, //Driver Timing A [04 11 7A]
+ 0xCB, 5, 0x39, 0x2C, 0x00, 0x34, 0x02, //Power Control A [39 2C 00 34 02]
+ 0xF7, 1, 0x20, //Pump Ratio [10]
+ 0xEA, 2, 0x00, 0x00, //Driver Timing B [66 00]
+ 0xB0, 1, 0x00, //RGB Signal [00]
+ 0xB1, 2, 0x00, 0x1B, //Frame Control [00 1B]
+ // 0xB6, 2, 0x0A, 0xA2, 0x27, //Display Function [0A 82 27 XX] .kbv SS=1
+ 0xB4, 1, 0x00, //Inversion Control [02] .kbv NLA=1, NLB=1, NLC=1
+ 0xC0, 1, 0x21, //Power Control 1 [26]
+ 0xC1, 1, 0x11, //Power Control 2 [00]
+ 0xC5, 2, 0x3F, 0x3C, //VCOM 1 [31 3C]
+ 0xC7, 1, 0xB5, //VCOM 2 [C0]
+ 0x36, 1, 0x48, //Memory Access [00]
+ 0xF2, 1, 0x00, //Enable 3G [02]
+ 0x26, 1, 0x01, //Gamma Set [01]
+ 0xE0, 15, 0x0f, 0x26, 0x24, 0x0b, 0x0e, 0x09, 0x54, 0xa8, 0x46, 0x0c, 0x17, 0x09, 0x0f, 0x07, 0x00,
+ 0xE1, 15, 0x00, 0x19, 0x1b, 0x04, 0x10, 0x07, 0x2a, 0x47, 0x39, 0x03, 0x06, 0x06, 0x30, 0x38, 0x0f,
+ };
+ static const uint8_t ILI9341_regValues_ada[] PROGMEM = { // Adafruit_TFTLCD only works with EXTC=0
+ // 0xF6, 3, 0x00, 0x01, 0x00, //Interface Control needs EXTC=1 TM=0, RIM=0
+ // 0xF6, 3, 0x01, 0x01, 0x03, //Interface Control needs EXTC=1 RM=1, RIM=1
+ 0xF6, 3, 0x09, 0x01, 0x03, //Interface Control needs EXTC=1 RM=0, RIM=1
+ 0xB0, 1, 0x40, //RGB Signal [40] RCM=2
+ 0xB4, 1, 0x00, //Inversion Control [02] .kbv NLA=1, NLB=1, NLC=1
+ 0xC0, 1, 0x23, //Power Control 1 [26]
+ 0xC1, 1, 0x10, //Power Control 2 [00]
+ 0xC5, 2, 0x2B, 0x2B, //VCOM 1 [31 3C]
+ 0xC7, 1, 0xC0, //VCOM 2 [C0]
+ 0x36, 1, 0x88, //Memory Access [00]
+ 0xB1, 2, 0x00, 0x1B, //Frame Control [00 1B]
+ 0xB7, 1, 0x07, //Entry Mode [00]
+ };
+ table8_ads = ILI9341_regValues_2_4, table_size = sizeof(ILI9341_regValues_2_4); //
+ break;
+#if defined(SUPPORT_9342)
+ case 0x9342:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS | INVERT_GS | REV_SCREEN;
+ static const uint8_t ILI9342_regValues_CPT24[] PROGMEM = { //CPT 2.4"
+ (0xB9), 3, 0xFF, 0x93, 0x42, //[00 00 00]
+ (0xC0), 2, 0x1D, 0x0A, //[26 09]
+ (0xC1), 1, 0x02, //[10]
+ (0xC5), 2, 0x2F, 0x2F, //[31 3C]
+ (0xC7), 1, 0xC3, //[C0]
+ (0xB8), 1, 0x0B, //[07]
+ (0xE0), 15, 0x0F, 0x33, 0x30, 0x0C, 0x0F, 0x08, 0x5D, 0x66, 0x4A, 0x07, 0x13, 0x05, 0x1B, 0x0E, 0x08,
+ (0xE1), 15, 0x08, 0x0E, 0x11, 0x02, 0x0E, 0x02, 0x24, 0x33, 0x37, 0x03, 0x0A, 0x09, 0x26, 0x33, 0x0F,
+ };
+ static const uint8_t ILI9342_regValues_Tianma23[] PROGMEM = { //Tianma 2.3"
+ (0xB9), 3, 0xFF, 0x93, 0x42,
+ (0xC0), 2, 0x1D, 0x0A,
+ (0xC1), 1, 0x01,
+ (0xC5), 2, 0x2C, 0x2C,
+ (0xC7), 1, 0xC6,
+ (0xB8), 1, 0x09,
+ (0xE0), 15, 0x0F, 0x26, 0x21, 0x07, 0x0A, 0x03, 0x4E, 0x62, 0x3E, 0x0B, 0x11, 0x00, 0x08, 0x02, 0x00,
+ (0xE1), 15, 0x00, 0x19, 0x1E, 0x03, 0x0E, 0x03, 0x30, 0x23, 0x41, 0x03, 0x0B, 0x07, 0x2F, 0x36, 0x0F,
+ };
+ static const uint8_t ILI9342_regValues_HSD23[] PROGMEM = { //HSD 2.3"
+ (0xB9), 3, 0xFF, 0x93, 0x42,
+ (0xC0), 2, 0x1D, 0x0A,
+ (0xC1), 1, 0x02,
+ (0xC5), 2, 0x2F, 0x27,
+ (0xC7), 1, 0xA4,
+ (0xB8), 1, 0x0B,
+ (0xE0), 15, 0x0F, 0x24, 0x21, 0x0C, 0x0F, 0x06, 0x50, 0x75, 0x3F, 0x07, 0x12, 0x05, 0x11, 0x0B, 0x08,
+ (0xE1), 15, 0x08, 0x1D, 0x20, 0x02, 0x0E, 0x04, 0x31, 0x24, 0x42, 0x03, 0x0B, 0x09, 0x30, 0x36, 0x0F,
+ };
+ table8_ads = ILI9342_regValues_CPT24, table_size = sizeof(ILI9342_regValues_CPT24); //
+ // table8_ads = ILI9342_regValues_Tianma23, table_size = sizeof(ILI9342_regValues_Tianma23); //
+ // table8_ads = ILI9342_regValues_HSD23, table_size = sizeof(ILI9342_regValues_HSD23); //
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 240;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 320;
+ break;
+#endif
+ case 0x1581: //no BGR in MADCTL. set BGR in Panel Control
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS; //thanks zdravke
+ goto common_9481;
+ case 0x9481:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_BGR;
+ common_9481:
+ static const uint8_t ILI9481_regValues[] PROGMEM = { // Atmel MaxTouch
+ 0xB0, 1, 0x00, // unlocks E0, F0
+ 0xB3, 4, 0x02, 0x00, 0x00, 0x00, //Frame Memory, interface [02 00 00 00]
+ 0xB4, 1, 0x00, // Frame mode [00]
+ 0xD0, 3, 0x07, 0x42, 0x18, // Set Power [00 43 18] x1.00, x6, x3
+ 0xD1, 3, 0x00, 0x07, 0x10, // Set VCOM [00 00 00] x0.72, x1.02
+ 0xD2, 2, 0x01, 0x02, // Set Power for Normal Mode [01 22]
+ 0xD3, 2, 0x01, 0x02, // Set Power for Partial Mode [01 22]
+ 0xD4, 2, 0x01, 0x02, // Set Power for Idle Mode [01 22]
+ 0xC0, 5, 0x12, 0x3B, 0x00, 0x02, 0x11, //Panel Driving BGR for 1581 [10 3B 00 02 11]
+ 0xC1, 3, 0x10, 0x10, 0x88, // Display Timing Normal [10 10 88]
+ 0xC5, 1, 0x03, //Frame Rate [03]
+ 0xC6, 1, 0x02, //Interface Control [02]
+ 0xC8, 12, 0x00, 0x32, 0x36, 0x45, 0x06, 0x16, 0x37, 0x75, 0x77, 0x54, 0x0C, 0x00,
+ 0xCC, 1, 0x00, //Panel Control [00]
+ };
+ static const uint8_t ILI9481_CPT29_regValues[] PROGMEM = { // 320x430
+ 0xB0, 1, 0x00,
+ 0xD0, 3, 0x07, 0x42, 0x1C, // Set Power [00 43 18]
+ 0xD1, 3, 0x00, 0x02, 0x0F, // Set VCOM [00 00 00] x0.695, x1.00
+ 0xD2, 2, 0x01, 0x11, // Set Power for Normal Mode [01 22]
+ 0xC0, 5, 0x10, 0x35, 0x00, 0x02, 0x11, //Set Panel Driving [10 3B 00 02 11]
+ 0xC5, 1, 0x03, //Frame Rate [03]
+ 0xC8, 12, 0x00, 0x30, 0x36, 0x45, 0x04, 0x16, 0x37, 0x75, 0x77, 0x54, 0x0F, 0x00,
+ 0xE4, 1, 0xA0,
+ 0xF0, 1, 0x01,
+ 0xF3, 2, 0x02, 0x1A,
+ };
+ static const uint8_t ILI9481_PVI35_regValues[] PROGMEM = { // 320x480
+ 0xB0, 1, 0x00,
+ 0xD0, 3, 0x07, 0x41, 0x1D, // Set Power [00 43 18]
+ 0xD1, 3, 0x00, 0x2B, 0x1F, // Set VCOM [00 00 00] x0.900, x1.32
+ 0xD2, 2, 0x01, 0x11, // Set Power for Normal Mode [01 22]
+ 0xC0, 5, 0x10, 0x3B, 0x00, 0x02, 0x11, //Set Panel Driving [10 3B 00 02 11]
+ 0xC5, 1, 0x03, //Frame Rate [03]
+ 0xC8, 12, 0x00, 0x14, 0x33, 0x10, 0x00, 0x16, 0x44, 0x36, 0x77, 0x00, 0x0F, 0x00,
+ 0xE4, 1, 0xA0,
+ 0xF0, 1, 0x01,
+ 0xF3, 2, 0x40, 0x0A,
+ };
+ static const uint8_t ILI9481_AUO317_regValues[] PROGMEM = { // 320x480
+ 0xB0, 1, 0x00,
+ 0xD0, 3, 0x07, 0x40, 0x1D, // Set Power [00 43 18]
+ 0xD1, 3, 0x00, 0x18, 0x13, // Set VCOM [00 00 00] x0.805, x1.08
+ 0xD2, 2, 0x01, 0x11, // Set Power for Normal Mode [01 22]
+ 0xC0, 5, 0x10, 0x3B, 0x00, 0x02, 0x11, //Set Panel Driving [10 3B 00 02 11]
+ 0xC5, 1, 0x03, //Frame Rate [03]
+ 0xC8, 12, 0x00, 0x44, 0x06, 0x44, 0x0A, 0x08, 0x17, 0x33, 0x77, 0x44, 0x08, 0x0C,
+ 0xE4, 1, 0xA0,
+ 0xF0, 1, 0x01,
+ };
+ static const uint8_t ILI9481_CMO35_regValues[] PROGMEM = { // 320480
+ 0xB0, 1, 0x00,
+ 0xD0, 3, 0x07, 0x41, 0x1D, // Set Power [00 43 18] 07,41,1D
+ 0xD1, 3, 0x00, 0x1C, 0x1F, // Set VCOM [00 00 00] x0.825, x1.32 1C,1F
+ 0xD2, 2, 0x01, 0x11, // Set Power for Normal Mode [01 22]
+ 0xC0, 5, 0x10, 0x3B, 0x00, 0x02, 0x11, //Set Panel Driving [10 3B 00 02 11]
+ 0xC5, 1, 0x03, //Frame Rate [03]
+ 0xC6, 1, 0x83,
+ 0xC8, 12, 0x00, 0x26, 0x21, 0x00, 0x00, 0x1F, 0x65, 0x23, 0x77, 0x00, 0x0F, 0x00,
+ 0xF0, 1, 0x01, //?
+ 0xE4, 1, 0xA0, //?SETCABC on Himax
+ 0x36, 1, 0x48, //Memory Access [00]
+ 0xB4, 1, 0x11,
+ };
+ static const uint8_t ILI9481_RGB_regValues[] PROGMEM = { // 320x480
+ 0xB0, 1, 0x00,
+ 0xD0, 3, 0x07, 0x41, 0x1D, // SETPOWER [00 43 18]
+ 0xD1, 3, 0x00, 0x2B, 0x1F, // SETVCOM [00 00 00] x0.900, x1.32
+ 0xD2, 2, 0x01, 0x11, // SETNORPOW for Normal Mode [01 22]
+ 0xC0, 6, 0x10, 0x3B, 0x00, 0x02, 0x11, 0x00, //SETPANEL [10 3B 00 02 11]
+ 0xC5, 1, 0x03, //SETOSC Frame Rate [03]
+ 0xC6, 1, 0x80, //SETRGB interface control
+ 0xC8, 12, 0x00, 0x14, 0x33, 0x10, 0x00, 0x16, 0x44, 0x36, 0x77, 0x00, 0x0F, 0x00,
+ 0xF3, 2, 0x40, 0x0A,
+ 0xF0, 1, 0x08,
+ 0xF6, 1, 0x84,
+ 0xF7, 1, 0x80,
+ 0x0C, 2, 0x00, 0x55, //RDCOLMOD
+ 0xB4, 1, 0x00, //SETDISPLAY
+// 0xB3, 4, 0x00, 0x01, 0x06, 0x01, //SETGRAM simple example
+ 0xB3, 4, 0x00, 0x01, 0x06, 0x30, //jpegs example
+ };
+ table8_ads = ILI9481_regValues, table_size = sizeof(ILI9481_regValues);
+// table8_ads = ILI9481_CPT29_regValues, table_size = sizeof(ILI9481_CPT29_regValues);
+// table8_ads = ILI9481_PVI35_regValues, table_size = sizeof(ILI9481_PVI35_regValues);
+// table8_ads = ILI9481_AUO317_regValues, table_size = sizeof(ILI9481_AUO317_regValues);
+// table8_ads = ILI9481_CMO35_regValues, table_size = sizeof(ILI9481_CMO35_regValues);
+// table8_ads = ILI9481_RGB_regValues, table_size = sizeof(ILI9481_RGB_regValues);
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 480;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 320;
+ break;
+ case 0x9486:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS; //Red 3.5", Blue 3.5"
+// _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | REV_SCREEN; //old Red 3.5"
+ static const uint8_t ILI9486_regValues[] PROGMEM = {
+/*
+ 0xF2, 9, 0x1C, 0xA3, 0x32, 0x02, 0xB2, 0x12, 0xFF, 0x12, 0x00, //f.k
+ 0xF1, 2, 0x36, 0xA4, //
+ 0xF8, 2, 0x21, 0x04, //
+ 0xF9, 2, 0x00, 0x08, //
+*/
+ 0xC0, 2, 0x0d, 0x0d, //Power Control 1 [0E 0E]
+ 0xC1, 2, 0x43, 0x00, //Power Control 2 [43 00]
+ 0xC2, 1, 0x00, //Power Control 3 [33]
+ 0xC5, 4, 0x00, 0x48, 0x00, 0x48, //VCOM Control 1 [00 40 00 40]
+ 0xB4, 1, 0x00, //Inversion Control [00]
+ 0xB6, 3, 0x02, 0x02, 0x3B, // Display Function Control [02 02 3B]
+#define GAMMA9486 4
+#if GAMMA9486 == 0
+ // default GAMMA terrible
+#elif GAMMA9486 == 1
+ // GAMMA f.k. bad
+ 0xE0, 15, 0x0f, 0x31, 0x2b, 0x0c, 0x0e, 0x08, 0x4e, 0xf1, 0x37, 0x07, 0x10, 0x03, 0x0e, 0x09, 0x00,
+ 0xE1, 15, 0x00, 0x0e, 0x14, 0x03, 0x11, 0x07, 0x31, 0xC1, 0x48, 0x08, 0x0f, 0x0c, 0x31, 0x36, 0x0f,
+#elif GAMMA9486 == 2
+ // 1.2 CPT 3.5 Inch Initial Code not bad
+ 0xE0, 15, 0x0F, 0x1B, 0x18, 0x0B, 0x0E, 0x09, 0x47, 0x94, 0x35, 0x0A, 0x13, 0x05, 0x08, 0x03, 0x00,
+ 0xE1, 15, 0x0F, 0x3A, 0x37, 0x0B, 0x0C, 0x05, 0x4A, 0x24, 0x39, 0x07, 0x10, 0x04, 0x27, 0x25, 0x00,
+#elif GAMMA9486 == 3
+ // 2.2 HSD 3.5 Inch Initial Code not bad
+ 0xE0, 15, 0x0F, 0x1F, 0x1C, 0x0C, 0x0F, 0x08, 0x48, 0x98, 0x37, 0x0A, 0x13, 0x04, 0x11, 0x0D, 0x00,
+ 0xE1, 15, 0x0F, 0x32, 0x2E, 0x0B, 0x0D, 0x05, 0x47, 0x75, 0x37, 0x06, 0x10, 0x03, 0x24, 0x20, 0x00,
+#elif GAMMA9486 == 4
+ // 3.2 TM 3.2 Inch Initial Code not bad
+ 0xE0, 15, 0x0F, 0x21, 0x1C, 0x0B, 0x0E, 0x08, 0x49, 0x98, 0x38, 0x09, 0x11, 0x03, 0x14, 0x10, 0x00,
+ 0xE1, 15, 0x0F, 0x2F, 0x2B, 0x0C, 0x0E, 0x06, 0x47, 0x76, 0x37, 0x07, 0x11, 0x04, 0x23, 0x1E, 0x00,
+#elif GAMMA9486 == 5
+ // 4.2 WTK 3.5 Inch Initial Code too white
+ 0xE0, 15, 0x0F, 0x10, 0x08, 0x05, 0x09, 0x05, 0x37, 0x98, 0x26, 0x07, 0x0F, 0x02, 0x09, 0x07, 0x00,
+ 0xE1, 15, 0x0F, 0x38, 0x36, 0x0D, 0x10, 0x08, 0x59, 0x76, 0x48, 0x0A, 0x16, 0x0A, 0x37, 0x2F, 0x00,
+#endif
+ };
+ table8_ads = ILI9486_regValues, table_size = sizeof(ILI9486_regValues);
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 480;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 320;
+ break;
+ case 0x7796:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS; //thanks to safari1
+ goto common_9488;
+ case 0x9487: //with thanks to Charlyf
+ case 0x9488:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS;
+ common_9488:
+ static const uint8_t ILI9488_regValues_max[] PROGMEM = { // Atmel MaxTouch
+ 0xC0, 2, 0x10, 0x10, //Power Control 1 [0E 0E]
+ 0xC1, 1, 0x41, //Power Control 2 [43]
+ 0xC5, 4, 0x00, 0x22, 0x80, 0x40, //VCOM Control 1 [00 40 00 40]
+ 0x36, 1, 0x68, //Memory Access [00]
+ 0xB0, 1, 0x00, //Interface [00]
+ 0xB1, 2, 0xB0, 0x11, //Frame Rate Control [B0 11]
+ 0xB4, 1, 0x02, //Inversion Control [02]
+ 0xB6, 3, 0x02, 0x02, 0x3B, // Display Function Control [02 02 3B] .kbv NL=480
+ 0xB7, 1, 0xC6, //Entry Mode [06]
+ 0x3A, 1, 0x55, //Interlace Pixel Format [XX]
+ 0xF7, 4, 0xA9, 0x51, 0x2C, 0x82, //Adjustment Control 3 [A9 51 2C 82]
+ };
+ table8_ads = ILI9488_regValues_max, table_size = sizeof(ILI9488_regValues_max);
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 480;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 320;
+ break;
+ case 0xB505: //R61505V
+ case 0xC505: //R61505W
+ _lcd_capable = 0 | REV_SCREEN | READ_LOWHIGH;
+ static const uint16_t R61505V_regValues[] PROGMEM = {
+ 0x0000, 0x0000,
+ 0x0000, 0x0000,
+ 0x0000, 0x0000,
+ 0x0000, 0x0001,
+ 0x00A4, 0x0001, //CALB=1
+ TFTLCD_DELAY, 10,
+ 0x0060, 0x2700, //NL
+ 0x0008, 0x0808, //FP & BP
+ 0x0030, 0x0214, //Gamma settings
+ 0x0031, 0x3715,
+ 0x0032, 0x0604,
+ 0x0033, 0x0E16,
+ 0x0034, 0x2211,
+ 0x0035, 0x1500,
+ 0x0036, 0x8507,
+ 0x0037, 0x1407,
+ 0x0038, 0x1403,
+ 0x0039, 0x0020,
+ 0x0090, 0x0015, //DIVI & RTNI
+ 0x0010, 0x0410, //BT=4,AP=1
+ 0x0011, 0x0237, //DC1=2,DC0=3, VC=7
+ 0x0029, 0x0046, //VCM1=70
+ 0x002A, 0x0046, //VCMSEL=0,VCM2=70
+ // Sleep mode IN sequence
+ 0x0007, 0x0000,
+ //0x0012, 0x0000, //PSON=0,PON=0
+ // Sleep mode EXIT sequence
+ 0x0012, 0x0189, //VCMR=1,PSON=0,PON=0,VRH=9
+ 0x0013, 0x1100, //VDV=17
+ TFTLCD_DELAY, 150,
+ 0x0012, 0x01B9, //VCMR=1,PSON=1,PON=1,VRH=9 [018F]
+ 0x0001, 0x0100, //SS=1 Other mode settings
+ 0x0002, 0x0200, //BC0=1--Line inversion
+ 0x0003, 0x1030,
+ 0x0009, 0x0001, //ISC=1 [0000]
+ 0x000A, 0x0000, // [0000]
+ // 0x000C, 0x0001, //RIM=1 [0000]
+ 0x000D, 0x0000, // [0000]
+ 0x000E, 0x0030, //VEM=3 VCOM equalize [0000]
+ 0x0061, 0x0001,
+ 0x006A, 0x0000,
+ 0x0080, 0x0000,
+ 0x0081, 0x0000,
+ 0x0082, 0x005F,
+ 0x0092, 0x0100,
+ 0x0093, 0x0701,
+ TFTLCD_DELAY, 80,
+ 0x0007, 0x0100, //BASEE=1--Display On
+ };
+ init_table16(R61505V_regValues, sizeof(R61505V_regValues));
+ break;
+
+#if defined(SUPPORT_B509_7793)
+ case 0x7793:
+ case 0xB509:
+ _lcd_capable = REV_SCREEN;
+ static const uint16_t R61509V_regValues[] PROGMEM = {
+ 0x0000, 0x0000,
+ 0x0000, 0x0000,
+ 0x0000, 0x0000,
+ 0x0000, 0x0000,
+ TFTLCD_DELAY, 15,
+ 0x0400, 0x6200, //NL=0x31 (49) i.e. 400 rows
+ 0x0008, 0x0808,
+ //gamma
+ 0x0300, 0x0C00,
+ 0x0301, 0x5A0B,
+ 0x0302, 0x0906,
+ 0x0303, 0x1017,
+ 0x0304, 0x2300,
+ 0x0305, 0x1700,
+ 0x0306, 0x6309,
+ 0x0307, 0x0C09,
+ 0x0308, 0x100C,
+ 0x0309, 0x2232,
+
+ 0x0010, 0x0016, //69.5Hz 0016
+ 0x0011, 0x0101,
+ 0x0012, 0x0000,
+ 0x0013, 0x0001,
+
+ 0x0100, 0x0330, //BT,AP
+ 0x0101, 0x0237, //DC0,DC1,VC
+ 0x0103, 0x0D00, //VDV
+ 0x0280, 0x6100, //VCM
+ 0x0102, 0xC1B0, //VRH,VCMR,PSON,PON
+ TFTLCD_DELAY, 50,
+
+ 0x0001, 0x0100,
+ 0x0002, 0x0100,
+ 0x0003, 0x1030, //1030
+ 0x0009, 0x0001,
+ 0x000C, 0x0000,
+ 0x0090, 0x8000,
+ 0x000F, 0x0000,
+
+ 0x0210, 0x0000,
+ 0x0211, 0x00EF,
+ 0x0212, 0x0000,
+ 0x0213, 0x018F, //432=01AF,400=018F
+ 0x0500, 0x0000,
+ 0x0501, 0x0000,
+ 0x0502, 0x005F, //???
+ 0x0401, 0x0001, //REV=1
+ 0x0404, 0x0000,
+ TFTLCD_DELAY, 50,
+
+ 0x0007, 0x0100, //BASEE
+ TFTLCD_DELAY, 50,
+
+ 0x0200, 0x0000,
+ 0x0201, 0x0000,
+ };
+ init_table16(R61509V_regValues, sizeof(R61509V_regValues));
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 400;
+ break;
+#endif
+
+#ifdef SUPPORT_9806
+ case 0x9806:
+ _lcd_capable = AUTO_READINC | MIPI_DCS_REV1 | MV_AXIS | READ_24BITS;
+ // from ZinggJM
+ static const uint8_t ILI9806_regValues[] PROGMEM = {
+ (0xFF), 3, /* EXTC Command Set enable register*/ 0xFF, 0x98, 0x06,
+ (0xBA), 1, /* SPI Interface Setting*/0xE0,
+ (0xBC), 21, /* GIP 1*/0x03, 0x0F, 0x63, 0x69, 0x01, 0x01, 0x1B, 0x11, 0x70, 0x73, 0xFF, 0xFF, 0x08, 0x09, 0x05, 0x00, 0xEE, 0xE2, 0x01, 0x00, 0xC1,
+ (0xBD), 8, /* GIP 2*/0x01, 0x23, 0x45, 0x67, 0x01, 0x23, 0x45, 0x67,
+ (0xBE), 9, /* GIP 3*/0x00, 0x22, 0x27, 0x6A, 0xBC, 0xD8, 0x92, 0x22, 0x22,
+ (0xC7), 1, /* Vcom*/0x1E,
+ (0xED), 3, /* EN_volt_reg*/0x7F, 0x0F, 0x00,
+ (0xC0), 3, /* Power Control 1*/0xE3, 0x0B, 0x00,
+ (0xFC), 1, 0x08,
+ (0xDF), 6, /* Engineering Setting*/0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+ (0xF3), 1, /* DVDD Voltage Setting*/0x74,
+ (0xB4), 3, /* Display Inversion Control*/0x00, 0x00, 0x00,
+ (0xF7), 1, /* 480x854*/0x81,
+ (0xB1), 3, /* Frame Rate*/0x00, 0x10, 0x14,
+ (0xF1), 3, /* Panel Timing Control*/0x29, 0x8A, 0x07,
+ (0xF2), 4, /*Panel Timing Control*/0x40, 0xD2, 0x50, 0x28,
+ (0xC1), 4, /* Power Control 2*/0x17, 0x85, 0x85, 0x20,
+ (0xE0), 16, 0x00, 0x0C, 0x15, 0x0D, 0x0F, 0x0C, 0x07, 0x05, 0x07, 0x0B, 0x10, 0x10, 0x0D, 0x17, 0x0F, 0x00,
+ (0xE1), 16, 0x00, 0x0D, 0x15, 0x0E, 0x10, 0x0D, 0x08, 0x06, 0x07, 0x0C, 0x11, 0x11, 0x0E, 0x17, 0x0F, 0x00,
+ (0x35), 1, /*Tearing Effect ON*/0x00,
+ };
+ table8_ads = ILI9806_regValues, table_size = sizeof(ILI9806_regValues);
+ p16 = (int16_t *) & HEIGHT;
+ *p16 = 480;
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 854;
+ break;
+#endif
+ default:
+ p16 = (int16_t *) & WIDTH;
+ *p16 = 0; //error value for WIDTH
+ break;
+ }
+ _lcd_rev = ((_lcd_capable & REV_SCREEN) != 0);
+ if (table8_ads != NULL) {
+ static const uint8_t reset_off[] PROGMEM = {
+ 0x01, 0, //Soft Reset
+ TFTLCD_DELAY8, 150, // .kbv will power up with ONLY reset, sleep out, display on
+ 0x28, 0, //Display Off
+ 0x3A, 1, 0x55, //Pixel read=565, write=565.
+ };
+ static const uint8_t wake_on[] PROGMEM = {
+ 0x11, 0, //Sleep Out
+ TFTLCD_DELAY8, 150,
+ 0x29, 0, //Display On
+ };
+ init_table(&reset_off, sizeof(reset_off));
+ init_table(table8_ads, table_size); //can change PIXFMT
+ init_table(&wake_on, sizeof(wake_on));
+ }
+ setRotation(0); //PORTRAIT
+ invertDisplay(false);
+#if defined(SUPPORT_9488_555)
+ if (_lcd_ID == 0x9488) {
+ is555 = 0;
+ drawPixel(0, 0, 0xFFE0);
+ if (readPixel(0, 0) == 0xFF1F) {
+ uint8_t pixfmt = 0x06;
+ pushCommand(0x3A, &pixfmt, 1);
+ _lcd_capable &= ~READ_24BITS;
+ is555 = 1;
+ }
+ }
+#endif
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MCUFRIEND_kbv/MCUFRIEND_kbv.h Wed Apr 21 14:54:37 2021 +0000
@@ -0,0 +1,88 @@
+// link:
+// https://os.mbed.com/users/davidprentice/code/Nucleo_dir_L152//file/d88d2ad55fac/main.cpp/
+// Committer: davidprentice
+// Date: 19 months ago
+// 2021-04-21
+//
+// MCUFRIEND_kbv.h
+//
+
+/*
+ * MCUFRIEND_kbv class inherits from Adafruit_GFX class and the Arduino Print class.
+ * Any use of MCUFRIEND_kbv class and examples is dependent on Adafruit and Arduino licenses
+ * The license texts are in the accompanying license.txt file
+ */
+
+#ifndef MCUFRIEND_KBV_H_
+#define MCUFRIEND_KBV_H_ 299
+
+//#define USE_SERIAL
+
+#if ARDUINO < 101
+#define USE_GFX_KBV
+#include "ADA_GFX_kbv.h"
+#else
+#include "Adafruit_GFX.h"
+#endif
+
+class MCUFRIEND_kbv : public Adafruit_GFX {
+
+ public:
+// MCUFRIEND_kbv(int CS=A3, int RS=A2, int WR=A1, int RD=A0, int RST=A4); //shield wiring
+ MCUFRIEND_kbv(int CS=0, int RS=0, int WR=0, int RD=0, int _RST=0); //dummy arguments
+ void reset(void); // you only need the constructor
+ void begin(uint16_t ID = 0x9341); // you only need the constructor
+ virtual void drawPixel(int16_t x, int16_t y, uint16_t color); // and these three
+ void WriteCmdData(uint16_t cmd, uint16_t dat); // ?public methods !!!
+ void pushCommand(uint16_t cmd, uint8_t * block, int8_t N);
+ uint16_t color565(uint8_t r, uint8_t g, uint8_t b) { return ((r & 0xF8) << 8) | ((g & 0xFC) << 3) | ((b & 0xF8) >> 3); }
+ uint16_t readID(void);
+ virtual void fillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);
+ virtual void drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color) { fillRect(x, y, 1, h, color); }
+ virtual void drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color) { fillRect(x, y, w, 1, color); }
+ virtual void fillScreen(uint16_t color) { fillRect(0, 0, _width, _height, color); }
+ virtual void setRotation(uint8_t r);
+ virtual void invertDisplay(boolean i);
+
+ uint16_t readReg(uint16_t reg, int8_t index=0);
+ int16_t readGRAM(int16_t x, int16_t y, uint16_t *block, int16_t w, int16_t h);
+ uint16_t readPixel(int16_t x, int16_t y) { uint16_t color; readGRAM(x, y, &color, 1, 1); return color; }
+ void setAddrWindow(int16_t x, int16_t y, int16_t x1, int16_t y1);
+ void pushColors(uint16_t *block, int16_t n, bool first);
+ void pushColors(uint8_t *block, int16_t n, bool first);
+ void pushColors(const uint8_t *block, int16_t n, bool first, bool bigend = false);
+ void vertScroll(int16_t top, int16_t scrollines, int16_t offset);
+
+ protected:
+ uint32_t readReg32(uint16_t reg);
+ uint32_t readReg40(uint16_t reg);
+ uint16_t _lcd_xor, _lcd_capable;
+
+ private:
+ uint16_t _lcd_ID, _lcd_rev, _lcd_madctl, _lcd_drivOut, _MC, _MP, _MW, _SC, _EC, _SP, _EP;
+};
+
+// New color definitions. thanks to Bodmer
+#define TFT_BLACK 0x0000 /* 0, 0, 0 */
+#define TFT_NAVY 0x000F /* 0, 0, 128 */
+#define TFT_DARKGREEN 0x03E0 /* 0, 128, 0 */
+#define TFT_DARKCYAN 0x03EF /* 0, 128, 128 */
+#define TFT_MAROON 0x7800 /* 128, 0, 0 */
+#define TFT_PURPLE 0x780F /* 128, 0, 128 */
+#define TFT_OLIVE 0x7BE0 /* 128, 128, 0 */
+#define TFT_LIGHTGREY 0xC618 /* 192, 192, 192 */
+#define TFT_DARKGREY 0x7BEF /* 128, 128, 128 */
+#define TFT_BLUE 0x001F /* 0, 0, 255 */
+#define TFT_GREEN 0x07E0 /* 0, 255, 0 */
+#define TFT_CYAN 0x07FF /* 0, 255, 255 */
+#define TFT_RED 0xF800 /* 255, 0, 0 */
+#define TFT_MAGENTA 0xF81F /* 255, 0, 255 */
+#define TFT_YELLOW 0xFFE0 /* 255, 255, 0 */
+#define TFT_WHITE 0xFFFF /* 255, 255, 255 */
+#define TFT_ORANGE 0xFDA0 /* 255, 180, 0 */
+#define TFT_GREENYELLOW 0xB7E0 /* 180, 255, 0 */
+#define TFT_PINK 0xFC9F
+
+#endif
+
+
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MCUFRIEND_kbv/utility/mcufriend_keil.h Wed Apr 21 14:54:37 2021 +0000
@@ -0,0 +1,106 @@
+#ifndef MCUFRIEND_KEIL_H_
+#define MCUFRIEND_KEIL_H_
+
+#if defined(USE_SERIAL)
+#include "mcufriend_keil_spi.h"
+#else
+#include "pin_shield_1.h" //shield pin macros e.g. A2_PORT, PIN_OUTPUT()
+#include "pin_shield_8.h" //macros for write_8(), read_8(), setWriteDir(), ...
+
+// control pins as used in MCUFRIEND shields
+ #define RD_PORT A0_PORT
+ #define RD_PIN A0_PIN
+ #define WR_PORT A1_PORT
+ #define WR_PIN A1_PIN
+ #define CD_PORT A2_PORT
+ #define CD_PIN A2_PIN
+ #define CS_PORT A3_PORT
+ #define CS_PIN A3_PIN
+ #define RESET_PORT A4_PORT
+ #define RESET_PIN A4_PIN
+
+// general purpose pin macros
+ #define RD_ACTIVE PIN_LOW(RD_PORT, RD_PIN)
+ #define RD_IDLE PIN_HIGH(RD_PORT, RD_PIN)
+ #define RD_OUTPUT PIN_OUTPUT(RD_PORT, RD_PIN)
+ #define WR_ACTIVE PIN_LOW(WR_PORT, WR_PIN)
+ #define WR_IDLE PIN_HIGH(WR_PORT, WR_PIN)
+ #define WR_OUTPUT PIN_OUTPUT(WR_PORT, WR_PIN)
+ #define CD_COMMAND PIN_LOW(CD_PORT, CD_PIN)
+ #define CD_DATA PIN_HIGH(CD_PORT, CD_PIN)
+ #define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN)
+ #define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN)
+ #define CS_IDLE PIN_HIGH(CS_PORT, CS_PIN)
+ #define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN)
+ #define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN)
+ #define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN)
+ #define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN)
+
+#define WR_ACTIVE2 {WR_ACTIVE; WR_ACTIVE;}
+#define WR_ACTIVE4 {WR_ACTIVE2; WR_ACTIVE2;}
+#define WR_ACTIVE8 {WR_ACTIVE4; WR_ACTIVE4;}
+#define RD_ACTIVE2 {RD_ACTIVE; RD_ACTIVE;}
+#define RD_ACTIVE4 {RD_ACTIVE2; RD_ACTIVE2;}
+#define RD_ACTIVE8 {RD_ACTIVE4; RD_ACTIVE4;}
+#define RD_ACTIVE16 {RD_ACTIVE8; RD_ACTIVE8;}
+#define WR_IDLE2 {WR_IDLE; WR_IDLE;}
+#define WR_IDLE4 {WR_IDLE2; WR_IDLE2;}
+#define RD_IDLE2 {RD_IDLE; RD_IDLE;}
+#define RD_IDLE4 {RD_IDLE2; RD_IDLE2;}
+
+// General macros. IOCLR registers are 1 cycle when optimised.
+#define WR_STROBE { WR_ACTIVE; WR_IDLE; } //PWLW=TWRL=50ns
+#define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE //PWLR=TRDL=150ns
+
+#if defined(TEENSY) || defined(__ARM_ARCH_7EM__) // -O2: F411@100MHz = 1.44s
+//#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; WR_ACTIVE; }
+//#define READ_DELAY { RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; RD_ACTIVE; }
+#if 0
+#elif defined(STM32F401xx)
+#warning 84MHz
+#define WRITE_DELAY { WR_ACTIVE2; } //100MHz
+#define READ_DELAY { RD_ACTIVE4; }
+#elif defined(STM32F411xx)
+#define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //100MHz
+#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE2; }
+#elif defined(STM32F446xx)
+#warning 180MHz
+#define WRITE_DELAY { WR_ACTIVE8; } //180MHz
+#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
+#define READ_DELAY { RD_ACTIVE16;}
+#elif defined(STM32F767xx)
+#warning 216MHz
+#define WRITE_DELAY { WR_ACTIVE8; WR_ACTIVE8; } //216MHz
+#define IDLE_DELAY { WR_IDLE4;WR_IDLE4; }
+#define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE16;}
+#elif defined(STM32H743xx) //STM32H743 GPIO needs testing
+#define WRITE_DELAY { WR_ACTIVE8;WR_ACTIVE2; } //F_CPU=400MHz
+#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
+#define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE4;}
+#else
+#error check specific STM32
+#endif
+#elif defined(__ARM_ARCH_7M__) // -O2: F103@72MHz = 2.68s
+#define WRITE_DELAY { }
+#define READ_DELAY { RD_ACTIVE; }
+#elif defined(__ARM_ARCH_6M__) // -O2: F072@48MHz = 5.03s
+#define WRITE_DELAY { }
+#define READ_DELAY { }
+#endif
+
+#ifndef IDLE_DELAY
+#define IDLE_DELAY { WR_IDLE; }
+#endif
+
+#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE2; RD_IDLE; } // read 250ns after RD_ACTIVE goes low
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define CTL_INIT() { RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; }
+#define WriteCmd(x) { CD_COMMAND; write16(x); CD_DATA; }
+#define WriteData(x) { write16(x); }
+
+#endif //!USE_SERIAL
+#endif //MCUFRIEND_KEIL_H_
+
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MCUFRIEND_kbv/utility/mcufriend_mbed.h Wed Apr 21 14:54:37 2021 +0000
@@ -0,0 +1,101 @@
+#ifndef MCUFRIEND_MBED_H_
+#define MCUFRIEND_MBED_H_
+
+#include <mbed.h>
+
+#if defined(USE_SERIAL)
+#include "mcufriend_keil_spi.h"
+#else
+
+BusOut digitalL(D0, D1, D2, D3, D4, D5, D6, D7);
+BusOut digitalH(D8, D9, D10, D11, D12, D13, NC, NC);
+BusOut analog(A0, A1, A2, A3, A4, A5, NC, NC);
+
+#include "pin_shield_1.h" //shield pin macros e.g. A2_PORT, PIN_OUTPUT()
+#include "pin_shield_8.h" //macros for write_8(), read_8(), setWriteDir(), ...
+
+// control pins as used in MCUFRIEND shields
+ #define RD_PORT A0_PORT
+ #define RD_PIN A0_PIN
+ #define WR_PORT A1_PORT
+ #define WR_PIN A1_PIN
+ #define CD_PORT A2_PORT
+ #define CD_PIN A2_PIN
+ #define CS_PORT A3_PORT
+ #define CS_PIN A3_PIN
+ #define RESET_PORT A4_PORT
+ #define RESET_PIN A4_PIN
+
+// general purpose pin macros
+ #define RD_ACTIVE PIN_LOW(RD_PORT, RD_PIN)
+ #define RD_IDLE PIN_HIGH(RD_PORT, RD_PIN)
+ #define RD_OUTPUT PIN_OUTPUT(RD_PORT, RD_PIN)
+ #define WR_ACTIVE PIN_LOW(WR_PORT, WR_PIN)
+ #define WR_IDLE PIN_HIGH(WR_PORT, WR_PIN)
+ #define WR_OUTPUT PIN_OUTPUT(WR_PORT, WR_PIN)
+ #define CD_COMMAND PIN_LOW(CD_PORT, CD_PIN)
+ #define CD_DATA PIN_HIGH(CD_PORT, CD_PIN)
+ #define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN)
+ #define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN)
+ #define CS_IDLE PIN_HIGH(CS_PORT, CS_PIN)
+ #define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN)
+ #define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN)
+ #define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN)
+ #define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN)
+
+#define WR_ACTIVE2 {WR_ACTIVE; WR_ACTIVE;}
+#define WR_ACTIVE4 {WR_ACTIVE2; WR_ACTIVE2;}
+#define WR_ACTIVE8 {WR_ACTIVE4; WR_ACTIVE4;}
+#define RD_ACTIVE2 {RD_ACTIVE; RD_ACTIVE;}
+#define RD_ACTIVE4 {RD_ACTIVE2; RD_ACTIVE2;}
+#define RD_ACTIVE8 {RD_ACTIVE4; RD_ACTIVE4;}
+#define RD_ACTIVE16 {RD_ACTIVE8; RD_ACTIVE8;}
+#define WR_IDLE2 {WR_IDLE; WR_IDLE;}
+#define WR_IDLE4 {WR_IDLE2; WR_IDLE2;}
+#define RD_IDLE2 {RD_IDLE; RD_IDLE;}
+#define RD_IDLE4 {RD_IDLE2; RD_IDLE2;}
+
+#if defined(__MK20DX128__) || defined(___MK20DX256__) // Teensy3.0 || 3.2 96MHz
+#define WRITE_DELAY { WR_ACTIVE2; }
+#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; }
+#elif defined(__MK64FX512__) || defined(TARGET_M4) // Teensy3.5 120MHz thanks to PeteJohno
+#define WRITE_DELAY { WR_ACTIVE4; }
+#define READ_DELAY { RD_ACTIVE8; }
+#elif defined(__MK66FX1M0__) || defined(TARGET_M4) // Teensy3.6 180MHz untested. delays can possibly be reduced.
+#define WRITE_DELAY { WR_ACTIVE8; }
+#define READ_DELAY { RD_ACTIVE8; RD_ACTIVE8; }
+#elif defined(TARGET_M7) // Nucleo-F767 216MHz untested. delays can possibly be reduced.
+#define WRITE_DELAY { WR_ACTIVE8; WR_ACTIVE2; }
+#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
+#define READ_DELAY { RD_ACTIVE16; RD_ACTIVE16; RD_ACTIVE4; }
+#define READ_IDLE { RD_IDLE2;RD_IDLE; }
+#else
+//#error unspecified delays
+//#define WRITE_DELAY { WR_ACTIVE2; }
+//#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; }
+#define WRITE_DELAY
+#define READ_DELAY
+#endif
+
+#if !defined(IDLE_DELAY)
+#define IDLE_DELAY WR_IDLE
+#endif
+#if !defined(READ_IDLE)
+#define READ_IDLE RD_IDLE
+#endif
+
+// General macros. IOCLR registers are 1 cycle when optimised.
+#define WR_STROBE { WR_ACTIVE; WR_IDLE; } //PWLW=TWRL=50ns
+#define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE //PWLR=TRDL=150ns
+#define write8(d) { write_8(d); WRITE_DELAY; WR_STROBE; IDLE_DELAY; } // STROBEs are defined later
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); READ_IDLE; } // read 250ns after RD_ACTIVE goes low
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define CTL_INIT() { RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; }
+#define WriteCmd(x) { CD_COMMAND; write16(x); CD_DATA; }
+#define WriteData(x) { write16(x); }
+
+#endif //!USE_SERIAL
+#endif //MCUFRIEND_KEIL_H_
+
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MCUFRIEND_kbv/utility/mcufriend_serial.h Wed Apr 21 14:54:37 2021 +0000
@@ -0,0 +1,244 @@
+#if ARDUINO >= 165
+#include <SPI.h>
+#endif
+
+#if 0
+#elif defined(__AVR_ATmega328P__)
+
+#define SPI_INIT() { DDRB |= (1<<5)|(1<<3)|(1<<2); SPCR = (1<<SPE)|(1<<MSTR); SPSR = (1<<SPI2X); SPSR; SPDR; }
+static inline uint8_t spi_xfer(uint8_t c)
+{
+ SPDR = c;
+ while ((SPSR & (1<<SPIF)) == 0) ;
+ return SPDR;
+}
+extern uint8_t running;
+static inline void write8(uint8_t x) {
+ if (running) {
+ while ((SPSR & 0x80) == 0);
+ SPDR;
+ }
+ SPDR = x;
+ running = 1;
+ }
+static inline uint8_t read8(void) {
+ if (running) while ((SPSR & 0x80) == 0);
+ running = 0;
+ return SPDR;
+ }
+static inline uint8_t xchg8(uint8_t x) { write8(x); return read8(); }
+static inline void flush(void) {
+ if (running) {
+ while ((SPSR & 0x80) == 0);
+ }
+ running = 0;
+ SPDR;
+ }
+
+#if defined(SUPPORT_8347D)
+#warning using HX8347D hardware
+#define CD_PORT PORTD
+#define CD_PIN PD7
+#define CS_PORT PORTB
+#define CS_PIN PB2
+#define RESET_PORT PORTB
+#define RESET_PIN PB1
+#define SD_PIN PD5
+#define XPT_PIN PD4
+#define RD_IDLE
+#define WR_IDLE
+#else
+#warning using regular SPI hardware
+#define CD_PORT PORTB
+#define CD_PIN 1
+#define CS_PORT PORTB
+#define CS_PIN 2
+#define RESET_PORT PORTB
+#define RESET_PIN 0
+#define RD_IDLE
+#define WR_IDLE
+#endif
+
+#define setWriteDir() { }
+#define setReadDir() { }
+//#define write8(x) spi_xfer(x)
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { dst = xchg8(0); }
+#define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); }
+
+#define PIN_LOW(p, b) (p) &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p) |= (1<<(b))
+#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
+#elif defined(__SAMD21G18A__)
+
+#define SPI_INIT() { SPI.begin(); SPI.setDataMode(SPI_MODE0); SPI.setClockDivider(6); }
+
+#define CD_PORT PORT->Group[0]
+#define CD_PIN 7
+#define CS_PORT PORT->Group[0]
+#define CS_PIN 18
+#define RESET_PORT PORT->Group[0]
+#define RESET_PIN 6
+#define RD_IDLE
+#define WR_IDLE
+
+
+uint8_t running;
+static inline void write8(uint8_t c)
+{
+ running = 1;
+ while( SERCOM1->SPI.INTFLAG.bit.DRE == 0) ;
+ SERCOM1->SPI.DATA.bit.DATA = c; // Writing data into Data register
+}
+
+static inline void flush(void)
+{
+ if (running) while( SERCOM1->SPI.INTFLAG.bit.TXC == 0) ;
+ running = 0;
+}
+
+static inline uint8_t xchg8(uint8_t c)
+{
+// flush();
+ while( SERCOM1->SPI.INTFLAG.bit.RXC != 0) SERCOM1->SPI.DATA.bit.DATA; //eat up
+ while( SERCOM1->SPI.INTFLAG.bit.DRE == 0) ;
+ SERCOM1->SPI.DATA.bit.DATA = c; // Writing data into Data register
+ while( SERCOM1->SPI.INTFLAG.bit.RXC == 0) ;
+ return SERCOM1->SPI.DATA.bit.DATA;
+}
+
+
+#define setWriteDir() { }
+#define setReadDir() { }
+//#define flush()
+//#define write8(x) xchg8(x)
+//#define xchg8(x) SPI.transfer(x)
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { dst = xchg8(0); }
+#define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); }
+
+// Shield Control macros.
+#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
+#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
+
+#elif defined(__AVR_ATxmega128A1__) //3.49s @ 32MHz -O2
+ #define CD_PORT VPORT2
+ #define CD_PIN 1
+ #define CS_PORT VPORT3
+ #define CS_PIN 4
+ #define RESET_PORT VPORT2
+ #define RESET_PIN 0
+#define SPCRVAL (USART_CLK2X_bm | USART_RXEN_bm | USART_TXEN_bm)
+#define SETDDR {VPORT3.DIR |= (1<<4)|(1<<5)|(1<<7); VPORT2.DIR |= 0x03; }
+#define SPI_INIT() { PORTCFG.VPCTRLB=PORTCFG_VP3MAP_PORTF_gc | PORTCFG_VP2MAP_PORTC_gc; CS_IDLE; RESET_IDLE; SETDDR; spi_init(); }
+
+void spi_init(void)
+{
+ SPIF.CTRL=SPI_ENABLE_bm | SPI_MODE_3_gc | (1<<SPI_MASTER_bp) | (1<<SPI_CLK2X_bp);
+}
+
+#define write8(x) {\
+ SPIF.DATA=x;\
+ while ((SPIF.STATUS & SPI_IF_bm)==0);\
+ SPIF.DATA;\
+ }
+#define flush() {\
+ }
+
+#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
+#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
+
+#elif defined(__AVR_ATxmega32A4U__) //3.49s @ 32MHz -O2.
+// 100ns/150ns for ILI9341 W/R cycle. 100ns/200ns for ILI920. 20ns/150ns HX8347
+// Xmega @ 60MHz i.e. 30MHz SCK works with 9341.
+#warning Using ATxmega32A4U USART_MSPI
+ #define CD_PORT VPORT2
+ #define CD_PIN 1
+ #define CS_PORT VPORT3
+ #define CS_PIN 0
+ #define RESET_PORT VPORT2
+ #define RESET_PIN 0
+ #define SD_PORT PORTC
+ #define SD_PIN 4
+#define SPCRVAL (USART_CLK2X_bm | USART_RXEN_bm | USART_TXEN_bm)
+#define SETDDR {PORTCFG.VPCTRLB=PORTCFG_VP13MAP_PORTD_gc | PORTCFG_VP02MAP_PORTC_gc; VPORT3.DIR |= (1<<0)|(1<<1)|(1<<3); VPORT2.DIR |= 0x03; PIN_HIGH(SD_PORT, SD_PIN); SD_PORT.DIR |= (1<<SD_PIN); }
+#define SPI_INIT() { CS_IDLE; RESET_IDLE; SETDDR; spi_init(); }
+
+static inline void spi_init(void)
+{
+ USARTD0.CTRLB = SPCRVAL;
+ USARTD0.CTRLC = USART_CMODE_MSPI_gc | 0x00 | 0x00; //mode #0
+// PORTD.PIN1CTRL |= PORT_INVEN_bm; //CPOL
+ USARTD0.BAUDCTRLA = 0x00; //F_CPU/2
+ USARTD0.BAUDCTRLB = ((0x00 << USART_BSCALE_gp) & USART_BSCALE_gm) | 0x00;
+ USARTD0.DATA;
+}
+
+extern uint8_t running;
+
+#define write8(x) {\
+ while ((USARTD0.STATUS & USART_DREIF_bm) == 0) ;\
+ asm("cli");\
+ USARTD0.DATA = x;\
+ USARTD0.STATUS = USART_TXCIF_bm;\
+ asm("sei");\
+ running = 1;\
+ }
+static inline uint8_t read8(void) {
+ if (running) while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;
+ return USARTD0.DATA;
+ }
+#define flush() {\
+ if (running) while ((USARTD0.STATUS & USART_TXCIF_bm) == 0) ;\
+ while ((USARTD0.STATUS & USART_RXCIF_bm) != 0) USARTD0.DATA;\
+ running = 0;\
+ }
+static inline uint8_t xchg8(uint8_t x) {
+ USARTD0.DATA = x;
+ while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;
+ return USARTD0.DATA;
+ }
+/*
+#define write8(x) {\
+ while ((USARTD0.STATUS & USART_DREIF_bm) == 0) ;\
+ USARTD0.DATA = x;\
+ while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;\
+ USARTD0.DATA;\
+ }
+#define flush()
+*/
+
+#define RD_IDLE
+#define WR_IDLE
+//#define SPI_INIT() spi_init()
+#define setWriteDir() { }
+#define setReadDir() { }
+//#define write8(x) spi_xfer(x)
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { dst = xchg8(0); }
+#define READ_16(dst) { dst = xchg8(0); dst = (dst << 8) | xchg8(0); }
+
+#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
+#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
+
+#endif
+
+#define CD_COMMAND {flush(); PIN_LOW(CD_PORT, CD_PIN); }
+#define CD_DATA {flush(); PIN_HIGH(CD_PORT, CD_PIN); }
+#define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN)
+#define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN)
+#define CS_IDLE {flush(); PIN_HIGH(CS_PORT, CS_PIN); }
+#define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN)
+#define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN)
+#define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN)
+#define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN)
+
+// General macros. IOCLR registers are 1 cycle when optimised.
+
+#define CTL_INIT() { CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; SPI_INIT(); }
+#define WriteCmd(x) { CD_COMMAND; write8(x); }
+#define WriteData(x) { CD_DATA; write16(x); }
+
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MCUFRIEND_kbv/utility/mcufriend_shield.h Wed Apr 21 14:54:37 2021 +0000
@@ -0,0 +1,966 @@
+//#define USE_SPECIAL //check for custom drivers
+
+#define WR_ACTIVE2 {WR_ACTIVE; WR_ACTIVE;}
+#define WR_ACTIVE4 {WR_ACTIVE2; WR_ACTIVE2;}
+#define WR_ACTIVE8 {WR_ACTIVE4; WR_ACTIVE4;}
+#define RD_ACTIVE2 {RD_ACTIVE; RD_ACTIVE;}
+#define RD_ACTIVE4 {RD_ACTIVE2; RD_ACTIVE2;}
+#define RD_ACTIVE8 {RD_ACTIVE4; RD_ACTIVE4;}
+#define RD_ACTIVE16 {RD_ACTIVE8; RD_ACTIVE8;}
+#define WR_IDLE2 {WR_IDLE; WR_IDLE;}
+#define WR_IDLE4 {WR_IDLE2; WR_IDLE2;}
+#define RD_IDLE2 {RD_IDLE; RD_IDLE;}
+#define RD_IDLE4 {RD_IDLE2; RD_IDLE2;}
+
+#if defined(USE_SPECIAL)
+#include "mcufriend_special.h"
+#if !defined(USE_SPECIAL_FAIL)
+#warning WE ARE USING A SPECIAL CUSTOM DRIVER
+#endif
+#endif
+#if !defined(USE_SPECIAL) || defined (USE_SPECIAL_FAIL)
+
+#if 0
+//################################### UNO ##############################
+#elif defined(__AVR_ATmega328P__) || defined(__AVR_ATmega328PB__) //regular UNO shield on UNO
+#define RD_PORT PORTC
+#define RD_PIN 0
+#define WR_PORT PORTC
+#define WR_PIN 1
+#define CD_PORT PORTC
+#define CD_PIN 2
+#define CS_PORT PORTC
+#define CS_PIN 3
+#define RESET_PORT PORTC
+#define RESET_PIN 4
+
+#define BMASK 0x03 //more intuitive style for mixed Ports
+#define DMASK 0xFC //does exactly the same as previous
+#define write_8(x) { PORTB = (PORTB & ~BMASK) | ((x) & BMASK); PORTD = (PORTD & ~DMASK) | ((x) & DMASK); }
+#define read_8() ( (PINB & BMASK) | (PIND & DMASK) )
+#define setWriteDir() { DDRB |= BMASK; DDRD |= DMASK; }
+#define setReadDir() { DDRB &= ~BMASK; DDRD &= ~DMASK; }
+#define write8(x) { write_8(x); WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (p) &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p) |= (1<<(b))
+#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
+
+//################################### MEGA2560 ##############################
+#elif defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1280__) //regular UNO shield on MEGA2560
+#define RD_PORT PORTF
+#define RD_PIN 0
+#define WR_PORT PORTF
+#define WR_PIN 1
+#define CD_PORT PORTF
+#define CD_PIN 2
+#define CS_PORT PORTF
+#define CS_PIN 3
+#define RESET_PORT PORTF
+#define RESET_PIN 4
+
+#define EMASK 0x38
+#define GMASK 0x20
+#define HMASK 0x78
+#define write_8(x) { PORTH &= ~HMASK; PORTG &= ~GMASK; PORTE &= ~EMASK; \
+ PORTH |= (((x) & (3<<0)) << 5); \
+ PORTE |= (((x) & (3<<2)) << 2); \
+ PORTG |= (((x) & (1<<4)) << 1); \
+ PORTE |= (((x) & (1<<5)) >> 2); \
+ PORTH |= (((x) & (3<<6)) >> 3); \
+ }
+
+#define read_8() ( ((PINH & (3<<5)) >> 5)\
+ | ((PINE & (3<<4)) >> 2)\
+ | ((PING & (1<<5)) >> 1)\
+ | ((PINE & (1<<3)) << 2)\
+ | ((PINH & (3<<3)) << 3)\
+ )
+#define setWriteDir() { DDRH |= HMASK; DDRG |= GMASK; DDRE |= EMASK; }
+#define setReadDir() { DDRH &= ~HMASK; DDRG &= ~GMASK; DDRE &= ~EMASK; }
+#define write8(x) { write_8(x); WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (p) &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p) |= (1<<(b))
+#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
+
+//################################### MEGA4809 NANO_EVERY 4808 ##############################
+#elif defined(__AVR_ATmega4808__) // Thinary EVERY-4808 with Nano-Shield_Adapter
+#warning EVERY-4808 with Nano-Shield_Adapter
+#define RD_PORT VPORTD //
+#define RD_PIN 0
+#define WR_PORT VPORTD
+#define WR_PIN 1
+#define CD_PORT VPORTD
+#define CD_PIN 2
+#define CS_PORT VPORTD
+#define CS_PIN 3
+#define RESET_PORT VPORTF
+#define RESET_PIN 2
+
+#define AMASK 0xFF
+#define write_8(x) { VPORTA.OUT = ((x) << 6) | ((x) >> 2); }
+#define read_8() ( (VPORTA.IN >> 6) | (VPORTA.IN << 2) )
+#define setWriteDir() { VPORTA_DIR |= AMASK; }
+#define setReadDir() { VPORTA_DIR &= ~AMASK; }
+
+//#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; } //6.47s no_inline
+#define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=5.43s @20MHz always_inline. (-O1=5.41s, -O3=5.25s)
+#define READ_DELAY { RD_ACTIVE4; } //ID=0x7789
+#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
+#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
+
+//################################### MEGA4809 NANO_EVERY ##############################
+#elif defined(__AVR_ATmega4809__) && defined(ARDUINO_AVR_NANO_EVERY) // EVERY-4809 with Nano-Shield_Adapter
+#warning EVERY-4809 with Nano-Shield_Adapter using VPORT.OUT and BLD/BST
+#define RD_PORT VPORTD //
+#define RD_PIN 3
+#define WR_PORT VPORTD
+#define WR_PIN 2
+#define CD_PORT VPORTD
+#define CD_PIN 1
+#define CS_PORT VPORTD
+#define CS_PIN 0
+#define RESET_PORT VPORTF
+#define RESET_PIN 2
+
+#define AMASK (3<<0)
+#define BMASK (5<<0)
+#define CMASK (1<<6)
+#define EMASK (1<<3)
+#define FMASK (3<<4)
+static __attribute((always_inline))
+void write_8(uint8_t val)
+{
+ asm volatile("in __tmp_reg__,0x01" "\n\t" //VPORTA.OUT
+ "BST %0,2" "\n\t" "BLD __tmp_reg__,0" "\n\t"
+ "BST %0,7" "\n\t" "BLD __tmp_reg__,1" "\n\t"
+ "out 0x01,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x05" "\n\t" //VPORTB.OUT
+ "BST %0,1" "\n\t" "BLD __tmp_reg__,0" "\n\t"
+ "BST %0,5" "\n\t" "BLD __tmp_reg__,2" "\n\t"
+ "out 0x05,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x09" "\n\t" //VPORTC.OUT
+ "BST %0,4" "\n\t" "BLD __tmp_reg__,6" "\n\t"
+ "out 0x09,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x11" "\n\t" //VPORTE.OUT
+ "BST %0,0" "\n\t" "BLD __tmp_reg__,3" "\n\t"
+ "out 0x11,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x15" "\n\t" //VPORTF.OUT
+ "BST %0,3" "\n\t" "BLD __tmp_reg__,5" "\n\t"
+ "BST %0,6" "\n\t" "BLD __tmp_reg__,4" "\n\t"
+ "out 0x15,__tmp_reg__" : : "a" (val));
+}
+
+#define read_8() ( 0 \
+ | ((VPORTA_IN & (1<<0)) << 2)\
+ | ((VPORTA_IN & (1<<1)) << 6)\
+ | ((VPORTB_IN & (1<<0)) << 1)\
+ | ((VPORTB_IN & (1<<2)) << 3)\
+ | ((VPORTC_IN & CMASK) >> 2)\
+ | ((VPORTE_IN & EMASK) >> 3)\
+ | ((VPORTF_IN & (1<<5)) >> 2)\
+ | ((VPORTF_IN & (1<<4)) << 2)\
+ )
+#define setWriteDir() { VPORTA_DIR |= AMASK; VPORTB_DIR |= BMASK; VPORTC_DIR |= CMASK; VPORTE_DIR |= EMASK; VPORTF_DIR |= FMASK; }
+#define setReadDir() { VPORTA_DIR &= ~AMASK; VPORTB_DIR &= ~BMASK; VPORTC_DIR &= ~CMASK; VPORTE_DIR &= ~EMASK; VPORTF_DIR &= ~FMASK; }
+
+//#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; } //6.47s no_inline
+#define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=5.43s @20MHz always_inline. (-O1=5.41s, -O3=5.25s)
+#define READ_DELAY { RD_ACTIVE4; } //ID=0x7789
+#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
+#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
+
+//################################### TEENSY++2.0 ##############################
+#elif defined(__AVR_AT90USB1286__) //regular UNO shield on TEENSY++ 2.0 thanks tysonlt
+
+//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST|
+//AVR pin |PD7|PD6|PD5|PD4|PD3|PD2|PE1|PE0| |PF0|PF1|PF2|PF3|PF4|
+
+#define RD_PORT PORTF
+#define RD_PIN 0
+#define WR_PORT PORTF
+#define WR_PIN 1
+#define CD_PORT PORTF
+#define CD_PIN 2
+#define CS_PORT PORTF
+#define CS_PIN 3
+#define RESET_PORT PORTF
+#define RESET_PIN 4
+
+#define EMASK 0x03 //more intuitive style for mixed Ports
+#define DMASK 0xFC //does exactly the same as previous
+#define write_8(x) { PORTE = (PORTE & ~EMASK) | ((x) & EMASK); PORTD = (PORTD & ~DMASK) | ((x) & DMASK); }
+#define read_8() ( (PINE & EMASK) | (PIND & DMASK) )
+#define setWriteDir() { DDRE |= EMASK; DDRD |= DMASK; }
+#define setReadDir() { DDRE &= ~EMASK; DDRD &= ~DMASK; }
+#define write8(x) { write_8(x); WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (p) &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p) |= (1<<(b))
+#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
+
+//################################# ZERO and M0_PRO ############################
+#elif defined(__SAMD21G18A__) //regular UNO shield on ZERO or M0_PRO
+#include "sam.h"
+ // configure macros for the control pins
+#define RD_PORT PORT->Group[0]
+#define RD_PIN 2
+#define WR_PORT PORT->Group[1]
+#define WR_PIN 8
+#define CD_PORT PORT->Group[1]
+#define CD_PIN 9
+#define CS_PORT PORT->Group[0]
+#define CS_PIN 4
+#define RESET_PORT PORT->Group[0]
+#define RESET_PIN 5
+ // configure macros for data bus
+#define DMASK 0x0030C3C0
+ // #define write_8(x) PORT->Group[0].OUT.reg = (PORT->Group[0].OUT.reg & ~DMASK)|(((x) & 0x0F) << 6)|(((x) & 0x30) << 10)|(((x) & 0xC0)<<14)
+#if defined(ARDUINO_SAMD_ZERO) || defined(ARDUINO_SAMD_ZERO) // American ZERO
+#define write_8(x) {\
+ PORT->Group[0].OUTCLR.reg = DMASK;\
+ PORT->Group[0].OUTSET.reg = (((x) & 0x0B) << 6)\
+ |(((x) & (1<<2)) << 12)\
+ |(((x) & (1<<4)) << 4)\
+ |(((x) & (1<<5)) << 10)\
+ |(((x) & 0xC0) << 14);\
+ }
+#define read_8() (((PORT->Group[0].IN.reg >> 6) & 0x0B)\
+ |((PORT->Group[0].IN.reg >> 12) & (1<<2))\
+ |((PORT->Group[0].IN.reg >> 4) & (1<<4))\
+ |((PORT->Group[0].IN.reg >> 10) & (1<<5))\
+ |((PORT->Group[0].IN.reg >> 14) & 0xC0))
+#else //default to an M0_PRO on v1.6.5 or 1.7.6
+#define write_8(x) {\
+ PORT->Group[0].OUTCLR.reg = DMASK;\
+ PORT->Group[0].OUTSET.reg = (((x) & 0x0F) << 6)\
+ |(((x) & 0x30) << 10)\
+ |(((x) & 0xC0) << 14);\
+ }
+#define read_8() (((PORT->Group[0].IN.reg >> 6) & 0x0F)|((PORT->Group[0].IN.reg >> 10) & 0x30)|((PORT->Group[0].IN.reg >> 14) & 0xC0))
+#endif
+#define setWriteDir() { PORT->Group[0].DIRSET.reg = DMASK; \
+ PORT->Group[0].WRCONFIG.reg = (DMASK & 0xFFFF) | (0<<22) | (1<<28) | (1<<30); \
+ PORT->Group[0].WRCONFIG.reg = (DMASK>>16) | (0<<22) | (1<<28) | (1<<30) | (1<<31); \
+ }
+#define setReadDir() { PORT->Group[0].DIRCLR.reg = DMASK; \
+ PORT->Group[0].WRCONFIG.reg = (DMASK & 0xFFFF) | (1<<17) | (1<<28) | (1<<30); \
+ PORT->Group[0].WRCONFIG.reg = (DMASK>>16) | (1<<17) | (1<<28) | (1<<30) | (1<<31); \
+ }
+#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+ // Shield Control macros.
+#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
+#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
+
+//####################################### DUE ############################
+#elif defined(__SAM3X8E__) //regular UNO shield on DUE
+#define WRITE_DELAY { WR_ACTIVE; }
+#define IDLE_DELAY { WR_IDLE; }
+#define READ_DELAY { RD_ACTIVE;}
+ // configure macros for the control pins
+#define RD_PORT PIOA
+#define RD_PIN 16
+#define WR_PORT PIOA
+#define WR_PIN 24
+#define CD_PORT PIOA
+#define CD_PIN 23
+#define CS_PORT PIOA
+#define CS_PIN 22
+#define RESET_PORT PIOA
+#define RESET_PIN 6
+ // configure macros for data bus
+#define BMASK (1<<25)
+#define CMASK (0xBF << 21)
+#define write_8(x) { PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; \
+ PIOB->PIO_SODR = (((x) & (1<<2)) << 23); \
+ PIOC->PIO_SODR = (((x) & (1<<0)) << 22) \
+ | (((x) & (1<<1)) << 20) \
+ | (((x) & (1<<3)) << 25) \
+ | (((x) & (1<<4)) << 22) \
+ | (((x) & (1<<5)) << 20) \
+ | (((x) & (1<<6)) << 18) \
+ | (((x) & (1<<7)) << 16); \
+ }
+
+#define read_8() ( ((PIOC->PIO_PDSR & (1<<22)) >> 22)\
+ | ((PIOC->PIO_PDSR & (1<<21)) >> 20)\
+ | ((PIOB->PIO_PDSR & (1<<25)) >> 23)\
+ | ((PIOC->PIO_PDSR & (1<<28)) >> 25)\
+ | ((PIOC->PIO_PDSR & (1<<26)) >> 22)\
+ | ((PIOC->PIO_PDSR & (1<<25)) >> 20)\
+ | ((PIOC->PIO_PDSR & (1<<24)) >> 18)\
+ | ((PIOC->PIO_PDSR & (1<<23)) >> 16)\
+ )
+#define setWriteDir() { PIOB->PIO_OER = BMASK; PIOC->PIO_OER = CMASK; }
+#define setReadDir() { \
+ PMC->PMC_PCER0 = (1 << ID_PIOB)|(1 << ID_PIOC);\
+ PIOB->PIO_ODR = BMASK; PIOC->PIO_ODR = CMASK;\
+ }
+#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+ // Shield Control macros.
+#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
+#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
+
+//################################### LEONARDO ##############################
+#elif defined(__AVR_ATmega32U4__) //regular UNO shield on Leonardo
+#define RD_PORT PORTF
+#define RD_PIN 7
+#define WR_PORT PORTF
+#define WR_PIN 6
+#define CD_PORT PORTF
+#define CD_PIN 5
+#define CS_PORT PORTF
+#define CS_PIN 4
+#define RESET_PORT PORTF
+#define RESET_PIN 1
+
+#define BMASK (3<<4)
+#define CMASK (1<<6)
+#define DMASK ((1<<7)|(1<<4)|(3<<0))
+#define EMASK (1<<6)
+static inline //hope we use r24
+void write_8(uint8_t x)
+{
+ PORTB &= ~BMASK;
+ PORTC &= ~CMASK;
+ PORTD &= ~DMASK;
+ PORTE &= ~EMASK;
+ PORTB |= (((x) & (3 << 0)) << 4);
+ PORTD |= (((x) & (1 << 2)) >> 1);
+ PORTD |= (((x) & (1 << 3)) >> 3);
+ PORTD |= (((x) & (1 << 4)) << 0);
+ PORTC |= (((x) & (1 << 5)) << 1);
+ PORTD |= (((x) & (1 << 6)) << 1);
+ PORTE |= (((x) & (1 << 7)) >> 1);
+}
+
+#define read_8() ( ((PINB & (3<<4)) >> 4)\
+| ((PIND & (1<<1)) << 1)\
+| ((PIND & (1<<0)) << 3)\
+| ((PIND & (1<<4)) >> 0)\
+| ((PINC & (1<<6)) >> 1)\
+| ((PIND & (1<<7)) >> 1)\
+| ((PINE & (1<<6)) << 1)\
+)
+#define setWriteDir() { DDRB |= BMASK; DDRC |= CMASK; DDRD |= DMASK; DDRE |= EMASK; }
+#define setReadDir() { DDRB &= ~BMASK; DDRC &= ~CMASK; DDRD &= ~DMASK; DDRE &= ~EMASK; }
+#define write8(x) { write_8(x); WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (p) &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p) |= (1<<(b))
+#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
+
+//################################### UNO SHIELD on BOBUINO ##############################
+#elif defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega644P__) //UNO shield on BOBUINO
+#warning regular UNO shield on BOBUINO
+
+//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST|
+//AVR pin |PB3|PB2|PB1|PB0|PD3|PD2|PD6|PD5| |PA7|PA6|PA5|PA4|PA3|
+
+#define RD_PORT PORTA
+#define RD_PIN 7
+#define WR_PORT PORTA
+#define WR_PIN 6
+#define CD_PORT PORTA
+#define CD_PIN 5
+#define CS_PORT PORTA
+#define CS_PIN 4
+#define RESET_PORT PORTA
+#define RESET_PIN 3
+
+#define BMASK 0x0F //
+#define DMASK 0x6C //
+#define write_8(x) { PORTB = (PORTB & ~BMASK) | ((x) >> 4); \
+ PORTD = (PORTD & ~DMASK) | ((x) & 0x0C) | (((x) & 0x03) << 5); }
+#define read_8() ( (PINB << 4) | (PIND & 0x0C) | ((PIND & 0x60) >> 5) )
+#define setWriteDir() { DDRB |= BMASK; DDRD |= DMASK; }
+#define setReadDir() { DDRB &= ~BMASK; DDRD &= ~DMASK; }
+#define write8(x) { write_8(x); WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (p) &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p) |= (1<<(b))
+#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
+
+//####################################### TEENSY ############################
+#elif defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MK64FX512__) || defined(__MK66FX1M0__) // regular UNO shield on a Teensy 3.x
+#warning regular UNO shield on a Teensy 3.x
+
+//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST|
+//MK20 pin |PD2|PD4|PD7|PA13|PA12|PD2|PC3|PD3| |PD1|PC0|PB0|PB1|PB3|
+
+#if defined(__MK20DX128__) || defined(__MK20DX256__) // Teensy3.0 || 3.2 96MHz
+#define WRITE_DELAY { WR_ACTIVE2; }
+#define READ_DELAY { RD_ACTIVE8; RD_ACTIVE; }
+#elif defined(__MK64FX512__) // Teensy3.5 120MHz thanks to PeteJohno
+#define WRITE_DELAY { WR_ACTIVE4; }
+#define READ_DELAY { RD_ACTIVE8; }
+#elif defined(__MK66FX1M0__) // Teensy3.6 180MHz untested. delays can possibly be reduced.
+#define WRITE_DELAY { WR_ACTIVE8; }
+#define READ_DELAY { RD_ACTIVE16; }
+#else
+#error unspecified delays
+#endif
+
+#define RD_PORT GPIOD
+#define RD_PIN 1
+#define WR_PORT GPIOC
+#define WR_PIN 0
+#define CD_PORT GPIOB
+#define CD_PIN 0
+#define CS_PORT GPIOB
+#define CS_PIN 1
+#define RESET_PORT GPIOB
+#define RESET_PIN 3
+
+// configure macros for the data pins
+#define AMASK ((1<<12)|(1<<13))
+#define CMASK ((1<<3))
+#define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<7))
+
+#define write_8(d) { \
+ GPIOA_PCOR = AMASK; GPIOC_PCOR = CMASK; GPIOD_PCOR = DMASK; \
+ GPIOA_PSOR = (((d) & (1 << 3)) << 9) \
+ | (((d) & (1 << 4)) << 9); \
+ GPIOC_PSOR = (((d) & (1 << 1)) << 2); \
+ GPIOD_PSOR = (((d) & (1 << 0)) << 3) \
+ | (((d) & (1 << 2)) >> 2) \
+ | (((d) & (1 << 5)) << 2) \
+ | (((d) & (1 << 6)) >> 2) \
+ | (((d) & (1 << 7)) >> 5); \
+ }
+#define read_8() ((((GPIOD_PDIR & (1<<3)) >> 3) \
+ | ((GPIOC_PDIR & (1 << 3)) >> 2) \
+ | ((GPIOD_PDIR & (1 << 0)) << 2) \
+ | ((GPIOA_PDIR & (1 << 12)) >> 9) \
+ | ((GPIOA_PDIR & (1 << 13)) >> 9) \
+ | ((GPIOD_PDIR & (1 << 7)) >> 2) \
+ | ((GPIOD_PDIR & (1 << 4)) << 2) \
+ | ((GPIOD_PDIR & (1 << 2)) << 5)))
+#define setWriteDir() {GPIOA_PDDR |= AMASK;GPIOC_PDDR |= CMASK;GPIOD_PDDR |= DMASK; }
+#define setReadDir() {GPIOA_PDDR &= ~AMASK;GPIOC_PDDR &= ~CMASK;GPIOD_PDDR &= ~DMASK; }
+#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; } //PJ adjusted
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; } //PJ adjusted
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+//#define GPIO_INIT() {SIM_SCGC5 |= 0x3E00;} //PORTA-PORTE
+#define GPIO_INIT() {for (int i = 2; i <= 9; i++) pinMode(i, OUTPUT); for (int i = A0; i <= A4; i++) pinMode(i, OUTPUT);}
+
+#define PASTE(x, y) x ## y
+
+#define PIN_LOW(port, pin) PASTE(port, _PCOR) = (1<<(pin))
+#define PIN_HIGH(port, pin) PASTE(port, _PSOR) = (1<<(pin))
+#define PIN_OUTPUT(port, pin) PASTE(port, _PDDR) |= (1<<(pin))
+
+//####################################### STM32 ############################
+// NUCLEO: ARDUINO_NUCLEO_xxxx from ST Core or ARDUINO_STM_NUCLEO_F103RB from MapleCore
+// BLUEPILL: ARDUINO_NUCLEO_F103C8 / ARDUINO_BLUEPILL_F103C8 from ST Core or ARDUINO_GENERIC_STM32F103C from MapleCore
+// MAPLE_REV3: n/a from ST Core or ARDUINO_MAPLE_REV3 from MapleCore
+// ST Core: ARDUINO_ARCH_STM32
+// MapleCore: __STM32F1__
+#elif defined(__STM32F1__) || defined(ARDUINO_ARCH_STM32) //MapleCore or ST Core
+#define IS_NUCLEO64 ( defined(ARDUINO_STM_NUCLEO_F103RB) \
+ || defined(ARDUINO_NUCLEO_F030R8) || defined(ARDUINO_NUCLEO_F091RC) \
+ || defined(ARDUINO_NUCLEO_F103RB) || defined(ARDUINO_NUCLEO_F303RE) \
+ || defined(ARDUINO_NUCLEO_F401RE) || defined(ARDUINO_NUCLEO_F411RE) \
+ || defined(ARDUINO_NUCLEO_F446RE) || defined(ARDUINO_NUCLEO_L053R8) \
+ || defined(ARDUINO_NUCLEO_L152RE) || defined(ARDUINO_NUCLEO_L476RG) \
+ || defined(ARDUINO_NUCLEO_F072RB) \
+ )
+#define IS_NUCLEO144 ( defined(ARDUINO_NUCLEO_F207ZG) \
+ || defined(ARDUINO_NUCLEO_F429ZI) || defined(ARDUINO_NUCLEO_F767ZI) \
+ || defined(ARDUINO_NUCLEO_L496ZG) || defined(ARDUINO_NUCLEO_L496ZG_P) \
+ || defined(ARDUINO_NUCLEO_H743ZI) \
+ )
+// F1xx, F4xx, L4xx have different registers and styles. General Macros
+#if defined(__STM32F1__) //weird Maple Core
+#define REGS(x) regs->x
+#else //regular ST Core
+#define REGS(x) x
+#endif
+#define PIN_HIGH(port, pin) (port)-> REGS(BSRR) = (1<<(pin))
+#define PIN_LOW(port, pin) (port)-> REGS(BSRR) = (1<<((pin)+16))
+#define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1))
+#define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); }
+
+// Family specific Macros. F103 needs ST and Maple compatibility
+// note that ILI9320 class of controller has much slower Read cycles
+#if 0
+#elif defined(__STM32F1__) || defined(ARDUINO_NUCLEO_F103C8) || defined(ARDUINO_BLUEPILL_F103C8) || defined(ARDUINO_NUCLEO_F103RB)
+#define WRITE_DELAY { }
+#define READ_DELAY { RD_ACTIVE; }
+#if defined(__STM32F1__) //MapleCore crts.o does RCC. not understand regular syntax anyway
+#define GPIO_INIT()
+#else
+#define GPIO_INIT() { RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_AFIOEN; \
+ AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;}
+#endif
+#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
+#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
+#define PIN_OUTPUT(port, pin) {\
+ if (pin < 8) {GP_OUT(port, CRL, 0xF<<((pin)<<2));} \
+ else {GP_OUT(port, CRH, 0xF<<((pin&7)<<2));} \
+ }
+#define PIN_INPUT(port, pin) { \
+ if (pin < 8) { GP_INP(port, CRL, 0xF<<((pin)<<2)); } \
+ else { GP_INP(port, CRH, 0xF<<((pin&7)<<2)); } \
+ }
+
+// should be easy to add F030, F091, F303, L053, ...
+#elif defined(STM32F030x8)
+#define WRITE_DELAY { }
+#define READ_DELAY { RD_ACTIVE; }
+#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#elif defined(STM32F072xB)
+#define WRITE_DELAY { }
+#define READ_DELAY { RD_ACTIVE; }
+#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#elif defined(STM32F091xC)
+#define WRITE_DELAY { }
+#define READ_DELAY { RD_ACTIVE; }
+#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#elif defined(STM32F207xx)
+#warning DELAY macros untested yet
+#define WRITE_DELAY { WR_ACTIVE8; } //120MHz
+#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
+#define READ_DELAY { RD_ACTIVE16;}
+#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#elif defined(STM32F303xE)
+#define WRITE_DELAY { }
+#define READ_DELAY { RD_ACTIVE8; } //thanks MasterT
+#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; \
+ /* AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1; */ }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) //thanks fpiSTM
+
+#elif defined(STM32F401xE)
+#define WRITE_DELAY { WR_ACTIVE2; } //84MHz
+#define READ_DELAY { RD_ACTIVE4; }
+#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#elif defined(STM32F411xE)
+#define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //100MHz
+#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE2; }
+#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#elif defined(STM32F429xx)
+#warning DELAY macros untested yet
+#define WRITE_DELAY { WR_ACTIVE8; } //180MHz
+#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
+#define READ_DELAY { RD_ACTIVE16;}
+#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#elif defined(STM32F446xx)
+#define WRITE_DELAY { WR_ACTIVE8; } //180MHz
+#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
+#define READ_DELAY { RD_ACTIVE16;}
+#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#elif defined(STM32F767xx)
+#warning DELAY macros untested yet
+#define WRITE_DELAY { WR_ACTIVE8;WR_ACTIVE2; } //216MHz
+#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
+#define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE4;}
+#define GPIO_INIT() { RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#elif defined(STM32H743xx) // thanks MagicianT
+#warning STM32H743xx< DELAY macros untested yet
+#define WRITE_DELAY { WR_ACTIVE8;WR_ACTIVE2; } //F_CPU=400MHz
+#define IDLE_DELAY { WR_IDLE2;WR_IDLE; }
+#define READ_DELAY { RD_ACTIVE16;RD_ACTIVE16;RD_ACTIVE4;}
+#define GPIO_INIT() { RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN | RCC_AHB4ENR_GPIOCEN | RCC_AHB4ENR_GPIODEN | RCC_AHB4ENR_GPIOEEN | RCC_AHB4ENR_GPIOFEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#elif defined(STM32L053xx)
+#define WRITE_DELAY { } //32MHz M0+
+#define READ_DELAY { RD_ACTIVE; }
+#define GPIO_INIT() { RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | RCC_IOPENR_GPIOCEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#elif defined(STM32L152xE)
+#define WRITE_DELAY { } //32MHz M3
+#define READ_DELAY { RD_ACTIVE; }
+#define GPIO_INIT() { RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#elif defined(STM32L476xx)
+#define WRITE_DELAY { WR_ACTIVE2; } //80MHz
+#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; }
+#define GPIO_INIT() { RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#elif defined(STM32L496xx)
+#warning DELAY macros untested yet
+#define WRITE_DELAY { WR_ACTIVE2; } //80MHz
+#define READ_DELAY { RD_ACTIVE4; RD_ACTIVE; }
+#define GPIO_INIT() { RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOCEN | RCC_AHB2ENR_GPIODEN | RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOFEN; }
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+
+#else
+#error unsupported STM32
+#endif
+
+#if 0
+#elif defined(ARDUINO_GENERIC_STM32F103C) || defined(ARDUINO_NUCLEO_F103C8) || defined(ARDUINO_BLUEPILL_F103C8)
+#warning Uno Shield on BLUEPILL
+
+//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |SD_SS|SD_DI|SD_DO|SD_SCK|
+//STM32 pin |PA7|PA6|PA5|PA4|PA3|PA2|PA1|PA0| |PB0|PB6|PB7|PB8|PB9| |PA15 |PB5 |PB4 |PB3 | **ALT-SPI1**
+
+#define RD_PORT GPIOB
+//#define RD_PIN 5
+#define RD_PIN 0 //hardware mod to Adapter. Allows use of PB5 for SD Card
+#define WR_PORT GPIOB
+#define WR_PIN 6
+#define CD_PORT GPIOB
+#define CD_PIN 7
+#define CS_PORT GPIOB
+#define CS_PIN 8
+#define RESET_PORT GPIOB
+#define RESET_PIN 9
+
+// configure macros for the data pins
+#define write_8(d) { GPIOA->REGS(BSRR) = 0x00FF << 16; GPIOA->REGS(BSRR) = (d) & 0xFF; }
+#define read_8() (GPIOA->REGS(IDR) & 0xFF)
+// PA7 ..PA0
+#define setWriteDir() {GP_OUT(GPIOA, CRL, 0xFFFFFFFF); }
+#define setReadDir() {GP_INP(GPIOA, CRL, 0xFFFFFFFF); }
+
+#elif IS_NUCLEO64 // Uno Shield on NUCLEO-64
+#warning Uno Shield on NUCLEO-64
+#define RD_PORT GPIOA //PA0
+#define RD_PIN 0
+#define WR_PORT GPIOA //PA1
+#define WR_PIN 1
+#define CD_PORT GPIOA //PA4
+#define CD_PIN 4
+#define CS_PORT GPIOB //PB0
+#define CS_PIN 0
+#define RESET_PORT GPIOC //PC1
+#define RESET_PIN 1
+
+// configure macros for the data pins
+#define AMASK ((1<<9)|(1<<10)|(1<<8)) //#0, #2, #7
+#define BMASK ((1<<3)|(1<<5)|(1<<4)|(1<<10)) //#3, #4, #5, #6
+#define CMASK ((1<<7)) //#1
+
+#define write_8(d) { \
+ GPIOA->REGS(BSRR) = AMASK << 16; \
+ GPIOB->REGS(BSRR) = BMASK << 16; \
+ GPIOC->REGS(BSRR) = CMASK << 16; \
+ GPIOA->REGS(BSRR) = ( ((d) & (1<<0)) << 9) \
+ | (((d) & (1<<2)) << 8) \
+ | (((d) & (1<<7)) << 1); \
+ GPIOB->REGS(BSRR) = ( ((d) & (1<<3)) << 0) \
+ | (((d) & (1<<4)) << 1) \
+ | (((d) & (1<<5)) >> 1) \
+ | (((d) & (1<<6)) << 4); \
+ GPIOC->REGS(BSRR) = ( ((d) & (1<<1)) << 6); \
+ }
+
+#define read_8() ( ( ( (GPIOA->REGS(IDR) & (1<<9)) >> 9) \
+ | ((GPIOC->REGS(IDR) & (1<<7)) >> 6) \
+ | ((GPIOA->REGS(IDR) & (1<<10)) >> 8) \
+ | ((GPIOB->REGS(IDR) & (1<<3)) >> 0) \
+ | ((GPIOB->REGS(IDR) & (1<<5)) >> 1) \
+ | ((GPIOB->REGS(IDR) & (1<<4)) << 1) \
+ | ((GPIOB->REGS(IDR) & (1<<10)) >> 4) \
+ | ((GPIOA->REGS(IDR) & (1<<8)) >> 1)))
+
+
+#if defined(ARDUINO_NUCLEO_F103RB) || defined(ARDUINO_STM_NUCLEO_F103RB) //F103 has unusual GPIO modes
+// PA10,PA9,PA8 PB10 PB5,PB4,PB3 PC7
+#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOB, CRH, 0xF00); GP_OUT(GPIOB, CRL, 0xFFF000); GP_OUT(GPIOC, CRL, 0xF0000000); }
+#define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOB, CRH, 0xF00); GP_INP(GPIOB, CRL, 0xFFF000); GP_INP(GPIOC, CRL, 0xF0000000); }
+#else //F0xx, F3xx, F4xx, L0xx, L1xx, L4xx use MODER
+// PA10,PA9,PA8 PB10,PB5,PB4,PB3 PC7
+#define setWriteDir() { setReadDir(); \
+ GPIOA->MODER |= 0x150000; GPIOB->MODER |= 0x100540; GPIOC->MODER |= 0x4000; }
+#define setReadDir() { GPIOA->MODER &= ~0x3F0000; GPIOB->MODER &= ~0x300FC0; GPIOC->MODER &= ~0xC000; }
+#endif
+
+#elif IS_NUCLEO144 // Uno Shield on NUCLEO-144
+#warning Uno Shield on NUCLEO-144
+#define RD_PORT GPIOA //PA3
+#define RD_PIN 3
+#define WR_PORT GPIOC //PC0
+#define WR_PIN 0
+#define CD_PORT GPIOC //PC3
+#define CD_PIN 3
+#define CS_PORT GPIOF //PF3
+#define CS_PIN 3
+#define RESET_PORT GPIOF //PF5
+#define RESET_PIN 5
+
+// configure macros for the data pins
+#define DMASK ((1<<15)) //#1
+#define EMASK ((1<<13)|(1<<11)|(1<<9)) //#3, #5, #6
+#define FMASK ((1<<12)|(1<<15)|(1<<14)|(1<<13)) //#0, #2, #4, #7
+
+#define write_8(d) { \
+ GPIOD->REGS(BSRR) = DMASK << 16; \
+ GPIOE->REGS(BSRR) = EMASK << 16; \
+ GPIOF->REGS(BSRR) = FMASK << 16; \
+ GPIOD->REGS(BSRR) = ( ((d) & (1<<1)) << 14); \
+ GPIOE->REGS(BSRR) = ( ((d) & (1<<3)) << 10) \
+ | (((d) & (1<<5)) << 6) \
+ | (((d) & (1<<6)) << 3); \
+ GPIOF->REGS(BSRR) = ( ((d) & (1<<0)) << 12) \
+ | (((d) & (1<<2)) << 13) \
+ | (((d) & (1<<4)) << 10) \
+ | (((d) & (1<<7)) << 6); \
+ }
+
+#define read_8() ( ( ( (GPIOF->REGS(IDR) & (1<<12)) >> 12) \
+ | ((GPIOD->REGS(IDR) & (1<<15)) >> 14) \
+ | ((GPIOF->REGS(IDR) & (1<<15)) >> 13) \
+ | ((GPIOE->REGS(IDR) & (1<<13)) >> 10) \
+ | ((GPIOF->REGS(IDR) & (1<<14)) >> 10) \
+ | ((GPIOE->REGS(IDR) & (1<<11)) >> 6) \
+ | ((GPIOE->REGS(IDR) & (1<<9)) >> 3) \
+ | ((GPIOF->REGS(IDR) & (1<<13)) >> 6)))
+
+
+// PD15 PE13,PE11,PE9 PF15,PF14,PF13,PF12
+#define setWriteDir() { setReadDir(); \
+ GPIOD->MODER |= 0x40000000; GPIOE->MODER |= 0x04440000; GPIOF->MODER |= 0x55000000; }
+#define setReadDir() { GPIOD->MODER &= ~0xC0000000; GPIOE->MODER &= ~0x0CCC0000; GPIOF->MODER &= ~0xFF000000; }
+
+#elif defined(ARDUINO_MAPLE_REV3) // Uno Shield on MAPLE_REV3 board
+#warning Uno Shield on MAPLE_REV3 board
+#define RD_PORT GPIOC
+#define RD_PIN 0
+#define WR_PORT GPIOC
+#define WR_PIN 1
+#define CD_PORT GPIOC
+#define CD_PIN 2
+#define CS_PORT GPIOC
+#define CS_PIN 3
+#define RESET_PORT GPIOC
+#define RESET_PIN 4
+
+// configure macros for the data pins
+#define write_8(d) { \
+ GPIOA->REGS(BSRR) = 0x0703 << 16; \
+ GPIOB->REGS(BSRR) = 0x00E0 << 16; \
+ GPIOA->REGS(BSRR) = ( ((d) & (1<<0)) << 10) \
+ | (((d) & (1<<2)) >> 2) \
+ | (((d) & (1<<3)) >> 2) \
+ | (((d) & (1<<6)) << 2) \
+ | (((d) & (1<<7)) << 2); \
+ GPIOB->REGS(BSRR) = ( ((d) & (1<<1)) << 6) \
+ | (((d) & (1<<4)) << 1) \
+ | (((d) & (1<<5)) << 1); \
+ }
+
+#define read_8() ( ( ( (GPIOA->REGS(IDR) & (1<<10)) >> 10) \
+ | ((GPIOB->REGS(IDR) & (1<<7)) >> 6) \
+ | ((GPIOA->REGS(IDR) & (1<<0)) << 2) \
+ | ((GPIOA->REGS(IDR) & (1<<1)) << 2) \
+ | ((GPIOB->REGS(IDR) & (1<<5)) >> 1) \
+ | ((GPIOB->REGS(IDR) & (1<<6)) >> 1) \
+ | ((GPIOA->REGS(IDR) & (1<<8)) >> 2) \
+ | ((GPIOA->REGS(IDR) & (1<<9)) >> 2)))
+
+// PA10,PA9,PA8 PA1,PA0 PB7,PB6,PB5
+#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOA, CRL, 0xFF); GP_OUT(GPIOB, CRL, 0xFFF00000); }
+#define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOA, CRL, 0xFF); GP_INP(GPIOB, CRL, 0xFFF00000); }
+
+#else
+#error REGS group
+#endif
+
+#ifndef IDLE_DELAY
+#define IDLE_DELAY { WR_IDLE; }
+#endif
+
+#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; IDLE_DELAY; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE2; RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+//################################### ESP32 ##############################
+#elif defined(ESP32) //regular UNO shield on TTGO D1 R32 (ESP32)
+#define LCD_RD 2 //LED
+#define LCD_WR 4
+#define LCD_RS 15 //hard-wired to A2 (GPIO35)
+#define LCD_CS 33 //hard-wired to A3 (GPIO34)
+#define LCD_RST 32 //hard-wired to A4 (GPIO36)
+
+#define LCD_D0 12
+#define LCD_D1 13
+#define LCD_D2 26
+#define LCD_D3 25
+#define LCD_D4 17
+#define LCD_D5 16
+#define LCD_D6 27
+#define LCD_D7 14
+
+#define RD_PORT GPIO.out
+#define RD_PIN LCD_RD
+#define WR_PORT GPIO.out
+#define WR_PIN LCD_WR
+#define CD_PORT GPIO.out
+#define CD_PIN LCD_RS
+#define CS_PORT GPIO.out1.val
+#define CS_PIN LCD_CS
+#define RESET_PORT GPIO.out1.val
+#define RESET_PIN LCD_RST
+
+static inline uint32_t map_8(uint32_t d)
+{
+ return (
+ 0
+ | ((d & (1 << 0)) << (LCD_D0 - 0))
+ | ((d & (1 << 1)) << (LCD_D1 - 1))
+ | ((d & (1 << 2)) << (LCD_D2 - 2))
+ | ((d & (1 << 3)) << (LCD_D3 - 3))
+ | ((d & (1 << 4)) << (LCD_D4 - 4))
+ | ((d & (1 << 5)) << (LCD_D5 - 5))
+ | ((d & (1 << 6)) << (LCD_D6 - 6))
+ | ((d & (1 << 7)) << (LCD_D7 - 7))
+ );
+}
+
+static inline uint8_t map_32(uint32_t d)
+{
+ return (
+ 0
+ | ((d & (1 << LCD_D0)) >> (LCD_D0 - 0))
+ | ((d & (1 << LCD_D1)) >> (LCD_D1 - 1))
+ | ((d & (1 << LCD_D2)) >> (LCD_D2 - 2))
+ | ((d & (1 << LCD_D3)) >> (LCD_D3 - 3))
+ | ((d & (1 << LCD_D4)) >> (LCD_D4 - 4))
+ | ((d & (1 << LCD_D5)) >> (LCD_D5 - 5))
+ | ((d & (1 << LCD_D6)) >> (LCD_D6 - 6))
+ | ((d & (1 << LCD_D7)) >> (LCD_D7 - 7))
+ );
+}
+
+static inline void write_8(uint16_t data)
+{
+ GPIO.out_w1tc = map_8(0xFF); //could define once as DMASK
+ GPIO.out_w1ts = map_8(data);
+}
+
+static inline uint8_t read_8()
+{
+ return map_32(GPIO.in);
+}
+static void setWriteDir()
+{
+ pinMode(LCD_D0, OUTPUT);
+ pinMode(LCD_D1, OUTPUT);
+ pinMode(LCD_D2, OUTPUT);
+ pinMode(LCD_D3, OUTPUT);
+ pinMode(LCD_D4, OUTPUT);
+ pinMode(LCD_D5, OUTPUT);
+ pinMode(LCD_D6, OUTPUT);
+ pinMode(LCD_D7, OUTPUT);
+}
+
+static void setReadDir()
+{
+ pinMode(LCD_D0, INPUT);
+ pinMode(LCD_D1, INPUT);
+ pinMode(LCD_D2, INPUT);
+ pinMode(LCD_D3, INPUT);
+ pinMode(LCD_D4, INPUT);
+ pinMode(LCD_D5, INPUT);
+ pinMode(LCD_D6, INPUT);
+ pinMode(LCD_D7, INPUT);
+}
+
+#define WRITE_DELAY { }
+#define READ_DELAY { }
+
+#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (digitalWrite(b, LOW))
+#define PIN_HIGH(p, b) (digitalWrite(b, HIGH))
+#define PIN_OUTPUT(p, b) (pinMode(b, OUTPUT))
+
+#else
+#error MCU unsupported
+#endif // regular UNO shields on Arduino boards
+
+#endif //!defined(USE_SPECIAL) || defined (USE_SPECIAL_FAIL)
+
+#define RD_ACTIVE PIN_LOW(RD_PORT, RD_PIN)
+#define RD_IDLE PIN_HIGH(RD_PORT, RD_PIN)
+#define RD_OUTPUT PIN_OUTPUT(RD_PORT, RD_PIN)
+#define WR_ACTIVE PIN_LOW(WR_PORT, WR_PIN)
+#define WR_IDLE PIN_HIGH(WR_PORT, WR_PIN)
+#define WR_OUTPUT PIN_OUTPUT(WR_PORT, WR_PIN)
+#define CD_COMMAND PIN_LOW(CD_PORT, CD_PIN)
+#define CD_DATA PIN_HIGH(CD_PORT, CD_PIN)
+#define CD_OUTPUT PIN_OUTPUT(CD_PORT, CD_PIN)
+#define CS_ACTIVE PIN_LOW(CS_PORT, CS_PIN)
+#define CS_IDLE PIN_HIGH(CS_PORT, CS_PIN)
+#define CS_OUTPUT PIN_OUTPUT(CS_PORT, CS_PIN)
+#define RESET_ACTIVE PIN_LOW(RESET_PORT, RESET_PIN)
+#define RESET_IDLE PIN_HIGH(RESET_PORT, RESET_PIN)
+#define RESET_OUTPUT PIN_OUTPUT(RESET_PORT, RESET_PIN)
+
+ // General macros. IOCLR registers are 1 cycle when optimised.
+#define WR_STROBE { WR_ACTIVE; WR_IDLE; } //PWLW=TWRL=50ns
+#define RD_STROBE RD_IDLE, RD_ACTIVE, RD_ACTIVE, RD_ACTIVE //PWLR=TRDL=150ns, tDDR=100ns
+
+#if !defined(GPIO_INIT)
+#define GPIO_INIT()
+#endif
+#define CTL_INIT() { GPIO_INIT(); RD_OUTPUT; WR_OUTPUT; CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; }
+#define WriteCmd(x) { CD_COMMAND; write16(x); CD_DATA; }
+#define WriteData(x) { write16(x); }
+
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MCUFRIEND_kbv/utility/mcufriend_special.h Wed Apr 21 14:54:37 2021 +0000
@@ -0,0 +1,958 @@
+// only define one "USE_XXX" macro at any time
+
+//#define USE_MEGA_8BIT_PROTOSHIELD
+//#define USE_MEGA_8BIT_SHIELD // 4.7sec Mega2560 Shield
+//#define USE_MEGA_16BIT_SHIELD // 2.14sec Mega2560 Shield
+//#define USE_BLD_BST_MEGA32U4
+//#define USE_BLD_BST_MEGA2560 // 12.23sec Uno Shield (17.38s C)
+//#define USE_BLD_BST_MEGA4809 // 5.43sec XPRO-Adapter (7.09s C)
+//#define USE_DUE_8BIT_PROTOSHIELD
+//#define USE_DUE_16BIT_SHIELD //RD on PA15 (D24)
+//#define USE_BOBCACHELOT_TEENSY
+//#define USE_OPENSMART_SHIELD_PINOUT_UNO
+//#define USE_OPENSMART_SHIELD_PINOUT_MEGA
+//#define USE_OPENSMART_SHIELD_PINOUT_DUE //thanks Michel53
+//#define USE_ELECHOUSE_DUE_16BIT_SHIELD //Untested yet
+//#define USE_MY_BLUEPILL
+//#define USE_ADIGITALEU_TEENSY
+//#define USE_MIKROELEKTRONIKA
+//#define USE_XPRO_MEGA4809
+
+/*
+HX8347A tWC =100ns tWRH = 35ns tRCFM = 450ns tRC = ? ns
+HX8347D tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
+HX8347I tWC =100ns tWRH = 15ns tRCFM = 600ns tRC = 160ns
+HX8357C tWC = 50ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
+ILI9320 tWC =100ns tWRH = 50ns tRCFM = 300ns tRC = 300ns
+ILI9341 tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
+ILI9481 tWC =100ns tWRH = 30ns tRCFM = 450ns tRC = 450ns
+ILI9486 tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns (tWCFM= 286ns on mystery 9486_16)
+ILI9486L tWC = 50ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
+ILI9488 tWC = 30ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
+NT35310 tWC = 40ns tWRH = 19ns tRCFM = 400ns tRC = 160ns
+RM68140 tWC = 50ns tWRH = 15ns tRCFM = 450ns tRC = 160ns (tWCFM= 119ns)
+SPFD5408 tWC =125ns tWRH = 70ns tRCFM = 450ns tRC = 450ns
+SSD1289 tWC =100ns tWRH = 50ns tRCFM =1000ns tRC =1000ns (tWCFM= 238ns)
+SSD1963 tWC = 26ns tWRH = 13ns tRCFM = 110ns tRC = 72ns
+ST7789V tWC = 66ns tWRH = 15ns tRCFM = 450ns tRC = 160ns
+*/
+
+#if 0
+
+#elif defined(__AVR_ATxmega128A1__) // Xplained or MIKROE
+#if defined(USE_MIKROELEKTRONIKA) // HX8347-D 16.2ns@62MHz 20.9ns@48MHz
+#if F_CPU > 46000000
+#error MIKROELEKTRONIKA must be less than 48MHz
+#else
+#warning MIKROELEKTRONIKA DEV BOARD (48MHz max)
+#endif
+#define WRITE_DELAY { }
+#define READ_DELAY { RD_ACTIVE4; }
+#define VPMAP10 0x58 // VPORT0=J, 1=F, 2=K, 3=D
+#define VPMAP32 0x39 // VPORT0=J, 1=F, 2=K, 3=D
+#define RD_PORT VPORT0 //PJ2.
+#define RD_PIN 2
+#define WR_PORT VPORT0
+#define WR_PIN 3
+#define CD_PORT VPORT0
+#define CD_PIN 4
+#define CS_PORT VPORT0
+#define CS_PIN 5
+#define RESET_PORT VPORT0 //PJ1
+#define RESET_PIN 1
+#else
+#warning Home made shield with Xplained
+#define WRITE_DELAY { }
+#define READ_DELAY { RD_ACTIVE4; }
+#define VPMAP10 0x15 // VPORT0=F, 1=B, 2=C, 3=D
+#define VPMAP32 0x32 // VPORT0=F, 1=B, 2=C, 3=D
+#define RD_PORT VPORT0 //PF0.
+#define RD_PIN 0
+#define WR_PORT VPORT0
+#define WR_PIN 1
+#define CD_PORT VPORT0
+#define CD_PIN 2
+#define CS_PORT VPORT0
+#define CS_PIN 3
+#define RESET_PORT VPORT0 //PK4
+#define RESET_PIN 4
+#endif
+
+// VPORTs are very fast. CBI, SBI are only one cycle. Hence all those RD_ACTIVEs
+// ILI9320 data sheet says tDDR=100ns. We need 218ns to read REGs correctly.
+#define write_8(x) { VPORT2.OUT = x; }
+#define read_8() ( VPORT2.IN )
+#define setWriteDir() { PORTCFG.VPCTRLA=VPMAP10; PORTCFG.VPCTRLB=VPMAP32; VPORT2.DIR = 0xFF; }
+#define setReadDir() { VPORT2.DIR = 0x00; }
+#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+//#define READ_8(dst) { RD_STROBE; RD_ACTIVE2; RD_ACTIVE; dst = read_8(); RD_IDLE; }
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
+#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
+#elif defined(__AVR_ATxmega32A4U__) || defined(__AVR_ATxmega128A4U__) // Home made shield with Batsocks module
+#warning Home made shield with Batsocks module
+#define RD_PORT VPORT1 //PB0. VPORT0=A, 1=B, 2=C, 3=D
+#define RD_PIN 0
+#define WR_PORT VPORT1
+#define WR_PIN 1
+#define CD_PORT VPORT1
+#define CD_PIN 2
+#define CS_PORT VPORT1
+#define CS_PIN 3
+#define RESET_PORT PORTE
+#define RESET_PIN 0
+
+// VPORTs are very fast. CBI, SBI are only one cycle. Hence all those RD_ACTIVEs
+// ILI9320 data sheet says tDDR=100ns. We need 218ns to read REGs correctly.
+// S6D0154 data sheet says tDDR=250ns. We need ~500ns to read REGs correctly.
+// ST7789 data sheet says tRC=450ns. We need ~167ns to read REGs correctly. (10 cycles @ 60MHz )
+// ST7789 says tRC=160ns for ID and tRC=450ns for Frame Memory
+// ILI9341 says tRC=160ns for ID and tRC=450ns for Frame Memory. They are FASTER
+#define WRITE_DELAY { }
+#define READ_DELAY { RD_ACTIVE4; }
+#define write_8(x) { VPORT2.OUT = x; }
+#define read_8() ( VPORT2.IN )
+#define setWriteDir() { PORTCFG.VPCTRLA=0x10; PORTCFG.VPCTRLB=0x32; VPORT2.DIR = 0xFF; }
+#define setReadDir() { VPORT2.DIR = 0x00; }
+#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
+#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
+
+//################################# XPRO-4809 with XPRO-Shield_Adapter ############################
+#elif defined(__AVR_ATmega4809__) && !defined(USE_BLD_BST_MEGA4809) && defined(USE_XPRO_MEGA4809) // XPRO-4809 with XPRO-Shield_Adapter
+#warning XPRO-4809 with XPRO-Shield_Adapter using PORT.OUTSET
+#define RD_PORT PORTD //
+#define RD_PIN 2
+#define WR_PORT PORTD
+#define WR_PIN 3
+#define CD_PORT PORTD
+#define CD_PIN 4
+#define CS_PORT PORTD
+#define CS_PIN 5
+#define RESET_PORT PORTC
+#define RESET_PIN 2
+
+// PORT.OUTSET is fast but still 2 cycles. Hence all those RD_ACTIVEs
+#define AMASK (3<<2)
+#define BMASK (3<<2)
+#define CMASK (3<<6)
+#define EMASK (1<<1)
+#define FMASK (1<<6)
+#define write_8(x) { \
+ PORTA.OUTCLR = AMASK; PORTA.OUTSET = (((x) & (3<<0)) << 2); \
+ PORTB.OUTCLR = BMASK; PORTB.OUTSET = (((x) & (1<<2))) | (((x) & (1<<6)) >> 3); \
+ PORTC.OUTCLR = CMASK; PORTC.OUTSET = (((x) & (3<<3)) << 3); \
+ PORTE.OUTCLR = EMASK; PORTE.OUTSET = (((x) & (1<<7)) >> 6); \
+ PORTF.OUTCLR = FMASK; PORTF.OUTSET = (((x) & (1<<5)) << 1); \
+ }
+#define read_8() ( ((PORTA.IN & AMASK) >> 2)\
+| ((PORTB.IN & (1<<2)) >> 0)\
+| ((PORTB.IN & (1<<3)) << 3)\
+| ((PORTC.IN & CMASK) >> 3)\
+| ((PORTE.IN & EMASK) << 6)\
+| ((PORTF.IN & FMASK) >> 1)\
+)
+#define setWriteDir() { PORTA.DIRSET = AMASK; PORTB.DIRSET = BMASK; PORTC.DIRSET = CMASK; PORTE.DIRSET = EMASK; PORTF.DIRSET = FMASK; }
+#define setReadDir() { PORTA.DIRCLR = AMASK; PORTB.DIRCLR = BMASK; PORTC.DIRCLR = CMASK; PORTE.DIRCLR = EMASK; PORTF.DIRCLR = FMASK; }
+
+#define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=7.09s @20MHz (-O1=8.13s, -O3=6.03s)
+#define READ_DELAY { RD_ACTIVE2; } //ID=0x7789
+#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (p).OUTCLR = (1<<(b))
+#define PIN_HIGH(p, b) (p).OUTSET = (1<<(b))
+#define PIN_OUTPUT(p, b) (p).DIRSET = (1<<(b))
+
+#elif defined(__AVR_ATmega4809__) && defined(USE_BLD_BST_MEGA4809) && defined(USE_XPRO_MEGA4809) // XPRO-4809 with XPRO-Shield_Adapter
+#warning XPRO-4809 with XPRO-Shield_Adapter using VPORT.OUT and BLD/BST
+#define RD_PORT VPORTD //
+#define RD_PIN 2
+#define WR_PORT VPORTD
+#define WR_PIN 3
+#define CD_PORT VPORTD
+#define CD_PIN 4
+#define CS_PORT VPORTD
+#define CS_PIN 5
+#define RESET_PORT VPORTC
+#define RESET_PIN 2
+
+#define AMASK (3<<2)
+#define BMASK (3<<2)
+#define CMASK (3<<6)
+#define EMASK (1<<1)
+#define FMASK (1<<6)
+static __attribute((always_inline))
+ void write_8(uint8_t val)
+{
+ asm volatile("in __tmp_reg__,0x01" "\n\t" //VPORTA.OUT
+ "BST %0,0" "\n\t" "BLD __tmp_reg__,2" "\n\t"
+ "BST %0,1" "\n\t" "BLD __tmp_reg__,3" "\n\t"
+ "out 0x01,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x05" "\n\t" //VPORTB.OUT
+ "BST %0,2" "\n\t" "BLD __tmp_reg__,2" "\n\t"
+ "BST %0,6" "\n\t" "BLD __tmp_reg__,3" "\n\t"
+ "out 0x05,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x09" "\n\t" //VPORTC.OUT
+ "BST %0,3" "\n\t" "BLD __tmp_reg__,6" "\n\t"
+ "BST %0,4" "\n\t" "BLD __tmp_reg__,7" "\n\t"
+ "out 0x09,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x11" "\n\t" //VPORTE.OUT
+ "BST %0,7" "\n\t" "BLD __tmp_reg__,1" "\n\t"
+ "out 0x11,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x15" "\n\t" //VPORTF.OUT
+ "BST %0,5" "\n\t" "BLD __tmp_reg__,6" "\n\t"
+ "out 0x15,__tmp_reg__" : : "a" (val));
+}
+
+#define read_8() ( ((VPORTA_IN & AMASK) >> 2)\
+| ((VPORTB_IN & (1<<2)) >> 0)\
+| ((VPORTB_IN & (1<<3)) << 3)\
+| ((VPORTC_IN & CMASK) >> 3)\
+| ((VPORTE_IN & EMASK) << 6)\
+| ((VPORTF_IN & FMASK) >> 1)\
+)
+#define setWriteDir() { VPORTA_DIR |= AMASK; VPORTB_DIR |= BMASK; VPORTC_DIR |= CMASK; VPORTE_DIR |= EMASK; VPORTF_DIR |= FMASK; }
+#define setReadDir() { VPORTA_DIR &= ~AMASK; VPORTB_DIR &= ~BMASK; VPORTC_DIR &= ~CMASK; VPORTE_DIR &= ~EMASK; VPORTF_DIR &= ~FMASK; }
+
+//#define WRITE_DELAY { WR_ACTIVE; WR_ACTIVE; } //6.47s no_inline
+#define WRITE_DELAY { WR_ACTIVE2; WR_ACTIVE; } //-Os=5.43s @20MHz always_inline. (-O1=5.41s, -O3=5.25s)
+#define READ_DELAY { RD_ACTIVE4; } //ID=0x7789
+#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (p).OUT &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p).OUT |= (1<<(b))
+#define PIN_OUTPUT(p, b) (p).DIR |= (1<<(b))
+
+#elif defined(__AVR_ATmega328P__) && defined(USE_OPENSMART_SHIELD_PINOUT_UNO)
+#define RD_PORT PORTC
+#define RD_PIN 0
+#define WR_PORT PORTC
+#define WR_PIN 1
+#define CD_PORT PORTC
+#define CD_PIN 2
+#define CS_PORT PORTC
+#define CS_PIN 3
+#define RESET_PORT PORTC
+#define RESET_PIN 1 // n/a. so mimic WR_PIN
+
+#define BMASK B00101111
+#define DMASK B11010000
+
+#define write_8(x) { \
+ PORTD = (PORTD & ~DMASK) | ((x) & DMASK); \
+ PORTB = (PORTB & ~BMASK) | ((x) & BMASK);} // STROBEs are defined later
+
+#define read_8() ((PIND & DMASK) | (PINB & BMASK))
+
+#define setWriteDir() { DDRD |= DMASK; DDRB |= BMASK; }
+#define setReadDir() { DDRD &= ~DMASK; DDRB &= ~BMASK; }
+
+
+#define write8(x) { write_8(x); WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (p) &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p) |= (1<<(b))
+#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
+
+#elif defined(__AVR_ATmega2560__) && defined(USE_OPENSMART_SHIELD_PINOUT_MEGA)
+#define RD_PORT PORTF
+#define RD_PIN 0
+#define WR_PORT PORTF
+#define WR_PIN 1
+#define CD_PORT PORTF
+#define CD_PIN 2
+#define CS_PORT PORTF
+#define CS_PIN 3
+#define RESET_PORT PORTF
+#define RESET_PIN 1 // n/a. so mimic WR_PIN
+
+#define BMASK B10110000 //D13, D11, D10
+#define GMASK 0x20 //D4
+#define HMASK 0x78 //D6, D7, D8, D9
+
+#if defined(USE_BLD_BST_MEGA2560)
+static __attribute((always_inline)) void write_8(uint8_t val)
+{
+ asm volatile("lds __tmp_reg__,0x0102" "\n\t" //PORTH
+ "BST %0,0" "\n\t" "BLD __tmp_reg__,5" "\n\t"
+ "BST %0,1" "\n\t" "BLD __tmp_reg__,6" "\n\t"
+ "BST %0,6" "\n\t" "BLD __tmp_reg__,3" "\n\t"
+ "BST %0,7" "\n\t" "BLD __tmp_reg__,4" "\n\t"
+ "sts 0x0102,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x05" "\n\t" //PORTB
+ "BST %0,2" "\n\t" "BLD __tmp_reg__,4" "\n\t"
+ "BST %0,3" "\n\t" "BLD __tmp_reg__,5" "\n\t"
+ "BST %0,5" "\n\t" "BLD __tmp_reg__,7" "\n\t"
+ "out 0x05,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x14" "\n\t" //PORTG
+ "BST %0,4" "\n\t" "BLD __tmp_reg__,5" "\n\t"
+ "out 0x14,__tmp_reg__" : : "a" (val));
+}
+#else
+#define write_8(x) { \
+ PORTH = (PORTH&~HMASK)|(((x)&B11000000)>>3)|(((x)&B00000011)<<5); \
+ PORTB = (PORTB&~BMASK)|(((x)&B00101100)<<2); \
+ PORTG = (PORTG&~GMASK)|(((x)&B00010000)<<1); \
+ }
+#endif
+
+#define read_8()(\
+ ((PINH & B00011000) << 3) | ((PINB & BMASK) >> 2) | \
+ ((PING & GMASK) >> 1) | ((PINH & B01100000) >> 5) )
+#define setWriteDir() { DDRH |= HMASK; DDRB |= BMASK; DDRG |= GMASK; }
+#define setReadDir() { DDRH &= ~HMASK; DDRB &= ~BMASK; DDRG &= ~GMASK; }
+
+#define write8(x) { write_8(x); WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PIN_LOW(p, b) (p) &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p) |= (1<<(b))
+#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
+
+#elif defined(__SAM3X8E__) && defined(USE_OPENSMART_SHIELD_PINOUT_DUE) //OPENSMART shield on DUE
+#warning USE_OPENSMART_SHIELD_PINOUT on DUE
+ // configure macros for the control pins
+#define RD_PORT PIOA
+#define RD_PIN 16
+#define WR_PORT PIOA
+#define WR_PIN 24
+#define CD_PORT PIOA
+#define CD_PIN 23
+#define CS_PORT PIOA
+#define CS_PIN 22
+#define RESET_PORT PIOA
+#define RESET_PIN 24 // n/a. so mimic WR_PIN
+ // configure macros for data bus
+#define BMASK (1<<27)
+#define CMASK (0x12F << 21)
+#define DMASK (1<<7)
+#define write_8(x) { PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; PIOD->PIO_CODR = DMASK; \
+ PIOC->PIO_SODR = (((x) & (1<<0)) << 22); \
+ PIOC->PIO_SODR = (((x) & (1<<1)) << 20); \
+ PIOC->PIO_SODR = (((x) & (1<<2)) << 27); \
+ PIOD->PIO_SODR = (((x) & (1<<3)) << 4); \
+ PIOC->PIO_SODR = (((x) & (1<<4)) << 22); \
+ PIOB->PIO_SODR = (((x) & (1<<5)) << 22); \
+ PIOC->PIO_SODR = (((x) & (1<<6)) << 18); \
+ PIOC->PIO_SODR = (((x) & (1<<7)) << 16); \
+ }
+
+#define read_8() ( ((PIOC->PIO_PDSR & (1<<22)) >> 22)\
+ | ((PIOC->PIO_PDSR & (1<<21)) >> 20)\
+ | ((PIOC->PIO_PDSR & (1<<29)) >> 27)\
+ | ((PIOD->PIO_PDSR & (1<<7)) >> 4)\
+ | ((PIOC->PIO_PDSR & (1<<26)) >> 22)\
+ | ((PIOB->PIO_PDSR & (1<<27)) >> 22)\
+ | ((PIOC->PIO_PDSR & (1<<24)) >> 18)\
+ | ((PIOC->PIO_PDSR & (1<<23)) >> 16)\
+ )
+#define setWriteDir() { PIOB->PIO_OER = BMASK; PIOC->PIO_OER = CMASK; PIOD->PIO_OER = DMASK; }
+#define setReadDir() { \
+ PMC->PMC_PCER0 = (1 << ID_PIOB)|(1 << ID_PIOC)|(1 << ID_PIOD);\
+ PIOB->PIO_ODR = BMASK; PIOC->PIO_ODR = CMASK; PIOD->PIO_ODR = DMASK;\
+ }
+#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; }
+//#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; WR_IDLE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; RD_ACTIVE; dst = read_8(); RD_IDLE; RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+ // Shield Control macros.
+#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
+#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
+
+#elif defined(__AVR_ATmega2560__) && defined(USE_BLD_BST_MEGA2560) //regular UNO shield on MEGA2560 using BLD/BST
+#warning regular UNO shield on MEGA2560 using BLD/BST
+#define RD_PORT PORTF
+#define RD_PIN 0
+#define WR_PORT PORTF
+#define WR_PIN 1
+#define CD_PORT PORTF
+#define CD_PIN 2
+#define CS_PORT PORTF
+#define CS_PIN 3
+#define RESET_PORT PORTF
+#define RESET_PIN 4
+
+#define EMASK 0x38
+#define GMASK 0x20
+#define HMASK 0x78
+static __attribute((always_inline)) void write_8(uint8_t val)
+{
+ asm volatile("lds __tmp_reg__,0x0102" "\n\t"
+ "BST %0,0" "\n\t" "BLD __tmp_reg__,5" "\n\t"
+ "BST %0,1" "\n\t" "BLD __tmp_reg__,6" "\n\t"
+ "BST %0,6" "\n\t" "BLD __tmp_reg__,3" "\n\t"
+ "BST %0,7" "\n\t" "BLD __tmp_reg__,4" "\n\t"
+ "sts 0x0102,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x0E" "\n\t"
+ "BST %0,2" "\n\t" "BLD __tmp_reg__,4" "\n\t"
+ "BST %0,3" "\n\t" "BLD __tmp_reg__,5" "\n\t"
+ "BST %0,5" "\n\t" "BLD __tmp_reg__,3" "\n\t"
+ "out 0x0E,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x14" "\n\t"
+ "BST %0,4" "\n\t" "BLD __tmp_reg__,5" "\n\t"
+ "out 0x14,__tmp_reg__" : : "a" (val));
+}
+
+#define read_8() ( ((PINH & (3<<5)) >> 5)\
+| ((PINE & (3<<4)) >> 2)\
+| ((PING & (1<<5)) >> 1)\
+| ((PINE & (1<<3)) << 2)\
+| ((PINH & (3<<3)) << 3)\
+)
+#define setWriteDir() { DDRH |= HMASK; DDRG |= GMASK; DDRE |= EMASK; }
+#define setReadDir() { DDRH &= ~HMASK; DDRG &= ~GMASK; DDRE &= ~EMASK; }
+#define write8(x) { write_8(x); WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
+
+#define PIN_LOW(p, b) (p) &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p) |= (1<<(b))
+#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
+
+#elif defined(__AVR_ATmega2560__) && defined(USE_MEGA_16BIT_SHIELD)
+#warning USE_MEGA_16BIT_SHIELD
+#define USES_16BIT_BUS
+#define RD_PORT PORTL
+#define RD_PIN 6 //PL6 (D43). Graham has PA15 (D24) on Due Shield
+#define WR_PORT PORTG
+#define WR_PIN 2 //D39 CTE
+#define CD_PORT PORTD
+#define CD_PIN 7 //D38 CTE
+#define CS_PORT PORTG
+#define CS_PIN 1 //D40 CTE
+#define RESET_PORT PORTG
+#define RESET_PIN 0 //D41 CTE
+
+#define write_8(x) { PORTC = x; }
+#define write_16(x) { PORTA = (x) >> 8; PORTC = x; }
+
+#define read_16() ( (PINA<<8) | (PINC) )
+#define setWriteDir() { DDRC = 0xFF; DDRA = 0xff; }
+#define setReadDir() { DDRC = 0x00; DDRA = 0x00; }
+//#define write8(x) { write_8(x); WR_STROBE; }
+#define write8(x) { write16((x) & 0xFF); }
+#define write16(x) { write_16(x); WR_ACTIVE; WR_STROBE; }
+#define READ_16(dst) { RD_STROBE; dst = read_16(); RD_IDLE; }
+#define READ_8(dst) { READ_16(dst); dst &= 0x00FF; }
+
+#define PIN_LOW(p, b) (p) &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p) |= (1<<(b))
+#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
+
+#elif defined(__AVR_ATmega2560__) && defined(USE_MEGA_8BIT_SHIELD)
+#warning USE_MEGA_8BIT_SHIELD for vagos21
+#define RD_PORT PORTL
+#define RD_PIN 6 //PL6 (D43). Graham has PA15 (D24) on Due Shield
+#define WR_PORT PORTG
+#define WR_PIN 2 //D39 CTE
+#define CD_PORT PORTD
+#define CD_PIN 7 //D38 CTE
+#define CS_PORT PORTG
+#define CS_PIN 1 //D40 CTE
+#define RESET_PORT PORTG
+#define RESET_PIN 0 //D41 CTE
+
+#define write_8(x) { PORTA = x;}
+
+#define read_8() ( PINA )
+#define setWriteDir() { DDRA = 0xFF; }
+#define setReadDir() { DDRA = 0x00; }
+#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; } // HX8357-D is slower
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
+
+#define PIN_LOW(p, b) (p) &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p) |= (1<<(b))
+#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
+
+#elif defined(__AVR_ATmega2560__) && defined(USE_MEGA_8BIT_PROTOSHIELD)
+#warning USE_MEGA_8BIT_PROTOSHIELD
+#define RD_PORT PORTF
+#define RD_PIN 0
+#define WR_PORT PORTF
+#define WR_PIN 1
+#define CD_PORT PORTF
+#define CD_PIN 2
+#define CS_PORT PORTF
+#define CS_PIN 3
+#define RESET_PORT PORTF
+#define RESET_PIN 4
+
+#define write_8(x) { PORTA = x;}
+
+#define read_8() ( PINA )
+#define setWriteDir() { DDRA = 0xFF; }
+#define setReadDir() { DDRA = 0x00; }
+#define write8(x) { write_8(x); WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
+
+#define PIN_LOW(p, b) (p) &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p) |= (1<<(b))
+#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
+
+#elif defined(__AVR_ATmega32U4__) && defined(USE_BLD_BST_MEGA32U4) //regular UNO shield on Leonardo using BST/BLD
+#warning regular UNO shield on Leonardo using BST/BLD
+#define RD_PORT PORTF
+#define RD_PIN 7
+#define WR_PORT PORTF
+#define WR_PIN 6
+#define CD_PORT PORTF
+#define CD_PIN 5
+#define CS_PORT PORTF
+#define CS_PIN 4
+#define RESET_PORT PORTF
+#define RESET_PIN 1
+
+#define BMASK (3<<4)
+#define CMASK (1<<6)
+#define DMASK ((1<<7)|(1<<4)|(3<<0))
+#define EMASK (1<<6)
+static __attribute((always_inline)) void write_8(uint8_t val)
+{
+ asm volatile("in __tmp_reg__,0x05" "\n\t"
+ "BST %0,0" "\n\t" "BLD __tmp_reg__,4" "\n\t"
+ "BST %0,1" "\n\t" "BLD __tmp_reg__,5" "\n\t"
+ "out 0x05,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x0B" "\n\t"
+ "BST %0,2" "\n\t" "BLD __tmp_reg__,1" "\n\t"
+ "BST %0,3" "\n\t" "BLD __tmp_reg__,0" "\n\t"
+ "BST %0,4" "\n\t" "BLD __tmp_reg__,4" "\n\t"
+ "BST %0,6" "\n\t" "BLD __tmp_reg__,7" "\n\t"
+ "out 0x0B,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x08" "\n\t"
+ "BST %0,5" "\n\t" "BLD __tmp_reg__,6" "\n\t"
+ "out 0x08,__tmp_reg__" : : "a" (val));
+ asm volatile("in __tmp_reg__,0x0E" "\n\t"
+ "BST %0,7" "\n\t" "BLD __tmp_reg__,6" "\n\t"
+ "out 0x0E,__tmp_reg__" : : "a" (val));
+}
+#define read_8() ( ((PINB & (3<<4)) >> 4)\
+| ((PIND & (1<<1)) << 1)\
+| ((PIND & (1<<0)) << 3)\
+| ((PIND & (1<<4)) >> 0)\
+| ((PINC & (1<<6)) >> 1)\
+| ((PIND & (1<<7)) >> 1)\
+| ((PINE & (1<<6)) << 1)\
+)
+#define setWriteDir() { DDRB |= BMASK; DDRC |= CMASK; DDRD |= DMASK; DDRE |= EMASK; }
+#define setReadDir() { DDRB &= ~BMASK; DDRC &= ~CMASK; DDRD &= ~DMASK; DDRE &= ~EMASK; }
+#define write8(x) { write_8(x); WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { RD_STROBE; dst = read_8(); RD_IDLE; RD_STROBE; dst = (dst<<8) | read_8(); RD_IDLE; }
+
+#define PIN_LOW(p, b) (p) &= ~(1<<(b))
+#define PIN_HIGH(p, b) (p) |= (1<<(b))
+#define PIN_OUTPUT(p, b) *(&p-1) |= (1<<(b))
+
+#elif defined(__SAM3X8E__) && defined(USE_DUE_8BIT_PROTOSHIELD) //regular UNO shield on DUE
+#warning USE_DUE_8BIT_PROTOSHIELD
+// configure macros for the control pins
+ #define RD_PORT PIOA
+ #define RD_PIN 16 //A0
+ #define WR_PORT PIOA
+ #define WR_PIN 24 //A1
+ #define CD_PORT PIOA
+ #define CD_PIN 23 //A2
+ #define CS_PORT PIOA
+ #define CS_PIN 22 //A3
+ #define RESET_PORT PIOA
+ #define RESET_PIN 6 //A4
+// configure macros for data bus
+#define DMASK (0xFF<<0)
+#define write_8(x) { PIOD->PIO_CODR = DMASK; PIOD->PIO_SODR = x; }
+
+#define read_8() ( PIOD->PIO_PDSR & DMASK)
+ #define setWriteDir() { PIOD->PIO_OER = DMASK; PIOD->PIO_PER = DMASK; }
+ #define setReadDir() { PMC->PMC_PCER0 = (1 << ID_PIOD); PIOD->PIO_ODR = DMASK;}
+#define write8(x) { write_8(x); WR_ACTIVE; WR_STROBE; WR_IDLE; WR_IDLE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; RD_ACTIVE4; dst = read_8(); RD_IDLE; RD_IDLE; RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+// Shield Control macros.
+#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
+#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
+
+#elif defined(__SAM3X8E__) && defined(USE_DUE_16BIT_SHIELD) //regular CTE shield on DUE
+#warning USE_DUE_16BIT_SHIELD
+#define USES_16BIT_BUS
+// configure macros for the control pins
+#define RD_PORT PIOA
+#define RD_PIN 15 //D24 Graham
+#define WR_PORT PIOD
+#define WR_PIN 1 //D26
+#define CD_PORT PIOD
+#define CD_PIN 0 //D25
+#define CS_PORT PIOD
+#define CS_PIN 2 //D27
+#define RESET_PORT PIOD
+#define RESET_PIN 3 //D28
+// configure macros for data bus
+// DB0..DB7 on PIOC1..PIOC8, DB8..DB15 on PIOC12..PIOC19
+//
+#define CMASKH (0xFF00<<4)
+#define CMASKL (0x00FF<<1)
+#define CMASK (CMASKH | CMASKL)
+#define write_8(x) { PIOC->PIO_CODR = CMASKL; PIOC->PIO_SODR = (((x)&0x00FF)<<1); }
+#define write_16(x) { PIOC->PIO_CODR = CMASK; \
+ PIOC->PIO_SODR = (((x)&0x00FF)<<1)|(((x)&0xFF00)<<4); }
+#define read_16() (((PIOC->PIO_PDSR & CMASKH)>>4)|((PIOC->PIO_PDSR & CMASKL)>>1) )
+#define read_8() (read_16() & 0xFF)
+#define setWriteDir() { PIOC->PIO_OER = CMASK; PIOC->PIO_PER = CMASK; }
+#define setReadDir() { PMC->PMC_PCER0 = (1 << ID_PIOC); PIOC->PIO_ODR = CMASK; }
+#define write8(x) { write16(x & 0xFF); }
+#define write16(x) { write_16(x); WR_ACTIVE; WR_STROBE; WR_IDLE; WR_IDLE; }
+#define READ_16(dst) { RD_STROBE; RD_ACTIVE4; dst = read_16(); RD_IDLE; RD_IDLE; RD_IDLE; }
+#define READ_8(dst) { READ_16(dst); dst &= 0xFF; }
+
+// Shield Control macros.
+#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
+#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
+
+#elif defined(__SAM3X8E__) && defined(USE_ELECHOUSE_DUE_16BIT_SHIELD) //ELECHOUSE_DUE shield on DUE
+#warning USE_ELECHOUSE_DUE_16BIT_SHIELD
+#define USES_16BIT_BUS
+// configure macros for the control pins
+#define RD_PORT PIOA
+#define RD_PIN 15 //D24 Graham
+#define WR_PORT PIOA
+#define WR_PIN 14 //D23
+#define CD_PORT PIOB
+#define CD_PIN 26 //D22
+#define CS_PORT PIOA
+#define CS_PIN 7 //D31
+#define RESET_PORT PIOC
+#define RESET_PIN 1 //D33
+// configure macros for data bus
+// DB0..DB7 on PIOC2..PIOC9, DB8..DB15 on PIOC12..PIOC19
+//
+#define CMASKH (0xFF00<<4)
+#define CMASKL (0x00FF<<2)
+#define CMASK (CMASKH | CMASKL)
+#define write_8(x) { PIOC->PIO_CODR = CMASKL; PIOC->PIO_SODR = (((x)&0x00FF)<<2); }
+#define write_16(x) { PIOC->PIO_CODR = CMASK; \
+ PIOC->PIO_SODR = (((x)&0x00FF)<<2)|(((x)&0xFF00)<<4); }
+#define read_16() (((PIOC->PIO_PDSR & CMASKH)>>4)|((PIOC->PIO_PDSR & CMASKL)>>2) )
+#define read_8() (read_16() & 0xFF)
+#define setWriteDir() { PIOC->PIO_OER = CMASK; PIOC->PIO_PER = CMASK; }
+#define setReadDir() { PMC->PMC_PCER0 = (1 << ID_PIOC); PIOC->PIO_ODR = CMASK; }
+#define write8(x) { write16(x & 0xFF); }
+#define write16(x) { write_16(x); WR_ACTIVE; WR_STROBE; WR_IDLE; WR_IDLE; }
+#define READ_16(dst) { RD_STROBE; RD_ACTIVE4; dst = read_16(); RD_IDLE; RD_IDLE; RD_IDLE; }
+#define READ_8(dst) { READ_16(dst); dst &= 0xFF; }
+
+// Shield Control macros.
+#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
+#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
+
+#elif defined(__SAM3X8E__) && defined(USE_MEGA_16BIT_SHIELD) //regular MEGA shield on DUE
+#warning USE_MEGA_16BIT_SHIELD
+#define USES_16BIT_BUS
+// configure macros for the control pins
+#define RD_PORT PIOA
+#define RD_PIN 20 //D43
+#define WR_PORT PIOC
+#define WR_PIN 7 //D39
+#define CD_PORT PIOC
+#define CD_PIN 6 //D38
+#define CS_PORT PIOC
+#define CS_PIN 8 //D40
+#define RESET_PORT PIOC
+#define RESET_PIN 9 //D41
+// configure macros for data bus
+//
+#define AMASK ((1<<7)|(3<<14)) //PA7, PA14-PA15
+#define BMASK (1<<26) //PB26
+#define CMASK (31<<1) //PC1-PC5
+#define DMASK ((15<<0)|(1<<6)|(3<<9)) //PD0-PD3, PD6, PD9-PD10
+
+#define write_16(x) { PIOA->PIO_CODR = AMASK; PIOB->PIO_CODR = BMASK; PIOC->PIO_CODR = CMASK; PIOD->PIO_CODR = DMASK; \
+ PIOA->PIO_SODR = (((x)&(1<<6))<<1)|(((x)&(3<<9))<<5); \
+ PIOB->PIO_SODR = (((x)&(1<<8))<<18); \
+ PIOC->PIO_SODR = (((x)&(1<<0))<<5); \
+ PIOC->PIO_SODR = (((x)&(1<<1))<<3); \
+ PIOC->PIO_SODR = (((x)&(1<<2))<<1); \
+ PIOC->PIO_SODR = (((x)&(1<<3))>>1); \
+ PIOC->PIO_SODR = (((x)&(1<<4))>>3); \
+ PIOD->PIO_SODR = (((x)&(1<<7))<<2)|(((x)&(1<<5))<<5)|(((x)&(15<<11))>>11)|(((x)&(1<<15))>>9); \
+ }
+
+/*
+#define write_16(VL) { PIOA->PIO_CODR = AMASK; PIOC->PIO_CODR = CMASK; PIOD->PIO_CODR = DMASK; \
+ REG_PIOA_SODR=((((VL)>>8) & 0x06)<<13) | ((VL & 0x40)<<1);\
+ if ((VL)&(1<<8)) REG_PIOB_SODR=(1<<26); else REG_PIOB_CODR=(1<<26);\
+ REG_PIOC_SODR=((VL & 0x01)<<5) | ((VL & 0x02)<<3) | ((VL & 0x04)<<1) | ((VL & 0x08)>>1) | ((VL & 0x10)>>3);\
+ REG_PIOD_SODR=((((VL)>>8) & 0x78)>>3) | ((((VL)>>8) & 0x80)>>1) | ((VL & 0x20)<<5) | ((VL & 0x80)<<2);\
+}
+*/
+#define read_16() ( 0\
+ |((PIOC->PIO_PDSR & (1<<5))>>5)\
+ |((PIOC->PIO_PDSR & (1<<4))>>3)\
+ |((PIOC->PIO_PDSR & (1<<3))>>1)\
+ |((PIOC->PIO_PDSR & (1<<2))<<1)\
+ |((PIOC->PIO_PDSR & (1<<1))<<3)\
+ |((PIOD->PIO_PDSR & (1<<10))>>5)\
+ |((PIOA->PIO_PDSR & (1<<7))>>1)\
+ |((PIOD->PIO_PDSR & (1<<9))>>2)\
+ |((PIOB->PIO_PDSR & (1<<26))>>18)\
+ |((PIOA->PIO_PDSR & (3<<14))>>5)\
+ |((PIOD->PIO_PDSR & (15<<0))<<11)\
+ |((PIOD->PIO_PDSR & (1<<6))<<9)\
+ )
+#define read_8() (read_16() & 0xFF)
+#define setWriteDir() {\
+ PIOA->PIO_OER = AMASK; PIOA->PIO_PER = AMASK; \
+ PIOB->PIO_OER = BMASK; PIOB->PIO_PER = BMASK; \
+ PIOC->PIO_OER = CMASK; PIOC->PIO_PER = CMASK; \
+ PIOD->PIO_OER = DMASK; PIOD->PIO_PER = DMASK; \
+ }
+#define setReadDir() { \
+ PMC->PMC_PCER0 = (1 << ID_PIOA)|(1 << ID_PIOB)|(1 << ID_PIOC)|(1 << ID_PIOD); \
+ PIOA->PIO_ODR = AMASK; \
+ PIOB->PIO_ODR = BMASK; \
+ PIOC->PIO_ODR = CMASK; \
+ PIOD->PIO_ODR = DMASK; \
+ }
+#define write8(x) { write16(x & 0xFF); }
+// ILI9486 is slower than ILI9481
+#define write16(x) { write_16(x); WR_ACTIVE8; WR_STROBE; WR_IDLE4;}
+#define READ_16(dst) { RD_STROBE; RD_ACTIVE4; dst = read_16(); RD_IDLE; RD_IDLE; RD_IDLE; }
+#define READ_8(dst) { READ_16(dst); dst &= 0xFF; }
+
+// Shield Control macros.
+#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
+#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
+
+#elif defined(__SAM3X8E__) && defined(USE_MEGA_8BIT_SHIELD) //regular CTE shield on DUE
+#warning USE_MEGA_8BIT_SHIELD for peloxp
+// configure macros for the control pins
+#define RD_PORT PIOA
+#define RD_PIN 20 //D43
+#define WR_PORT PIOC
+#define WR_PIN 7 //D39
+#define CD_PORT PIOC
+#define CD_PIN 6 //D38
+#define CS_PORT PIOC
+#define CS_PIN 8 //D40
+#define RESET_PORT PIOC
+#define RESET_PIN 9 //D41
+// configure macros for data bus
+//
+#define AMASK ((3<<14)) //PA14-PA15 D23-D24
+#define BMASK (1<<26) //PB26 D22
+#define DMASK ((15<<0)|(1<<6)) //PD0-PD3, PD6 D25-D28,D29
+
+#define write_8(x) { PIOA->PIO_CODR = AMASK; PIOB->PIO_CODR = BMASK; PIOD->PIO_CODR = DMASK; \
+ PIOB->PIO_SODR = (((x)&(1<<0))<<26); \
+ PIOA->PIO_SODR = (((x)&(3<<1))<<13); \
+ PIOD->PIO_SODR = (((x)&(15<<3))>>3); \
+ PIOD->PIO_SODR = (((x)&(1<<7))>>1); \
+ }
+
+#define read_8() ( 0\
+ |((PIOB->PIO_PDSR & (1<<26))>>26)\
+ |((PIOA->PIO_PDSR & (3<<14))>>13)\
+ |((PIOD->PIO_PDSR & (15<<0))<<3)\
+ |((PIOD->PIO_PDSR & (1<<6))<<1)\
+ )
+
+#define setWriteDir() {\
+ PIOA->PIO_OER = AMASK; PIOA->PIO_PER = AMASK; \
+ PIOB->PIO_OER = BMASK; PIOB->PIO_PER = BMASK; \
+ PIOD->PIO_OER = DMASK; PIOD->PIO_PER = DMASK; \
+ }
+#define setReadDir() { \
+ PMC->PMC_PCER0 = (1 << ID_PIOA)|(1 << ID_PIOB)|(1 << ID_PIOC)|(1 << ID_PIOD); \
+ PIOA->PIO_ODR = AMASK; \
+ PIOB->PIO_ODR = BMASK; \
+ PIOD->PIO_ODR = DMASK; \
+ }
+
+// ILI9486 is slower than ILI9481. HX8357-D is slower
+#define write8(x) { write_8(x); WR_ACTIVE4; WR_STROBE; WR_IDLE; WR_IDLE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; RD_ACTIVE4; dst = read_8(); RD_IDLE; RD_IDLE; RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+// Shield Control macros.
+#define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin))
+#define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin))
+
+#elif defined(__MK20DX256__) && defined(USE_BOBCACHELOT_TEENSY) // special for BOBCACHEALOT_TEENSY
+#warning special for BOBCACHEALOT_TEENSY
+#define RD_PORT GPIOD
+#define RD_PIN 1
+#define WR_PORT GPIOC
+#define WR_PIN 0
+#define CD_PORT GPIOB
+#define CD_PIN 0
+#define CS_PORT GPIOB
+#define CS_PIN 1
+#define RESET_PORT GPIOB
+#define RESET_PIN 3
+
+// configure macros for the data pins
+#define CMASK ((1<<3))
+#define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7))
+
+ #define write_8(d) { \
+ GPIOC_PCOR = CMASK; GPIOD_PCOR = DMASK; \
+ GPIOC_PSOR = (((d) & (1<<1)) << 2); \
+ GPIOD_PSOR = (d) & DMASK; \
+ }
+ #define read_8() ( (GPIOD_PDIR & DMASK) | (GPIOC_PDIR & (1<<3)) >> 2 )
+ #define setWriteDir() {GPIOC_PDDR |= CMASK;GPIOD_PDDR |= DMASK; }
+ #define setReadDir() {GPIOC_PDDR &= ~CMASK;GPIOD_PDDR &= ~DMASK; }
+
+#define write8(x) { write_8(x); WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+#define PASTE(x, y) x ## y
+
+#define PIN_LOW(port, pin) PASTE(port, _PCOR) = (1<<(pin))
+#define PIN_HIGH(port, pin) PASTE(port, _PSOR) = (1<<(pin))
+#define PIN_OUTPUT(port, pin) PASTE(port, _PDDR) |= (1<<(pin))
+
+#elif defined(USE_MY_BLUEPILL) && (defined(ARDUINO_GENERIC_STM32F103C) || defined(ARDUINO_BLUEPILL_F103C8))
+#warning Uno Shield on MY BLUEPILL
+
+//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | |RD |WR |RS |CS |RST| |SD_SS|SD_DI|SD_DO|SD_SCK| |SDA|SCL|
+//STM32 pin |PA3 |PA2 |PA1|PA0|PB7|PB6|PA10|PA9| |PB1|PB0|PA7|PA6|PA5| |PB12 |PB15 |PB14 |PB13 | |PB9|PB8|
+
+#if defined(ARDUINO_BLUEPILL_F103C8) //regular CMSIS libraries
+#define REGS(x) x
+#define GPIO_INIT() { RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | RCC_APB2ENR_AFIOEN; \
+ AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_1;}
+#else //weird Maple libraries
+#define REGS(x) regs->x
+#endif
+
+#define WRITE_DELAY { }
+#define READ_DELAY { RD_ACTIVE; }
+#define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); }
+#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
+#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
+#define PIN_OUTPUT(port, pin) {\
+ if (pin < 8) {GP_OUT(port, CRL, 0xF<<((pin)<<2));} \
+ else {GP_OUT(port, CRH, 0xF<<((pin&7)<<2));} \
+ }
+#define PIN_INPUT(port, pin) { \
+ if (pin < 8) { GP_INP(port, CRL, 0xF<<((pin)<<2)); } \
+ else { GP_INP(port, CRH, 0xF<<((pin&7)<<2)); } \
+ }
+#define PIN_HIGH(port, pin) (port)-> REGS(BSRR) = (1<<(pin))
+#define PIN_LOW(port, pin) (port)-> REGS(BSRR) = (1<<((pin)+16))
+
+#define RD_PORT GPIOB
+#define RD_PIN 1
+#define WR_PORT GPIOB
+#define WR_PIN 0
+#define CD_PORT GPIOA
+#define CD_PIN 7
+#define CS_PORT GPIOA
+#define CS_PIN 6
+#define RESET_PORT GPIOA
+#define RESET_PIN 5
+
+// configure macros for the data pins
+#define AMASK 0x060F
+#define BMASK 0x00C0
+#define write_8(d) { GPIOA->REGS(BSRR) = AMASK << 16; GPIOB->REGS(BSRR) = BMASK << 16; \
+ GPIOA->REGS(BSRR) = (((d) & 3) << 9) | (((d) & 0xF0) >> 4); \
+ GPIOB->REGS(BSRR) = (((d) & 0x0C) << 4); \
+ }
+#define read_8() (((GPIOA->REGS(IDR) & (3<<9)) >> 9) | ((GPIOA->REGS(IDR) & (0x0F)) << 4) | ((GPIOB->REGS(IDR) & (3<<6)) >> 4))
+// PA10,PA9 PA3-PA0 PB7,PB6
+#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFF0); GP_OUT(GPIOA, CRL, 0xFFFF); GP_OUT(GPIOB, CRL, 0xFF000000); }
+#define setReadDir() {GP_INP(GPIOA, CRH, 0xFF0); GP_INP(GPIOA, CRL, 0xFFFF); GP_INP(GPIOB, CRL, 0xFF000000); }
+
+#define write8(x) { write_8(x); WRITE_DELAY; WR_STROBE; }
+#define write16(x) { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { uint8_t hi; READ_8(hi); READ_8(dst); dst |= (hi << 8); }
+
+//####################################### ADIGITALEU_TEENSY ############################
+//UNTESTED
+#elif defined(__MK66FX1M0__) && defined(USE_ADIGITALEU_TEENSY) // 16bit on a Teensy 3.6
+#warning "Teensy 3.6 16bit port C & D only (for now)"
+// Note: Port usage explained in UTFT Teensy edition ...\libraries\UTFT\hardware\arm\HW_Teensy3.h"
+
+#define USES_16BIT_BUS
+
+#define WRITE_DELAY { WR_ACTIVE8; }
+#define READ_DELAY { RD_ACTIVE16; }
+
+#define RD_PORT GPIOA
+#define RD_PIN 16 //28 RD
+#define WR_PORT GPIOA
+#define WR_PIN 5 //25 WR
+#define CD_PORT GPIOE
+#define CD_PIN 26 //24 RS
+#define CS_PORT GPIOA
+#define CS_PIN 14 //26 CS
+#define RESET_PORT GPIOA
+#define RESET_PIN 15 //27 Reset
+
+#define write_8(d) { GPIOC_PDOR = d; }
+#define write_16(d) { GPIOC_PDOR = d; GPIOD_PDOR = (d >> 8);}
+
+#define read_8() (GPIOC_PDIR)
+#define read_16() (GPIOC_PDIR | GPIOD_PDIR << 8)
+
+#define setWriteDir() {GPIOC_PDDR |= 0xFF; GPIOD_PDDR |= 0xFF; }
+#define setReadDir() {GPIOC_PDDR &= ~0xFF; GPIOD_PDDR &= ~0xFF; }
+
+#define write8(x) {write_8(x); WRITE_DELAY; WR_STROBE }
+#define write16(x) {write_16(x); WRITE_DELAY; WR_STROBE }
+
+#define READ_8(dst) { RD_STROBE; READ_DELAY; dst = read_8(); RD_IDLE; }
+#define READ_16(dst) { RD_STROBE; READ_DELAY; dst = read_16(); RD_IDLE;}
+
+//Data: Teensy pins -> D0-D15 :
+// Teensy probably initialises some pins for Analog, Timer, Alternate, ...
+// so it is probably wise to use pinMode(n, OUTPUT) for all the control and data lines
+#define GPIO_INIT() {pinMode(2, OUTPUT); for (int i = 5; i <= 15; i++) pinMode(i, OUTPUT); for (int i = 20; i <= 28; i++) pinMode(i, OUTPUT);}
+
+#define PASTE(x, y) x ## y
+
+#define PIN_LOW(port, pin) PASTE(port, _PCOR) = (1<<(pin))
+#define PIN_HIGH(port, pin) PASTE(port, _PSOR) = (1<<(pin))
+#define PIN_OUTPUT(port, pin) PASTE(port, _PDDR) |= (1<<(pin))
+
+#else
+#define USE_SPECIAL_FAIL
+#endif
+
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MCUFRIEND_kbv/utility/pin_shield_1.h Wed Apr 21 14:54:37 2021 +0000
@@ -0,0 +1,959 @@
+#ifndef PIN_SHIELD_1_H_
+#define PIN_SHIELD_1_H_
+
+// just provide macros for the Arduino pins
+// i.e. PIN_LOW(), PIN_HIGH(), PIN_OUTPUT(), PIN_INPUT(), PIN_READ()
+
+#define LPC810 810
+#define LPC812 812
+#define LPC1343 1343
+#define LPC1768 1768
+#define LPC2103 2103
+#define LPC2148 2148
+
+#define ISTARGET_NUCLEO64 (0 \
+ || defined(TARGET_NUCLEO_F072RB) \
+ || defined(TARGET_NUCLEO_F103RB) \
+ || defined(TARGET_NUCLEO_F401RE) \
+ || defined(TARGET_NUCLEO_F411RE) \
+ || defined(TARGET_NUCLEO_F446RE) \
+ || defined(TARGET_NUCLEO_L152RE) \
+ || defined(TARGET_NUCLEO_L433RC_P) \
+ || defined(TARGET_NUCLEO_L476RG) \
+ )
+
+#define ISTARGET_NUCLEO144 (0 \
+ || defined(TARGET_NUCLEO_F767ZI) \
+ )
+
+//#warning Using pin_SHIELD_1.h
+
+#if 0
+#elif defined(MY_BLUEPILL)
+#define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1))
+ #if defined(__CC_ARM)
+ #include <STM32F10X.h>
+ #else
+ #include <STM32F1XX.h>
+ #endif
+ #define D0_PORT GPIOB
+ #define D0_PIN 11
+ #define D1_PORT GPIOB
+ #define D1_PIN 10
+ #define D2_PORT GPIOB
+ #define D2_PIN 6
+ #define D3_PORT GPIOB
+ #define D3_PIN 7
+ #define D4_PORT GPIOA
+ #define D4_PIN 0
+ #define D5_PORT GPIOA
+ #define D5_PIN 1
+ #define D6_PORT GPIOA
+ #define D6_PIN 2
+ #define D7_PORT GPIOA
+ #define D7_PIN 3
+ #define D8_PORT GPIOA
+ #define D8_PIN 9
+ #define D9_PORT GPIOA
+ #define D9_PIN 10
+ #define D10_PORT GPIOB
+ #define D10_PIN 12
+ #define D11_PORT GPIOB
+ #define D11_PIN 15
+ #define D12_PORT GPIOB
+ #define D12_PIN 14
+ #define D13_PORT GPIOB
+ #define D13_PIN 13
+ #define A0_PORT GPIOB
+ #define A0_PIN 1
+ #define A1_PORT GPIOB
+ #define A1_PIN 0
+ #define A2_PORT GPIOA
+ #define A2_PIN 7
+ #define A3_PORT GPIOA
+ #define A3_PIN 6
+ #define A4_PORT GPIOA
+ #define A4_PIN 5
+ #define A5_PORT GPIOB
+ #define A5_PIN 4
+// Shield Control macros
+#define PIN_LOW(port, pin) (port)->BSRR = (1<<((pin)+16))
+#define PIN_HIGH(port, pin) (port)->BSRR = (1<<(pin))
+#define PIN_READ(port, pin) (port)->IDR & (1<<(pin))
+#define PIN_MODE4(reg, pin, mode) reg=(reg&~(0xF<<((pin)<<2)))|(mode<<((pin)<<2))
+#define PIN_OUTPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x3); else PIN_MODE4((port)->CRL, pin, 0x3); } //50MHz push-pull only 0-7
+#define PIN_INPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x4); else PIN_MODE4((port)->CRL, pin, 0x4); } //input
+
+
+#elif defined(BLUEPILL)
+#define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1))
+ #if defined(__CC_ARM)
+ #include <STM32F10X.h>
+ #else
+ #include <STM32F1XX.h>
+ #endif
+ #define D0_PORT GPIOA
+ #define D0_PIN 10
+ #define D1_PORT GPIOA
+ #define D1_PIN 9
+ #define D2_PORT GPIOA
+ #define D2_PIN 2
+ #define D3_PORT GPIOA
+ #define D3_PIN 3
+ #define D4_PORT GPIOA
+ #define D4_PIN 4
+ #define D5_PORT GPIOA
+ #define D5_PIN 5
+ #define D6_PORT GPIOA
+ #define D6_PIN 6
+ #define D7_PORT GPIOA
+ #define D7_PIN 7
+ #define D8_PORT GPIOA
+ #define D8_PIN 0
+ #define D9_PORT GPIOA
+ #define D9_PIN 1
+ #define D10_PORT GPIOA
+ #define D10_PIN 15
+ #define D11_PORT GPIOB
+ #define D11_PIN 5
+ #define D12_PORT GPIOB
+ #define D12_PIN 4
+ #define D13_PORT GPIOB
+ #define D13_PIN 3
+ #define A0_PORT GPIOB
+ #define A0_PIN 5 //original pcb uses SPI pin
+// #define A0_PIN 0 //hardware mod to Adapter to PB0. Allows use of PB5 for SD Card
+ #define A1_PORT GPIOB
+ #define A1_PIN 6
+ #define A2_PORT GPIOB
+ #define A2_PIN 7
+ #define A3_PORT GPIOB
+ #define A3_PIN 8
+ #define A4_PORT GPIOB
+ #define A4_PIN 9
+ #define A5_PORT GPIOB
+ #define A5_PIN 10
+// Shield Control macros
+#define PIN_LOW(port, pin) (port)->BSRR = (1<<((pin)+16))
+#define PIN_HIGH(port, pin) (port)->BSRR = (1<<(pin))
+#define PIN_READ(port, pin) (port)->IDR & (1<<(pin))
+#define PIN_MODE4(reg, pin, mode) reg=(reg&~(0xF<<((pin)<<2)))|(mode<<((pin)<<2))
+#define PIN_OUTPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x3); else PIN_MODE4((port)->CRL, pin, 0x3); } //50MHz push-pull only 0-7
+#define PIN_INPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x4); else PIN_MODE4((port)->CRL, pin, 0x4); } //input
+
+
+#elif defined(ITEADMAPLE)
+#define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1))
+ #if defined(__CC_ARM)
+ #include <STM32F10X.h>
+ #else
+ #include <STM32F1XX.h>
+ #endif
+ #define D0_PORT GPIOA
+ #define D0_PIN 3
+ #define D1_PORT GPIOA
+ #define D1_PIN 2
+ #define D2_PORT GPIOA
+ #define D2_PIN 0
+ #define D3_PORT GPIOA
+ #define D3_PIN 1
+ #define D4_PORT GPIOB
+ #define D4_PIN 5
+ #define D5_PORT GPIOB
+ #define D5_PIN 6
+ #define D6_PORT GPIOA
+ #define D6_PIN 8
+ #define D7_PORT GPIOA
+ #define D7_PIN 9
+ #define D8_PORT GPIOA
+ #define D8_PIN 10
+ #define D9_PORT GPIOB
+ #define D9_PIN 7
+ #define D10_PORT GPIOA
+ #define D10_PIN 4
+ #define D11_PORT GPIOA
+ #define D11_PIN 7
+ #define D12_PORT GPIOA
+ #define D12_PIN 6
+ #define D13_PORT GPIOA
+ #define D13_PIN 5
+ #define A0_PORT GPIOC
+ #define A0_PIN 0
+ #define A1_PORT GPIOC
+ #define A1_PIN 1
+ #define A2_PORT GPIOC
+ #define A2_PIN 2
+ #define A3_PORT GPIOC
+ #define A3_PIN 3
+ #define A4_PORT GPIOC
+ #define A4_PIN 4
+ #define A5_PORT GPIOC
+ #define A5_PIN 5
+// Shield Control macros
+#define PIN_LOW(port, pin) (port)->BSRR = (1<<((pin)+16))
+#define PIN_HIGH(port, pin) (port)->BSRR = (1<<(pin))
+#define PIN_READ(port, pin) (port)->IDR & (1<<(pin))
+#define PIN_MODE4(reg, pin, mode) reg=(reg&~(0xF<<((pin)<<2)))|(mode<<((pin)<<2))
+#define PIN_OUTPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x3); else PIN_MODE4((port)->CRL, pin, 0x3); } //50MHz push-pull only 0-7
+#define PIN_INPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x4); else PIN_MODE4((port)->CRL, pin, 0x4); } //input
+
+
+#elif defined(NUCLEO144) || ISTARGET_NUCLEO144
+#define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1))
+#if __MBED__
+#warning MBED knows everything
+#elif defined(STM32F767xx)
+ #include <STM32F7XX.h>
+#endif
+ #define D0_PORT GPIOG
+ #define D0_PIN 9
+ #define D1_PORT GPIOG
+ #define D1_PIN 14
+ #define D2_PORT GPIOF
+ #define D2_PIN 15
+ #define D3_PORT GPIOE
+ #define D3_PIN 13
+ #define D4_PORT GPIOF
+ #define D4_PIN 14
+ #define D5_PORT GPIOE
+ #define D5_PIN 11
+ #define D6_PORT GPIOE
+ #define D6_PIN 9
+ #define D7_PORT GPIOF
+ #define D7_PIN 13
+ #define D8_PORT GPIOF
+ #define D8_PIN 12
+ #define D9_PORT GPIOD
+ #define D9_PIN 15
+ #define D10_PORT GPIOD
+ #define D10_PIN 14
+ #define D11_PORT GPIOA
+ #define D11_PIN 7
+ #define D12_PORT GPIOA
+ #define D12_PIN 6
+ #define D13_PORT GPIOA
+ #define D13_PIN 5
+ #define A0_PORT GPIOA
+ #define A0_PIN 3
+ #define A1_PORT GPIOC
+ #define A1_PIN 0
+ #define A2_PORT GPIOC
+ #define A2_PIN 3
+ #define A3_PORT GPIOF
+ #define A3_PIN 3
+ #define A4_PORT GPIOF
+ #define A4_PIN 5
+ #define A5_PORT GPIOF
+ #define A5_PIN 10
+// Shield Control macros
+#define PIN_LOW(port, pin) (port)->BSRR = (1<<((pin)+16))
+#define PIN_HIGH(port, pin) (port)->BSRR = (1<<(pin))
+//#define PIN_LOW(port, pin) (port)->ODR &= ~(1<<(pin))
+//#define PIN_HIGH(port, pin) (port)->ODR |= (1<<(pin))
+#define PIN_READ(port, pin) (port)->IDR & (1<<(pin))
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+#define PIN_INPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x0) //.kbv check this
+
+#elif defined(NUCLEO) || ISTARGET_NUCLEO64
+#define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1))
+#if __MBED__
+#warning MBED knows everything
+#elif defined(STM32F072xB)
+ #include <STM32F0XX.h>
+#elif defined(STM32F103xB)
+ #if defined(__CC_ARM)
+ #include <STM32F10X.h>
+ #else
+ #include <STM32F1XX.h>
+ #endif
+#elif defined(STM32L476xx) || defined(STM32L433xx)
+ #include <STM32L4XX.h>
+#elif defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+ #include <STM32F4XX.h>
+#endif
+ #define D0_PORT GPIOA
+ #define D0_PIN 3
+ #define D1_PORT GPIOA
+ #define D1_PIN 2
+ #define D2_PORT GPIOA
+ #define D2_PIN 10
+ #define D3_PORT GPIOB
+ #define D3_PIN 3
+ #define D4_PORT GPIOB
+ #define D4_PIN 5
+ #define D5_PORT GPIOB
+ #define D5_PIN 4
+ #define D6_PORT GPIOB
+ #define D6_PIN 10
+ #define D7_PORT GPIOA
+ #define D7_PIN 8
+ #define D8_PORT GPIOA
+ #define D8_PIN 9
+ #define D9_PORT GPIOC
+ #define D9_PIN 7
+ #define D10_PORT GPIOB
+ #define D10_PIN 6
+ #define D11_PORT GPIOA
+ #define D11_PIN 7
+ #define D12_PORT GPIOA
+ #define D12_PIN 6
+ #define D13_PORT GPIOA
+ #define D13_PIN 5
+ #define A0_PORT GPIOA
+ #define A0_PIN 0
+ #define A1_PORT GPIOA
+ #define A1_PIN 1
+ #define A2_PORT GPIOA
+ #define A2_PIN 4
+ #define A3_PORT GPIOB
+ #define A3_PIN 0
+ #define A4_PORT GPIOC
+ #define A4_PIN 1
+ #define A5_PORT GPIOC
+ #define A5_PIN 0
+// Shield Control macros
+#define PIN_LOW(port, pin) (port)->BSRR = (1<<((pin)+16))
+#define PIN_HIGH(port, pin) (port)->BSRR = (1<<(pin))
+//#define PIN_LOW(port, pin) (port)->ODR &= ~(1<<(pin))
+//#define PIN_HIGH(port, pin) (port)->ODR |= (1<<(pin))
+#define PIN_READ(port, pin) (port)->IDR & (1<<(pin))
+#if defined(STM32F103xB)
+ #warning STM32F103xB ******************************
+#define PIN_MODE4(reg, pin, mode) reg=(reg&~(0xF<<((pin)<<2)))|(mode<<((pin)<<2))
+#define PIN_OUTPUT(port, pin) PIN_MODE4((port)->CRL, pin, 0x3) //50MHz push-pull only 0-7
+#define PIN_INPUT(port, pin) PIN_MODE4((port)->CRL, pin, 0x4) //digital input
+#else
+#define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1)
+#define PIN_INPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x0) //.kbv check this
+#endif
+
+#elif __TARGET_PROCESSOR == LPC1768
+ #include <LPC17xx.h>
+// configure macros for the control pins
+ #define D0_PORT LPC_GPIO0
+ #define D0_PIN 3
+ #define D1_PORT LPC_GPIO0
+ #define D1_PIN 2
+ #define D2_PORT LPC_GPIO0
+ #define D2_PIN 24 //p16
+ #define D3_PORT LPC_GPIO0
+ #define D3_PIN 23 //p15
+ #define D4_PORT LPC_GPIO0
+ #define D4_PIN 16 //p14
+ #define D5_PORT LPC_GPIO0
+ #define D5_PIN 15 //p13
+ #define D6_PORT LPC_GPIO0
+ #define D6_PIN 17 //p12
+ #define D7_PORT LPC_GPIO0
+ #define D7_PIN 18 //p11
+ #define D8_PORT LPC_GPIO0
+ #define D8_PIN 1 //p10
+ #define D9_PORT LPC_GPIO0
+ #define D9_PIN 0 //p9
+ #define D10_PORT LPC_GPIO0
+ #define D10_PIN 6 //p8
+ #define D11_PORT LPC_GPIO0
+ #define D11_PIN 9 //p5
+ #define D12_PORT LPC_GPIO0
+ #define D12_PIN 8 //p6 miso
+ #define D13_PORT LPC_GPIO0
+ #define D13_PIN 7 //p7
+ #define A0_PORT LPC_GPIO0
+ #define A0_PIN 25 //p17
+ #define A1_PORT LPC_GPIO0
+ #define A1_PIN 26 //p18
+ #define A2_PORT LPC_GPIO1
+ #define A2_PIN 30 //p19
+ #define A3_PORT LPC_GPIO1
+ #define A3_PIN 31 //p20
+ #define A4_PORT LPC_GPIO0
+ #define A4_PIN 10 //p28
+ #define A5_PORT LPC_GP100
+ #define A5_PIN 11 //p27
+// Shield Control macros
+#define PIN_LOW(port, pin) (port)->FIOCLR = (1u<<(pin))
+#define PIN_HIGH(port, pin) (port)->FIOSET = (1u<<(pin))
+#define PIN_OUTPUT(port, pin) (port)->FIODIR |= (1u<<(pin))
+#define PIN_INPUT(port, pin) (port)->FIODIR &= ~(1u<<(pin))
+#define PIN_READ(port, pin) (port)->FIOPIN & (1u<<(pin))
+
+#elif (defined(MK20D7) && defined(TEENSY)) || defined(TARGET_TEENSY3_1)
+#if __MBED__
+#warning MBED knows everything
+#else
+ #include <MK20D5.h>
+#endif
+ #define D0_PORT PTB
+ #define D0_PIN 16
+ #define D1_PORT PTB
+ #define D1_PIN 17
+ #define D2_PORT PTD
+ #define D2_PIN 0
+ #define D3_PORT PTA
+ #define D3_PIN 12
+ #define D4_PORT PTA
+ #define D4_PIN 13
+ #define D5_PORT PTD
+ #define D5_PIN 7
+ #define D6_PORT PTD
+ #define D6_PIN 4
+ #define D7_PORT PTD
+ #define D7_PIN 2
+ #define D8_PORT PTD
+ #define D8_PIN 3
+ #define D9_PORT PTC
+ #define D9_PIN 3
+ #define D10_PORT PTC
+ #define D10_PIN 4
+ #define D11_PORT PTC
+ #define D11_PIN 6
+ #define D12_PORT PTC
+ #define D12_PIN 7
+ #define D13_PORT PTC
+ #define D13_PIN 5
+ #define A0_PORT PTD
+ #define A0_PIN 1
+ #define A1_PORT PTC
+ #define A1_PIN 0
+ #define A2_PORT PTB
+ #define A2_PIN 0
+ #define A3_PORT PTB
+ #define A3_PIN 1
+ #define A4_PORT PTB
+ #define A4_PIN 3
+ #define A5_PORT PTB
+ #define A5_PIN 2
+// Shield Control macros. Deliberately avoid the IOSET registers
+#define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin))
+#define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin))
+//#define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin))
+//#define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin))
+#define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin))
+#define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin))
+
+
+#elif defined(MKL25Z4) || defined(TARGET_KL25Z)
+ #include <MKL25Z4.h>
+ #define D0_PORT PTA
+ #define D0_PIN 1
+ #define D1_PORT PTA
+ #define D1_PIN 2
+ #define D2_PORT PTD
+ #define D2_PIN 4
+ #define D3_PORT PTA
+ #define D3_PIN 12
+ #define D4_PORT PTA
+ #define D4_PIN 4
+ #define D5_PORT PTA
+ #define D5_PIN 5
+ #define D6_PORT PTC
+ #define D6_PIN 8
+ #define D7_PORT PTC
+ #define D7_PIN 9
+ #define D8_PORT PTA
+ #define D8_PIN 13
+ #define D9_PORT PTD
+ #define D9_PIN 5
+ #define D10_PORT PTD
+ #define D10_PIN 0
+ #define D11_PORT PTD
+ #define D11_PIN 2
+ #define D12_PORT PTD
+ #define D12_PIN 3
+ #define D13_PORT PTD
+ #define D13_PIN 1
+ #define A0_PORT PTB
+ #define A0_PIN 0
+ #define A1_PORT PTB
+ #define A1_PIN 1
+ #define A2_PORT PTB
+ #define A2_PIN 2
+ #define A3_PORT PTB
+ #define A3_PIN 3
+ #define A4_PORT PTC
+ #define A4_PIN 2
+ #define A5_PORT PTC
+ #define A5_PIN 1
+// Shield Control macros. Deliberately avoid the IOSET registers
+#define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin))
+#define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin))
+//#define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin))
+//#define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin))
+#define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin))
+#define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin))
+
+#elif defined(MKL26Z4)
+ #include <MKL26Z4.h>
+ #define D0_PORT PTA
+ #define D0_PIN 1
+ #define D1_PORT PTA
+ #define D1_PIN 2
+ #define D2_PORT PTD
+ #define D2_PIN 3 //PTD4 on KL25
+ #define D3_PORT PTA
+ #define D3_PIN 12
+ #define D4_PORT PTA
+ #define D4_PIN 4
+ #define D5_PORT PTA
+ #define D5_PIN 5
+ #define D6_PORT PTC
+ #define D6_PIN 8
+ #define D7_PORT PTC
+ #define D7_PIN 9
+ #define D8_PORT PTA
+ #define D8_PIN 13
+ #define D9_PORT PTD
+ #define D9_PIN 2 //PTD5 on KL25
+ #define D10_PORT PTD
+ #define D10_PIN 4 //PTD0
+ #define D11_PORT PTD
+ #define D11_PIN 6 //PTD2
+ #define D12_PORT PTD
+ #define D12_PIN 7 //PTD3
+ #define D13_PORT PTD
+ #define D13_PIN 5 //PTD1
+ #define A0_PORT PTB
+ #define A0_PIN 0
+ #define A1_PORT PTB
+ #define A1_PIN 1
+ #define A2_PORT PTB
+ #define A2_PIN 2
+ #define A3_PORT PTB
+ #define A3_PIN 3
+ #define A4_PORT PTC
+ #define A4_PIN 2
+ #define A5_PORT PTC
+ #define A5_PIN 1
+// Shield Control macros. Deliberately avoid the IOSET registers
+#define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin))
+#define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin))
+//#define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin))
+//#define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin))
+#define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin))
+#define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin))
+
+#elif defined(MKL05Z4) || defined(TARGET_KL05Z)
+ #include <MKL05Z4.h>
+ #define D0_PORT PTB
+ #define D0_PIN 2
+ #define D1_PORT PTB
+ #define D1_PIN 1
+ #define D2_PORT PTA
+ #define D2_PIN 11
+ #define D3_PORT PTB
+ #define D3_PIN 5
+ #define D4_PORT PTA
+ #define D4_PIN 10
+ #define D5_PORT PTA
+ #define D5_PIN 12
+ #define D6_PORT PTB
+ #define D6_PIN 6
+ #define D7_PORT PTB
+ #define D7_PIN 7
+ #define D8_PORT PTB
+ #define D8_PIN 13
+ #define D9_PORT PTB
+ #define D9_PIN 5
+ #define D10_PORT PTA
+ #define D10_PIN 0
+ #define D11_PORT PTA
+ #define D11_PIN 2
+ #define D12_PORT PTA
+ #define D12_PIN 3
+ #define D13_PORT PTB
+ #define D13_PIN 1
+ #define A0_PORT PTB
+ #define A0_PIN 8
+ #define A1_PORT PTB
+ #define A1_PIN 9
+ #define A2_PORT PTA
+ #define A2_PIN 8
+ #define A3_PORT PTA
+ #define A3_PIN 0
+ #define A4_PORT PTA
+ #define A4_PIN 9
+ #define A5_PORT PTB
+ #define A5_PIN 13
+// Shield Control macros
+//#define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin))
+//#define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin))
+#define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin))
+#define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin))
+#define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin))
+#define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin))
+
+#elif defined(MK20D5) || defined(TARGET_K20D50M)
+ #include <MK20D5.h>
+ #define D0_PORT PTE
+ #define D0_PIN 1
+ #define D1_PORT PTE
+ #define D1_PIN 0
+ #define D2_PORT PTA
+ #define D2_PIN 5
+ #define D3_PORT PTD
+ #define D3_PIN 4
+ #define D4_PORT PTC
+ #define D4_PIN 8
+ #define D5_PORT PTA
+ #define D5_PIN 1
+ #define D6_PORT PTC
+ #define D6_PIN 3
+ #define D7_PORT PTC
+ #define D7_PIN 4
+ #define D8_PORT PTA
+ #define D8_PIN 12
+ #define D9_PORT PTA
+ #define D9_PIN 2
+ #define D10_PORT PTC
+ #define D10_PIN 2
+ #define D11_PORT PTD
+ #define D11_PIN 2
+ #define D12_PORT PTD
+ #define D12_PIN 3
+ #define D13_PORT PTD
+ #define D13_PIN 1
+ #define A0_PORT PTC
+ #define A0_PIN 0
+ #define A1_PORT PTC
+ #define A1_PIN 1
+ #define A2_PORT PTD
+ #define A2_PIN 6
+ #define A3_PORT PTD
+ #define A3_PIN 5
+ #define A4_PORT PTB
+ #define A4_PIN 1
+ #define A5_PORT PTB
+ #define A5_PIN 0
+// Shield Control macros. Deliberately avoid the IOSET registers
+#define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin))
+#define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin))
+//#define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin))
+//#define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin))
+#define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin))
+#define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin))
+
+
+#elif defined(ZERO)
+ #include <samd21.h>
+// configure macros for the data pins
+#if defined(D21_XPRO)
+ #define D0_PORT PORT->Group[1]
+ #define D0_PIN 9
+ #define D1_PORT PORT->Group[1]
+ #define D1_PIN 8
+ #define D2_PORT PORT->Group[1]
+ #define D2_PIN 14
+ #define D3_PORT PORT->Group[1]
+ #define D3_PIN 2
+ #define D4_PORT PORT->Group[1]
+ #define D4_PIN 5
+ #define D5_PORT PORT->Group[0]
+ #define D5_PIN 21
+ #define D6_PORT PORT->Group[1]
+ #define D6_PIN 15
+ #define D7_PORT PORT->Group[0]
+ #define D7_PIN 17
+ #define D8_PORT PORT->Group[1]
+ #define D8_PIN 6
+ #define D9_PORT PORT->Group[1]
+ #define D9_PIN 7
+ #define D10_PORT PORT->Group[0]
+ #define D10_PIN 5
+ #define D11_PORT PORT->Group[0]
+ #define D11_PIN 6
+ #define D12_PORT PORT->Group[0]
+ #define D12_PIN 4
+ #define D13_PORT PORT->Group[0]
+ #define D13_PIN 7
+ #define A0_PORT PORT->Group[1]
+ #define A0_PIN 0
+ #define A1_PORT PORT->Group[1]
+ #define A1_PIN 1
+ #define A2_PORT PORT->Group[0]
+ #define A2_PIN 10
+ #define A3_PORT PORT->Group[0]
+ #define A3_PIN 11
+ #define A4_PORT PORT->Group[0]
+ #define A4_PIN 8
+ #define A5_PORT PORT->Group[0]
+ #define A5_PIN 9
+#elif defined(M0_PRO)
+ #define D0_PORT PORT->Group[0]
+ #define D0_PIN 11
+ #define D1_PORT PORT->Group[0]
+ #define D1_PIN 10
+ //M0 and Zero physical PA08 and PA14 are swapped
+ #define D2_PORT PORT->Group[0] //PA08 (Zero-D4)
+ #define D2_PIN 8
+ #define D3_PORT PORT->Group[0]
+ #define D3_PIN 9
+ #define D4_PORT PORT->Group[0] //PA14 (Zero-D2)
+ #define D4_PIN 14
+ #define D5_PORT PORT->Group[0]
+ #define D5_PIN 15
+ #define D6_PORT PORT->Group[0]
+ #define D6_PIN 20
+ #define D7_PORT PORT->Group[0]
+ #define D7_PIN 21
+ #define D8_PORT PORT->Group[0]
+ #define D8_PIN 6
+ #define D9_PORT PORT->Group[0]
+ #define D9_PIN 7
+ #define D10_PORT PORT->Group[0]
+ #define D10_PIN 18
+ #define D11_PORT PORT->Group[0]
+ #define D11_PIN 16
+ #define D12_PORT PORT->Group[0]
+ #define D12_PIN 19
+ #define D13_PORT PORT->Group[0]
+ #define D13_PIN 17
+ //M0 and Zero Arduino digital pin numbering is DIFFERENT
+ #define D16_PORT PORT->Group[0] //PA22 (SDA) (Zero-D20)
+ #define D16_PIN 22
+ #define D17_PORT PORT->Group[0] //PA23 (SCL) (Zero-D21)
+ #define D17_PIN 23
+ #define D18_PORT PORT->Group[0] //PA12 (MISO) (Zero-D22)
+ #define D18_PIN 12
+ #define D20_PORT PORT->Group[1] //PB11 (SCK) (Zero-D24)
+ #define D20_PIN 11
+ #define D21_PORT PORT->Group[1] //PB10 (MOSI) (Zero-D23)
+ #define D21_PIN 10
+ #define A0_PORT PORT->Group[0] //PA02(M0-D24) (Zero-D14)
+ #define A0_PIN 2
+ #define A1_PORT PORT->Group[1] //PB08
+ #define A1_PIN 8
+ #define A2_PORT PORT->Group[1] //PB09
+ #define A2_PIN 9
+ #define A3_PORT PORT->Group[0] //PA04
+ #define A3_PIN 4
+ #define A4_PORT PORT->Group[0] //PA05
+ #define A4_PIN 5
+ #define A5_PORT PORT->Group[1] //PB02
+ #define A5_PIN 2
+
+#endif
+// Shield Control macros.
+#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
+#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
+#define PIN_INPUT(port, pin) (port).DIR.reg &= ~(1u<<(pin))
+#define PIN_READ(port, pin) (port).IN.reg & (1u<<(pin))
+
+
+#elif defined(__AVR_ATxmegaA4U__)
+ #include <avr/io.h>
+ // PD6, PD7 is used for USB. I could have used PORTA for bus, PORTC for MSPI, SPI and remap
+ #define D0_PORT PORTE
+ #define D0_PIN 2
+ #define D1_PORT PORTE
+ #define D1_PIN 3
+ #define D2_PORT PORTC
+ #define D2_PIN 2
+ #define D3_PORT PORTC
+ #define D3_PIN 3
+ #define D4_PORT PORTC
+ #define D4_PIN 4
+ #define D5_PORT PORTC
+ #define D5_PIN 5
+ #define D6_PORT PORTC
+ #define D6_PIN 6
+ #define D7_PORT PORTC
+ #define D7_PIN 7
+ #define D8_PORT PORTC
+ #define D8_PIN 0
+ #define D9_PORT PORTC
+ #define D9_PIN 1
+ #define D10_PORT PORTD
+ #define D10_PIN 0
+ #define D11_PORT PORTD
+ #define D11_PIN 3
+ #define D12_PORT PORTD
+ #define D12_PIN 2
+ #define D13_PORT PORTD
+ #define D13_PIN 1
+ #define A0_PORT PORTB
+ #define A0_PIN 0
+ #define A1_PORT PORTB
+ #define A1_PIN 1
+ #define A2_PORT PORTB
+ #define A2_PIN 2
+ #define A3_PORT PORTB
+ #define A3_PIN 3
+ #define A4_PORT PORTE
+ #define A4_PIN 0
+ #define A5_PORT PORTE
+ #define A5_PIN 1
+// Shield Control macros.
+#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
+#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
+#define PIN_INPUT(port, pin) (port).DIR.reg &= ~(1u<<(pin))
+#define PIN_READ(port, pin) (port).IN.reg & (1u<<(pin))
+
+
+#elif defined(__AVR_ATmega4809__) && defined(ARDUINO_AVR_NANO_EVERY) //NANO-EVERY
+#warning using NANO-EVERY
+ #include <avr/io.h>
+ #define D0_PORT PORTC
+ #define D0_PIN 5
+ #define D1_PORT PORTC
+ #define D1_PIN 4
+ #define D2_PORT PORTA
+ #define D2_PIN 0
+ #define D3_PORT PORTF
+ #define D3_PIN 5
+ #define D4_PORT PORTC
+ #define D4_PIN 6
+ #define D5_PORT PORTB
+ #define D5_PIN 2
+ #define D6_PORT PORTF
+ #define D6_PIN 4
+ #define D7_PORT PORTA
+ #define D7_PIN 1
+ #define D8_PORT PORTE
+ #define D8_PIN 3
+ #define D9_PORT PORTB
+ #define D9_PIN 0
+ #define D10_PORT PORTB //PB1
+ #define D10_PIN 1
+ #define D11_PORT PORTE
+ #define D11_PIN 0
+ #define D12_PORT PORTE
+ #define D12_PIN 1
+ #define D13_PORT PORTE
+ #define D13_PIN 2
+ #define A0_PORT PORTD
+ #define A0_PIN 3
+ #define A1_PORT PORTD
+ #define A1_PIN 2
+ #define A2_PORT PORTD
+ #define A2_PIN 1
+ #define A3_PORT PORTD
+ #define A3_PIN 0
+ #define A4_PORT PORTF
+ #define A4_PIN 2
+ #define A5_PORT PORTF
+ #define A5_PIN 3
+ #define A6_PORT PORTD
+ #define A6_PIN 5
+ #define A7_PORT PORTD
+ #define A7_PIN 4
+// Shield Control macros.
+#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
+#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
+#define PIN_INPUT(port, pin) (port).DIR.reg &= ~(1u<<(pin))
+#define PIN_READ(port, pin) (port).IN.reg & (1u<<(pin))
+
+
+#elif defined(__AVR_ATmega4809__) //XPRO_4809 with XPRO_SHIELD_ADAPTER
+#warning using XPRO_4809 with XPRO_SHIELD_ADAPTER
+ #include <avr/io.h>
+ #define D0_PORT PORTA
+ #define D0_PIN 1
+ #define D1_PORT PORTA
+ #define D1_PIN 0
+ #define D2_PORT PORTB
+ #define D2_PIN 2
+ #define D3_PORT PORTC
+ #define D3_PIN 6
+ #define D4_PORT PORTC
+ #define D4_PIN 7
+ #define D5_PORT PORTF
+ #define D5_PIN 6
+ #define D6_PORT PORTB
+ #define D6_PIN 3
+ #define D7_PORT PORTE
+ #define D7_PIN 1
+ #define D8_PORT PORTA
+ #define D8_PIN 2
+ #define D9_PORT PORTA
+ #define D9_PIN 3
+ #define D10_PORT PORTA
+ #define D10_PIN 7
+ #define D11_PORT PORTA //PC5
+ #define D11_PIN 4
+ #define D12_PORT PORTA
+ #define D12_PIN 5
+ #define D13_PORT PORTA
+ #define D13_PIN 6
+ #define A0_PORT PORTD
+ #define A0_PIN 2
+ #define A1_PORT PORTD
+ #define A1_PIN 3
+ #define A2_PORT PORTD
+ #define A2_PIN 4
+ #define A3_PORT PORTD
+ #define A3_PIN 5
+ #define A4_PORT PORTC
+ #define A4_PIN 2
+ #define A5_PORT PORTC
+ #define A5_PIN 3
+// Shield Control macros.
+#define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin))
+#define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin))
+#define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
+#define PIN_INPUT(port, pin) (port).DIR.reg &= ~(1u<<(pin))
+#define PIN_READ(port, pin) (port).IN.reg & (1u<<(pin))
+
+
+#elif defined(__AVR_ATtiny1634__)
+ #include <avr/io.h>
+ //
+ #define D0_PORT PORTA //PA7
+ #define D0_PIN 7
+ #define D1_PORT PORTB //PB0
+ #define D1_PIN 0
+ #define D2_PORT PORTC //PC2
+ #define D2_PIN 2
+ #define D3_PORT PORTA //PA3
+ #define D3_PIN 3
+ #define D4_PORT PORTA //PA4
+ #define D4_PIN 4
+ #define D5_PORT PORTC //PC4
+ #define D5_PIN 4
+ #define D6_PORT PORTA //PA1
+ #define D6_PIN 1
+ #define D7_PORT PORTA //PA0
+ #define D7_PIN 0
+ #define D8_PORT PORTA //PA2
+ #define D8_PIN 2
+ #define D9_PORT PORTC //PC5
+ #define D9_PIN 5
+ #define D10_PORT PORTA //PA6
+ #define D10_PIN 6
+ #define D11_PORT PORTB //PB2
+ #define D11_PIN 2
+ #define D12_PORT PORTB //PB1
+ #define D12_PIN 1
+ #define D13_PORT PORTC //PC1
+ #define D13_PIN 1
+ #define A0_PORT PORTB //PB3
+ #define A0_PIN 3
+ #define A1_PORT PORTC //PC0
+ #define A1_PIN 0
+ #define A2_PORT PORTA //PA5
+ #define A2_PIN 5
+ #define A3_PORT PORTB //PB2
+ #define A3_PIN 2
+ #define A4_PORT PORTB //PB1
+ #define A4_PIN 1
+ #define A5_PORT PORTC //PC1
+ #define A5_PIN 1
+#else
+#error MCU unselected
+#endif // MCUs
+
+#endif //PIN_SHIELD_1_H
+#if 0
+#if defined(M0_PRO)
+#endif
+#if defined(D21_XPRO)
+#endif
+#endif
+
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/MCUFRIEND_kbv/utility/pin_shield_8.h Wed Apr 21 14:54:37 2021 +0000
@@ -0,0 +1,444 @@
+#ifndef PIN_SHIELD_8_H_
+#define PIN_SHIELD_8_H_
+
+// just provide macros for the 8-bit data bus
+// i.e. write_8(), read_8(), setWriteDir(), setReadDir()
+
+
+#define LPC810 810
+#define LPC812 812
+#define LPC1343 1343
+#define LPC1768 1768
+#define LPC2103 2103
+#define LPC2148 2148
+
+#define ISTARGET_NUCLEO64 (0 \
+ || defined(TARGET_NUCLEO_F072RB) \
+ || defined(TARGET_NUCLEO_F103RB) \
+ || defined(TARGET_NUCLEO_F401RE) \
+ || defined(TARGET_NUCLEO_F411RE) \
+ || defined(TARGET_NUCLEO_F446RE) \
+ || defined(TARGET_NUCLEO_L152RE) \
+ || defined(TARGET_NUCLEO_L433RC_P) \
+ || defined(TARGET_NUCLEO_L476RG) \
+ )
+
+#define ISTARGET_NUCLEO144 (0 \
+ || defined(TARGET_NUCLEO_F767ZI) \
+ )
+
+//#warning Using pin_SHIELD_8.h
+
+#if 0
+
+#elif defined(MY_BLUEPILL) // Uno Shield on BLUEPILL_ADAPTER
+#warning Uno Shield on MY_BLUEPILL_ADAPTER
+
+// configure macros for the data pins
+#define AMASK 0x060F
+#define BMASK 0x00C0
+#define write_8(d) { GPIOA->BSRR = AMASK << 16; GPIOB->BSRR = BMASK << 16; \
+ GPIOA->BSRR = (((d) & 3) << 9) | (((d) & 0xF0) >> 4); \
+ GPIOB->BSRR = (((d) & 0x0C) << 4); \
+ }
+#define read_8() (((GPIOA->IDR & (3<<9)) >> 9) | ((GPIOA->IDR & (0x0F)) << 4) | ((GPIOB->IDR & (3<<6)) >> 4))
+
+#define GROUP_MODE(port, reg, mask, val) {port->reg = (port->reg & ~(mask)) | ((mask)&(val)); }
+#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
+#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
+// PA10,PA9 PA3-PA0 PB7,PB6
+#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFF0); GP_OUT(GPIOA, CRL, 0xFFFF); GP_OUT(GPIOB, CRL, 0xFF000000); }
+#define setReadDir() {GP_INP(GPIOA, CRH, 0xFF0); GP_INP(GPIOA, CRL, 0xFFFF); GP_INP(GPIOB, CRL, 0xFF000000); }
+
+#elif defined(BLUEPILL) // Uno Shield on BLUEPILL_ADAPTER
+#warning Uno Shield on BLUEPILL_ADAPTER
+
+// configure macros for the data pins
+#define write_8(d) { GPIOA->BSRR = 0x00FF << 16; GPIOA->BSRR = (d) & 0xFF; }
+#define read_8() (GPIOA->IDR & 0xFF)
+
+#define GROUP_MODE(port, reg, mask, val) {port->reg = (port->reg & ~(mask)) | ((mask)&(val)); }
+#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
+#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
+// PA7 ..PA0
+#define setWriteDir() {GP_OUT(GPIOA, CRL, 0xFFFFFFFF); }
+#define setReadDir() {GP_INP(GPIOA, CRL, 0xFFFFFFFF); }
+
+#elif defined(ITEADMAPLE) // Uno Shield on MAPLE_REV3 board
+#warning Uno Shield on MAPLE_REV3 board
+
+#define REGS(x) x
+#define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); }
+#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
+#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
+
+ // configure macros for the data pins
+#define write_8(d) { \
+ GPIOA->REGS(BSRR) = 0x0703 << 16; \
+ GPIOB->REGS(BSRR) = 0x00E0 << 16; \
+ GPIOA->REGS(BSRR) = ( ((d) & (1<<0)) << 10) \
+ | (((d) & (1<<2)) >> 2) \
+ | (((d) & (1<<3)) >> 2) \
+ | (((d) & (1<<6)) << 2) \
+ | (((d) & (1<<7)) << 2); \
+ GPIOB->REGS(BSRR) = ( ((d) & (1<<1)) << 6) \
+ | (((d) & (1<<4)) << 1) \
+ | (((d) & (1<<5)) << 1); \
+ }
+
+#define read_8() ( ( ( (GPIOA->REGS(IDR) & (1<<10)) >> 10) \
+ | ((GPIOB->REGS(IDR) & (1<<7)) >> 6) \
+ | ((GPIOA->REGS(IDR) & (1<<0)) << 2) \
+ | ((GPIOA->REGS(IDR) & (1<<1)) << 2) \
+ | ((GPIOB->REGS(IDR) & (1<<5)) >> 1) \
+ | ((GPIOB->REGS(IDR) & (1<<6)) >> 1) \
+ | ((GPIOA->REGS(IDR) & (1<<8)) >> 2) \
+ | ((GPIOA->REGS(IDR) & (1<<9)) >> 2)))
+
+// PA10,PA9,PA8 PA1,PA0 PB7,PB6,PB5
+#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOA, CRL, 0xFF); GP_OUT(GPIOB, CRL, 0xFFF00000); }
+#define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOA, CRL, 0xFF); GP_INP(GPIOB, CRL, 0xFFF00000); }
+
+#elif defined(NUCLEO144) || ISTARGET_NUCLEO144
+#if __MBED__
+#warning MBED knows everything
+#elif defined(STM32F767xx)
+ #include <STM32F7XX.h>
+#endif
+
+#define REGS(x) x
+// configure macros for the data pins
+#define DMASK ((1<<15)) //#1
+#define EMASK ((1<<13)|(1<<11)|(1<<9)) //#3, #5, #6
+#define FMASK ((1<<12)|(1<<15)|(1<<14)|(1<<13)) //#0, #2, #4, #7
+
+#define write_8(d) { \
+ GPIOD->REGS(BSRR) = DMASK << 16; \
+ GPIOE->REGS(BSRR) = EMASK << 16; \
+ GPIOF->REGS(BSRR) = FMASK << 16; \
+ GPIOD->REGS(BSRR) = ( ((d) & (1<<1)) << 14); \
+ GPIOE->REGS(BSRR) = ( ((d) & (1<<3)) << 10) \
+ | (((d) & (1<<5)) << 6) \
+ | (((d) & (1<<6)) << 3); \
+ GPIOF->REGS(BSRR) = ( ((d) & (1<<0)) << 12) \
+ | (((d) & (1<<2)) << 13) \
+ | (((d) & (1<<4)) << 10) \
+ | (((d) & (1<<7)) << 6); \
+ }
+
+#define read_8() ( ( ( (GPIOF->REGS(IDR) & (1<<12)) >> 12) \
+ | ((GPIOD->REGS(IDR) & (1<<15)) >> 14) \
+ | ((GPIOF->REGS(IDR) & (1<<15)) >> 13) \
+ | ((GPIOE->REGS(IDR) & (1<<13)) >> 10) \
+ | ((GPIOF->REGS(IDR) & (1<<14)) >> 10) \
+ | ((GPIOE->REGS(IDR) & (1<<11)) >> 6) \
+ | ((GPIOE->REGS(IDR) & (1<<9)) >> 3) \
+ | ((GPIOF->REGS(IDR) & (1<<13)) >> 6)))
+
+
+// PD15 PE13,PE11,PE9 PF15,PF14,PF13,PF12
+#define setWriteDir() { setReadDir(); \
+ GPIOD->MODER |= 0x40000000; GPIOE->MODER |= 0x04440000; GPIOF->MODER |= 0x55000000; }
+#define setReadDir() { GPIOD->MODER &= ~0xC0000000; GPIOE->MODER &= ~0x0CCC0000; GPIOF->MODER &= ~0xFF000000; }
+
+
+#elif defined(NUCLEO) || ISTARGET_NUCLEO64
+#if __MBED__
+#warning MBED knows everything
+#elif defined(STM32F072xB)
+ #include <STM32F0XX.h>
+#elif defined(STM32F103xB)
+ #if defined(__CC_ARM)
+ #include <STM32F10X.h>
+ #else
+ #include <STM32F1XX.h>
+ #endif
+#elif defined(STM32L476xx) || defined(STM32L433xx)
+ #include <STM32L4XX.h>
+#elif defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+ #include <STM32F4XX.h>
+#endif
+// configure macros for the data pins. -00=10.06, -O1=7.85, -O1t=7.21, -O2=7.87, -O3=7.45, -O3t=7.03
+ #define write_8(d) { \
+ GPIOA->BSRR = 0x0700 << 16; \
+ GPIOB->BSRR = 0x0438 << 16; \
+ GPIOC->BSRR = 0x0080 << 16; \
+ GPIOA->BSRR = (((d) & (1<<0)) << 9) \
+ | (((d) & (1<<2)) << 8) \
+ | (((d) & (1<<7)) << 1); \
+ GPIOB->BSRR = (((d) & (1<<3)) << 0) \
+ | (((d) & (1<<4)) << 1) \
+ | (((d) & (1<<5)) >> 1) \
+ | (((d) & (1<<6)) << 4); \
+ GPIOC->BSRR = (((d) & (1<<1)) << 6); \
+ }
+ #define read_8() ( (((GPIOA->IDR & (1<<9)) >> 9) \
+ | ((GPIOC->IDR & (1<<7)) >> 6) \
+ | ((GPIOA->IDR & (1<<10)) >> 8) \
+ | ((GPIOB->IDR & (1<<3)) >> 0) \
+ | ((GPIOB->IDR & (1<<5)) >> 1) \
+ | ((GPIOB->IDR & (1<<4)) << 1) \
+ | ((GPIOB->IDR & (1<<10)) >> 4) \
+ | ((GPIOA->IDR & (1<<8)) >> 1)))
+// be wise to clear both MODER bits properly.
+#if defined(STM32F103xB)
+#define GROUP_MODE(port, reg, mask, val) {port->reg = (port->reg & ~(mask)) | ((mask)&(val)); }
+#define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333)
+#define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444)
+// PA10,PA9,PA8 PB10 PB5,PB4,PB3 PC7
+#define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOB, CRH, 0xF00); GP_OUT(GPIOB, CRL, 0xFFF000); GP_OUT(GPIOC, CRL, 0xF0000000); }
+#define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOB, CRH, 0xF00); GP_INP(GPIOB, CRL, 0xFFF000); GP_INP(GPIOC, CRL, 0xF0000000); }
+#else
+ #define setWriteDir() { setReadDir(); \
+ GPIOA->MODER |= 0x150000; GPIOB->MODER |= 0x100540; GPIOC->MODER |= 0x4000; }
+ #define setReadDir() { GPIOA->MODER &= ~0x3F0000; GPIOB->MODER &= ~0x300FC0; GPIOC->MODER &= ~0xC000; }
+#endif
+
+
+#elif __TARGET_PROCESSOR == LPC1768
+ #include <LPC17xx.h>
+// configure macros for the data pins
+ #define write_8(d) { \
+ LPC_GPIO0->FIOPIN = (LPC_GPIO0->FIOPIN & ~0x01878003) \
+ | (((d) & (1<<0)) << 1) \
+ | (((d) & (1<<1)) >> 1) \
+ | (((d) & (1<<2)) << 22) \
+ | (((d) & (1<<3)) << 20) \
+ | (((d) & (1<<4)) << 12) \
+ | (((d) & (1<<5)) << 10) \
+ | (((d) & (1<<6)) << 11) \
+ | (((d) & (1<<7)) << 11); \
+ }
+ #define read_8() ( (((LPC_GPIO0->FIOPIN & (1<<1)) >> 1) \
+ | ((LPC_GPIO0->FIOPIN & (1<<0)) << 1) \
+ | ((LPC_GPIO0->FIOPIN & (1<<24)) >> 22) \
+ | ((LPC_GPIO0->FIOPIN & (1<<23)) >> 20) \
+ | ((LPC_GPIO0->FIOPIN & (1<<16)) >> 12) \
+ | ((LPC_GPIO0->FIOPIN & (1<<15)) >> 10) \
+ | ((LPC_GPIO0->FIOPIN & (1<<17)) >> 11) \
+ | ((LPC_GPIO0->FIOPIN & (1<<18)) >> 11)))
+ #define setWriteDir() {LPC_GPIO0->FIODIR |= 0x01878003; }
+ #define setReadDir() {LPC_GPIO0->FIODIR &= ~0x01878003; }
+
+
+#elif defined(MKL25Z4) || defined(TARGET_KL25Z)
+ #include <MKL25Z4.h>
+// configure macros for the data pins
+#if 1
+#define AMASK ((1<<13)|(1<<12)|(1<<5)|(1<<4))
+#define CMASK ((1<<9)|(1<<8))
+#define DMASK ((1<<5)|(1<<4))
+ #define write_8(d) { \
+ PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \
+ PTA->PSOR = (((d) & (1<<0)) << 13) \
+ | (((d) & (1<<3)) << 9) \
+ | (((d) & (1<<4)) >> 0) \
+ | (((d) & (1<<5)) >> 0); \
+ PTC->PSOR = (((d) & (1<<6)) << 2) \
+ | (((d) & (1<<7)) << 2); \
+ PTD->PSOR = (((d) & (1<<1)) << 4) \
+ | (((d) & (1<<2)) << 2); \
+ }
+ #define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \
+ | ((PTA->PDIR & (1<<12)) >> 9) \
+ | ((PTA->PDIR & (3<<4)) >> 0) \
+ | ((PTC->PDIR & (3<<8)) >> 2) \
+ | ((PTD->PDIR & (1<<4)) >> 2) \
+ | ((PTD->PDIR & (1<<5)) >> 4)))
+ #define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; }
+ #define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; }
+#else
+ #define write_8(d) { \
+ PTA->PDOR = (PTA->PDOR & ~0x3030) \
+ | (((d) & (1<<0)) << 13) \
+ | (((d) & (1<<3)) << 9) \
+ | (((d) & (3<<4)) << 0); \
+ PTC->PDOR = (PTC->PDOR & ~0x0300) \
+ | (((d) & (3<<6)) << 2); \
+ PTD->PDOR = (PTD->PDOR & ~0x0030) \
+ | (((d) & (1<<1)) << 4) \
+ | (((d) & (1<<2)) << 2); \
+ }
+ #define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \
+ | ((PTA->PDIR & (1<<12)) >> 9) \
+ | ((PTA->PDIR & (3<<4)) >> 0) \
+ | ((PTC->PDIR & (3<<8)) >> 2) \
+ | ((PTD->PDIR & (1<<4)) >> 2) \
+ | ((PTD->PDIR & (1<<5)) >> 4)))
+ #define setWriteDir() {PTA->PDDR |= 0x3030;PTC->PDDR |= 0x0300;PTD->PDDR |= 0x0030; }
+ #define setReadDir() {PTA->PDDR &= ~0x3030;PTC->PDDR &= ~0x0300;PTD->PDDR &= ~0x0030; }
+#endif
+
+#elif defined(MKL26Z4)
+ #include <MKL26Z4.h>
+// configure macros for the data pins
+#define AMASK ((1<<13)|(1<<12)|(1<<5)|(1<<4))
+#define CMASK ((1<<9)|(1<<8))
+#define DMASK ((1<<3)|(1<<2)) //PTD5, PTD4 on KL25Z
+ #define write_8(d) { \
+ PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \
+ PTA->PSOR = (((d) & (1<<0)) << 13) \
+ | (((d) & (1<<3)) << 9) \
+ | (((d) & (1<<4)) >> 0) \
+ | (((d) & (1<<5)) >> 0); \
+ PTC->PSOR = (((d) & (1<<6)) << 2) \
+ | (((d) & (1<<7)) << 2); \
+ PTD->PSOR = (((d) & (1<<1)) << 1) \
+ | (((d) & (1<<2)) << 1); \
+ }
+ #define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \
+ | ((PTA->PDIR & (1<<12)) >> 9) \
+ | ((PTA->PDIR & (3<<4)) >> 0) \
+ | ((PTC->PDIR & (3<<8)) >> 2) \
+ | ((PTD->PDIR & (1<<3)) >> 1) \
+ | ((PTD->PDIR & (1<<2)) >> 1)))
+ #define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; }
+ #define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; }
+
+#elif defined(MKL05Z4) || defined(TARGET_KL05Z)
+ #include <MKL05Z4.h>
+// configure macros for the data pins
+ #define write_8(d) { \
+ PTA->PDOR = (PTA->PDOR & ~0x1C00) \
+ | (((d) & (1<<2)) << 9) \
+ | (((d) & (1<<4)) << 6) \
+ | (((d) & (1<<5)) << 7); \
+ PTB->PDOR = (PTB->PDOR & ~0x0CE0) \
+ | (((d) & (3<<0)) << 10) \
+ | (((d) & (1<<3)) << 2) \
+ | (((d) & (3<<6)) << 0); \
+ }
+ #define read_8() ( (((PTA->PDIR & (1<<11)) >> 9) \
+ | ((PTA->PDIR & (1<<10)) >> 6) \
+ | ((PTA->PDIR & (1<<12)) >> 7) \
+ | ((PTB->PDIR & (3<<10)) >> 10) \
+ | ((PTB->PDIR & (1<<5)) >> 2) \
+ | ((PTB->PDIR & (3<<6)) >> 0)))
+ #define setWriteDir() { PTA->PDDR |= 0x1C00; PTB->PDDR |= 0x0CE0; }
+ #define setReadDir() { PTA->PDDR &= ~0x1C00; PTB->PDDR &= ~0x0CE0; }
+
+
+#elif (defined(MK20D7) && defined(TEENSY)) || defined(TARGET_TEENSY3_1)
+#if __MBED__
+#warning MBED knows everything
+#else
+ #include <MK20D5.h>
+#endif
+// configure macros for the data pins
+#define AMASK ((1<<12)|(1<<13))
+#define CMASK ((1<<3))
+#define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<7))
+
+ #define write_8(d) { \
+ PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \
+ PTA->PSOR = (((d) & (1<<3)) << 9) \
+ | (((d) & (1<<4)) << 9); \
+ PTC->PSOR = (((d) & (1<<1)) << 2); \
+ PTD->PSOR = (((d) & (1<<0)) << 3) \
+ | (((d) & (1<<2)) >> 2) \
+ | (((d) & (1<<5)) << 2) \
+ | (((d) & (1<<6)) >> 2) \
+ | (((d) & (1<<7)) >> 5); \
+ }
+ #define read_8() ( (((PTD->PDIR & (1<<3)) >> 3) \
+ | ((PTC->PDIR & (1<<3)) >> 2) \
+ | ((PTD->PDIR & (1<<0)) << 2) \
+ | ((PTA->PDIR & (1<<12)) >> 9) \
+ | ((PTA->PDIR & (1<<13)) >> 9) \
+ | ((PTD->PDIR & (1<<7)) >> 2) \
+ | ((PTD->PDIR & (1<<4)) << 2) \
+ | ((PTD->PDIR & (1<<2)) << 5)))
+ #define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; }
+ #define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; }
+
+#elif defined(MK20D5) || defined(TARGET_K20D50M)
+ #include <MK20D5.h>
+// configure macros for the data pins
+#define AMASK ((1<<12)|(1<<5)|(1<<2)|(1<<1))
+#define CMASK ((1<<8)|(1<<4)|(1<<3))
+#define DMASK ((1<<4))
+ #define write_8(d) { \
+ PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \
+ PTA->PSOR = (((d) & (1<<0)) << 12) \
+ | (((d) & (1<<1)) << 1) \
+ | (((d) & (1<<2)) << 3) \
+ | (((d) & (1<<5)) >> 4); \
+ PTC->PSOR = (((d) & (1<<4)) << 4) \
+ | (((d) & (3<<6)) >> 3); \
+ PTD->PSOR = (((d) & (1<<3)) << 1); \
+ }
+ #define read_8() ( (((PTA->PDIR & (1<<5)) >> 3) \
+ | ((PTA->PDIR & (1<<1)) << 4) \
+ | ((PTA->PDIR & (1<<12)) >> 12) \
+ | ((PTA->PDIR & (1<<2)) >> 1) \
+ | ((PTC->PDIR & (1<<8)) >> 4) \
+ | ((PTC->PDIR & (3<<3)) << 3) \
+ | ((PTD->PDIR & (1<<4)) >> 1)))
+ #define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; }
+ #define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; }
+
+#elif defined(ZERO)
+ #include <samd21.h>
+
+ #ifndef PORTA
+ #define PORTA PORT->Group[0]
+ #define PORTB PORT->Group[1]
+ #endif
+// configure macros for the data pins
+#if defined(D21_XPRO)
+ #define AMASK 0x00220000
+ #define BMASK 0x0000C0E4
+ #define write_8(d) { \
+ PORTA.OUT.reg = (PORTA.OUT.reg & ~AMASK) \
+ | (((d) & (1<<5)) << 16) \
+ | (((d) & (1<<7)) << 10); \
+ PORTB.OUT.reg = (PORTB.OUT.reg & ~BMASK) \
+ | (((d) & (3<<0)) << 6) \
+ | (((d) & (1<<2)) << 12) \
+ | (((d) & (1<<3)) >> 1) \
+ | (((d) & (1<<4)) << 1) \
+ | (((d) & (1<<6)) << 9); \
+ }
+ #define read_8() ( (((PORTA.IN.reg & (1<<21)) >> 16) \
+ | ((PORTA.IN.reg & (1<<17)) >> 10) \
+ | ((PORTB.IN.reg & (3<<6)) >> 6) \
+ | ((PORTB.IN.reg & (1<<14)) >> 12) \
+ | ((PORTB.IN.reg & (1<<2)) << 1) \
+ | ((PORTB.IN.reg & (1<<5)) >> 1) \
+ | ((PORTB.IN.reg & (1<<15)) >> 9)))
+ #define setWriteDir() { \
+ PORTA.DIRSET.reg = AMASK; \
+ PORTB.DIRSET.reg = BMASK; \
+ PORTA.WRCONFIG.reg = (AMASK>>16) | (0<<22) | (0<<28) | (1<<30) | (1<<31); \
+ PORTB.WRCONFIG.reg = (BMASK & 0xFFFF) | (0<<22) | (0<<28) | (1<<30); \
+ }
+ #define setReadDir() { \
+ PORTA.DIRCLR.reg = AMASK; \
+ PORTB.DIRCLR.reg = BMASK; \
+ PORTA.WRCONFIG.reg = (AMASK>>16) | (1<<17) | (0<<28) | (1<<30) | (1<<31); \
+ PORTB.WRCONFIG.reg = (BMASK & 0xFFFF) | (1<<17) | (0<<28) | (1<<30); \
+ }
+#else
+ #define DMASK 0x0030C3C0
+ #define write_8(x) {PORTA.OUTCLR.reg = (DMASK); \
+ PORTA.OUTSET.reg = (((x) & 0x0F) << 6) \
+ | (((x) & 0x30) << 10) \
+ | (((x) & 0xC0)<<14); }
+ #define read_8() (((PORTA.IN.reg >> 6) & 0x0F) \
+ | ((PORTA.IN.reg >> 10) & 0x30) \
+ | ((PORTA.IN.reg >> 14) & 0xC0))
+ #define setWriteDir() { PORTA.DIRSET.reg = DMASK; \
+ PORTA.WRCONFIG.reg = (DMASK & 0xFFFF) | (0<<22) | (1<<28) | (1<<30); \
+ PORTA.WRCONFIG.reg = (DMASK>>16) | (0<<22) | (1<<28) | (1<<30) | (1<<31); \
+ }
+ #define setReadDir() { PORTA.DIRCLR.reg = DMASK; \
+ PORTA.WRCONFIG.reg = (DMASK & 0xFFFF) | (1<<17) | (1<<28) | (1<<30); \
+ PORTA.WRCONFIG.reg = (DMASK>>16) | (1<<17) | (1<<28) | (1<<30) | (1<<31); \
+ }
+#endif
+#else
+#error MCU unselected
+#endif // MCUs
+
+#endif //PIN_SHIELD_8_H
+
\ No newline at end of file
--- a/main.cpp Wed Apr 21 14:47:37 2021 +0000 +++ b/main.cpp Wed Apr 21 14:54:37 2021 +0000 @@ -2,7 +2,10 @@ // https://os.mbed.com/users/davidprentice/code/Nucleo_dir_L152//file/d88d2ad55fac/main.cpp/ // Committer: davidprentice // Date: 19 months ago -// 2021-04-21 +// 2021-04-21 +// Testado com sucesso na NUCLEO-F103RB + ILI9341 Arduino Shield +// interface paralela >>> ver "dataBus" +// usando mbed 2.0 #include "Arduino.h"