Kiyoteru Hayama / mbedRobotracer_Edu

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mbed/LPC1768/core_cm3.h@1:200aad416161, 2013-10-02 (annotated)

Committer:
hayama
Date:
Wed Oct 02 01:09:55 2013 +0000
Revision:
1:200aad416161
Parent:
0:da22b0b4395a 
mbed robotracer for education.

;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hayama 0:da22b0b4395a 1 /**************************************************************************//**
hayama 0:da22b0b4395a 2 * @file core_cm3.h
hayama 0:da22b0b4395a 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
hayama 0:da22b0b4395a 4 * @version V3.02
hayama 0:da22b0b4395a 5 * @date 16. July 2012
hayama 0:da22b0b4395a 6 *
hayama 0:da22b0b4395a 7 * @note
hayama 0:da22b0b4395a 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
hayama 0:da22b0b4395a 9 *
hayama 0:da22b0b4395a 10 * @par
hayama 0:da22b0b4395a 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
hayama 0:da22b0b4395a 12 * processor based microcontrollers. This file can be freely distributed
hayama 0:da22b0b4395a 13 * within development tools that are supporting such ARM based processors.
hayama 0:da22b0b4395a 14 *
hayama 0:da22b0b4395a 15 * @par
hayama 0:da22b0b4395a 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
hayama 0:da22b0b4395a 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
hayama 0:da22b0b4395a 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
hayama 0:da22b0b4395a 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
hayama 0:da22b0b4395a 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
hayama 0:da22b0b4395a 21 *
hayama 0:da22b0b4395a 22 ******************************************************************************/
hayama 0:da22b0b4395a 23 #if defined ( __ICCARM__ )
hayama 0:da22b0b4395a 24 #pragma system_include /* treat file as system include file for MISRA check */
hayama 0:da22b0b4395a 25 #endif
hayama 0:da22b0b4395a 26
hayama 0:da22b0b4395a 27 #ifdef __cplusplus
hayama 0:da22b0b4395a 28 extern "C" {
hayama 0:da22b0b4395a 29 #endif
hayama 0:da22b0b4395a 30
hayama 0:da22b0b4395a 31 #ifndef __CORE_CM3_H_GENERIC
hayama 0:da22b0b4395a 32 #define __CORE_CM3_H_GENERIC
hayama 0:da22b0b4395a 33
hayama 0:da22b0b4395a 34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
hayama 0:da22b0b4395a 35 CMSIS violates the following MISRA-C:2004 rules:
hayama 0:da22b0b4395a 36
hayama 0:da22b0b4395a 37 \li Required Rule 8.5, object/function definition in header file.<br>
hayama 0:da22b0b4395a 38 Function definitions in header files are used to allow 'inlining'.
hayama 0:da22b0b4395a 39
hayama 0:da22b0b4395a 40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
hayama 0:da22b0b4395a 41 Unions are used for effective representation of core registers.
hayama 0:da22b0b4395a 42
hayama 0:da22b0b4395a 43 \li Advisory Rule 19.7, Function-like macro defined.<br>
hayama 0:da22b0b4395a 44 Function-like macros are used to allow more efficient code.
hayama 0:da22b0b4395a 45 */
hayama 0:da22b0b4395a 46
hayama 0:da22b0b4395a 47
hayama 0:da22b0b4395a 48 /*******************************************************************************
hayama 0:da22b0b4395a 49 * CMSIS definitions
hayama 0:da22b0b4395a 50 ******************************************************************************/
hayama 0:da22b0b4395a 51 /** \ingroup Cortex_M3
hayama 0:da22b0b4395a 52 @{
hayama 0:da22b0b4395a 53 */
hayama 0:da22b0b4395a 54
hayama 0:da22b0b4395a 55 /* CMSIS CM3 definitions */
hayama 0:da22b0b4395a 56 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
hayama 0:da22b0b4395a 57 #define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
hayama 0:da22b0b4395a 58 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
hayama 0:da22b0b4395a 59 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
hayama 0:da22b0b4395a 60
hayama 0:da22b0b4395a 61 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
hayama 0:da22b0b4395a 62
hayama 0:da22b0b4395a 63
hayama 0:da22b0b4395a 64 #if defined ( __CC_ARM )
hayama 0:da22b0b4395a 65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
hayama 0:da22b0b4395a 66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
hayama 0:da22b0b4395a 67 #define __STATIC_INLINE static __inline
hayama 0:da22b0b4395a 68
hayama 0:da22b0b4395a 69 #elif defined ( __ICCARM__ )
hayama 0:da22b0b4395a 70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
hayama 0:da22b0b4395a 71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
hayama 0:da22b0b4395a 72 #define __STATIC_INLINE static inline
hayama 0:da22b0b4395a 73
hayama 0:da22b0b4395a 74 #elif defined ( __TMS470__ )
hayama 0:da22b0b4395a 75 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
hayama 0:da22b0b4395a 76 #define __STATIC_INLINE static inline
hayama 0:da22b0b4395a 77
hayama 0:da22b0b4395a 78 #elif defined ( __GNUC__ )
hayama 0:da22b0b4395a 79 #define __ASM __asm /*!< asm keyword for GNU Compiler */
hayama 0:da22b0b4395a 80 #define __INLINE inline /*!< inline keyword for GNU Compiler */
hayama 0:da22b0b4395a 81 #define __STATIC_INLINE static inline
hayama 0:da22b0b4395a 82
hayama 0:da22b0b4395a 83 #elif defined ( __TASKING__ )
hayama 0:da22b0b4395a 84 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
hayama 0:da22b0b4395a 85 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
hayama 0:da22b0b4395a 86 #define __STATIC_INLINE static inline
hayama 0:da22b0b4395a 87
hayama 0:da22b0b4395a 88 #endif
hayama 0:da22b0b4395a 89
hayama 0:da22b0b4395a 90 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
hayama 0:da22b0b4395a 91 */
hayama 0:da22b0b4395a 92 #define __FPU_USED 0
hayama 0:da22b0b4395a 93
hayama 0:da22b0b4395a 94 #if defined ( __CC_ARM )
hayama 0:da22b0b4395a 95 #if defined __TARGET_FPU_VFP
hayama 0:da22b0b4395a 96 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
hayama 0:da22b0b4395a 97 #endif
hayama 0:da22b0b4395a 98
hayama 0:da22b0b4395a 99 #elif defined ( __ICCARM__ )
hayama 0:da22b0b4395a 100 #if defined __ARMVFP__
hayama 0:da22b0b4395a 101 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
hayama 0:da22b0b4395a 102 #endif
hayama 0:da22b0b4395a 103
hayama 0:da22b0b4395a 104 #elif defined ( __TMS470__ )
hayama 0:da22b0b4395a 105 #if defined __TI__VFP_SUPPORT____
hayama 0:da22b0b4395a 106 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
hayama 0:da22b0b4395a 107 #endif
hayama 0:da22b0b4395a 108
hayama 0:da22b0b4395a 109 #elif defined ( __GNUC__ )
hayama 0:da22b0b4395a 110 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
hayama 0:da22b0b4395a 111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
hayama 0:da22b0b4395a 112 #endif
hayama 0:da22b0b4395a 113
hayama 0:da22b0b4395a 114 #elif defined ( __TASKING__ )
hayama 0:da22b0b4395a 115 #if defined __FPU_VFP__
hayama 0:da22b0b4395a 116 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
hayama 0:da22b0b4395a 117 #endif
hayama 0:da22b0b4395a 118 #endif
hayama 0:da22b0b4395a 119
hayama 0:da22b0b4395a 120 #include <stdint.h> /* standard types definitions */
hayama 0:da22b0b4395a 121 #include <core_cmInstr.h> /* Core Instruction Access */
hayama 0:da22b0b4395a 122 #include <core_cmFunc.h> /* Core Function Access */
hayama 0:da22b0b4395a 123
hayama 0:da22b0b4395a 124 #endif /* __CORE_CM3_H_GENERIC */
hayama 0:da22b0b4395a 125
hayama 0:da22b0b4395a 126 #ifndef __CMSIS_GENERIC
hayama 0:da22b0b4395a 127
hayama 0:da22b0b4395a 128 #ifndef __CORE_CM3_H_DEPENDANT
hayama 0:da22b0b4395a 129 #define __CORE_CM3_H_DEPENDANT
hayama 0:da22b0b4395a 130
hayama 0:da22b0b4395a 131 /* check device defines and use defaults */
hayama 0:da22b0b4395a 132 #if defined __CHECK_DEVICE_DEFINES
hayama 0:da22b0b4395a 133 #ifndef __CM3_REV
hayama 0:da22b0b4395a 134 #define __CM3_REV 0x0200
hayama 0:da22b0b4395a 135 #warning "__CM3_REV not defined in device header file; using default!"
hayama 0:da22b0b4395a 136 #endif
hayama 0:da22b0b4395a 137
hayama 0:da22b0b4395a 138 #ifndef __MPU_PRESENT
hayama 0:da22b0b4395a 139 #define __MPU_PRESENT 0
hayama 0:da22b0b4395a 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
hayama 0:da22b0b4395a 141 #endif
hayama 0:da22b0b4395a 142
hayama 0:da22b0b4395a 143 #ifndef __NVIC_PRIO_BITS
hayama 0:da22b0b4395a 144 #define __NVIC_PRIO_BITS 4
hayama 0:da22b0b4395a 145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
hayama 0:da22b0b4395a 146 #endif
hayama 0:da22b0b4395a 147
hayama 0:da22b0b4395a 148 #ifndef __Vendor_SysTickConfig
hayama 0:da22b0b4395a 149 #define __Vendor_SysTickConfig 0
hayama 0:da22b0b4395a 150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
hayama 0:da22b0b4395a 151 #endif
hayama 0:da22b0b4395a 152 #endif
hayama 0:da22b0b4395a 153
hayama 0:da22b0b4395a 154 /* IO definitions (access restrictions to peripheral registers) */
hayama 0:da22b0b4395a 155 /**
hayama 0:da22b0b4395a 156 \defgroup CMSIS_glob_defs CMSIS Global Defines
hayama 0:da22b0b4395a 157
hayama 0:da22b0b4395a 158 <strong>IO Type Qualifiers</strong> are used
hayama 0:da22b0b4395a 159 \li to specify the access to peripheral variables.
hayama 0:da22b0b4395a 160 \li for automatic generation of peripheral register debug information.
hayama 0:da22b0b4395a 161 */
hayama 0:da22b0b4395a 162 #ifdef __cplusplus
hayama 0:da22b0b4395a 163 #define __I volatile /*!< Defines 'read only' permissions */
hayama 0:da22b0b4395a 164 #else
hayama 0:da22b0b4395a 165 #define __I volatile const /*!< Defines 'read only' permissions */
hayama 0:da22b0b4395a 166 #endif
hayama 0:da22b0b4395a 167 #define __O volatile /*!< Defines 'write only' permissions */
hayama 0:da22b0b4395a 168 #define __IO volatile /*!< Defines 'read / write' permissions */
hayama 0:da22b0b4395a 169
hayama 0:da22b0b4395a 170 /*@} end of group Cortex_M3 */
hayama 0:da22b0b4395a 171
hayama 0:da22b0b4395a 172
hayama 0:da22b0b4395a 173
hayama 0:da22b0b4395a 174 /*******************************************************************************
hayama 0:da22b0b4395a 175 * Register Abstraction
hayama 0:da22b0b4395a 176 Core Register contain:
hayama 0:da22b0b4395a 177 - Core Register
hayama 0:da22b0b4395a 178 - Core NVIC Register
hayama 0:da22b0b4395a 179 - Core SCB Register
hayama 0:da22b0b4395a 180 - Core SysTick Register
hayama 0:da22b0b4395a 181 - Core Debug Register
hayama 0:da22b0b4395a 182 - Core MPU Register
hayama 0:da22b0b4395a 183 ******************************************************************************/
hayama 0:da22b0b4395a 184 /** \defgroup CMSIS_core_register Defines and Type Definitions
hayama 0:da22b0b4395a 185 \brief Type definitions and defines for Cortex-M processor based devices.
hayama 0:da22b0b4395a 186 */
hayama 0:da22b0b4395a 187
hayama 0:da22b0b4395a 188 /** \ingroup CMSIS_core_register
hayama 0:da22b0b4395a 189 \defgroup CMSIS_CORE Status and Control Registers
hayama 0:da22b0b4395a 190 \brief Core Register type definitions.
hayama 0:da22b0b4395a 191 @{
hayama 0:da22b0b4395a 192 */
hayama 0:da22b0b4395a 193
hayama 0:da22b0b4395a 194 /** \brief Union type to access the Application Program Status Register (APSR).
hayama 0:da22b0b4395a 195 */
hayama 0:da22b0b4395a 196 typedef union
hayama 0:da22b0b4395a 197 {
hayama 0:da22b0b4395a 198 struct
hayama 0:da22b0b4395a 199 {
hayama 0:da22b0b4395a 200 #if (__CORTEX_M != 0x04)
hayama 0:da22b0b4395a 201 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
hayama 0:da22b0b4395a 202 #else
hayama 0:da22b0b4395a 203 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
hayama 0:da22b0b4395a 204 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
hayama 0:da22b0b4395a 205 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
hayama 0:da22b0b4395a 206 #endif
hayama 0:da22b0b4395a 207 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
hayama 0:da22b0b4395a 208 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
hayama 0:da22b0b4395a 209 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
hayama 0:da22b0b4395a 210 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
hayama 0:da22b0b4395a 211 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
hayama 0:da22b0b4395a 212 } b; /*!< Structure used for bit access */
hayama 0:da22b0b4395a 213 uint32_t w; /*!< Type used for word access */
hayama 0:da22b0b4395a 214 } APSR_Type;
hayama 0:da22b0b4395a 215
hayama 0:da22b0b4395a 216
hayama 0:da22b0b4395a 217 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
hayama 0:da22b0b4395a 218 */
hayama 0:da22b0b4395a 219 typedef union
hayama 0:da22b0b4395a 220 {
hayama 0:da22b0b4395a 221 struct
hayama 0:da22b0b4395a 222 {
hayama 0:da22b0b4395a 223 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
hayama 0:da22b0b4395a 224 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
hayama 0:da22b0b4395a 225 } b; /*!< Structure used for bit access */
hayama 0:da22b0b4395a 226 uint32_t w; /*!< Type used for word access */
hayama 0:da22b0b4395a 227 } IPSR_Type;
hayama 0:da22b0b4395a 228
hayama 0:da22b0b4395a 229
hayama 0:da22b0b4395a 230 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
hayama 0:da22b0b4395a 231 */
hayama 0:da22b0b4395a 232 typedef union
hayama 0:da22b0b4395a 233 {
hayama 0:da22b0b4395a 234 struct
hayama 0:da22b0b4395a 235 {
hayama 0:da22b0b4395a 236 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
hayama 0:da22b0b4395a 237 #if (__CORTEX_M != 0x04)
hayama 0:da22b0b4395a 238 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
hayama 0:da22b0b4395a 239 #else
hayama 0:da22b0b4395a 240 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
hayama 0:da22b0b4395a 241 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
hayama 0:da22b0b4395a 242 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
hayama 0:da22b0b4395a 243 #endif
hayama 0:da22b0b4395a 244 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
hayama 0:da22b0b4395a 245 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
hayama 0:da22b0b4395a 246 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
hayama 0:da22b0b4395a 247 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
hayama 0:da22b0b4395a 248 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
hayama 0:da22b0b4395a 249 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
hayama 0:da22b0b4395a 250 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
hayama 0:da22b0b4395a 251 } b; /*!< Structure used for bit access */
hayama 0:da22b0b4395a 252 uint32_t w; /*!< Type used for word access */
hayama 0:da22b0b4395a 253 } xPSR_Type;
hayama 0:da22b0b4395a 254
hayama 0:da22b0b4395a 255
hayama 0:da22b0b4395a 256 /** \brief Union type to access the Control Registers (CONTROL).
hayama 0:da22b0b4395a 257 */
hayama 0:da22b0b4395a 258 typedef union
hayama 0:da22b0b4395a 259 {
hayama 0:da22b0b4395a 260 struct
hayama 0:da22b0b4395a 261 {
hayama 0:da22b0b4395a 262 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
hayama 0:da22b0b4395a 263 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
hayama 0:da22b0b4395a 264 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
hayama 0:da22b0b4395a 265 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
hayama 0:da22b0b4395a 266 } b; /*!< Structure used for bit access */
hayama 0:da22b0b4395a 267 uint32_t w; /*!< Type used for word access */
hayama 0:da22b0b4395a 268 } CONTROL_Type;
hayama 0:da22b0b4395a 269
hayama 0:da22b0b4395a 270 /*@} end of group CMSIS_CORE */
hayama 0:da22b0b4395a 271
hayama 0:da22b0b4395a 272
hayama 0:da22b0b4395a 273 /** \ingroup CMSIS_core_register
hayama 0:da22b0b4395a 274 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
hayama 0:da22b0b4395a 275 \brief Type definitions for the NVIC Registers
hayama 0:da22b0b4395a 276 @{
hayama 0:da22b0b4395a 277 */
hayama 0:da22b0b4395a 278
hayama 0:da22b0b4395a 279 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
hayama 0:da22b0b4395a 280 */
hayama 0:da22b0b4395a 281 typedef struct
hayama 0:da22b0b4395a 282 {
hayama 0:da22b0b4395a 283 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
hayama 0:da22b0b4395a 284 uint32_t RESERVED0[24];
hayama 0:da22b0b4395a 285 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
hayama 0:da22b0b4395a 286 uint32_t RSERVED1[24];
hayama 0:da22b0b4395a 287 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
hayama 0:da22b0b4395a 288 uint32_t RESERVED2[24];
hayama 0:da22b0b4395a 289 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
hayama 0:da22b0b4395a 290 uint32_t RESERVED3[24];
hayama 0:da22b0b4395a 291 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
hayama 0:da22b0b4395a 292 uint32_t RESERVED4[56];
hayama 0:da22b0b4395a 293 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
hayama 0:da22b0b4395a 294 uint32_t RESERVED5[644];
hayama 0:da22b0b4395a 295 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
hayama 0:da22b0b4395a 296 } NVIC_Type;
hayama 0:da22b0b4395a 297
hayama 0:da22b0b4395a 298 /* Software Triggered Interrupt Register Definitions */
hayama 0:da22b0b4395a 299 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
hayama 0:da22b0b4395a 300 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
hayama 0:da22b0b4395a 301
hayama 0:da22b0b4395a 302 /*@} end of group CMSIS_NVIC */
hayama 0:da22b0b4395a 303
hayama 0:da22b0b4395a 304
hayama 0:da22b0b4395a 305 /** \ingroup CMSIS_core_register
hayama 0:da22b0b4395a 306 \defgroup CMSIS_SCB System Control Block (SCB)
hayama 0:da22b0b4395a 307 \brief Type definitions for the System Control Block Registers
hayama 0:da22b0b4395a 308 @{
hayama 0:da22b0b4395a 309 */
hayama 0:da22b0b4395a 310
hayama 0:da22b0b4395a 311 /** \brief Structure type to access the System Control Block (SCB).
hayama 0:da22b0b4395a 312 */
hayama 0:da22b0b4395a 313 typedef struct
hayama 0:da22b0b4395a 314 {
hayama 0:da22b0b4395a 315 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
hayama 0:da22b0b4395a 316 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
hayama 0:da22b0b4395a 317 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
hayama 0:da22b0b4395a 318 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
hayama 0:da22b0b4395a 319 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
hayama 0:da22b0b4395a 320 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
hayama 0:da22b0b4395a 321 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
hayama 0:da22b0b4395a 322 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
hayama 0:da22b0b4395a 323 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
hayama 0:da22b0b4395a 324 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
hayama 0:da22b0b4395a 325 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
hayama 0:da22b0b4395a 326 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
hayama 0:da22b0b4395a 327 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
hayama 0:da22b0b4395a 328 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
hayama 0:da22b0b4395a 329 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
hayama 0:da22b0b4395a 330 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
hayama 0:da22b0b4395a 331 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
hayama 0:da22b0b4395a 332 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
hayama 0:da22b0b4395a 333 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
hayama 0:da22b0b4395a 334 uint32_t RESERVED0[5];
hayama 0:da22b0b4395a 335 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
hayama 0:da22b0b4395a 336 } SCB_Type;
hayama 0:da22b0b4395a 337
hayama 0:da22b0b4395a 338 /* SCB CPUID Register Definitions */
hayama 0:da22b0b4395a 339 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
hayama 0:da22b0b4395a 340 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
hayama 0:da22b0b4395a 341
hayama 0:da22b0b4395a 342 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
hayama 0:da22b0b4395a 343 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
hayama 0:da22b0b4395a 344
hayama 0:da22b0b4395a 345 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
hayama 0:da22b0b4395a 346 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
hayama 0:da22b0b4395a 347
hayama 0:da22b0b4395a 348 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
hayama 0:da22b0b4395a 349 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
hayama 0:da22b0b4395a 350
hayama 0:da22b0b4395a 351 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
hayama 0:da22b0b4395a 352 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
hayama 0:da22b0b4395a 353
hayama 0:da22b0b4395a 354 /* SCB Interrupt Control State Register Definitions */
hayama 0:da22b0b4395a 355 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
hayama 0:da22b0b4395a 356 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
hayama 0:da22b0b4395a 357
hayama 0:da22b0b4395a 358 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
hayama 0:da22b0b4395a 359 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
hayama 0:da22b0b4395a 360
hayama 0:da22b0b4395a 361 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
hayama 0:da22b0b4395a 362 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
hayama 0:da22b0b4395a 363
hayama 0:da22b0b4395a 364 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
hayama 0:da22b0b4395a 365 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
hayama 0:da22b0b4395a 366
hayama 0:da22b0b4395a 367 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
hayama 0:da22b0b4395a 368 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
hayama 0:da22b0b4395a 369
hayama 0:da22b0b4395a 370 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
hayama 0:da22b0b4395a 371 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
hayama 0:da22b0b4395a 372
hayama 0:da22b0b4395a 373 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
hayama 0:da22b0b4395a 374 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
hayama 0:da22b0b4395a 375
hayama 0:da22b0b4395a 376 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
hayama 0:da22b0b4395a 377 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
hayama 0:da22b0b4395a 378
hayama 0:da22b0b4395a 379 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
hayama 0:da22b0b4395a 380 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
hayama 0:da22b0b4395a 381
hayama 0:da22b0b4395a 382 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
hayama 0:da22b0b4395a 383 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
hayama 0:da22b0b4395a 384
hayama 0:da22b0b4395a 385 /* SCB Vector Table Offset Register Definitions */
hayama 0:da22b0b4395a 386 #if (__CM3_REV < 0x0201) /* core r2p1 */
hayama 0:da22b0b4395a 387 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
hayama 0:da22b0b4395a 388 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
hayama 0:da22b0b4395a 389
hayama 0:da22b0b4395a 390 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
hayama 0:da22b0b4395a 391 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
hayama 0:da22b0b4395a 392 #else
hayama 0:da22b0b4395a 393 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
hayama 0:da22b0b4395a 394 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
hayama 0:da22b0b4395a 395 #endif
hayama 0:da22b0b4395a 396
hayama 0:da22b0b4395a 397 /* SCB Application Interrupt and Reset Control Register Definitions */
hayama 0:da22b0b4395a 398 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
hayama 0:da22b0b4395a 399 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
hayama 0:da22b0b4395a 400
hayama 0:da22b0b4395a 401 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
hayama 0:da22b0b4395a 402 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
hayama 0:da22b0b4395a 403
hayama 0:da22b0b4395a 404 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
hayama 0:da22b0b4395a 405 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
hayama 0:da22b0b4395a 406
hayama 0:da22b0b4395a 407 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
hayama 0:da22b0b4395a 408 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
hayama 0:da22b0b4395a 409
hayama 0:da22b0b4395a 410 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
hayama 0:da22b0b4395a 411 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
hayama 0:da22b0b4395a 412
hayama 0:da22b0b4395a 413 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
hayama 0:da22b0b4395a 414 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
hayama 0:da22b0b4395a 415
hayama 0:da22b0b4395a 416 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
hayama 0:da22b0b4395a 417 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
hayama 0:da22b0b4395a 418
hayama 0:da22b0b4395a 419 /* SCB System Control Register Definitions */
hayama 0:da22b0b4395a 420 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
hayama 0:da22b0b4395a 421 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
hayama 0:da22b0b4395a 422
hayama 0:da22b0b4395a 423 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
hayama 0:da22b0b4395a 424 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
hayama 0:da22b0b4395a 425
hayama 0:da22b0b4395a 426 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
hayama 0:da22b0b4395a 427 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
hayama 0:da22b0b4395a 428
hayama 0:da22b0b4395a 429 /* SCB Configuration Control Register Definitions */
hayama 0:da22b0b4395a 430 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
hayama 0:da22b0b4395a 431 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
hayama 0:da22b0b4395a 432
hayama 0:da22b0b4395a 433 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
hayama 0:da22b0b4395a 434 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
hayama 0:da22b0b4395a 435
hayama 0:da22b0b4395a 436 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
hayama 0:da22b0b4395a 437 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
hayama 0:da22b0b4395a 438
hayama 0:da22b0b4395a 439 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
hayama 0:da22b0b4395a 440 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
hayama 0:da22b0b4395a 441
hayama 0:da22b0b4395a 442 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
hayama 0:da22b0b4395a 443 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
hayama 0:da22b0b4395a 444
hayama 0:da22b0b4395a 445 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
hayama 0:da22b0b4395a 446 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
hayama 0:da22b0b4395a 447
hayama 0:da22b0b4395a 448 /* SCB System Handler Control and State Register Definitions */
hayama 0:da22b0b4395a 449 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
hayama 0:da22b0b4395a 450 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
hayama 0:da22b0b4395a 451
hayama 0:da22b0b4395a 452 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
hayama 0:da22b0b4395a 453 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
hayama 0:da22b0b4395a 454
hayama 0:da22b0b4395a 455 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
hayama 0:da22b0b4395a 456 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
hayama 0:da22b0b4395a 457
hayama 0:da22b0b4395a 458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
hayama 0:da22b0b4395a 459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
hayama 0:da22b0b4395a 460
hayama 0:da22b0b4395a 461 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
hayama 0:da22b0b4395a 462 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
hayama 0:da22b0b4395a 463
hayama 0:da22b0b4395a 464 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
hayama 0:da22b0b4395a 465 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
hayama 0:da22b0b4395a 466
hayama 0:da22b0b4395a 467 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
hayama 0:da22b0b4395a 468 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
hayama 0:da22b0b4395a 469
hayama 0:da22b0b4395a 470 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
hayama 0:da22b0b4395a 471 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
hayama 0:da22b0b4395a 472
hayama 0:da22b0b4395a 473 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
hayama 0:da22b0b4395a 474 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
hayama 0:da22b0b4395a 475
hayama 0:da22b0b4395a 476 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
hayama 0:da22b0b4395a 477 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
hayama 0:da22b0b4395a 478
hayama 0:da22b0b4395a 479 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
hayama 0:da22b0b4395a 480 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
hayama 0:da22b0b4395a 481
hayama 0:da22b0b4395a 482 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
hayama 0:da22b0b4395a 483 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
hayama 0:da22b0b4395a 484
hayama 0:da22b0b4395a 485 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
hayama 0:da22b0b4395a 486 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
hayama 0:da22b0b4395a 487
hayama 0:da22b0b4395a 488 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
hayama 0:da22b0b4395a 489 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
hayama 0:da22b0b4395a 490
hayama 0:da22b0b4395a 491 /* SCB Configurable Fault Status Registers Definitions */
hayama 0:da22b0b4395a 492 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
hayama 0:da22b0b4395a 493 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
hayama 0:da22b0b4395a 494
hayama 0:da22b0b4395a 495 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
hayama 0:da22b0b4395a 496 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
hayama 0:da22b0b4395a 497
hayama 0:da22b0b4395a 498 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
hayama 0:da22b0b4395a 499 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
hayama 0:da22b0b4395a 500
hayama 0:da22b0b4395a 501 /* SCB Hard Fault Status Registers Definitions */
hayama 0:da22b0b4395a 502 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
hayama 0:da22b0b4395a 503 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
hayama 0:da22b0b4395a 504
hayama 0:da22b0b4395a 505 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
hayama 0:da22b0b4395a 506 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
hayama 0:da22b0b4395a 507
hayama 0:da22b0b4395a 508 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
hayama 0:da22b0b4395a 509 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
hayama 0:da22b0b4395a 510
hayama 0:da22b0b4395a 511 /* SCB Debug Fault Status Register Definitions */
hayama 0:da22b0b4395a 512 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
hayama 0:da22b0b4395a 513 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
hayama 0:da22b0b4395a 514
hayama 0:da22b0b4395a 515 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
hayama 0:da22b0b4395a 516 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
hayama 0:da22b0b4395a 517
hayama 0:da22b0b4395a 518 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
hayama 0:da22b0b4395a 519 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
hayama 0:da22b0b4395a 520
hayama 0:da22b0b4395a 521 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
hayama 0:da22b0b4395a 522 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
hayama 0:da22b0b4395a 523
hayama 0:da22b0b4395a 524 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
hayama 0:da22b0b4395a 525 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
hayama 0:da22b0b4395a 526
hayama 0:da22b0b4395a 527 /*@} end of group CMSIS_SCB */
hayama 0:da22b0b4395a 528
hayama 0:da22b0b4395a 529
hayama 0:da22b0b4395a 530 /** \ingroup CMSIS_core_register
hayama 0:da22b0b4395a 531 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
hayama 0:da22b0b4395a 532 \brief Type definitions for the System Control and ID Register not in the SCB
hayama 0:da22b0b4395a 533 @{
hayama 0:da22b0b4395a 534 */
hayama 0:da22b0b4395a 535
hayama 0:da22b0b4395a 536 /** \brief Structure type to access the System Control and ID Register not in the SCB.
hayama 0:da22b0b4395a 537 */
hayama 0:da22b0b4395a 538 typedef struct
hayama 0:da22b0b4395a 539 {
hayama 0:da22b0b4395a 540 uint32_t RESERVED0[1];
hayama 0:da22b0b4395a 541 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
hayama 0:da22b0b4395a 542 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
hayama 0:da22b0b4395a 543 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
hayama 0:da22b0b4395a 544 #else
hayama 0:da22b0b4395a 545 uint32_t RESERVED1[1];
hayama 0:da22b0b4395a 546 #endif
hayama 0:da22b0b4395a 547 } SCnSCB_Type;
hayama 0:da22b0b4395a 548
hayama 0:da22b0b4395a 549 /* Interrupt Controller Type Register Definitions */
hayama 0:da22b0b4395a 550 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
hayama 0:da22b0b4395a 551 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
hayama 0:da22b0b4395a 552
hayama 0:da22b0b4395a 553 /* Auxiliary Control Register Definitions */
hayama 0:da22b0b4395a 554
hayama 0:da22b0b4395a 555 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
hayama 0:da22b0b4395a 556 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
hayama 0:da22b0b4395a 557
hayama 0:da22b0b4395a 558 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
hayama 0:da22b0b4395a 559 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
hayama 0:da22b0b4395a 560
hayama 0:da22b0b4395a 561 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
hayama 0:da22b0b4395a 562 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
hayama 0:da22b0b4395a 563
hayama 0:da22b0b4395a 564 /*@} end of group CMSIS_SCnotSCB */
hayama 0:da22b0b4395a 565
hayama 0:da22b0b4395a 566
hayama 0:da22b0b4395a 567 /** \ingroup CMSIS_core_register
hayama 0:da22b0b4395a 568 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
hayama 0:da22b0b4395a 569 \brief Type definitions for the System Timer Registers.
hayama 0:da22b0b4395a 570 @{
hayama 0:da22b0b4395a 571 */
hayama 0:da22b0b4395a 572
hayama 0:da22b0b4395a 573 /** \brief Structure type to access the System Timer (SysTick).
hayama 0:da22b0b4395a 574 */
hayama 0:da22b0b4395a 575 typedef struct
hayama 0:da22b0b4395a 576 {
hayama 0:da22b0b4395a 577 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
hayama 0:da22b0b4395a 578 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
hayama 0:da22b0b4395a 579 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
hayama 0:da22b0b4395a 580 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
hayama 0:da22b0b4395a 581 } SysTick_Type;
hayama 0:da22b0b4395a 582
hayama 0:da22b0b4395a 583 /* SysTick Control / Status Register Definitions */
hayama 0:da22b0b4395a 584 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
hayama 0:da22b0b4395a 585 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
hayama 0:da22b0b4395a 586
hayama 0:da22b0b4395a 587 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
hayama 0:da22b0b4395a 588 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
hayama 0:da22b0b4395a 589
hayama 0:da22b0b4395a 590 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
hayama 0:da22b0b4395a 591 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
hayama 0:da22b0b4395a 592
hayama 0:da22b0b4395a 593 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
hayama 0:da22b0b4395a 594 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
hayama 0:da22b0b4395a 595
hayama 0:da22b0b4395a 596 /* SysTick Reload Register Definitions */
hayama 0:da22b0b4395a 597 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
hayama 0:da22b0b4395a 598 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
hayama 0:da22b0b4395a 599
hayama 0:da22b0b4395a 600 /* SysTick Current Register Definitions */
hayama 0:da22b0b4395a 601 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
hayama 0:da22b0b4395a 602 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
hayama 0:da22b0b4395a 603
hayama 0:da22b0b4395a 604 /* SysTick Calibration Register Definitions */
hayama 0:da22b0b4395a 605 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
hayama 0:da22b0b4395a 606 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
hayama 0:da22b0b4395a 607
hayama 0:da22b0b4395a 608 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
hayama 0:da22b0b4395a 609 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
hayama 0:da22b0b4395a 610
hayama 0:da22b0b4395a 611 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
hayama 0:da22b0b4395a 612 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
hayama 0:da22b0b4395a 613
hayama 0:da22b0b4395a 614 /*@} end of group CMSIS_SysTick */
hayama 0:da22b0b4395a 615
hayama 0:da22b0b4395a 616
hayama 0:da22b0b4395a 617 /** \ingroup CMSIS_core_register
hayama 0:da22b0b4395a 618 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
hayama 0:da22b0b4395a 619 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
hayama 0:da22b0b4395a 620 @{
hayama 0:da22b0b4395a 621 */
hayama 0:da22b0b4395a 622
hayama 0:da22b0b4395a 623 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
hayama 0:da22b0b4395a 624 */
hayama 0:da22b0b4395a 625 typedef struct
hayama 0:da22b0b4395a 626 {
hayama 0:da22b0b4395a 627 __O union
hayama 0:da22b0b4395a 628 {
hayama 0:da22b0b4395a 629 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
hayama 0:da22b0b4395a 630 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
hayama 0:da22b0b4395a 631 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
hayama 0:da22b0b4395a 632 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
hayama 0:da22b0b4395a 633 uint32_t RESERVED0[864];
hayama 0:da22b0b4395a 634 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
hayama 0:da22b0b4395a 635 uint32_t RESERVED1[15];
hayama 0:da22b0b4395a 636 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
hayama 0:da22b0b4395a 637 uint32_t RESERVED2[15];
hayama 0:da22b0b4395a 638 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
hayama 0:da22b0b4395a 639 uint32_t RESERVED3[29];
hayama 0:da22b0b4395a 640 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
hayama 0:da22b0b4395a 641 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
hayama 0:da22b0b4395a 642 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
hayama 0:da22b0b4395a 643 uint32_t RESERVED4[43];
hayama 0:da22b0b4395a 644 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
hayama 0:da22b0b4395a 645 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
hayama 0:da22b0b4395a 646 uint32_t RESERVED5[6];
hayama 0:da22b0b4395a 647 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
hayama 0:da22b0b4395a 648 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
hayama 0:da22b0b4395a 649 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
hayama 0:da22b0b4395a 650 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
hayama 0:da22b0b4395a 651 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
hayama 0:da22b0b4395a 652 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
hayama 0:da22b0b4395a 653 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
hayama 0:da22b0b4395a 654 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
hayama 0:da22b0b4395a 655 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
hayama 0:da22b0b4395a 656 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
hayama 0:da22b0b4395a 657 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
hayama 0:da22b0b4395a 658 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
hayama 0:da22b0b4395a 659 } ITM_Type;
hayama 0:da22b0b4395a 660
hayama 0:da22b0b4395a 661 /* ITM Trace Privilege Register Definitions */
hayama 0:da22b0b4395a 662 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
hayama 0:da22b0b4395a 663 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
hayama 0:da22b0b4395a 664
hayama 0:da22b0b4395a 665 /* ITM Trace Control Register Definitions */
hayama 0:da22b0b4395a 666 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
hayama 0:da22b0b4395a 667 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
hayama 0:da22b0b4395a 668
hayama 0:da22b0b4395a 669 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
hayama 0:da22b0b4395a 670 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
hayama 0:da22b0b4395a 671
hayama 0:da22b0b4395a 672 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
hayama 0:da22b0b4395a 673 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
hayama 0:da22b0b4395a 674
hayama 0:da22b0b4395a 675 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
hayama 0:da22b0b4395a 676 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
hayama 0:da22b0b4395a 677
hayama 0:da22b0b4395a 678 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
hayama 0:da22b0b4395a 679 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
hayama 0:da22b0b4395a 680
hayama 0:da22b0b4395a 681 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
hayama 0:da22b0b4395a 682 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
hayama 0:da22b0b4395a 683
hayama 0:da22b0b4395a 684 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
hayama 0:da22b0b4395a 685 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
hayama 0:da22b0b4395a 686
hayama 0:da22b0b4395a 687 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
hayama 0:da22b0b4395a 688 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
hayama 0:da22b0b4395a 689
hayama 0:da22b0b4395a 690 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
hayama 0:da22b0b4395a 691 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
hayama 0:da22b0b4395a 692
hayama 0:da22b0b4395a 693 /* ITM Integration Write Register Definitions */
hayama 0:da22b0b4395a 694 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
hayama 0:da22b0b4395a 695 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
hayama 0:da22b0b4395a 696
hayama 0:da22b0b4395a 697 /* ITM Integration Read Register Definitions */
hayama 0:da22b0b4395a 698 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
hayama 0:da22b0b4395a 699 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
hayama 0:da22b0b4395a 700
hayama 0:da22b0b4395a 701 /* ITM Integration Mode Control Register Definitions */
hayama 0:da22b0b4395a 702 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
hayama 0:da22b0b4395a 703 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
hayama 0:da22b0b4395a 704
hayama 0:da22b0b4395a 705 /* ITM Lock Status Register Definitions */
hayama 0:da22b0b4395a 706 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
hayama 0:da22b0b4395a 707 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
hayama 0:da22b0b4395a 708
hayama 0:da22b0b4395a 709 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
hayama 0:da22b0b4395a 710 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
hayama 0:da22b0b4395a 711
hayama 0:da22b0b4395a 712 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
hayama 0:da22b0b4395a 713 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
hayama 0:da22b0b4395a 714
hayama 0:da22b0b4395a 715 /*@}*/ /* end of group CMSIS_ITM */
hayama 0:da22b0b4395a 716
hayama 0:da22b0b4395a 717
hayama 0:da22b0b4395a 718 /** \ingroup CMSIS_core_register
hayama 0:da22b0b4395a 719 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
hayama 0:da22b0b4395a 720 \brief Type definitions for the Data Watchpoint and Trace (DWT)
hayama 0:da22b0b4395a 721 @{
hayama 0:da22b0b4395a 722 */
hayama 0:da22b0b4395a 723
hayama 0:da22b0b4395a 724 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
hayama 0:da22b0b4395a 725 */
hayama 0:da22b0b4395a 726 typedef struct
hayama 0:da22b0b4395a 727 {
hayama 0:da22b0b4395a 728 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
hayama 0:da22b0b4395a 729 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
hayama 0:da22b0b4395a 730 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
hayama 0:da22b0b4395a 731 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
hayama 0:da22b0b4395a 732 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
hayama 0:da22b0b4395a 733 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
hayama 0:da22b0b4395a 734 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
hayama 0:da22b0b4395a 735 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
hayama 0:da22b0b4395a 736 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
hayama 0:da22b0b4395a 737 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
hayama 0:da22b0b4395a 738 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
hayama 0:da22b0b4395a 739 uint32_t RESERVED0[1];
hayama 0:da22b0b4395a 740 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
hayama 0:da22b0b4395a 741 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
hayama 0:da22b0b4395a 742 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
hayama 0:da22b0b4395a 743 uint32_t RESERVED1[1];
hayama 0:da22b0b4395a 744 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
hayama 0:da22b0b4395a 745 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
hayama 0:da22b0b4395a 746 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
hayama 0:da22b0b4395a 747 uint32_t RESERVED2[1];
hayama 0:da22b0b4395a 748 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
hayama 0:da22b0b4395a 749 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
hayama 0:da22b0b4395a 750 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
hayama 0:da22b0b4395a 751 } DWT_Type;
hayama 0:da22b0b4395a 752
hayama 0:da22b0b4395a 753 /* DWT Control Register Definitions */
hayama 0:da22b0b4395a 754 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
hayama 0:da22b0b4395a 755 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
hayama 0:da22b0b4395a 756
hayama 0:da22b0b4395a 757 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
hayama 0:da22b0b4395a 758 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
hayama 0:da22b0b4395a 759
hayama 0:da22b0b4395a 760 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
hayama 0:da22b0b4395a 761 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
hayama 0:da22b0b4395a 762
hayama 0:da22b0b4395a 763 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
hayama 0:da22b0b4395a 764 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
hayama 0:da22b0b4395a 765
hayama 0:da22b0b4395a 766 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
hayama 0:da22b0b4395a 767 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
hayama 0:da22b0b4395a 768
hayama 0:da22b0b4395a 769 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
hayama 0:da22b0b4395a 770 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
hayama 0:da22b0b4395a 771
hayama 0:da22b0b4395a 772 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
hayama 0:da22b0b4395a 773 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
hayama 0:da22b0b4395a 774
hayama 0:da22b0b4395a 775 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
hayama 0:da22b0b4395a 776 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
hayama 0:da22b0b4395a 777
hayama 0:da22b0b4395a 778 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
hayama 0:da22b0b4395a 779 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
hayama 0:da22b0b4395a 780
hayama 0:da22b0b4395a 781 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
hayama 0:da22b0b4395a 782 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
hayama 0:da22b0b4395a 783
hayama 0:da22b0b4395a 784 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
hayama 0:da22b0b4395a 785 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
hayama 0:da22b0b4395a 786
hayama 0:da22b0b4395a 787 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
hayama 0:da22b0b4395a 788 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
hayama 0:da22b0b4395a 789
hayama 0:da22b0b4395a 790 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
hayama 0:da22b0b4395a 791 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
hayama 0:da22b0b4395a 792
hayama 0:da22b0b4395a 793 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
hayama 0:da22b0b4395a 794 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
hayama 0:da22b0b4395a 795
hayama 0:da22b0b4395a 796 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
hayama 0:da22b0b4395a 797 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
hayama 0:da22b0b4395a 798
hayama 0:da22b0b4395a 799 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
hayama 0:da22b0b4395a 800 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
hayama 0:da22b0b4395a 801
hayama 0:da22b0b4395a 802 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
hayama 0:da22b0b4395a 803 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
hayama 0:da22b0b4395a 804
hayama 0:da22b0b4395a 805 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
hayama 0:da22b0b4395a 806 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
hayama 0:da22b0b4395a 807
hayama 0:da22b0b4395a 808 /* DWT CPI Count Register Definitions */
hayama 0:da22b0b4395a 809 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
hayama 0:da22b0b4395a 810 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
hayama 0:da22b0b4395a 811
hayama 0:da22b0b4395a 812 /* DWT Exception Overhead Count Register Definitions */
hayama 0:da22b0b4395a 813 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
hayama 0:da22b0b4395a 814 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
hayama 0:da22b0b4395a 815
hayama 0:da22b0b4395a 816 /* DWT Sleep Count Register Definitions */
hayama 0:da22b0b4395a 817 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
hayama 0:da22b0b4395a 818 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
hayama 0:da22b0b4395a 819
hayama 0:da22b0b4395a 820 /* DWT LSU Count Register Definitions */
hayama 0:da22b0b4395a 821 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
hayama 0:da22b0b4395a 822 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
hayama 0:da22b0b4395a 823
hayama 0:da22b0b4395a 824 /* DWT Folded-instruction Count Register Definitions */
hayama 0:da22b0b4395a 825 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
hayama 0:da22b0b4395a 826 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
hayama 0:da22b0b4395a 827
hayama 0:da22b0b4395a 828 /* DWT Comparator Mask Register Definitions */
hayama 0:da22b0b4395a 829 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
hayama 0:da22b0b4395a 830 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
hayama 0:da22b0b4395a 831
hayama 0:da22b0b4395a 832 /* DWT Comparator Function Register Definitions */
hayama 0:da22b0b4395a 833 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
hayama 0:da22b0b4395a 834 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
hayama 0:da22b0b4395a 835
hayama 0:da22b0b4395a 836 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
hayama 0:da22b0b4395a 837 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
hayama 0:da22b0b4395a 838
hayama 0:da22b0b4395a 839 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
hayama 0:da22b0b4395a 840 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
hayama 0:da22b0b4395a 841
hayama 0:da22b0b4395a 842 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
hayama 0:da22b0b4395a 843 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
hayama 0:da22b0b4395a 844
hayama 0:da22b0b4395a 845 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
hayama 0:da22b0b4395a 846 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
hayama 0:da22b0b4395a 847
hayama 0:da22b0b4395a 848 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
hayama 0:da22b0b4395a 849 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
hayama 0:da22b0b4395a 850
hayama 0:da22b0b4395a 851 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
hayama 0:da22b0b4395a 852 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
hayama 0:da22b0b4395a 853
hayama 0:da22b0b4395a 854 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
hayama 0:da22b0b4395a 855 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
hayama 0:da22b0b4395a 856
hayama 0:da22b0b4395a 857 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
hayama 0:da22b0b4395a 858 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
hayama 0:da22b0b4395a 859
hayama 0:da22b0b4395a 860 /*@}*/ /* end of group CMSIS_DWT */
hayama 0:da22b0b4395a 861
hayama 0:da22b0b4395a 862
hayama 0:da22b0b4395a 863 /** \ingroup CMSIS_core_register
hayama 0:da22b0b4395a 864 \defgroup CMSIS_TPI Trace Port Interface (TPI)
hayama 0:da22b0b4395a 865 \brief Type definitions for the Trace Port Interface (TPI)
hayama 0:da22b0b4395a 866 @{
hayama 0:da22b0b4395a 867 */
hayama 0:da22b0b4395a 868
hayama 0:da22b0b4395a 869 /** \brief Structure type to access the Trace Port Interface Register (TPI).
hayama 0:da22b0b4395a 870 */
hayama 0:da22b0b4395a 871 typedef struct
hayama 0:da22b0b4395a 872 {
hayama 0:da22b0b4395a 873 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
hayama 0:da22b0b4395a 874 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
hayama 0:da22b0b4395a 875 uint32_t RESERVED0[2];
hayama 0:da22b0b4395a 876 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
hayama 0:da22b0b4395a 877 uint32_t RESERVED1[55];
hayama 0:da22b0b4395a 878 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
hayama 0:da22b0b4395a 879 uint32_t RESERVED2[131];
hayama 0:da22b0b4395a 880 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
hayama 0:da22b0b4395a 881 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
hayama 0:da22b0b4395a 882 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
hayama 0:da22b0b4395a 883 uint32_t RESERVED3[759];
hayama 0:da22b0b4395a 884 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
hayama 0:da22b0b4395a 885 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
hayama 0:da22b0b4395a 886 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
hayama 0:da22b0b4395a 887 uint32_t RESERVED4[1];
hayama 0:da22b0b4395a 888 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
hayama 0:da22b0b4395a 889 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
hayama 0:da22b0b4395a 890 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
hayama 0:da22b0b4395a 891 uint32_t RESERVED5[39];
hayama 0:da22b0b4395a 892 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
hayama 0:da22b0b4395a 893 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
hayama 0:da22b0b4395a 894 uint32_t RESERVED7[8];
hayama 0:da22b0b4395a 895 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
hayama 0:da22b0b4395a 896 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
hayama 0:da22b0b4395a 897 } TPI_Type;
hayama 0:da22b0b4395a 898
hayama 0:da22b0b4395a 899 /* TPI Asynchronous Clock Prescaler Register Definitions */
hayama 0:da22b0b4395a 900 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
hayama 0:da22b0b4395a 901 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
hayama 0:da22b0b4395a 902
hayama 0:da22b0b4395a 903 /* TPI Selected Pin Protocol Register Definitions */
hayama 0:da22b0b4395a 904 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
hayama 0:da22b0b4395a 905 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
hayama 0:da22b0b4395a 906
hayama 0:da22b0b4395a 907 /* TPI Formatter and Flush Status Register Definitions */
hayama 0:da22b0b4395a 908 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
hayama 0:da22b0b4395a 909 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
hayama 0:da22b0b4395a 910
hayama 0:da22b0b4395a 911 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
hayama 0:da22b0b4395a 912 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
hayama 0:da22b0b4395a 913
hayama 0:da22b0b4395a 914 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
hayama 0:da22b0b4395a 915 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
hayama 0:da22b0b4395a 916
hayama 0:da22b0b4395a 917 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
hayama 0:da22b0b4395a 918 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
hayama 0:da22b0b4395a 919
hayama 0:da22b0b4395a 920 /* TPI Formatter and Flush Control Register Definitions */
hayama 0:da22b0b4395a 921 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
hayama 0:da22b0b4395a 922 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
hayama 0:da22b0b4395a 923
hayama 0:da22b0b4395a 924 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
hayama 0:da22b0b4395a 925 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
hayama 0:da22b0b4395a 926
hayama 0:da22b0b4395a 927 /* TPI TRIGGER Register Definitions */
hayama 0:da22b0b4395a 928 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
hayama 0:da22b0b4395a 929 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
hayama 0:da22b0b4395a 930
hayama 0:da22b0b4395a 931 /* TPI Integration ETM Data Register Definitions (FIFO0) */
hayama 0:da22b0b4395a 932 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
hayama 0:da22b0b4395a 933 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
hayama 0:da22b0b4395a 934
hayama 0:da22b0b4395a 935 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
hayama 0:da22b0b4395a 936 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
hayama 0:da22b0b4395a 937
hayama 0:da22b0b4395a 938 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
hayama 0:da22b0b4395a 939 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
hayama 0:da22b0b4395a 940
hayama 0:da22b0b4395a 941 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
hayama 0:da22b0b4395a 942 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
hayama 0:da22b0b4395a 943
hayama 0:da22b0b4395a 944 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
hayama 0:da22b0b4395a 945 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
hayama 0:da22b0b4395a 946
hayama 0:da22b0b4395a 947 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
hayama 0:da22b0b4395a 948 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
hayama 0:da22b0b4395a 949
hayama 0:da22b0b4395a 950 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
hayama 0:da22b0b4395a 951 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
hayama 0:da22b0b4395a 952
hayama 0:da22b0b4395a 953 /* TPI ITATBCTR2 Register Definitions */
hayama 0:da22b0b4395a 954 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
hayama 0:da22b0b4395a 955 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
hayama 0:da22b0b4395a 956
hayama 0:da22b0b4395a 957 /* TPI Integration ITM Data Register Definitions (FIFO1) */
hayama 0:da22b0b4395a 958 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
hayama 0:da22b0b4395a 959 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
hayama 0:da22b0b4395a 960
hayama 0:da22b0b4395a 961 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
hayama 0:da22b0b4395a 962 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
hayama 0:da22b0b4395a 963
hayama 0:da22b0b4395a 964 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
hayama 0:da22b0b4395a 965 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
hayama 0:da22b0b4395a 966
hayama 0:da22b0b4395a 967 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
hayama 0:da22b0b4395a 968 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
hayama 0:da22b0b4395a 969
hayama 0:da22b0b4395a 970 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
hayama 0:da22b0b4395a 971 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
hayama 0:da22b0b4395a 972
hayama 0:da22b0b4395a 973 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
hayama 0:da22b0b4395a 974 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
hayama 0:da22b0b4395a 975
hayama 0:da22b0b4395a 976 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
hayama 0:da22b0b4395a 977 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
hayama 0:da22b0b4395a 978
hayama 0:da22b0b4395a 979 /* TPI ITATBCTR0 Register Definitions */
hayama 0:da22b0b4395a 980 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
hayama 0:da22b0b4395a 981 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
hayama 0:da22b0b4395a 982
hayama 0:da22b0b4395a 983 /* TPI Integration Mode Control Register Definitions */
hayama 0:da22b0b4395a 984 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
hayama 0:da22b0b4395a 985 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
hayama 0:da22b0b4395a 986
hayama 0:da22b0b4395a 987 /* TPI DEVID Register Definitions */
hayama 0:da22b0b4395a 988 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
hayama 0:da22b0b4395a 989 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
hayama 0:da22b0b4395a 990
hayama 0:da22b0b4395a 991 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
hayama 0:da22b0b4395a 992 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
hayama 0:da22b0b4395a 993
hayama 0:da22b0b4395a 994 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
hayama 0:da22b0b4395a 995 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
hayama 0:da22b0b4395a 996
hayama 0:da22b0b4395a 997 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
hayama 0:da22b0b4395a 998 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
hayama 0:da22b0b4395a 999
hayama 0:da22b0b4395a 1000 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
hayama 0:da22b0b4395a 1001 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
hayama 0:da22b0b4395a 1002
hayama 0:da22b0b4395a 1003 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
hayama 0:da22b0b4395a 1004 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
hayama 0:da22b0b4395a 1005
hayama 0:da22b0b4395a 1006 /* TPI DEVTYPE Register Definitions */
hayama 0:da22b0b4395a 1007 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
hayama 0:da22b0b4395a 1008 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
hayama 0:da22b0b4395a 1009
hayama 0:da22b0b4395a 1010 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
hayama 0:da22b0b4395a 1011 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
hayama 0:da22b0b4395a 1012
hayama 0:da22b0b4395a 1013 /*@}*/ /* end of group CMSIS_TPI */
hayama 0:da22b0b4395a 1014
hayama 0:da22b0b4395a 1015
hayama 0:da22b0b4395a 1016 #if (__MPU_PRESENT == 1)
hayama 0:da22b0b4395a 1017 /** \ingroup CMSIS_core_register
hayama 0:da22b0b4395a 1018 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
hayama 0:da22b0b4395a 1019 \brief Type definitions for the Memory Protection Unit (MPU)
hayama 0:da22b0b4395a 1020 @{
hayama 0:da22b0b4395a 1021 */
hayama 0:da22b0b4395a 1022
hayama 0:da22b0b4395a 1023 /** \brief Structure type to access the Memory Protection Unit (MPU).
hayama 0:da22b0b4395a 1024 */
hayama 0:da22b0b4395a 1025 typedef struct
hayama 0:da22b0b4395a 1026 {
hayama 0:da22b0b4395a 1027 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
hayama 0:da22b0b4395a 1028 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
hayama 0:da22b0b4395a 1029 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
hayama 0:da22b0b4395a 1030 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
hayama 0:da22b0b4395a 1031 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
hayama 0:da22b0b4395a 1032 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
hayama 0:da22b0b4395a 1033 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
hayama 0:da22b0b4395a 1034 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
hayama 0:da22b0b4395a 1035 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
hayama 0:da22b0b4395a 1036 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
hayama 0:da22b0b4395a 1037 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
hayama 0:da22b0b4395a 1038 } MPU_Type;
hayama 0:da22b0b4395a 1039
hayama 0:da22b0b4395a 1040 /* MPU Type Register */
hayama 0:da22b0b4395a 1041 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
hayama 0:da22b0b4395a 1042 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
hayama 0:da22b0b4395a 1043
hayama 0:da22b0b4395a 1044 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
hayama 0:da22b0b4395a 1045 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
hayama 0:da22b0b4395a 1046
hayama 0:da22b0b4395a 1047 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
hayama 0:da22b0b4395a 1048 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
hayama 0:da22b0b4395a 1049
hayama 0:da22b0b4395a 1050 /* MPU Control Register */
hayama 0:da22b0b4395a 1051 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
hayama 0:da22b0b4395a 1052 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
hayama 0:da22b0b4395a 1053
hayama 0:da22b0b4395a 1054 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
hayama 0:da22b0b4395a 1055 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
hayama 0:da22b0b4395a 1056
hayama 0:da22b0b4395a 1057 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
hayama 0:da22b0b4395a 1058 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
hayama 0:da22b0b4395a 1059
hayama 0:da22b0b4395a 1060 /* MPU Region Number Register */
hayama 0:da22b0b4395a 1061 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
hayama 0:da22b0b4395a 1062 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
hayama 0:da22b0b4395a 1063
hayama 0:da22b0b4395a 1064 /* MPU Region Base Address Register */
hayama 0:da22b0b4395a 1065 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
hayama 0:da22b0b4395a 1066 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
hayama 0:da22b0b4395a 1067
hayama 0:da22b0b4395a 1068 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
hayama 0:da22b0b4395a 1069 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
hayama 0:da22b0b4395a 1070
hayama 0:da22b0b4395a 1071 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
hayama 0:da22b0b4395a 1072 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
hayama 0:da22b0b4395a 1073
hayama 0:da22b0b4395a 1074 /* MPU Region Attribute and Size Register */
hayama 0:da22b0b4395a 1075 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
hayama 0:da22b0b4395a 1076 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
hayama 0:da22b0b4395a 1077
hayama 0:da22b0b4395a 1078 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
hayama 0:da22b0b4395a 1079 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
hayama 0:da22b0b4395a 1080
hayama 0:da22b0b4395a 1081 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
hayama 0:da22b0b4395a 1082 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
hayama 0:da22b0b4395a 1083
hayama 0:da22b0b4395a 1084 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
hayama 0:da22b0b4395a 1085 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
hayama 0:da22b0b4395a 1086
hayama 0:da22b0b4395a 1087 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
hayama 0:da22b0b4395a 1088 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
hayama 0:da22b0b4395a 1089
hayama 0:da22b0b4395a 1090 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
hayama 0:da22b0b4395a 1091 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
hayama 0:da22b0b4395a 1092
hayama 0:da22b0b4395a 1093 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
hayama 0:da22b0b4395a 1094 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
hayama 0:da22b0b4395a 1095
hayama 0:da22b0b4395a 1096 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
hayama 0:da22b0b4395a 1097 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
hayama 0:da22b0b4395a 1098
hayama 0:da22b0b4395a 1099 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
hayama 0:da22b0b4395a 1100 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
hayama 0:da22b0b4395a 1101
hayama 0:da22b0b4395a 1102 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
hayama 0:da22b0b4395a 1103 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
hayama 0:da22b0b4395a 1104
hayama 0:da22b0b4395a 1105 /*@} end of group CMSIS_MPU */
hayama 0:da22b0b4395a 1106 #endif
hayama 0:da22b0b4395a 1107
hayama 0:da22b0b4395a 1108
hayama 0:da22b0b4395a 1109 /** \ingroup CMSIS_core_register
hayama 0:da22b0b4395a 1110 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
hayama 0:da22b0b4395a 1111 \brief Type definitions for the Core Debug Registers
hayama 0:da22b0b4395a 1112 @{
hayama 0:da22b0b4395a 1113 */
hayama 0:da22b0b4395a 1114
hayama 0:da22b0b4395a 1115 /** \brief Structure type to access the Core Debug Register (CoreDebug).
hayama 0:da22b0b4395a 1116 */
hayama 0:da22b0b4395a 1117 typedef struct
hayama 0:da22b0b4395a 1118 {
hayama 0:da22b0b4395a 1119 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
hayama 0:da22b0b4395a 1120 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
hayama 0:da22b0b4395a 1121 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
hayama 0:da22b0b4395a 1122 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
hayama 0:da22b0b4395a 1123 } CoreDebug_Type;
hayama 0:da22b0b4395a 1124
hayama 0:da22b0b4395a 1125 /* Debug Halting Control and Status Register */
hayama 0:da22b0b4395a 1126 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
hayama 0:da22b0b4395a 1127 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
hayama 0:da22b0b4395a 1128
hayama 0:da22b0b4395a 1129 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
hayama 0:da22b0b4395a 1130 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
hayama 0:da22b0b4395a 1131
hayama 0:da22b0b4395a 1132 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
hayama 0:da22b0b4395a 1133 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
hayama 0:da22b0b4395a 1134
hayama 0:da22b0b4395a 1135 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
hayama 0:da22b0b4395a 1136 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
hayama 0:da22b0b4395a 1137
hayama 0:da22b0b4395a 1138 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
hayama 0:da22b0b4395a 1139 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
hayama 0:da22b0b4395a 1140
hayama 0:da22b0b4395a 1141 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
hayama 0:da22b0b4395a 1142 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
hayama 0:da22b0b4395a 1143
hayama 0:da22b0b4395a 1144 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
hayama 0:da22b0b4395a 1145 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
hayama 0:da22b0b4395a 1146
hayama 0:da22b0b4395a 1147 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
hayama 0:da22b0b4395a 1148 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
hayama 0:da22b0b4395a 1149
hayama 0:da22b0b4395a 1150 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
hayama 0:da22b0b4395a 1151 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
hayama 0:da22b0b4395a 1152
hayama 0:da22b0b4395a 1153 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
hayama 0:da22b0b4395a 1154 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
hayama 0:da22b0b4395a 1155
hayama 0:da22b0b4395a 1156 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
hayama 0:da22b0b4395a 1157 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
hayama 0:da22b0b4395a 1158
hayama 0:da22b0b4395a 1159 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
hayama 0:da22b0b4395a 1160 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
hayama 0:da22b0b4395a 1161
hayama 0:da22b0b4395a 1162 /* Debug Core Register Selector Register */
hayama 0:da22b0b4395a 1163 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
hayama 0:da22b0b4395a 1164 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
hayama 0:da22b0b4395a 1165
hayama 0:da22b0b4395a 1166 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
hayama 0:da22b0b4395a 1167 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
hayama 0:da22b0b4395a 1168
hayama 0:da22b0b4395a 1169 /* Debug Exception and Monitor Control Register */
hayama 0:da22b0b4395a 1170 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
hayama 0:da22b0b4395a 1171 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
hayama 0:da22b0b4395a 1172
hayama 0:da22b0b4395a 1173 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
hayama 0:da22b0b4395a 1174 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
hayama 0:da22b0b4395a 1175
hayama 0:da22b0b4395a 1176 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
hayama 0:da22b0b4395a 1177 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
hayama 0:da22b0b4395a 1178
hayama 0:da22b0b4395a 1179 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
hayama 0:da22b0b4395a 1180 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
hayama 0:da22b0b4395a 1181
hayama 0:da22b0b4395a 1182 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
hayama 0:da22b0b4395a 1183 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
hayama 0:da22b0b4395a 1184
hayama 0:da22b0b4395a 1185 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
hayama 0:da22b0b4395a 1186 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
hayama 0:da22b0b4395a 1187
hayama 0:da22b0b4395a 1188 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
hayama 0:da22b0b4395a 1189 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
hayama 0:da22b0b4395a 1190
hayama 0:da22b0b4395a 1191 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
hayama 0:da22b0b4395a 1192 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
hayama 0:da22b0b4395a 1193
hayama 0:da22b0b4395a 1194 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
hayama 0:da22b0b4395a 1195 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
hayama 0:da22b0b4395a 1196
hayama 0:da22b0b4395a 1197 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
hayama 0:da22b0b4395a 1198 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
hayama 0:da22b0b4395a 1199
hayama 0:da22b0b4395a 1200 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
hayama 0:da22b0b4395a 1201 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
hayama 0:da22b0b4395a 1202
hayama 0:da22b0b4395a 1203 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
hayama 0:da22b0b4395a 1204 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
hayama 0:da22b0b4395a 1205
hayama 0:da22b0b4395a 1206 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
hayama 0:da22b0b4395a 1207 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
hayama 0:da22b0b4395a 1208
hayama 0:da22b0b4395a 1209 /*@} end of group CMSIS_CoreDebug */
hayama 0:da22b0b4395a 1210
hayama 0:da22b0b4395a 1211
hayama 0:da22b0b4395a 1212 /** \ingroup CMSIS_core_register
hayama 0:da22b0b4395a 1213 \defgroup CMSIS_core_base Core Definitions
hayama 0:da22b0b4395a 1214 \brief Definitions for base addresses, unions, and structures.
hayama 0:da22b0b4395a 1215 @{
hayama 0:da22b0b4395a 1216 */
hayama 0:da22b0b4395a 1217
hayama 0:da22b0b4395a 1218 /* Memory mapping of Cortex-M3 Hardware */
hayama 0:da22b0b4395a 1219 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
hayama 0:da22b0b4395a 1220 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
hayama 0:da22b0b4395a 1221 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
hayama 0:da22b0b4395a 1222 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
hayama 0:da22b0b4395a 1223 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
hayama 0:da22b0b4395a 1224 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
hayama 0:da22b0b4395a 1225 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
hayama 0:da22b0b4395a 1226 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
hayama 0:da22b0b4395a 1227
hayama 0:da22b0b4395a 1228 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
hayama 0:da22b0b4395a 1229 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
hayama 0:da22b0b4395a 1230 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
hayama 0:da22b0b4395a 1231 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
hayama 0:da22b0b4395a 1232 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
hayama 0:da22b0b4395a 1233 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
hayama 0:da22b0b4395a 1234 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
hayama 0:da22b0b4395a 1235 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
hayama 0:da22b0b4395a 1236
hayama 0:da22b0b4395a 1237 #if (__MPU_PRESENT == 1)
hayama 0:da22b0b4395a 1238 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
hayama 0:da22b0b4395a 1239 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
hayama 0:da22b0b4395a 1240 #endif
hayama 0:da22b0b4395a 1241
hayama 0:da22b0b4395a 1242 /*@} */
hayama 0:da22b0b4395a 1243
hayama 0:da22b0b4395a 1244
hayama 0:da22b0b4395a 1245
hayama 0:da22b0b4395a 1246 /*******************************************************************************
hayama 0:da22b0b4395a 1247 * Hardware Abstraction Layer
hayama 0:da22b0b4395a 1248 Core Function Interface contains:
hayama 0:da22b0b4395a 1249 - Core NVIC Functions
hayama 0:da22b0b4395a 1250 - Core SysTick Functions
hayama 0:da22b0b4395a 1251 - Core Debug Functions
hayama 0:da22b0b4395a 1252 - Core Register Access Functions
hayama 0:da22b0b4395a 1253 ******************************************************************************/
hayama 0:da22b0b4395a 1254 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
hayama 0:da22b0b4395a 1255 */
hayama 0:da22b0b4395a 1256
hayama 0:da22b0b4395a 1257
hayama 0:da22b0b4395a 1258
hayama 0:da22b0b4395a 1259 /* ########################## NVIC functions #################################### */
hayama 0:da22b0b4395a 1260 /** \ingroup CMSIS_Core_FunctionInterface
hayama 0:da22b0b4395a 1261 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
hayama 0:da22b0b4395a 1262 \brief Functions that manage interrupts and exceptions via the NVIC.
hayama 0:da22b0b4395a 1263 @{
hayama 0:da22b0b4395a 1264 */
hayama 0:da22b0b4395a 1265
hayama 0:da22b0b4395a 1266 /** \brief Set Priority Grouping
hayama 0:da22b0b4395a 1267
hayama 0:da22b0b4395a 1268 The function sets the priority grouping field using the required unlock sequence.
hayama 0:da22b0b4395a 1269 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
hayama 0:da22b0b4395a 1270 Only values from 0..7 are used.
hayama 0:da22b0b4395a 1271 In case of a conflict between priority grouping and available
hayama 0:da22b0b4395a 1272 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
hayama 0:da22b0b4395a 1273
hayama 0:da22b0b4395a 1274 \param [in] PriorityGroup Priority grouping field.
hayama 0:da22b0b4395a 1275 */
hayama 0:da22b0b4395a 1276 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
hayama 0:da22b0b4395a 1277 {
hayama 0:da22b0b4395a 1278 uint32_t reg_value;
hayama 0:da22b0b4395a 1279 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
hayama 0:da22b0b4395a 1280
hayama 0:da22b0b4395a 1281 reg_value = SCB->AIRCR; /* read old register configuration */
hayama 0:da22b0b4395a 1282 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
hayama 0:da22b0b4395a 1283 reg_value = (reg_value |
hayama 0:da22b0b4395a 1284 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
hayama 0:da22b0b4395a 1285 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
hayama 0:da22b0b4395a 1286 SCB->AIRCR = reg_value;
hayama 0:da22b0b4395a 1287 }
hayama 0:da22b0b4395a 1288
hayama 0:da22b0b4395a 1289
hayama 0:da22b0b4395a 1290 /** \brief Get Priority Grouping
hayama 0:da22b0b4395a 1291
hayama 0:da22b0b4395a 1292 The function reads the priority grouping field from the NVIC Interrupt Controller.
hayama 0:da22b0b4395a 1293
hayama 0:da22b0b4395a 1294 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
hayama 0:da22b0b4395a 1295 */
hayama 0:da22b0b4395a 1296 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
hayama 0:da22b0b4395a 1297 {
hayama 0:da22b0b4395a 1298 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
hayama 0:da22b0b4395a 1299 }
hayama 0:da22b0b4395a 1300
hayama 0:da22b0b4395a 1301
hayama 0:da22b0b4395a 1302 /** \brief Enable External Interrupt
hayama 0:da22b0b4395a 1303
hayama 0:da22b0b4395a 1304 The function enables a device-specific interrupt in the NVIC interrupt controller.
hayama 0:da22b0b4395a 1305
hayama 0:da22b0b4395a 1306 \param [in] IRQn External interrupt number. Value cannot be negative.
hayama 0:da22b0b4395a 1307 */
hayama 0:da22b0b4395a 1308 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
hayama 0:da22b0b4395a 1309 {
hayama 0:da22b0b4395a 1310 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
hayama 0:da22b0b4395a 1311 }
hayama 0:da22b0b4395a 1312
hayama 0:da22b0b4395a 1313
hayama 0:da22b0b4395a 1314 /** \brief Disable External Interrupt
hayama 0:da22b0b4395a 1315
hayama 0:da22b0b4395a 1316 The function disables a device-specific interrupt in the NVIC interrupt controller.
hayama 0:da22b0b4395a 1317
hayama 0:da22b0b4395a 1318 \param [in] IRQn External interrupt number. Value cannot be negative.
hayama 0:da22b0b4395a 1319 */
hayama 0:da22b0b4395a 1320 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
hayama 0:da22b0b4395a 1321 {
hayama 0:da22b0b4395a 1322 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
hayama 0:da22b0b4395a 1323 }
hayama 0:da22b0b4395a 1324
hayama 0:da22b0b4395a 1325
hayama 0:da22b0b4395a 1326 /** \brief Get Pending Interrupt
hayama 0:da22b0b4395a 1327
hayama 0:da22b0b4395a 1328 The function reads the pending register in the NVIC and returns the pending bit
hayama 0:da22b0b4395a 1329 for the specified interrupt.
hayama 0:da22b0b4395a 1330
hayama 0:da22b0b4395a 1331 \param [in] IRQn Interrupt number.
hayama 0:da22b0b4395a 1332
hayama 0:da22b0b4395a 1333 \return 0 Interrupt status is not pending.
hayama 0:da22b0b4395a 1334 \return 1 Interrupt status is pending.
hayama 0:da22b0b4395a 1335 */
hayama 0:da22b0b4395a 1336 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
hayama 0:da22b0b4395a 1337 {
hayama 0:da22b0b4395a 1338 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
hayama 0:da22b0b4395a 1339 }
hayama 0:da22b0b4395a 1340
hayama 0:da22b0b4395a 1341
hayama 0:da22b0b4395a 1342 /** \brief Set Pending Interrupt
hayama 0:da22b0b4395a 1343
hayama 0:da22b0b4395a 1344 The function sets the pending bit of an external interrupt.
hayama 0:da22b0b4395a 1345
hayama 0:da22b0b4395a 1346 \param [in] IRQn Interrupt number. Value cannot be negative.
hayama 0:da22b0b4395a 1347 */
hayama 0:da22b0b4395a 1348 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
hayama 0:da22b0b4395a 1349 {
hayama 0:da22b0b4395a 1350 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
hayama 0:da22b0b4395a 1351 }
hayama 0:da22b0b4395a 1352
hayama 0:da22b0b4395a 1353
hayama 0:da22b0b4395a 1354 /** \brief Clear Pending Interrupt
hayama 0:da22b0b4395a 1355
hayama 0:da22b0b4395a 1356 The function clears the pending bit of an external interrupt.
hayama 0:da22b0b4395a 1357
hayama 0:da22b0b4395a 1358 \param [in] IRQn External interrupt number. Value cannot be negative.
hayama 0:da22b0b4395a 1359 */
hayama 0:da22b0b4395a 1360 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
hayama 0:da22b0b4395a 1361 {
hayama 0:da22b0b4395a 1362 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
hayama 0:da22b0b4395a 1363 }
hayama 0:da22b0b4395a 1364
hayama 0:da22b0b4395a 1365
hayama 0:da22b0b4395a 1366 /** \brief Get Active Interrupt
hayama 0:da22b0b4395a 1367
hayama 0:da22b0b4395a 1368 The function reads the active register in NVIC and returns the active bit.
hayama 0:da22b0b4395a 1369
hayama 0:da22b0b4395a 1370 \param [in] IRQn Interrupt number.
hayama 0:da22b0b4395a 1371
hayama 0:da22b0b4395a 1372 \return 0 Interrupt status is not active.
hayama 0:da22b0b4395a 1373 \return 1 Interrupt status is active.
hayama 0:da22b0b4395a 1374 */
hayama 0:da22b0b4395a 1375 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
hayama 0:da22b0b4395a 1376 {
hayama 0:da22b0b4395a 1377 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
hayama 0:da22b0b4395a 1378 }
hayama 0:da22b0b4395a 1379
hayama 0:da22b0b4395a 1380
hayama 0:da22b0b4395a 1381 /** \brief Set Interrupt Priority
hayama 0:da22b0b4395a 1382
hayama 0:da22b0b4395a 1383 The function sets the priority of an interrupt.
hayama 0:da22b0b4395a 1384
hayama 0:da22b0b4395a 1385 \note The priority cannot be set for every core interrupt.
hayama 0:da22b0b4395a 1386
hayama 0:da22b0b4395a 1387 \param [in] IRQn Interrupt number.
hayama 0:da22b0b4395a 1388 \param [in] priority Priority to set.
hayama 0:da22b0b4395a 1389 */
hayama 0:da22b0b4395a 1390 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
hayama 0:da22b0b4395a 1391 {
hayama 0:da22b0b4395a 1392 if(IRQn < 0) {
hayama 0:da22b0b4395a 1393 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
hayama 0:da22b0b4395a 1394 else {
hayama 0:da22b0b4395a 1395 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
hayama 0:da22b0b4395a 1396 }
hayama 0:da22b0b4395a 1397
hayama 0:da22b0b4395a 1398
hayama 0:da22b0b4395a 1399 /** \brief Get Interrupt Priority
hayama 0:da22b0b4395a 1400
hayama 0:da22b0b4395a 1401 The function reads the priority of an interrupt. The interrupt
hayama 0:da22b0b4395a 1402 number can be positive to specify an external (device specific)
hayama 0:da22b0b4395a 1403 interrupt, or negative to specify an internal (core) interrupt.
hayama 0:da22b0b4395a 1404
hayama 0:da22b0b4395a 1405
hayama 0:da22b0b4395a 1406 \param [in] IRQn Interrupt number.
hayama 0:da22b0b4395a 1407 \return Interrupt Priority. Value is aligned automatically to the implemented
hayama 0:da22b0b4395a 1408 priority bits of the microcontroller.
hayama 0:da22b0b4395a 1409 */
hayama 0:da22b0b4395a 1410 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
hayama 0:da22b0b4395a 1411 {
hayama 0:da22b0b4395a 1412
hayama 0:da22b0b4395a 1413 if(IRQn < 0) {
hayama 0:da22b0b4395a 1414 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
hayama 0:da22b0b4395a 1415 else {
hayama 0:da22b0b4395a 1416 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
hayama 0:da22b0b4395a 1417 }
hayama 0:da22b0b4395a 1418
hayama 0:da22b0b4395a 1419
hayama 0:da22b0b4395a 1420 /** \brief Encode Priority
hayama 0:da22b0b4395a 1421
hayama 0:da22b0b4395a 1422 The function encodes the priority for an interrupt with the given priority group,
hayama 0:da22b0b4395a 1423 preemptive priority value, and subpriority value.
hayama 0:da22b0b4395a 1424 In case of a conflict between priority grouping and available
hayama 0:da22b0b4395a 1425 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
hayama 0:da22b0b4395a 1426
hayama 0:da22b0b4395a 1427 \param [in] PriorityGroup Used priority group.
hayama 0:da22b0b4395a 1428 \param [in] PreemptPriority Preemptive priority value (starting from 0).
hayama 0:da22b0b4395a 1429 \param [in] SubPriority Subpriority value (starting from 0).
hayama 0:da22b0b4395a 1430 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
hayama 0:da22b0b4395a 1431 */
hayama 0:da22b0b4395a 1432 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
hayama 0:da22b0b4395a 1433 {
hayama 0:da22b0b4395a 1434 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
hayama 0:da22b0b4395a 1435 uint32_t PreemptPriorityBits;
hayama 0:da22b0b4395a 1436 uint32_t SubPriorityBits;
hayama 0:da22b0b4395a 1437
hayama 0:da22b0b4395a 1438 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
hayama 0:da22b0b4395a 1439 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
hayama 0:da22b0b4395a 1440
hayama 0:da22b0b4395a 1441 return (
hayama 0:da22b0b4395a 1442 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
hayama 0:da22b0b4395a 1443 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
hayama 0:da22b0b4395a 1444 );
hayama 0:da22b0b4395a 1445 }
hayama 0:da22b0b4395a 1446
hayama 0:da22b0b4395a 1447
hayama 0:da22b0b4395a 1448 /** \brief Decode Priority
hayama 0:da22b0b4395a 1449
hayama 0:da22b0b4395a 1450 The function decodes an interrupt priority value with a given priority group to
hayama 0:da22b0b4395a 1451 preemptive priority value and subpriority value.
hayama 0:da22b0b4395a 1452 In case of a conflict between priority grouping and available
hayama 0:da22b0b4395a 1453 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
hayama 0:da22b0b4395a 1454
hayama 0:da22b0b4395a 1455 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
hayama 0:da22b0b4395a 1456 \param [in] PriorityGroup Used priority group.
hayama 0:da22b0b4395a 1457 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
hayama 0:da22b0b4395a 1458 \param [out] pSubPriority Subpriority value (starting from 0).
hayama 0:da22b0b4395a 1459 */
hayama 0:da22b0b4395a 1460 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
hayama 0:da22b0b4395a 1461 {
hayama 0:da22b0b4395a 1462 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
hayama 0:da22b0b4395a 1463 uint32_t PreemptPriorityBits;
hayama 0:da22b0b4395a 1464 uint32_t SubPriorityBits;
hayama 0:da22b0b4395a 1465
hayama 0:da22b0b4395a 1466 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
hayama 0:da22b0b4395a 1467 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
hayama 0:da22b0b4395a 1468
hayama 0:da22b0b4395a 1469 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
hayama 0:da22b0b4395a 1470 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
hayama 0:da22b0b4395a 1471 }
hayama 0:da22b0b4395a 1472
hayama 0:da22b0b4395a 1473
hayama 0:da22b0b4395a 1474 /** \brief System Reset
hayama 0:da22b0b4395a 1475
hayama 0:da22b0b4395a 1476 The function initiates a system reset request to reset the MCU.
hayama 0:da22b0b4395a 1477 */
hayama 0:da22b0b4395a 1478 __STATIC_INLINE void NVIC_SystemReset(void)
hayama 0:da22b0b4395a 1479 {
hayama 0:da22b0b4395a 1480 __DSB(); /* Ensure all outstanding memory accesses included
hayama 0:da22b0b4395a 1481 buffered write are completed before reset */
hayama 0:da22b0b4395a 1482 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
hayama 0:da22b0b4395a 1483 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
hayama 0:da22b0b4395a 1484 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
hayama 0:da22b0b4395a 1485 __DSB(); /* Ensure completion of memory access */
hayama 0:da22b0b4395a 1486 while(1); /* wait until reset */
hayama 0:da22b0b4395a 1487 }
hayama 0:da22b0b4395a 1488
hayama 0:da22b0b4395a 1489 /*@} end of CMSIS_Core_NVICFunctions */
hayama 0:da22b0b4395a 1490
hayama 0:da22b0b4395a 1491
hayama 0:da22b0b4395a 1492
hayama 0:da22b0b4395a 1493 /* ################################## SysTick function ############################################ */
hayama 0:da22b0b4395a 1494 /** \ingroup CMSIS_Core_FunctionInterface
hayama 0:da22b0b4395a 1495 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
hayama 0:da22b0b4395a 1496 \brief Functions that configure the System.
hayama 0:da22b0b4395a 1497 @{
hayama 0:da22b0b4395a 1498 */
hayama 0:da22b0b4395a 1499
hayama 0:da22b0b4395a 1500 #if (__Vendor_SysTickConfig == 0)
hayama 0:da22b0b4395a 1501
hayama 0:da22b0b4395a 1502 /** \brief System Tick Configuration
hayama 0:da22b0b4395a 1503
hayama 0:da22b0b4395a 1504 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
hayama 0:da22b0b4395a 1505 Counter is in free running mode to generate periodic interrupts.
hayama 0:da22b0b4395a 1506
hayama 0:da22b0b4395a 1507 \param [in] ticks Number of ticks between two interrupts.
hayama 0:da22b0b4395a 1508
hayama 0:da22b0b4395a 1509 \return 0 Function succeeded.
hayama 0:da22b0b4395a 1510 \return 1 Function failed.
hayama 0:da22b0b4395a 1511
hayama 0:da22b0b4395a 1512 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
hayama 0:da22b0b4395a 1513 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
hayama 0:da22b0b4395a 1514 must contain a vendor-specific implementation of this function.
hayama 0:da22b0b4395a 1515
hayama 0:da22b0b4395a 1516 */
hayama 0:da22b0b4395a 1517 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
hayama 0:da22b0b4395a 1518 {
hayama 0:da22b0b4395a 1519 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
hayama 0:da22b0b4395a 1520
hayama 0:da22b0b4395a 1521 SysTick->LOAD = ticks - 1; /* set reload register */
hayama 0:da22b0b4395a 1522 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
hayama 0:da22b0b4395a 1523 SysTick->VAL = 0; /* Load the SysTick Counter Value */
hayama 0:da22b0b4395a 1524 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
hayama 0:da22b0b4395a 1525 SysTick_CTRL_TICKINT_Msk |
hayama 0:da22b0b4395a 1526 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
hayama 0:da22b0b4395a 1527 return (0); /* Function successful */
hayama 0:da22b0b4395a 1528 }
hayama 0:da22b0b4395a 1529
hayama 0:da22b0b4395a 1530 #endif
hayama 0:da22b0b4395a 1531
hayama 0:da22b0b4395a 1532 /*@} end of CMSIS_Core_SysTickFunctions */
hayama 0:da22b0b4395a 1533
hayama 0:da22b0b4395a 1534
hayama 0:da22b0b4395a 1535
hayama 0:da22b0b4395a 1536 /* ##################################### Debug In/Output function ########################################### */
hayama 0:da22b0b4395a 1537 /** \ingroup CMSIS_Core_FunctionInterface
hayama 0:da22b0b4395a 1538 \defgroup CMSIS_core_DebugFunctions ITM Functions
hayama 0:da22b0b4395a 1539 \brief Functions that access the ITM debug interface.
hayama 0:da22b0b4395a 1540 @{
hayama 0:da22b0b4395a 1541 */
hayama 0:da22b0b4395a 1542
hayama 0:da22b0b4395a 1543 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
hayama 0:da22b0b4395a 1544 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
hayama 0:da22b0b4395a 1545
hayama 0:da22b0b4395a 1546
hayama 0:da22b0b4395a 1547 /** \brief ITM Send Character
hayama 0:da22b0b4395a 1548
hayama 0:da22b0b4395a 1549 The function transmits a character via the ITM channel 0, and
hayama 0:da22b0b4395a 1550 \li Just returns when no debugger is connected that has booked the output.
hayama 0:da22b0b4395a 1551 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
hayama 0:da22b0b4395a 1552
hayama 0:da22b0b4395a 1553 \param [in] ch Character to transmit.
hayama 0:da22b0b4395a 1554
hayama 0:da22b0b4395a 1555 \returns Character to transmit.
hayama 0:da22b0b4395a 1556 */
hayama 0:da22b0b4395a 1557 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
hayama 0:da22b0b4395a 1558 {
hayama 0:da22b0b4395a 1559 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
hayama 0:da22b0b4395a 1560 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
hayama 0:da22b0b4395a 1561 {
hayama 0:da22b0b4395a 1562 while (ITM->PORT[0].u32 == 0);
hayama 0:da22b0b4395a 1563 ITM->PORT[0].u8 = (uint8_t) ch;
hayama 0:da22b0b4395a 1564 }
hayama 0:da22b0b4395a 1565 return (ch);
hayama 0:da22b0b4395a 1566 }
hayama 0:da22b0b4395a 1567
hayama 0:da22b0b4395a 1568
hayama 0:da22b0b4395a 1569 /** \brief ITM Receive Character
hayama 0:da22b0b4395a 1570
hayama 0:da22b0b4395a 1571 The function inputs a character via the external variable \ref ITM_RxBuffer.
hayama 0:da22b0b4395a 1572
hayama 0:da22b0b4395a 1573 \return Received character.
hayama 0:da22b0b4395a 1574 \return -1 No character pending.
hayama 0:da22b0b4395a 1575 */
hayama 0:da22b0b4395a 1576 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
hayama 0:da22b0b4395a 1577 int32_t ch = -1; /* no character available */
hayama 0:da22b0b4395a 1578
hayama 0:da22b0b4395a 1579 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
hayama 0:da22b0b4395a 1580 ch = ITM_RxBuffer;
hayama 0:da22b0b4395a 1581 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
hayama 0:da22b0b4395a 1582 }
hayama 0:da22b0b4395a 1583
hayama 0:da22b0b4395a 1584 return (ch);
hayama 0:da22b0b4395a 1585 }
hayama 0:da22b0b4395a 1586
hayama 0:da22b0b4395a 1587
hayama 0:da22b0b4395a 1588 /** \brief ITM Check Character
hayama 0:da22b0b4395a 1589
hayama 0:da22b0b4395a 1590 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
hayama 0:da22b0b4395a 1591
hayama 0:da22b0b4395a 1592 \return 0 No character available.
hayama 0:da22b0b4395a 1593 \return 1 Character available.
hayama 0:da22b0b4395a 1594 */
hayama 0:da22b0b4395a 1595 __STATIC_INLINE int32_t ITM_CheckChar (void) {
hayama 0:da22b0b4395a 1596
hayama 0:da22b0b4395a 1597 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
hayama 0:da22b0b4395a 1598 return (0); /* no character available */
hayama 0:da22b0b4395a 1599 } else {
hayama 0:da22b0b4395a 1600 return (1); /* character available */
hayama 0:da22b0b4395a 1601 }
hayama 0:da22b0b4395a 1602 }
hayama 0:da22b0b4395a 1603
hayama 0:da22b0b4395a 1604 /*@} end of CMSIS_core_DebugFunctions */
hayama 0:da22b0b4395a 1605
hayama 0:da22b0b4395a 1606 #endif /* __CORE_CM3_H_DEPENDANT */
hayama 0:da22b0b4395a 1607
hayama 0:da22b0b4395a 1608 #endif /* __CMSIS_GENERIC */
hayama 0:da22b0b4395a 1609
hayama 0:da22b0b4395a 1610 #ifdef __cplusplus
hayama 0:da22b0b4395a 1611 }
hayama 0:da22b0b4395a 1612 #endif