Solar Cell Powered - Periodic logging of sensor data into SD card

Dependencies:   mbed

Committer:
gsundaresan3
Date:
Mon Feb 28 20:05:48 2011 +0000
Revision:
0:248aa51eeb12

        

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gsundaresan3 0:248aa51eeb12 1 /* mbed PowerControl Library
gsundaresan3 0:248aa51eeb12 2 * Copyright (c) 2010 Michael Wei
gsundaresan3 0:248aa51eeb12 3 */
gsundaresan3 0:248aa51eeb12 4
gsundaresan3 0:248aa51eeb12 5 #ifndef MBED_POWERCONTROL_H
gsundaresan3 0:248aa51eeb12 6 #define MBED_POWERCONTROL_H
gsundaresan3 0:248aa51eeb12 7
gsundaresan3 0:248aa51eeb12 8 //shouldn't have to include, but fixes weird problems with defines
gsundaresan3 0:248aa51eeb12 9 #include "LPC1768/LPC17xx.h"
gsundaresan3 0:248aa51eeb12 10
gsundaresan3 0:248aa51eeb12 11 //System Control Register
gsundaresan3 0:248aa51eeb12 12 // bit 0: Reserved
gsundaresan3 0:248aa51eeb12 13 // bit 1: Sleep on Exit
gsundaresan3 0:248aa51eeb12 14 #define LPC1768_SCR_SLEEPONEXIT 0x2
gsundaresan3 0:248aa51eeb12 15 // bit 2: Deep Sleep
gsundaresan3 0:248aa51eeb12 16 #define LPC1768_SCR_SLEEPDEEP 0x4
gsundaresan3 0:248aa51eeb12 17 // bit 3: Resereved
gsundaresan3 0:248aa51eeb12 18 // bit 4: Send on Pending
gsundaresan3 0:248aa51eeb12 19 #define LPC1768_SCR_SEVONPEND 0x10
gsundaresan3 0:248aa51eeb12 20 // bit 5-31: Reserved
gsundaresan3 0:248aa51eeb12 21
gsundaresan3 0:248aa51eeb12 22 //Power Control Register
gsundaresan3 0:248aa51eeb12 23 // bit 0: Power mode control bit 0 (power-down mode)
gsundaresan3 0:248aa51eeb12 24 #define LPC1768_PCON_PM0 0x1
gsundaresan3 0:248aa51eeb12 25 // bit 1: Power mode control bit 1 (deep power-down mode)
gsundaresan3 0:248aa51eeb12 26 #define LPC1768_PCON_PM1 0x2
gsundaresan3 0:248aa51eeb12 27 // bit 2: Brown-out reduced power mode
gsundaresan3 0:248aa51eeb12 28 #define LPC1768_PCON_BODRPM 0x4
gsundaresan3 0:248aa51eeb12 29 // bit 3: Brown-out global disable
gsundaresan3 0:248aa51eeb12 30 #define LPC1768_PCON_BOGD 0x8
gsundaresan3 0:248aa51eeb12 31 // bit 4: Brown-out reset disable
gsundaresan3 0:248aa51eeb12 32 #define LPC1768_PCON_BORD 0x10
gsundaresan3 0:248aa51eeb12 33 // bit 5-7 : Reserved
gsundaresan3 0:248aa51eeb12 34 // bit 8: Sleep Mode Entry Flag
gsundaresan3 0:248aa51eeb12 35 #define LPC1768_PCON_SMFLAG 0x100
gsundaresan3 0:248aa51eeb12 36 // bit 9: Deep Sleep Entry Flag
gsundaresan3 0:248aa51eeb12 37 #define LPC1768_PCON_DSFLAG 0x200
gsundaresan3 0:248aa51eeb12 38 // bit 10: Power Down Entry Flag
gsundaresan3 0:248aa51eeb12 39 #define LPC1768_PCON_PDFLAG 0x400
gsundaresan3 0:248aa51eeb12 40 // bit 11: Deep Power Down Entry Flag
gsundaresan3 0:248aa51eeb12 41 #define LPC1768_PCON_DPDFLAG 0x800
gsundaresan3 0:248aa51eeb12 42 // bit 12-31: Reserved
gsundaresan3 0:248aa51eeb12 43
gsundaresan3 0:248aa51eeb12 44 //"Sleep Mode" (WFI).
gsundaresan3 0:248aa51eeb12 45 inline void Sleep(void)
gsundaresan3 0:248aa51eeb12 46 {
gsundaresan3 0:248aa51eeb12 47 __WFI();
gsundaresan3 0:248aa51eeb12 48 }
gsundaresan3 0:248aa51eeb12 49
gsundaresan3 0:248aa51eeb12 50 //"Deep Sleep" Mode
gsundaresan3 0:248aa51eeb12 51 inline void DeepSleep(void)
gsundaresan3 0:248aa51eeb12 52 {
gsundaresan3 0:248aa51eeb12 53 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
gsundaresan3 0:248aa51eeb12 54 __WFI();
gsundaresan3 0:248aa51eeb12 55 }
gsundaresan3 0:248aa51eeb12 56
gsundaresan3 0:248aa51eeb12 57 //"Power-Down" Mode
gsundaresan3 0:248aa51eeb12 58 inline void PowerDown(void)
gsundaresan3 0:248aa51eeb12 59 {
gsundaresan3 0:248aa51eeb12 60 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
gsundaresan3 0:248aa51eeb12 61 LPC_SC->PCON &= ~LPC1768_PCON_PM1;
gsundaresan3 0:248aa51eeb12 62 LPC_SC->PCON |= LPC1768_PCON_PM0;
gsundaresan3 0:248aa51eeb12 63 __WFI();
gsundaresan3 0:248aa51eeb12 64 //reset back to normal
gsundaresan3 0:248aa51eeb12 65 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
gsundaresan3 0:248aa51eeb12 66 }
gsundaresan3 0:248aa51eeb12 67
gsundaresan3 0:248aa51eeb12 68 //"Deep Power-Down" Mode
gsundaresan3 0:248aa51eeb12 69 inline void DeepPowerDown(void)
gsundaresan3 0:248aa51eeb12 70 {
gsundaresan3 0:248aa51eeb12 71 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
gsundaresan3 0:248aa51eeb12 72 LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
gsundaresan3 0:248aa51eeb12 73 __WFI();
gsundaresan3 0:248aa51eeb12 74 //reset back to normal
gsundaresan3 0:248aa51eeb12 75 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
gsundaresan3 0:248aa51eeb12 76 }
gsundaresan3 0:248aa51eeb12 77
gsundaresan3 0:248aa51eeb12 78 //shut down BOD during power-down/deep sleep
gsundaresan3 0:248aa51eeb12 79 inline void BrownOut_ReducedPowerMode_Enable(void)
gsundaresan3 0:248aa51eeb12 80 {
gsundaresan3 0:248aa51eeb12 81 LPC_SC->PCON |= LPC1768_PCON_BODRPM;
gsundaresan3 0:248aa51eeb12 82 }
gsundaresan3 0:248aa51eeb12 83
gsundaresan3 0:248aa51eeb12 84 //turn on BOD during power-down/deep sleep
gsundaresan3 0:248aa51eeb12 85 inline void BrownOut_ReducedPowerMode_Disable(void)
gsundaresan3 0:248aa51eeb12 86 {
gsundaresan3 0:248aa51eeb12 87 LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
gsundaresan3 0:248aa51eeb12 88 }
gsundaresan3 0:248aa51eeb12 89
gsundaresan3 0:248aa51eeb12 90 //turn off brown out circutry
gsundaresan3 0:248aa51eeb12 91 inline void BrownOut_Global_Disable(void)
gsundaresan3 0:248aa51eeb12 92 {
gsundaresan3 0:248aa51eeb12 93 LPC_SC->PCON |= LPC1768_PCON_BOGD;
gsundaresan3 0:248aa51eeb12 94 }
gsundaresan3 0:248aa51eeb12 95
gsundaresan3 0:248aa51eeb12 96 //turn on brown out circutry
gsundaresan3 0:248aa51eeb12 97 inline void BrownOut_Global_Enable(void)
gsundaresan3 0:248aa51eeb12 98 {
gsundaresan3 0:248aa51eeb12 99 LPC_SC->PCON &= !LPC1768_PCON_BOGD;
gsundaresan3 0:248aa51eeb12 100 }
gsundaresan3 0:248aa51eeb12 101
gsundaresan3 0:248aa51eeb12 102 //turn off brown out reset circutry
gsundaresan3 0:248aa51eeb12 103 inline void BrownOut_Reset_Disable(void)
gsundaresan3 0:248aa51eeb12 104 {
gsundaresan3 0:248aa51eeb12 105 LPC_SC->PCON |= LPC1768_PCON_BORD;
gsundaresan3 0:248aa51eeb12 106 }
gsundaresan3 0:248aa51eeb12 107
gsundaresan3 0:248aa51eeb12 108 //turn on brown outreset circutry
gsundaresan3 0:248aa51eeb12 109 inline void BrownOut_Reset_Enable(void)
gsundaresan3 0:248aa51eeb12 110 {
gsundaresan3 0:248aa51eeb12 111 LPC_SC->PCON &= ~LPC1768_PCON_BORD;
gsundaresan3 0:248aa51eeb12 112 }
gsundaresan3 0:248aa51eeb12 113 //Peripheral Control Register
gsundaresan3 0:248aa51eeb12 114 // bit 0: Reserved
gsundaresan3 0:248aa51eeb12 115 // bit 1: PCTIM0: Timer/Counter 0 power/clock enable
gsundaresan3 0:248aa51eeb12 116 #define LPC1768_PCONP_PCTIM0 0x2
gsundaresan3 0:248aa51eeb12 117 // bit 2: PCTIM1: Timer/Counter 1 power/clock enable
gsundaresan3 0:248aa51eeb12 118 #define LPC1768_PCONP_PCTIM1 0x4
gsundaresan3 0:248aa51eeb12 119 // bit 3: PCUART0: UART 0 power/clock enable
gsundaresan3 0:248aa51eeb12 120 #define LPC1768_PCONP_PCUART0 0x8
gsundaresan3 0:248aa51eeb12 121 // bit 4: PCUART1: UART 1 power/clock enable
gsundaresan3 0:248aa51eeb12 122 #define LPC1768_PCONP_PCUART1 0x10
gsundaresan3 0:248aa51eeb12 123 // bit 5: Reserved
gsundaresan3 0:248aa51eeb12 124 // bit 6: PCPWM1: PWM 1 power/clock enable
gsundaresan3 0:248aa51eeb12 125 #define LPC1768_PCONP_PCPWM1 0x40
gsundaresan3 0:248aa51eeb12 126 // bit 7: PCI2C0: I2C interface 0 power/clock enable
gsundaresan3 0:248aa51eeb12 127 #define LPC1768_PCONP_PCI2C0 0x80
gsundaresan3 0:248aa51eeb12 128 // bit 8: PCSPI: SPI interface power/clock enable
gsundaresan3 0:248aa51eeb12 129 #define LPC1768_PCONP_PCSPI 0x100
gsundaresan3 0:248aa51eeb12 130 // bit 9: PCRTC: RTC power/clock enable
gsundaresan3 0:248aa51eeb12 131 #define LPC1768_PCONP_PCRTC 0x200
gsundaresan3 0:248aa51eeb12 132 // bit 10: PCSSP1: SSP interface 1 power/clock enable
gsundaresan3 0:248aa51eeb12 133 #define LPC1768_PCONP_PCSSP1 0x400
gsundaresan3 0:248aa51eeb12 134 // bit 11: Reserved
gsundaresan3 0:248aa51eeb12 135 // bit 12: PCADC: A/D converter power/clock enable
gsundaresan3 0:248aa51eeb12 136 #define LPC1768_PCONP_PCADC 0x1000
gsundaresan3 0:248aa51eeb12 137 // bit 13: PCCAN1: CAN controller 1 power/clock enable
gsundaresan3 0:248aa51eeb12 138 #define LPC1768_PCONP_PCCAN1 0x2000
gsundaresan3 0:248aa51eeb12 139 // bit 14: PCCAN2: CAN controller 2 power/clock enable
gsundaresan3 0:248aa51eeb12 140 #define LPC1768_PCONP_PCCAN2 0x4000
gsundaresan3 0:248aa51eeb12 141 // bit 15: PCGPIO: GPIOs power/clock enable
gsundaresan3 0:248aa51eeb12 142 #define LPC1768_PCONP_PCGPIO 0x8000
gsundaresan3 0:248aa51eeb12 143 // bit 16: PCRIT: Repetitive interrupt timer power/clock enable
gsundaresan3 0:248aa51eeb12 144 #define LPC1768_PCONP_PCRIT 0x10000
gsundaresan3 0:248aa51eeb12 145 // bit 17: PCMCPWM: Motor control PWM power/clock enable
gsundaresan3 0:248aa51eeb12 146 #define LPC1768_PCONP_PCMCPWM 0x20000
gsundaresan3 0:248aa51eeb12 147 // bit 18: PCQEI: Quadrature encoder interface power/clock enable
gsundaresan3 0:248aa51eeb12 148 #define LPC1768_PCONP_PCQEI 0x40000
gsundaresan3 0:248aa51eeb12 149 // bit 19: PCI2C1: I2C interface 1 power/clock enable
gsundaresan3 0:248aa51eeb12 150 #define LPC1768_PCONP_PCI2C1 0x80000
gsundaresan3 0:248aa51eeb12 151 // bit 20: Reserved
gsundaresan3 0:248aa51eeb12 152 // bit 21: PCSSP0: SSP interface 0 power/clock enable
gsundaresan3 0:248aa51eeb12 153 #define LPC1768_PCONP_PCSSP0 0x200000
gsundaresan3 0:248aa51eeb12 154 // bit 22: PCTIM2: Timer 2 power/clock enable
gsundaresan3 0:248aa51eeb12 155 #define LPC1768_PCONP_PCTIM2 0x400000
gsundaresan3 0:248aa51eeb12 156 // bit 23: PCTIM3: Timer 3 power/clock enable
gsundaresan3 0:248aa51eeb12 157 #define LPC1768_PCONP_PCQTIM3 0x800000
gsundaresan3 0:248aa51eeb12 158 // bit 24: PCUART2: UART 2 power/clock enable
gsundaresan3 0:248aa51eeb12 159 #define LPC1768_PCONP_PCUART2 0x1000000
gsundaresan3 0:248aa51eeb12 160 // bit 25: PCUART3: UART 3 power/clock enable
gsundaresan3 0:248aa51eeb12 161 #define LPC1768_PCONP_PCUART3 0x2000000
gsundaresan3 0:248aa51eeb12 162 // bit 26: PCI2C2: I2C interface 2 power/clock enable
gsundaresan3 0:248aa51eeb12 163 #define LPC1768_PCONP_PCI2C2 0x4000000
gsundaresan3 0:248aa51eeb12 164 // bit 27: PCI2S: I2S interface power/clock enable
gsundaresan3 0:248aa51eeb12 165 #define LPC1768_PCONP_PCI2S 0x8000000
gsundaresan3 0:248aa51eeb12 166 // bit 28: Reserved
gsundaresan3 0:248aa51eeb12 167 // bit 29: PCGPDMA: GP DMA function power/clock enable
gsundaresan3 0:248aa51eeb12 168 #define LPC1768_PCONP_PCGPDMA 0x20000000
gsundaresan3 0:248aa51eeb12 169 // bit 30: PCENET: Ethernet block power/clock enable
gsundaresan3 0:248aa51eeb12 170 #define LPC1768_PCONP_PCENET 0x40000000
gsundaresan3 0:248aa51eeb12 171 // bit 31: PCUSB: USB interface power/clock enable
gsundaresan3 0:248aa51eeb12 172 #define LPC1768_PCONP_PCUSB 0x80000000
gsundaresan3 0:248aa51eeb12 173
gsundaresan3 0:248aa51eeb12 174 //Powers Up specified Peripheral(s)
gsundaresan3 0:248aa51eeb12 175 inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
gsundaresan3 0:248aa51eeb12 176 {
gsundaresan3 0:248aa51eeb12 177 return LPC_SC->PCONP |= bitMask;
gsundaresan3 0:248aa51eeb12 178 }
gsundaresan3 0:248aa51eeb12 179
gsundaresan3 0:248aa51eeb12 180 //Powers Down specified Peripheral(s)
gsundaresan3 0:248aa51eeb12 181 inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
gsundaresan3 0:248aa51eeb12 182 {
gsundaresan3 0:248aa51eeb12 183 return LPC_SC->PCONP &= ~bitMask;
gsundaresan3 0:248aa51eeb12 184 }
gsundaresan3 0:248aa51eeb12 185
gsundaresan3 0:248aa51eeb12 186 //returns if the peripheral is on or off
gsundaresan3 0:248aa51eeb12 187 inline bool Peripheral_GetStatus(unsigned int peripheral)
gsundaresan3 0:248aa51eeb12 188 {
gsundaresan3 0:248aa51eeb12 189 return (LPC_SC->PCONP & peripheral) ? true : false;
gsundaresan3 0:248aa51eeb12 190 }
gsundaresan3 0:248aa51eeb12 191
gsundaresan3 0:248aa51eeb12 192 #endif