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Dependents: Seeed_Barometer_Sensor_Example
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Core Debug Registers (CoreDebug)
[Defines and Type Definitions]
Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. More...
Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
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