Guido Grassel
/
mbed-src
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Dependents: Seeed_Barometer_Sensor_Example
Fork of
mbed-src
by 
mbed official
Revision 336:cad63c80acb0, committed 2014-10-06
- Comitter:
- mbed_official
- Date:
- Mon Oct 06 09:15:06 2014 +0100
- Parent:
- 335:6848febe3436
- Child:
- 337:6ed01c00b962
- Commit message:
- Synchronized with git revision d583b167c50b3532a1d013ff0cd2a35373cd7b0b
Full URL: https://github.com/mbedmicro/mbed/commit/d583b167c50b3532a1d013ff0cd2a35373cd7b0b/
HAL: ARCH_MAX - STM_MODE_IT_EVT_RESET undefined error fix, uvision and gcc template
Changed in this revision
--- a/targets/hal/TARGET_NXP/TARGET_LPC11U6X/analogin_api.c Fri Oct 03 16:45:07 2014 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11U6X/analogin_api.c Mon Oct 06 09:15:06 2014 +0100
@@ -66,13 +66,15 @@
// Enable clock for ADC
LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 13);
- // Start ADC self-calibration
- LPC_ADC->CTRL = (1UL << 30);
- do {
- tmp = LPC_ADC->CTRL;
- } while ((tmp & (1UL << 30)) != 0);
+ // Determine the clock divider for a 500kHz ADC clock during calibration
+ uint32_t clkdiv = (SystemCoreClock / 500000) - 1;
+
+ // Perform a self-calibration
+ LPC_ADC->CTRL = (1UL << 30) | (clkdiv & 0xFF);
+ while ((LPC_ADC->CTRL & (1UL << 30)) != 0);
- LPC_ADC->CTRL = 1; // Sampling clock: SystemClock divided by 1
+ // Sampling clock: SystemClock divided by 1
+ LPC_ADC->CTRL = 0;
}
static inline uint32_t adc_read(analogin_t *obj) {
--- a/targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c Fri Oct 03 16:45:07 2014 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c Mon Oct 06 09:15:06 2014 +0100
@@ -77,19 +77,21 @@
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 28);
}
- // select IRC as async. clock, divided by 1
+ // select IRC as asynchronous clock, divided by 1
LPC_SYSCON->ADCASYNCCLKSEL = 0;
LPC_SYSCON->ADCASYNCCLKDIV = 1;
__IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
- // start calibration
- adc_reg->CTRL |= (1UL << 30);
- __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
+ // determine the system clock divider for a 500kHz ADC clock during calibration
+ uint32_t clkdiv = (SystemCoreClock / 500000) - 1;
+
+ // perform a self-calibration
+ adc_reg->CTRL = (1UL << 30) | (clkdiv & 0xFF);
+ while ((adc_reg->CTRL & (1UL << 30)) != 0);
- // asynchronous mode
+ // switch to asynchronous mode
adc_reg->CTRL = (1UL << 8);
-
}
static inline uint32_t adc_read(analogin_t *obj) {
--- a/targets/hal/TARGET_STM/TARGET_STM32F407VG/TARGET_ARCH_MAX/PinNames.h Fri Oct 03 16:45:07 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F407VG/TARGET_ARCH_MAX/PinNames.h Mon Oct 06 09:15:06 2014 +0100
@@ -53,6 +53,7 @@
#define STM_MODE_EVT_RISING (9)
#define STM_MODE_EVT_FALLING (10)
#define STM_MODE_EVT_RISING_FALLING (11)
+#define STM_MODE_IT_EVT_RESET (12)
// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
// Low nibble = pin number
@@ -132,7 +133,7 @@
PD_13 = 0x3D,
PD_14 = 0x3E,
PD_15 = 0x3F,
-
+
PE_0 = 0x40,
PE_1 = 0x41,
PE_2 = 0x42,
@@ -149,7 +150,7 @@
PE_13 = 0x4D,
PE_14 = 0x4E,
PE_15 = 0x4F,
-
+
PF_0 = 0x50,
PF_1 = 0x51,
PF_2 = 0x52,