Guido Grassel / mbed-src

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Dependents:   Seeed_Barometer_Sensor_Example

Fork of mbed-src by mbed official

Files at this revision

API Documentation at this revision

Revision 62:7731d679ae64, committed 2013-12-17

Comitter:
mbed_official
Date:
Tue Dec 17 11:00:05 2013 +0000
Parent:
61:cf80ee640ace
Child:
63:a46ad637dc84
Commit message:
Synchronized with git revision 1eec522274f4b78e86504ad3cde3c10574392441

Full URL: https://github.com/mbedmicro/mbed/commit/1eec522274f4b78e86504ad3cde3c10574392441/

[NUCLEO_F103RB] Use HSI/LSI instead of HSE/LSE (board rev C constraint)

Changed in this revision

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c Show annotated file Show diff for this revision Revisions of this file
targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/rtc_api.c Show annotated file Show diff for this revision Revisions of this file 
--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c	Tue Dec 17 10:15:06 2013 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c	Tue Dec 17 11:00:05 2013 +0000
@@ -105,14 +105,14 @@
     
 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
- #define SYSCLK_FREQ_24MHz  24000000
+/* #define SYSCLK_FREQ_24MHz  24000000 */
 #else
 /* #define SYSCLK_FREQ_HSE    HSE_VALUE */
 /* #define SYSCLK_FREQ_24MHz  24000000 */ 
 /* #define SYSCLK_FREQ_36MHz  36000000 */
 /* #define SYSCLK_FREQ_48MHz  48000000 */
 /* #define SYSCLK_FREQ_56MHz  56000000 */
-#define SYSCLK_FREQ_72MHz  72000000
+/* #define SYSCLK_FREQ_72MHz  72000000 */
 #endif
 
 /*!< Uncomment the following line if you need to use external SRAM mounted

--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/rtc_api.c	Tue Dec 17 10:15:06 2013 +0000
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/rtc_api.c	Tue Dec 17 11:00:05 2013 +0000
@@ -24,12 +24,18 @@
   
     BKP_DeInit(); // Reset Backup Domain
   
+    // Uncomment these lines if you use the LSE
     // Enable LSE and wait till it's ready
-    RCC_LSEConfig(RCC_LSE_ON);
-    while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) {}
+    //RCC_LSEConfig(RCC_LSE_ON);
+    //while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) {}     
+    //RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); // Select LSE as RTC Clock Source
       
-    RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); // Select LSE as RTC Clock Source
-      
+    // Uncomment these lines if you use the LSI
+    // Enable LSI and wait till it's ready  
+    RCC_LSICmd(ENABLE);
+    while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) {}
+    RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); // Select LSI as RTC Clock Source
+  
     RCC_RTCCLKCmd(ENABLE); // Enable RTC Clock 
       
     RTC_WaitForSynchro(); // Wait for RTC registers synchronization
@@ -37,8 +43,9 @@
     RTC_WaitForLastTask(); // Wait until last write operation on RTC registers has finished
 
     // Set RTC period to 1 sec
-    // RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1)
-    RTC_SetPrescaler(32767);
+    // For LSE: prescaler = RTCCLK/RTC period = 32768Hz/1Hz = 32768
+    // For LSI: prescaler = RTCCLK/RTC period = 40000Hz/1Hz = 40000      
+    RTC_SetPrescaler(39999);
     
     RTC_WaitForLastTask(); // Wait until last write operation on RTC registers has finished