Gleb Klochkov / Mbed OS Climatcontroll_Main

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Dependencies:   esp8266-driver

mbed-os/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_devinfo.h@0:2f0e1e23c242, 2018-04-13 (annotated)

Committer:
glebiuskv
Date:
Fri Apr 13 08:53:46 2018 +0000
Revision:
0:2f0e1e23c242
initial

Who changed what in which revision?

UserRevisionLine numberNew contents of line
glebiuskv 0:2f0e1e23c242 1 /**************************************************************************//**
glebiuskv 0:2f0e1e23c242 2 * @file efr32mg1p_devinfo.h
glebiuskv 0:2f0e1e23c242 3 * @brief EFR32MG1P_DEVINFO register and bit field definitions
glebiuskv 0:2f0e1e23c242 4 * @version 5.1.2
glebiuskv 0:2f0e1e23c242 5 ******************************************************************************
glebiuskv 0:2f0e1e23c242 6 * @section License
glebiuskv 0:2f0e1e23c242 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
glebiuskv 0:2f0e1e23c242 8 ******************************************************************************
glebiuskv 0:2f0e1e23c242 9 *
glebiuskv 0:2f0e1e23c242 10 * Permission is granted to anyone to use this software for any purpose,
glebiuskv 0:2f0e1e23c242 11 * including commercial applications, and to alter it and redistribute it
glebiuskv 0:2f0e1e23c242 12 * freely, subject to the following restrictions:
glebiuskv 0:2f0e1e23c242 13 *
glebiuskv 0:2f0e1e23c242 14 * 1. The origin of this software must not be misrepresented; you must not
glebiuskv 0:2f0e1e23c242 15 * claim that you wrote the original software.@n
glebiuskv 0:2f0e1e23c242 16 * 2. Altered source versions must be plainly marked as such, and must not be
glebiuskv 0:2f0e1e23c242 17 * misrepresented as being the original software.@n
glebiuskv 0:2f0e1e23c242 18 * 3. This notice may not be removed or altered from any source distribution.
glebiuskv 0:2f0e1e23c242 19 *
glebiuskv 0:2f0e1e23c242 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
glebiuskv 0:2f0e1e23c242 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
glebiuskv 0:2f0e1e23c242 22 * providing the Software "AS IS", with no express or implied warranties of any
glebiuskv 0:2f0e1e23c242 23 * kind, including, but not limited to, any implied warranties of
glebiuskv 0:2f0e1e23c242 24 * merchantability or fitness for any particular purpose or warranties against
glebiuskv 0:2f0e1e23c242 25 * infringement of any proprietary rights of a third party.
glebiuskv 0:2f0e1e23c242 26 *
glebiuskv 0:2f0e1e23c242 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
glebiuskv 0:2f0e1e23c242 28 * incidental, or special damages, or any other relief, or for any claim by
glebiuskv 0:2f0e1e23c242 29 * any third party, arising from your use of this Software.
glebiuskv 0:2f0e1e23c242 30 *
glebiuskv 0:2f0e1e23c242 31 *****************************************************************************/
glebiuskv 0:2f0e1e23c242 32 /**************************************************************************//**
glebiuskv 0:2f0e1e23c242 33 * @addtogroup Parts
glebiuskv 0:2f0e1e23c242 34 * @{
glebiuskv 0:2f0e1e23c242 35 ******************************************************************************/
glebiuskv 0:2f0e1e23c242 36 /**************************************************************************//**
glebiuskv 0:2f0e1e23c242 37 * @defgroup EFR32MG1P_DEVINFO
glebiuskv 0:2f0e1e23c242 38 * @{
glebiuskv 0:2f0e1e23c242 39 *****************************************************************************/
glebiuskv 0:2f0e1e23c242 40
glebiuskv 0:2f0e1e23c242 41 typedef struct
glebiuskv 0:2f0e1e23c242 42 {
glebiuskv 0:2f0e1e23c242 43 __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */
glebiuskv 0:2f0e1e23c242 44 uint32_t RESERVED0[7]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 45 __IM uint32_t EXTINFO; /**< External Component description */
glebiuskv 0:2f0e1e23c242 46 uint32_t RESERVED1[1]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 47 __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */
glebiuskv 0:2f0e1e23c242 48 __IM uint32_t EUI48H; /**< OUI */
glebiuskv 0:2f0e1e23c242 49 __IM uint32_t CUSTOMINFO; /**< Custom information */
glebiuskv 0:2f0e1e23c242 50 __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */
glebiuskv 0:2f0e1e23c242 51 uint32_t RESERVED2[2]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 52 __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
glebiuskv 0:2f0e1e23c242 53 __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
glebiuskv 0:2f0e1e23c242 54 __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */
glebiuskv 0:2f0e1e23c242 55 __IM uint32_t PART; /**< Part description */
glebiuskv 0:2f0e1e23c242 56 __IM uint32_t DEVINFOREV; /**< Device information page revision */
glebiuskv 0:2f0e1e23c242 57 __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */
glebiuskv 0:2f0e1e23c242 58 uint32_t RESERVED3[2]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 59 __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */
glebiuskv 0:2f0e1e23c242 60 __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */
glebiuskv 0:2f0e1e23c242 61 __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */
glebiuskv 0:2f0e1e23c242 62 __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */
glebiuskv 0:2f0e1e23c242 63 uint32_t RESERVED4[4]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 64 __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */
glebiuskv 0:2f0e1e23c242 65 uint32_t RESERVED5[2]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 66 __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */
glebiuskv 0:2f0e1e23c242 67 uint32_t RESERVED6[2]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 68 __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */
glebiuskv 0:2f0e1e23c242 69 __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */
glebiuskv 0:2f0e1e23c242 70 __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */
glebiuskv 0:2f0e1e23c242 71 uint32_t RESERVED7[1]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 72 __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */
glebiuskv 0:2f0e1e23c242 73 __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */
glebiuskv 0:2f0e1e23c242 74 __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */
glebiuskv 0:2f0e1e23c242 75 uint32_t RESERVED8[11]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 76 __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */
glebiuskv 0:2f0e1e23c242 77 uint32_t RESERVED9[2]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 78 __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */
glebiuskv 0:2f0e1e23c242 79 uint32_t RESERVED10[2]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 80 __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */
glebiuskv 0:2f0e1e23c242 81 __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */
glebiuskv 0:2f0e1e23c242 82 __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */
glebiuskv 0:2f0e1e23c242 83 uint32_t RESERVED11[1]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 84 __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */
glebiuskv 0:2f0e1e23c242 85 __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */
glebiuskv 0:2f0e1e23c242 86 __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */
glebiuskv 0:2f0e1e23c242 87 uint32_t RESERVED12[11]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 88 __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */
glebiuskv 0:2f0e1e23c242 89 __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */
glebiuskv 0:2f0e1e23c242 90 __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */
glebiuskv 0:2f0e1e23c242 91 uint32_t RESERVED13[3]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 92 __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */
glebiuskv 0:2f0e1e23c242 93 __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */
glebiuskv 0:2f0e1e23c242 94 uint32_t RESERVED14[2]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 95 __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */
glebiuskv 0:2f0e1e23c242 96 __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */
glebiuskv 0:2f0e1e23c242 97 __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */
glebiuskv 0:2f0e1e23c242 98 __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */
glebiuskv 0:2f0e1e23c242 99 __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */
glebiuskv 0:2f0e1e23c242 100 __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */
glebiuskv 0:2f0e1e23c242 101 __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */
glebiuskv 0:2f0e1e23c242 102 } DEVINFO_TypeDef; /** @} */
glebiuskv 0:2f0e1e23c242 103
glebiuskv 0:2f0e1e23c242 104 /**************************************************************************//**
glebiuskv 0:2f0e1e23c242 105 * @defgroup EFR32MG1P_DEVINFO_BitFields
glebiuskv 0:2f0e1e23c242 106 * @{
glebiuskv 0:2f0e1e23c242 107 *****************************************************************************/
glebiuskv 0:2f0e1e23c242 108
glebiuskv 0:2f0e1e23c242 109 /* Bit fields for DEVINFO CAL */
glebiuskv 0:2f0e1e23c242 110 #define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */
glebiuskv 0:2f0e1e23c242 111 #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */
glebiuskv 0:2f0e1e23c242 112 #define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */
glebiuskv 0:2f0e1e23c242 113 #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */
glebiuskv 0:2f0e1e23c242 114 #define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */
glebiuskv 0:2f0e1e23c242 115
glebiuskv 0:2f0e1e23c242 116 /* Bit fields for DEVINFO EXTINFO */
glebiuskv 0:2f0e1e23c242 117 #define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 118 #define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */
glebiuskv 0:2f0e1e23c242 119 #define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */
glebiuskv 0:2f0e1e23c242 120 #define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 121 #define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL /**< Mode AT25S041 for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 122 #define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 123 #define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 124 #define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0) /**< Shifted mode AT25S041 for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 125 #define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 126 #define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */
glebiuskv 0:2f0e1e23c242 127 #define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */
glebiuskv 0:2f0e1e23c242 128 #define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 129 #define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 130 #define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 131 #define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 132 #define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */
glebiuskv 0:2f0e1e23c242 133 #define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */
glebiuskv 0:2f0e1e23c242 134 #define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL /**< Mode REV1 for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 135 #define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 136 #define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16) /**< Shifted mode REV1 for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 137 #define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16) /**< Shifted mode NONE for DEVINFO_EXTINFO */
glebiuskv 0:2f0e1e23c242 138
glebiuskv 0:2f0e1e23c242 139 /* Bit fields for DEVINFO EUI48L */
glebiuskv 0:2f0e1e23c242 140 #define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */
glebiuskv 0:2f0e1e23c242 141 #define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */
glebiuskv 0:2f0e1e23c242 142 #define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */
glebiuskv 0:2f0e1e23c242 143 #define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */
glebiuskv 0:2f0e1e23c242 144 #define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */
glebiuskv 0:2f0e1e23c242 145
glebiuskv 0:2f0e1e23c242 146 /* Bit fields for DEVINFO EUI48H */
glebiuskv 0:2f0e1e23c242 147 #define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */
glebiuskv 0:2f0e1e23c242 148 #define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */
glebiuskv 0:2f0e1e23c242 149 #define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */
glebiuskv 0:2f0e1e23c242 150
glebiuskv 0:2f0e1e23c242 151 /* Bit fields for DEVINFO CUSTOMINFO */
glebiuskv 0:2f0e1e23c242 152 #define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */
glebiuskv 0:2f0e1e23c242 153 #define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */
glebiuskv 0:2f0e1e23c242 154 #define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */
glebiuskv 0:2f0e1e23c242 155
glebiuskv 0:2f0e1e23c242 156 /* Bit fields for DEVINFO MEMINFO */
glebiuskv 0:2f0e1e23c242 157 #define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 158 #define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */
glebiuskv 0:2f0e1e23c242 159 #define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */
glebiuskv 0:2f0e1e23c242 160 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 161 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 162 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 163 #define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 164 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 165 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 166 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 167 #define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 168 #define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */
glebiuskv 0:2f0e1e23c242 169 #define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */
glebiuskv 0:2f0e1e23c242 170 #define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 171 #define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 172 #define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 173 #define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 174 #define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 175 #define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */
glebiuskv 0:2f0e1e23c242 176 #define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */
glebiuskv 0:2f0e1e23c242 177 #define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */
glebiuskv 0:2f0e1e23c242 178 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */
glebiuskv 0:2f0e1e23c242 179 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */
glebiuskv 0:2f0e1e23c242 180
glebiuskv 0:2f0e1e23c242 181 /* Bit fields for DEVINFO UNIQUEL */
glebiuskv 0:2f0e1e23c242 182 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */
glebiuskv 0:2f0e1e23c242 183 #define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */
glebiuskv 0:2f0e1e23c242 184 #define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */
glebiuskv 0:2f0e1e23c242 185
glebiuskv 0:2f0e1e23c242 186 /* Bit fields for DEVINFO UNIQUEH */
glebiuskv 0:2f0e1e23c242 187 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */
glebiuskv 0:2f0e1e23c242 188 #define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */
glebiuskv 0:2f0e1e23c242 189 #define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */
glebiuskv 0:2f0e1e23c242 190
glebiuskv 0:2f0e1e23c242 191 /* Bit fields for DEVINFO MSIZE */
glebiuskv 0:2f0e1e23c242 192 #define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */
glebiuskv 0:2f0e1e23c242 193 #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */
glebiuskv 0:2f0e1e23c242 194 #define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */
glebiuskv 0:2f0e1e23c242 195 #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */
glebiuskv 0:2f0e1e23c242 196 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */
glebiuskv 0:2f0e1e23c242 197
glebiuskv 0:2f0e1e23c242 198 /* Bit fields for DEVINFO PART */
glebiuskv 0:2f0e1e23c242 199 #define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 200 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */
glebiuskv 0:2f0e1e23c242 201 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */
glebiuskv 0:2f0e1e23c242 202 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */
glebiuskv 0:2f0e1e23c242 203 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */
glebiuskv 0:2f0e1e23c242 204 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 205 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 206 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 207 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 208 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 209 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 210 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 211 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 212 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 213 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 214 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P 0x0000001CUL /**< Mode EFR32MG2P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 215 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 216 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 217 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 218 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 219 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 220 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 221 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 222 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 223 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 224 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 225 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 226 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 227 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 228 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 229 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 230 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 231 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 232 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 233 #define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 234 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 235 #define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 236 #define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 237 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 238 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 239 #define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 240 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 241 #define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 242 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 243 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 244 #define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 245 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 246 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 247 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 248 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 249 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 250 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 251 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 252 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 253 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 254 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 255 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 256 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 257 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 258 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 259 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 260 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 261 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 262 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 263 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 264 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 265 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16) /**< Shifted mode EFR32MG2P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 266 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 267 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 268 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 269 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 270 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 271 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 272 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 273 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 274 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 275 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 276 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 277 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 278 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 279 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 280 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 281 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 282 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 283 #define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 284 #define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 285 #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 286 #define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 287 #define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 288 #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 289 #define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 290 #define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 291 #define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 292 #define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 293 #define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 294 #define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 295 #define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 296 #define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 297 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 298 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 299 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 300 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 301 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 302 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 303 #define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 304 #define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 305 #define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */
glebiuskv 0:2f0e1e23c242 306 #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */
glebiuskv 0:2f0e1e23c242 307 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */
glebiuskv 0:2f0e1e23c242 308
glebiuskv 0:2f0e1e23c242 309 /* Bit fields for DEVINFO DEVINFOREV */
glebiuskv 0:2f0e1e23c242 310 #define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */
glebiuskv 0:2f0e1e23c242 311 #define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */
glebiuskv 0:2f0e1e23c242 312 #define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */
glebiuskv 0:2f0e1e23c242 313
glebiuskv 0:2f0e1e23c242 314 /* Bit fields for DEVINFO EMUTEMP */
glebiuskv 0:2f0e1e23c242 315 #define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */
glebiuskv 0:2f0e1e23c242 316 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */
glebiuskv 0:2f0e1e23c242 317 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */
glebiuskv 0:2f0e1e23c242 318
glebiuskv 0:2f0e1e23c242 319 /* Bit fields for DEVINFO ADC0CAL0 */
glebiuskv 0:2f0e1e23c242 320 #define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */
glebiuskv 0:2f0e1e23c242 321 #define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */
glebiuskv 0:2f0e1e23c242 322 #define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */
glebiuskv 0:2f0e1e23c242 323 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */
glebiuskv 0:2f0e1e23c242 324 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */
glebiuskv 0:2f0e1e23c242 325 #define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */
glebiuskv 0:2f0e1e23c242 326 #define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */
glebiuskv 0:2f0e1e23c242 327 #define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */
glebiuskv 0:2f0e1e23c242 328 #define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */
glebiuskv 0:2f0e1e23c242 329 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */
glebiuskv 0:2f0e1e23c242 330 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */
glebiuskv 0:2f0e1e23c242 331 #define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */
glebiuskv 0:2f0e1e23c242 332 #define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */
glebiuskv 0:2f0e1e23c242 333
glebiuskv 0:2f0e1e23c242 334 /* Bit fields for DEVINFO ADC0CAL1 */
glebiuskv 0:2f0e1e23c242 335 #define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */
glebiuskv 0:2f0e1e23c242 336 #define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */
glebiuskv 0:2f0e1e23c242 337 #define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */
glebiuskv 0:2f0e1e23c242 338 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */
glebiuskv 0:2f0e1e23c242 339 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */
glebiuskv 0:2f0e1e23c242 340 #define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */
glebiuskv 0:2f0e1e23c242 341 #define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */
glebiuskv 0:2f0e1e23c242 342 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */
glebiuskv 0:2f0e1e23c242 343 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */
glebiuskv 0:2f0e1e23c242 344 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */
glebiuskv 0:2f0e1e23c242 345 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */
glebiuskv 0:2f0e1e23c242 346 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */
glebiuskv 0:2f0e1e23c242 347 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */
glebiuskv 0:2f0e1e23c242 348
glebiuskv 0:2f0e1e23c242 349 /* Bit fields for DEVINFO ADC0CAL2 */
glebiuskv 0:2f0e1e23c242 350 #define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */
glebiuskv 0:2f0e1e23c242 351 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */
glebiuskv 0:2f0e1e23c242 352 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */
glebiuskv 0:2f0e1e23c242 353 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */
glebiuskv 0:2f0e1e23c242 354 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */
glebiuskv 0:2f0e1e23c242 355
glebiuskv 0:2f0e1e23c242 356 /* Bit fields for DEVINFO ADC0CAL3 */
glebiuskv 0:2f0e1e23c242 357 #define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */
glebiuskv 0:2f0e1e23c242 358 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */
glebiuskv 0:2f0e1e23c242 359 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */
glebiuskv 0:2f0e1e23c242 360
glebiuskv 0:2f0e1e23c242 361 /* Bit fields for DEVINFO HFRCOCAL0 */
glebiuskv 0:2f0e1e23c242 362 #define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */
glebiuskv 0:2f0e1e23c242 363 #define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 364 #define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 365 #define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 366 #define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 367 #define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 368 #define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 369 #define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 370 #define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 371 #define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 372 #define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 373 #define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 374 #define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 375 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 376 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 377 #define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 378 #define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 379
glebiuskv 0:2f0e1e23c242 380 /* Bit fields for DEVINFO HFRCOCAL3 */
glebiuskv 0:2f0e1e23c242 381 #define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */
glebiuskv 0:2f0e1e23c242 382 #define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 383 #define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 384 #define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 385 #define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 386 #define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 387 #define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 388 #define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 389 #define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 390 #define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 391 #define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 392 #define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 393 #define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 394 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 395 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 396 #define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 397 #define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 398
glebiuskv 0:2f0e1e23c242 399 /* Bit fields for DEVINFO HFRCOCAL6 */
glebiuskv 0:2f0e1e23c242 400 #define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */
glebiuskv 0:2f0e1e23c242 401 #define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 402 #define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 403 #define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 404 #define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 405 #define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 406 #define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 407 #define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 408 #define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 409 #define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 410 #define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 411 #define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 412 #define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 413 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 414 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 415 #define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 416 #define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 417
glebiuskv 0:2f0e1e23c242 418 /* Bit fields for DEVINFO HFRCOCAL7 */
glebiuskv 0:2f0e1e23c242 419 #define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */
glebiuskv 0:2f0e1e23c242 420 #define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 421 #define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 422 #define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 423 #define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 424 #define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 425 #define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 426 #define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 427 #define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 428 #define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 429 #define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 430 #define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 431 #define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 432 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 433 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 434 #define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 435 #define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 436
glebiuskv 0:2f0e1e23c242 437 /* Bit fields for DEVINFO HFRCOCAL8 */
glebiuskv 0:2f0e1e23c242 438 #define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */
glebiuskv 0:2f0e1e23c242 439 #define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 440 #define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 441 #define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 442 #define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 443 #define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 444 #define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 445 #define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 446 #define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 447 #define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 448 #define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 449 #define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 450 #define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 451 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 452 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 453 #define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 454 #define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 455
glebiuskv 0:2f0e1e23c242 456 /* Bit fields for DEVINFO HFRCOCAL10 */
glebiuskv 0:2f0e1e23c242 457 #define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */
glebiuskv 0:2f0e1e23c242 458 #define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 459 #define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 460 #define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 461 #define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 462 #define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 463 #define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 464 #define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 465 #define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 466 #define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 467 #define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 468 #define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 469 #define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 470 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 471 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 472 #define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 473 #define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 474
glebiuskv 0:2f0e1e23c242 475 /* Bit fields for DEVINFO HFRCOCAL11 */
glebiuskv 0:2f0e1e23c242 476 #define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */
glebiuskv 0:2f0e1e23c242 477 #define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 478 #define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 479 #define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 480 #define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 481 #define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 482 #define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 483 #define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 484 #define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 485 #define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 486 #define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 487 #define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 488 #define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 489 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 490 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 491 #define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 492 #define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 493
glebiuskv 0:2f0e1e23c242 494 /* Bit fields for DEVINFO HFRCOCAL12 */
glebiuskv 0:2f0e1e23c242 495 #define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */
glebiuskv 0:2f0e1e23c242 496 #define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 497 #define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 498 #define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 499 #define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 500 #define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 501 #define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 502 #define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 503 #define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 504 #define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 505 #define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 506 #define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 507 #define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 508 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 509 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 510 #define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 511 #define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 512
glebiuskv 0:2f0e1e23c242 513 /* Bit fields for DEVINFO AUXHFRCOCAL0 */
glebiuskv 0:2f0e1e23c242 514 #define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */
glebiuskv 0:2f0e1e23c242 515 #define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 516 #define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 517 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 518 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 519 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 520 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 521 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 522 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 523 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 524 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 525 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 526 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 527 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 528 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 529 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 530 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 531
glebiuskv 0:2f0e1e23c242 532 /* Bit fields for DEVINFO AUXHFRCOCAL3 */
glebiuskv 0:2f0e1e23c242 533 #define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */
glebiuskv 0:2f0e1e23c242 534 #define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 535 #define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 536 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 537 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 538 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 539 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 540 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 541 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 542 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 543 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 544 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 545 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 546 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 547 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 548 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 549 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 550
glebiuskv 0:2f0e1e23c242 551 /* Bit fields for DEVINFO AUXHFRCOCAL6 */
glebiuskv 0:2f0e1e23c242 552 #define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */
glebiuskv 0:2f0e1e23c242 553 #define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 554 #define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 555 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 556 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 557 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 558 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 559 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 560 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 561 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 562 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 563 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 564 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 565 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 566 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 567 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 568 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 569
glebiuskv 0:2f0e1e23c242 570 /* Bit fields for DEVINFO AUXHFRCOCAL7 */
glebiuskv 0:2f0e1e23c242 571 #define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */
glebiuskv 0:2f0e1e23c242 572 #define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 573 #define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 574 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 575 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 576 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 577 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 578 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 579 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 580 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 581 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 582 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 583 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 584 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 585 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 586 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 587 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 588
glebiuskv 0:2f0e1e23c242 589 /* Bit fields for DEVINFO AUXHFRCOCAL8 */
glebiuskv 0:2f0e1e23c242 590 #define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */
glebiuskv 0:2f0e1e23c242 591 #define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 592 #define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 593 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 594 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 595 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 596 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 597 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 598 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 599 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 600 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 601 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 602 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 603 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 604 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 605 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 606 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 607
glebiuskv 0:2f0e1e23c242 608 /* Bit fields for DEVINFO AUXHFRCOCAL10 */
glebiuskv 0:2f0e1e23c242 609 #define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */
glebiuskv 0:2f0e1e23c242 610 #define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 611 #define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 612 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 613 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 614 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 615 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 616 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 617 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 618 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 619 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 620 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 621 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 622 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 623 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 624 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 625 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 626
glebiuskv 0:2f0e1e23c242 627 /* Bit fields for DEVINFO AUXHFRCOCAL11 */
glebiuskv 0:2f0e1e23c242 628 #define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */
glebiuskv 0:2f0e1e23c242 629 #define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 630 #define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 631 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 632 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 633 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 634 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 635 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 636 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 637 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 638 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 639 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 640 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 641 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 642 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 643 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 644 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 645
glebiuskv 0:2f0e1e23c242 646 /* Bit fields for DEVINFO AUXHFRCOCAL12 */
glebiuskv 0:2f0e1e23c242 647 #define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */
glebiuskv 0:2f0e1e23c242 648 #define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */
glebiuskv 0:2f0e1e23c242 649 #define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
glebiuskv 0:2f0e1e23c242 650 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
glebiuskv 0:2f0e1e23c242 651 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
glebiuskv 0:2f0e1e23c242 652 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
glebiuskv 0:2f0e1e23c242 653 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
glebiuskv 0:2f0e1e23c242 654 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
glebiuskv 0:2f0e1e23c242 655 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
glebiuskv 0:2f0e1e23c242 656 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
glebiuskv 0:2f0e1e23c242 657 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
glebiuskv 0:2f0e1e23c242 658 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
glebiuskv 0:2f0e1e23c242 659 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
glebiuskv 0:2f0e1e23c242 660 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 661 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
glebiuskv 0:2f0e1e23c242 662 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
glebiuskv 0:2f0e1e23c242 663 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
glebiuskv 0:2f0e1e23c242 664
glebiuskv 0:2f0e1e23c242 665 /* Bit fields for DEVINFO VMONCAL0 */
glebiuskv 0:2f0e1e23c242 666 #define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */
glebiuskv 0:2f0e1e23c242 667 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */
glebiuskv 0:2f0e1e23c242 668 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */
glebiuskv 0:2f0e1e23c242 669 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */
glebiuskv 0:2f0e1e23c242 670 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */
glebiuskv 0:2f0e1e23c242 671 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */
glebiuskv 0:2f0e1e23c242 672 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */
glebiuskv 0:2f0e1e23c242 673 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */
glebiuskv 0:2f0e1e23c242 674 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */
glebiuskv 0:2f0e1e23c242 675 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */
glebiuskv 0:2f0e1e23c242 676 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */
glebiuskv 0:2f0e1e23c242 677 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */
glebiuskv 0:2f0e1e23c242 678 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */
glebiuskv 0:2f0e1e23c242 679 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */
glebiuskv 0:2f0e1e23c242 680 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */
glebiuskv 0:2f0e1e23c242 681 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */
glebiuskv 0:2f0e1e23c242 682 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */
glebiuskv 0:2f0e1e23c242 683
glebiuskv 0:2f0e1e23c242 684 /* Bit fields for DEVINFO VMONCAL1 */
glebiuskv 0:2f0e1e23c242 685 #define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */
glebiuskv 0:2f0e1e23c242 686 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */
glebiuskv 0:2f0e1e23c242 687 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */
glebiuskv 0:2f0e1e23c242 688 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */
glebiuskv 0:2f0e1e23c242 689 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */
glebiuskv 0:2f0e1e23c242 690 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */
glebiuskv 0:2f0e1e23c242 691 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */
glebiuskv 0:2f0e1e23c242 692 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */
glebiuskv 0:2f0e1e23c242 693 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */
glebiuskv 0:2f0e1e23c242 694 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */
glebiuskv 0:2f0e1e23c242 695 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */
glebiuskv 0:2f0e1e23c242 696 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */
glebiuskv 0:2f0e1e23c242 697 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */
glebiuskv 0:2f0e1e23c242 698 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */
glebiuskv 0:2f0e1e23c242 699 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */
glebiuskv 0:2f0e1e23c242 700 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */
glebiuskv 0:2f0e1e23c242 701 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */
glebiuskv 0:2f0e1e23c242 702
glebiuskv 0:2f0e1e23c242 703 /* Bit fields for DEVINFO VMONCAL2 */
glebiuskv 0:2f0e1e23c242 704 #define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */
glebiuskv 0:2f0e1e23c242 705 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */
glebiuskv 0:2f0e1e23c242 706 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */
glebiuskv 0:2f0e1e23c242 707 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */
glebiuskv 0:2f0e1e23c242 708 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */
glebiuskv 0:2f0e1e23c242 709 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */
glebiuskv 0:2f0e1e23c242 710 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */
glebiuskv 0:2f0e1e23c242 711 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */
glebiuskv 0:2f0e1e23c242 712 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */
glebiuskv 0:2f0e1e23c242 713 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */
glebiuskv 0:2f0e1e23c242 714 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */
glebiuskv 0:2f0e1e23c242 715 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */
glebiuskv 0:2f0e1e23c242 716 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */
glebiuskv 0:2f0e1e23c242 717 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */
glebiuskv 0:2f0e1e23c242 718 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */
glebiuskv 0:2f0e1e23c242 719 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */
glebiuskv 0:2f0e1e23c242 720 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */
glebiuskv 0:2f0e1e23c242 721
glebiuskv 0:2f0e1e23c242 722 /* Bit fields for DEVINFO IDAC0CAL0 */
glebiuskv 0:2f0e1e23c242 723 #define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */
glebiuskv 0:2f0e1e23c242 724 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */
glebiuskv 0:2f0e1e23c242 725 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */
glebiuskv 0:2f0e1e23c242 726 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */
glebiuskv 0:2f0e1e23c242 727 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */
glebiuskv 0:2f0e1e23c242 728 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */
glebiuskv 0:2f0e1e23c242 729 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */
glebiuskv 0:2f0e1e23c242 730 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */
glebiuskv 0:2f0e1e23c242 731 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */
glebiuskv 0:2f0e1e23c242 732
glebiuskv 0:2f0e1e23c242 733 /* Bit fields for DEVINFO IDAC0CAL1 */
glebiuskv 0:2f0e1e23c242 734 #define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */
glebiuskv 0:2f0e1e23c242 735 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */
glebiuskv 0:2f0e1e23c242 736 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */
glebiuskv 0:2f0e1e23c242 737 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */
glebiuskv 0:2f0e1e23c242 738 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */
glebiuskv 0:2f0e1e23c242 739 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */
glebiuskv 0:2f0e1e23c242 740 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */
glebiuskv 0:2f0e1e23c242 741 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */
glebiuskv 0:2f0e1e23c242 742 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */
glebiuskv 0:2f0e1e23c242 743
glebiuskv 0:2f0e1e23c242 744 /* Bit fields for DEVINFO DCDCLNVCTRL0 */
glebiuskv 0:2f0e1e23c242 745 #define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */
glebiuskv 0:2f0e1e23c242 746 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */
glebiuskv 0:2f0e1e23c242 747 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */
glebiuskv 0:2f0e1e23c242 748 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */
glebiuskv 0:2f0e1e23c242 749 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */
glebiuskv 0:2f0e1e23c242 750 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */
glebiuskv 0:2f0e1e23c242 751 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */
glebiuskv 0:2f0e1e23c242 752 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */
glebiuskv 0:2f0e1e23c242 753 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */
glebiuskv 0:2f0e1e23c242 754
glebiuskv 0:2f0e1e23c242 755 /* Bit fields for DEVINFO DCDCLPVCTRL0 */
glebiuskv 0:2f0e1e23c242 756 #define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */
glebiuskv 0:2f0e1e23c242 757 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */
glebiuskv 0:2f0e1e23c242 758 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */
glebiuskv 0:2f0e1e23c242 759 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */
glebiuskv 0:2f0e1e23c242 760 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */
glebiuskv 0:2f0e1e23c242 761 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */
glebiuskv 0:2f0e1e23c242 762 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */
glebiuskv 0:2f0e1e23c242 763 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */
glebiuskv 0:2f0e1e23c242 764 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */
glebiuskv 0:2f0e1e23c242 765
glebiuskv 0:2f0e1e23c242 766 /* Bit fields for DEVINFO DCDCLPVCTRL1 */
glebiuskv 0:2f0e1e23c242 767 #define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */
glebiuskv 0:2f0e1e23c242 768 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */
glebiuskv 0:2f0e1e23c242 769 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */
glebiuskv 0:2f0e1e23c242 770 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */
glebiuskv 0:2f0e1e23c242 771 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */
glebiuskv 0:2f0e1e23c242 772 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */
glebiuskv 0:2f0e1e23c242 773 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */
glebiuskv 0:2f0e1e23c242 774 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */
glebiuskv 0:2f0e1e23c242 775 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */
glebiuskv 0:2f0e1e23c242 776
glebiuskv 0:2f0e1e23c242 777 /* Bit fields for DEVINFO DCDCLPVCTRL2 */
glebiuskv 0:2f0e1e23c242 778 #define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */
glebiuskv 0:2f0e1e23c242 779 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */
glebiuskv 0:2f0e1e23c242 780 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */
glebiuskv 0:2f0e1e23c242 781 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */
glebiuskv 0:2f0e1e23c242 782 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */
glebiuskv 0:2f0e1e23c242 783 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */
glebiuskv 0:2f0e1e23c242 784 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */
glebiuskv 0:2f0e1e23c242 785 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */
glebiuskv 0:2f0e1e23c242 786 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */
glebiuskv 0:2f0e1e23c242 787
glebiuskv 0:2f0e1e23c242 788 /* Bit fields for DEVINFO DCDCLPVCTRL3 */
glebiuskv 0:2f0e1e23c242 789 #define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */
glebiuskv 0:2f0e1e23c242 790 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */
glebiuskv 0:2f0e1e23c242 791 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */
glebiuskv 0:2f0e1e23c242 792 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */
glebiuskv 0:2f0e1e23c242 793 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */
glebiuskv 0:2f0e1e23c242 794 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */
glebiuskv 0:2f0e1e23c242 795 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */
glebiuskv 0:2f0e1e23c242 796 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */
glebiuskv 0:2f0e1e23c242 797 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */
glebiuskv 0:2f0e1e23c242 798
glebiuskv 0:2f0e1e23c242 799 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */
glebiuskv 0:2f0e1e23c242 800 #define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */
glebiuskv 0:2f0e1e23c242 801 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */
glebiuskv 0:2f0e1e23c242 802 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */
glebiuskv 0:2f0e1e23c242 803 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */
glebiuskv 0:2f0e1e23c242 804 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */
glebiuskv 0:2f0e1e23c242 805
glebiuskv 0:2f0e1e23c242 806 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */
glebiuskv 0:2f0e1e23c242 807 #define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */
glebiuskv 0:2f0e1e23c242 808 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */
glebiuskv 0:2f0e1e23c242 809 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */
glebiuskv 0:2f0e1e23c242 810 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */
glebiuskv 0:2f0e1e23c242 811 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */
glebiuskv 0:2f0e1e23c242 812 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */
glebiuskv 0:2f0e1e23c242 813 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */
glebiuskv 0:2f0e1e23c242 814 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */
glebiuskv 0:2f0e1e23c242 815 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */
glebiuskv 0:2f0e1e23c242 816
glebiuskv 0:2f0e1e23c242 817 /** @} End of group EFR32MG1P_DEVINFO */
glebiuskv 0:2f0e1e23c242 818 /** @} End of group Parts */
glebiuskv 0:2f0e1e23c242 819