Gleb Klochkov / Mbed OS Climatcontroll_Main

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Dependencies:   esp8266-driver

mbed-os/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg_etm.h@0:2f0e1e23c242, 2018-04-13 (annotated)

Committer:
glebiuskv
Date:
Fri Apr 13 08:53:46 2018 +0000
Revision:
0:2f0e1e23c242
initial

Who changed what in which revision?

UserRevisionLine numberNew contents of line
glebiuskv 0:2f0e1e23c242 1 /**************************************************************************//**
glebiuskv 0:2f0e1e23c242 2 * @file efm32gg_etm.h
glebiuskv 0:2f0e1e23c242 3 * @brief EFM32GG_ETM register and bit field definitions
glebiuskv 0:2f0e1e23c242 4 * @version 5.1.2
glebiuskv 0:2f0e1e23c242 5 ******************************************************************************
glebiuskv 0:2f0e1e23c242 6 * @section License
glebiuskv 0:2f0e1e23c242 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
glebiuskv 0:2f0e1e23c242 8 ******************************************************************************
glebiuskv 0:2f0e1e23c242 9 *
glebiuskv 0:2f0e1e23c242 10 * Permission is granted to anyone to use this software for any purpose,
glebiuskv 0:2f0e1e23c242 11 * including commercial applications, and to alter it and redistribute it
glebiuskv 0:2f0e1e23c242 12 * freely, subject to the following restrictions:
glebiuskv 0:2f0e1e23c242 13 *
glebiuskv 0:2f0e1e23c242 14 * 1. The origin of this software must not be misrepresented; you must not
glebiuskv 0:2f0e1e23c242 15 * claim that you wrote the original software.@n
glebiuskv 0:2f0e1e23c242 16 * 2. Altered source versions must be plainly marked as such, and must not be
glebiuskv 0:2f0e1e23c242 17 * misrepresented as being the original software.@n
glebiuskv 0:2f0e1e23c242 18 * 3. This notice may not be removed or altered from any source distribution.
glebiuskv 0:2f0e1e23c242 19 *
glebiuskv 0:2f0e1e23c242 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
glebiuskv 0:2f0e1e23c242 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
glebiuskv 0:2f0e1e23c242 22 * providing the Software "AS IS", with no express or implied warranties of any
glebiuskv 0:2f0e1e23c242 23 * kind, including, but not limited to, any implied warranties of
glebiuskv 0:2f0e1e23c242 24 * merchantability or fitness for any particular purpose or warranties against
glebiuskv 0:2f0e1e23c242 25 * infringement of any proprietary rights of a third party.
glebiuskv 0:2f0e1e23c242 26 *
glebiuskv 0:2f0e1e23c242 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
glebiuskv 0:2f0e1e23c242 28 * incidental, or special damages, or any other relief, or for any claim by
glebiuskv 0:2f0e1e23c242 29 * any third party, arising from your use of this Software.
glebiuskv 0:2f0e1e23c242 30 *
glebiuskv 0:2f0e1e23c242 31 *****************************************************************************/
glebiuskv 0:2f0e1e23c242 32 /**************************************************************************//**
glebiuskv 0:2f0e1e23c242 33 * @addtogroup Parts
glebiuskv 0:2f0e1e23c242 34 * @{
glebiuskv 0:2f0e1e23c242 35 ******************************************************************************/
glebiuskv 0:2f0e1e23c242 36 /**************************************************************************//**
glebiuskv 0:2f0e1e23c242 37 * @defgroup EFM32GG_ETM
glebiuskv 0:2f0e1e23c242 38 * @{
glebiuskv 0:2f0e1e23c242 39 * @brief EFM32GG_ETM Register Declaration
glebiuskv 0:2f0e1e23c242 40 *****************************************************************************/
glebiuskv 0:2f0e1e23c242 41 typedef struct
glebiuskv 0:2f0e1e23c242 42 {
glebiuskv 0:2f0e1e23c242 43 __IOM uint32_t ETMCR; /**< Main Control Register */
glebiuskv 0:2f0e1e23c242 44 __IM uint32_t ETMCCR; /**< Configuration Code Register */
glebiuskv 0:2f0e1e23c242 45 __IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */
glebiuskv 0:2f0e1e23c242 46 uint32_t RESERVED0[1]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 47 __IOM uint32_t ETMSR; /**< ETM Status Register */
glebiuskv 0:2f0e1e23c242 48 __IM uint32_t ETMSCR; /**< ETM System Configuration Register */
glebiuskv 0:2f0e1e23c242 49 uint32_t RESERVED1[2]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 50 __IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */
glebiuskv 0:2f0e1e23c242 51 __IOM uint32_t ETMTECR1; /**< ETM Trace control Register */
glebiuskv 0:2f0e1e23c242 52 uint32_t RESERVED2[1]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 53 __IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */
glebiuskv 0:2f0e1e23c242 54 uint32_t RESERVED3[68]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 55 __IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */
glebiuskv 0:2f0e1e23c242 56 uint32_t RESERVED4[39]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 57 __IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */
glebiuskv 0:2f0e1e23c242 58 __IM uint32_t ETMIDR; /**< ID Register */
glebiuskv 0:2f0e1e23c242 59 __IM uint32_t ETMCCER; /**< Configuration Code Extension Register */
glebiuskv 0:2f0e1e23c242 60 uint32_t RESERVED5[1]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 61 __IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */
glebiuskv 0:2f0e1e23c242 62 uint32_t RESERVED6[1]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 63 __IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */
glebiuskv 0:2f0e1e23c242 64 uint32_t RESERVED7[1]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 65 __IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */
glebiuskv 0:2f0e1e23c242 66 uint32_t RESERVED8[1]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 67 __IM uint32_t ETMIDR2; /**< ETM ID Register 2 */
glebiuskv 0:2f0e1e23c242 68 uint32_t RESERVED9[66]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 69 __IM uint32_t ETMPDSR; /**< Device Power-down Status Register */
glebiuskv 0:2f0e1e23c242 70 uint32_t RESERVED10[754]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 71 __IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */
glebiuskv 0:2f0e1e23c242 72 uint32_t RESERVED11[1]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 73 __OM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */
glebiuskv 0:2f0e1e23c242 74 uint32_t RESERVED12[1]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 75 __IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */
glebiuskv 0:2f0e1e23c242 76 uint32_t RESERVED13[1]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 77 __OM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */
glebiuskv 0:2f0e1e23c242 78 uint32_t RESERVED14[1]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 79 __IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */
glebiuskv 0:2f0e1e23c242 80 uint32_t RESERVED15[39]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 81 __IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */
glebiuskv 0:2f0e1e23c242 82 __IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */
glebiuskv 0:2f0e1e23c242 83 uint32_t RESERVED16[2]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 84 __IOM uint32_t ETMLAR; /**< ETM Lock Access Register */
glebiuskv 0:2f0e1e23c242 85 __IM uint32_t ETMLSR; /**< Lock Status Register */
glebiuskv 0:2f0e1e23c242 86 __IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */
glebiuskv 0:2f0e1e23c242 87 uint32_t RESERVED17[4]; /**< Reserved for future use **/
glebiuskv 0:2f0e1e23c242 88 __IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */
glebiuskv 0:2f0e1e23c242 89 __IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */
glebiuskv 0:2f0e1e23c242 90 __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */
glebiuskv 0:2f0e1e23c242 91 __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */
glebiuskv 0:2f0e1e23c242 92 __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
glebiuskv 0:2f0e1e23c242 93 __IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */
glebiuskv 0:2f0e1e23c242 94 __IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */
glebiuskv 0:2f0e1e23c242 95 __IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */
glebiuskv 0:2f0e1e23c242 96 __IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */
glebiuskv 0:2f0e1e23c242 97 __IM uint32_t ETMCIDR0; /**< Component ID0 Register */
glebiuskv 0:2f0e1e23c242 98 __IM uint32_t ETMCIDR1; /**< Component ID1 Register */
glebiuskv 0:2f0e1e23c242 99 __IM uint32_t ETMCIDR2; /**< Component ID2 Register */
glebiuskv 0:2f0e1e23c242 100 __IM uint32_t ETMCIDR3; /**< Component ID3 Register */
glebiuskv 0:2f0e1e23c242 101 } ETM_TypeDef; /** @} */
glebiuskv 0:2f0e1e23c242 102
glebiuskv 0:2f0e1e23c242 103 /**************************************************************************//**
glebiuskv 0:2f0e1e23c242 104 * @defgroup EFM32GG_ETM_BitFields
glebiuskv 0:2f0e1e23c242 105 * @{
glebiuskv 0:2f0e1e23c242 106 *****************************************************************************/
glebiuskv 0:2f0e1e23c242 107
glebiuskv 0:2f0e1e23c242 108 /* Bit fields for ETM ETMCR */
glebiuskv 0:2f0e1e23c242 109 #define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 110 #define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 111 #define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */
glebiuskv 0:2f0e1e23c242 112 #define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */
glebiuskv 0:2f0e1e23c242 113 #define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */
glebiuskv 0:2f0e1e23c242 114 #define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 115 #define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 116 #define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */
glebiuskv 0:2f0e1e23c242 117 #define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */
glebiuskv 0:2f0e1e23c242 118 #define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 119 #define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 120 #define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */
glebiuskv 0:2f0e1e23c242 121 #define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */
glebiuskv 0:2f0e1e23c242 122 #define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */
glebiuskv 0:2f0e1e23c242 123 #define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 124 #define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 125 #define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */
glebiuskv 0:2f0e1e23c242 126 #define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */
glebiuskv 0:2f0e1e23c242 127 #define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */
glebiuskv 0:2f0e1e23c242 128 #define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 129 #define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 130 #define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */
glebiuskv 0:2f0e1e23c242 131 #define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */
glebiuskv 0:2f0e1e23c242 132 #define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */
glebiuskv 0:2f0e1e23c242 133 #define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 134 #define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 135 #define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */
glebiuskv 0:2f0e1e23c242 136 #define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */
glebiuskv 0:2f0e1e23c242 137 #define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */
glebiuskv 0:2f0e1e23c242 138 #define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 139 #define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 140 #define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */
glebiuskv 0:2f0e1e23c242 141 #define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */
glebiuskv 0:2f0e1e23c242 142 #define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */
glebiuskv 0:2f0e1e23c242 143 #define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 144 #define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 145 #define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 146 #define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 147 #define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 148 #define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 149 #define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */
glebiuskv 0:2f0e1e23c242 150 #define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */
glebiuskv 0:2f0e1e23c242 151 #define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */
glebiuskv 0:2f0e1e23c242 152 #define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 153 #define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 154 #define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */
glebiuskv 0:2f0e1e23c242 155 #define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */
glebiuskv 0:2f0e1e23c242 156 #define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 157 #define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 158 #define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */
glebiuskv 0:2f0e1e23c242 159 #define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */
glebiuskv 0:2f0e1e23c242 160 #define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 161 #define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 162 #define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */
glebiuskv 0:2f0e1e23c242 163 #define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */
glebiuskv 0:2f0e1e23c242 164 #define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */
glebiuskv 0:2f0e1e23c242 165 #define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 166 #define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */
glebiuskv 0:2f0e1e23c242 167
glebiuskv 0:2f0e1e23c242 168 /* Bit fields for ETM ETMCCR */
glebiuskv 0:2f0e1e23c242 169 #define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 170 #define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 171 #define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */
glebiuskv 0:2f0e1e23c242 172 #define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */
glebiuskv 0:2f0e1e23c242 173 #define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 174 #define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 175 #define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */
glebiuskv 0:2f0e1e23c242 176 #define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */
glebiuskv 0:2f0e1e23c242 177 #define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 178 #define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 179 #define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */
glebiuskv 0:2f0e1e23c242 180 #define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */
glebiuskv 0:2f0e1e23c242 181 #define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 182 #define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 183 #define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */
glebiuskv 0:2f0e1e23c242 184 #define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */
glebiuskv 0:2f0e1e23c242 185 #define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 186 #define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 187 #define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */
glebiuskv 0:2f0e1e23c242 188 #define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */
glebiuskv 0:2f0e1e23c242 189 #define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */
glebiuskv 0:2f0e1e23c242 190 #define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 191 #define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 192 #define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */
glebiuskv 0:2f0e1e23c242 193 #define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */
glebiuskv 0:2f0e1e23c242 194 #define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 195 #define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 196 #define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 197 #define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 198 #define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 199 #define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 200 #define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 201 #define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 202 #define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */
glebiuskv 0:2f0e1e23c242 203 #define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */
glebiuskv 0:2f0e1e23c242 204 #define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 205 #define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 206 #define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */
glebiuskv 0:2f0e1e23c242 207 #define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */
glebiuskv 0:2f0e1e23c242 208 #define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */
glebiuskv 0:2f0e1e23c242 209 #define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 210 #define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 211 #define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */
glebiuskv 0:2f0e1e23c242 212 #define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */
glebiuskv 0:2f0e1e23c242 213 #define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 214 #define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 215 #define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */
glebiuskv 0:2f0e1e23c242 216 #define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */
glebiuskv 0:2f0e1e23c242 217 #define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */
glebiuskv 0:2f0e1e23c242 218 #define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 219 #define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 220 #define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */
glebiuskv 0:2f0e1e23c242 221 #define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */
glebiuskv 0:2f0e1e23c242 222 #define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */
glebiuskv 0:2f0e1e23c242 223 #define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 224 #define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 225 #define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */
glebiuskv 0:2f0e1e23c242 226 #define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */
glebiuskv 0:2f0e1e23c242 227 #define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */
glebiuskv 0:2f0e1e23c242 228 #define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 229 #define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */
glebiuskv 0:2f0e1e23c242 230
glebiuskv 0:2f0e1e23c242 231 /* Bit fields for ETM ETMTRIGGER */
glebiuskv 0:2f0e1e23c242 232 #define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */
glebiuskv 0:2f0e1e23c242 233 #define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */
glebiuskv 0:2f0e1e23c242 234 #define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
glebiuskv 0:2f0e1e23c242 235 #define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
glebiuskv 0:2f0e1e23c242 236 #define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
glebiuskv 0:2f0e1e23c242 237 #define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
glebiuskv 0:2f0e1e23c242 238 #define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
glebiuskv 0:2f0e1e23c242 239 #define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
glebiuskv 0:2f0e1e23c242 240 #define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
glebiuskv 0:2f0e1e23c242 241 #define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
glebiuskv 0:2f0e1e23c242 242 #define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */
glebiuskv 0:2f0e1e23c242 243 #define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */
glebiuskv 0:2f0e1e23c242 244 #define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
glebiuskv 0:2f0e1e23c242 245 #define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
glebiuskv 0:2f0e1e23c242 246
glebiuskv 0:2f0e1e23c242 247 /* Bit fields for ETM ETMSR */
glebiuskv 0:2f0e1e23c242 248 #define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */
glebiuskv 0:2f0e1e23c242 249 #define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */
glebiuskv 0:2f0e1e23c242 250 #define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */
glebiuskv 0:2f0e1e23c242 251 #define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */
glebiuskv 0:2f0e1e23c242 252 #define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */
glebiuskv 0:2f0e1e23c242 253 #define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
glebiuskv 0:2f0e1e23c242 254 #define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */
glebiuskv 0:2f0e1e23c242 255 #define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */
glebiuskv 0:2f0e1e23c242 256 #define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */
glebiuskv 0:2f0e1e23c242 257 #define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */
glebiuskv 0:2f0e1e23c242 258 #define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */
glebiuskv 0:2f0e1e23c242 259 #define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */
glebiuskv 0:2f0e1e23c242 260 #define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */
glebiuskv 0:2f0e1e23c242 261 #define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */
glebiuskv 0:2f0e1e23c242 262 #define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */
glebiuskv 0:2f0e1e23c242 263 #define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
glebiuskv 0:2f0e1e23c242 264 #define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */
glebiuskv 0:2f0e1e23c242 265 #define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */
glebiuskv 0:2f0e1e23c242 266 #define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */
glebiuskv 0:2f0e1e23c242 267 #define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */
glebiuskv 0:2f0e1e23c242 268 #define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
glebiuskv 0:2f0e1e23c242 269 #define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */
glebiuskv 0:2f0e1e23c242 270
glebiuskv 0:2f0e1e23c242 271 /* Bit fields for ETM ETMSCR */
glebiuskv 0:2f0e1e23c242 272 #define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 273 #define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 274 #define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */
glebiuskv 0:2f0e1e23c242 275 #define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */
glebiuskv 0:2f0e1e23c242 276 #define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 277 #define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 278 #define ETM_ETMSCR_Reserved (0x1UL << 3) /**< Reserved */
glebiuskv 0:2f0e1e23c242 279 #define _ETM_ETMSCR_Reserved_SHIFT 3 /**< Shift value for ETM_Reserved */
glebiuskv 0:2f0e1e23c242 280 #define _ETM_ETMSCR_Reserved_MASK 0x8UL /**< Bit mask for ETM_Reserved */
glebiuskv 0:2f0e1e23c242 281 #define _ETM_ETMSCR_Reserved_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 282 #define ETM_ETMSCR_Reserved_DEFAULT (_ETM_ETMSCR_Reserved_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 283 #define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */
glebiuskv 0:2f0e1e23c242 284 #define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */
glebiuskv 0:2f0e1e23c242 285 #define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */
glebiuskv 0:2f0e1e23c242 286 #define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 287 #define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 288 #define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */
glebiuskv 0:2f0e1e23c242 289 #define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */
glebiuskv 0:2f0e1e23c242 290 #define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */
glebiuskv 0:2f0e1e23c242 291 #define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 292 #define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 293 #define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */
glebiuskv 0:2f0e1e23c242 294 #define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */
glebiuskv 0:2f0e1e23c242 295 #define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */
glebiuskv 0:2f0e1e23c242 296 #define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 297 #define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 298 #define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */
glebiuskv 0:2f0e1e23c242 299 #define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */
glebiuskv 0:2f0e1e23c242 300 #define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */
glebiuskv 0:2f0e1e23c242 301 #define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 302 #define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 303 #define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */
glebiuskv 0:2f0e1e23c242 304 #define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */
glebiuskv 0:2f0e1e23c242 305 #define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 306 #define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 307 #define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */
glebiuskv 0:2f0e1e23c242 308 #define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */
glebiuskv 0:2f0e1e23c242 309 #define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */
glebiuskv 0:2f0e1e23c242 310 #define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 311 #define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */
glebiuskv 0:2f0e1e23c242 312
glebiuskv 0:2f0e1e23c242 313 /* Bit fields for ETM ETMTEEVR */
glebiuskv 0:2f0e1e23c242 314 #define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */
glebiuskv 0:2f0e1e23c242 315 #define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */
glebiuskv 0:2f0e1e23c242 316 #define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
glebiuskv 0:2f0e1e23c242 317 #define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
glebiuskv 0:2f0e1e23c242 318 #define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
glebiuskv 0:2f0e1e23c242 319 #define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
glebiuskv 0:2f0e1e23c242 320 #define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
glebiuskv 0:2f0e1e23c242 321 #define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
glebiuskv 0:2f0e1e23c242 322 #define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
glebiuskv 0:2f0e1e23c242 323 #define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
glebiuskv 0:2f0e1e23c242 324 #define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */
glebiuskv 0:2f0e1e23c242 325 #define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */
glebiuskv 0:2f0e1e23c242 326 #define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
glebiuskv 0:2f0e1e23c242 327 #define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
glebiuskv 0:2f0e1e23c242 328
glebiuskv 0:2f0e1e23c242 329 /* Bit fields for ETM ETMTECR1 */
glebiuskv 0:2f0e1e23c242 330 #define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 331 #define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 332 #define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */
glebiuskv 0:2f0e1e23c242 333 #define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */
glebiuskv 0:2f0e1e23c242 334 #define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 335 #define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 336 #define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */
glebiuskv 0:2f0e1e23c242 337 #define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */
glebiuskv 0:2f0e1e23c242 338 #define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 339 #define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 340 #define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */
glebiuskv 0:2f0e1e23c242 341 #define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */
glebiuskv 0:2f0e1e23c242 342 #define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */
glebiuskv 0:2f0e1e23c242 343 #define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 344 #define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 345 #define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 346 #define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 347 #define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 348 #define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 349 #define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */
glebiuskv 0:2f0e1e23c242 350 #define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */
glebiuskv 0:2f0e1e23c242 351 #define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */
glebiuskv 0:2f0e1e23c242 352 #define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 353 #define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 354 #define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 355 #define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 356 #define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 357 #define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */
glebiuskv 0:2f0e1e23c242 358
glebiuskv 0:2f0e1e23c242 359 /* Bit fields for ETM ETMFFLR */
glebiuskv 0:2f0e1e23c242 360 #define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */
glebiuskv 0:2f0e1e23c242 361 #define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */
glebiuskv 0:2f0e1e23c242 362 #define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */
glebiuskv 0:2f0e1e23c242 363 #define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */
glebiuskv 0:2f0e1e23c242 364 #define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */
glebiuskv 0:2f0e1e23c242 365 #define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */
glebiuskv 0:2f0e1e23c242 366
glebiuskv 0:2f0e1e23c242 367 /* Bit fields for ETM ETMCNTRLDVR1 */
glebiuskv 0:2f0e1e23c242 368 #define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */
glebiuskv 0:2f0e1e23c242 369 #define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */
glebiuskv 0:2f0e1e23c242 370 #define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */
glebiuskv 0:2f0e1e23c242 371 #define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */
glebiuskv 0:2f0e1e23c242 372 #define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */
glebiuskv 0:2f0e1e23c242 373 #define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */
glebiuskv 0:2f0e1e23c242 374
glebiuskv 0:2f0e1e23c242 375 /* Bit fields for ETM ETMSYNCFR */
glebiuskv 0:2f0e1e23c242 376 #define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */
glebiuskv 0:2f0e1e23c242 377 #define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */
glebiuskv 0:2f0e1e23c242 378 #define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */
glebiuskv 0:2f0e1e23c242 379 #define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */
glebiuskv 0:2f0e1e23c242 380 #define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */
glebiuskv 0:2f0e1e23c242 381 #define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */
glebiuskv 0:2f0e1e23c242 382
glebiuskv 0:2f0e1e23c242 383 /* Bit fields for ETM ETMIDR */
glebiuskv 0:2f0e1e23c242 384 #define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 385 #define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 386 #define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */
glebiuskv 0:2f0e1e23c242 387 #define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */
glebiuskv 0:2f0e1e23c242 388 #define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 389 #define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 390 #define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */
glebiuskv 0:2f0e1e23c242 391 #define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */
glebiuskv 0:2f0e1e23c242 392 #define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 393 #define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 394 #define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */
glebiuskv 0:2f0e1e23c242 395 #define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */
glebiuskv 0:2f0e1e23c242 396 #define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 397 #define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 398 #define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */
glebiuskv 0:2f0e1e23c242 399 #define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */
glebiuskv 0:2f0e1e23c242 400 #define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 401 #define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 402 #define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */
glebiuskv 0:2f0e1e23c242 403 #define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */
glebiuskv 0:2f0e1e23c242 404 #define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */
glebiuskv 0:2f0e1e23c242 405 #define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 406 #define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 407 #define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */
glebiuskv 0:2f0e1e23c242 408 #define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */
glebiuskv 0:2f0e1e23c242 409 #define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */
glebiuskv 0:2f0e1e23c242 410 #define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 411 #define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 412 #define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */
glebiuskv 0:2f0e1e23c242 413 #define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */
glebiuskv 0:2f0e1e23c242 414 #define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */
glebiuskv 0:2f0e1e23c242 415 #define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 416 #define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 417 #define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */
glebiuskv 0:2f0e1e23c242 418 #define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */
glebiuskv 0:2f0e1e23c242 419 #define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */
glebiuskv 0:2f0e1e23c242 420 #define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 421 #define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 422 #define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */
glebiuskv 0:2f0e1e23c242 423 #define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */
glebiuskv 0:2f0e1e23c242 424 #define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 425 #define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */
glebiuskv 0:2f0e1e23c242 426
glebiuskv 0:2f0e1e23c242 427 /* Bit fields for ETM ETMCCER */
glebiuskv 0:2f0e1e23c242 428 #define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 429 #define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 430 #define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */
glebiuskv 0:2f0e1e23c242 431 #define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */
glebiuskv 0:2f0e1e23c242 432 #define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 433 #define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 434 #define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */
glebiuskv 0:2f0e1e23c242 435 #define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */
glebiuskv 0:2f0e1e23c242 436 #define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 437 #define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 438 #define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */
glebiuskv 0:2f0e1e23c242 439 #define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */
glebiuskv 0:2f0e1e23c242 440 #define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */
glebiuskv 0:2f0e1e23c242 441 #define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 442 #define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 443 #define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */
glebiuskv 0:2f0e1e23c242 444 #define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */
glebiuskv 0:2f0e1e23c242 445 #define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */
glebiuskv 0:2f0e1e23c242 446 #define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 447 #define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 448 #define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */
glebiuskv 0:2f0e1e23c242 449 #define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */
glebiuskv 0:2f0e1e23c242 450 #define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 451 #define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 452 #define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */
glebiuskv 0:2f0e1e23c242 453 #define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */
glebiuskv 0:2f0e1e23c242 454 #define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 455 #define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 456 #define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */
glebiuskv 0:2f0e1e23c242 457 #define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */
glebiuskv 0:2f0e1e23c242 458 #define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */
glebiuskv 0:2f0e1e23c242 459 #define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 460 #define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 461 #define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */
glebiuskv 0:2f0e1e23c242 462 #define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */
glebiuskv 0:2f0e1e23c242 463 #define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */
glebiuskv 0:2f0e1e23c242 464 #define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 465 #define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 466 #define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */
glebiuskv 0:2f0e1e23c242 467 #define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */
glebiuskv 0:2f0e1e23c242 468 #define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */
glebiuskv 0:2f0e1e23c242 469 #define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 470 #define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 471 #define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */
glebiuskv 0:2f0e1e23c242 472 #define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */
glebiuskv 0:2f0e1e23c242 473 #define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */
glebiuskv 0:2f0e1e23c242 474 #define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 475 #define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 476 #define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */
glebiuskv 0:2f0e1e23c242 477 #define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */
glebiuskv 0:2f0e1e23c242 478 #define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */
glebiuskv 0:2f0e1e23c242 479 #define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 480 #define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 481 #define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */
glebiuskv 0:2f0e1e23c242 482 #define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */
glebiuskv 0:2f0e1e23c242 483 #define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */
glebiuskv 0:2f0e1e23c242 484 #define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 485 #define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */
glebiuskv 0:2f0e1e23c242 486
glebiuskv 0:2f0e1e23c242 487 /* Bit fields for ETM ETMTESSEICR */
glebiuskv 0:2f0e1e23c242 488 #define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */
glebiuskv 0:2f0e1e23c242 489 #define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */
glebiuskv 0:2f0e1e23c242 490 #define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */
glebiuskv 0:2f0e1e23c242 491 #define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */
glebiuskv 0:2f0e1e23c242 492 #define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
glebiuskv 0:2f0e1e23c242 493 #define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
glebiuskv 0:2f0e1e23c242 494 #define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */
glebiuskv 0:2f0e1e23c242 495 #define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */
glebiuskv 0:2f0e1e23c242 496 #define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
glebiuskv 0:2f0e1e23c242 497 #define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
glebiuskv 0:2f0e1e23c242 498
glebiuskv 0:2f0e1e23c242 499 /* Bit fields for ETM ETMTSEVR */
glebiuskv 0:2f0e1e23c242 500 #define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */
glebiuskv 0:2f0e1e23c242 501 #define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */
glebiuskv 0:2f0e1e23c242 502 #define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */
glebiuskv 0:2f0e1e23c242 503 #define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */
glebiuskv 0:2f0e1e23c242 504 #define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
glebiuskv 0:2f0e1e23c242 505 #define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
glebiuskv 0:2f0e1e23c242 506 #define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */
glebiuskv 0:2f0e1e23c242 507 #define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */
glebiuskv 0:2f0e1e23c242 508 #define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
glebiuskv 0:2f0e1e23c242 509 #define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
glebiuskv 0:2f0e1e23c242 510 #define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */
glebiuskv 0:2f0e1e23c242 511 #define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */
glebiuskv 0:2f0e1e23c242 512 #define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
glebiuskv 0:2f0e1e23c242 513 #define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
glebiuskv 0:2f0e1e23c242 514
glebiuskv 0:2f0e1e23c242 515 /* Bit fields for ETM ETMTRACEIDR */
glebiuskv 0:2f0e1e23c242 516 #define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */
glebiuskv 0:2f0e1e23c242 517 #define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */
glebiuskv 0:2f0e1e23c242 518 #define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */
glebiuskv 0:2f0e1e23c242 519 #define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */
glebiuskv 0:2f0e1e23c242 520 #define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */
glebiuskv 0:2f0e1e23c242 521 #define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */
glebiuskv 0:2f0e1e23c242 522
glebiuskv 0:2f0e1e23c242 523 /* Bit fields for ETM ETMIDR2 */
glebiuskv 0:2f0e1e23c242 524 #define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 525 #define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 526 #define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */
glebiuskv 0:2f0e1e23c242 527 #define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */
glebiuskv 0:2f0e1e23c242 528 #define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */
glebiuskv 0:2f0e1e23c242 529 #define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 530 #define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 531 #define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 532 #define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 533 #define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 534 #define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 535 #define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */
glebiuskv 0:2f0e1e23c242 536 #define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */
glebiuskv 0:2f0e1e23c242 537 #define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */
glebiuskv 0:2f0e1e23c242 538 #define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 539 #define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 540 #define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 541 #define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 542 #define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 543 #define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */
glebiuskv 0:2f0e1e23c242 544
glebiuskv 0:2f0e1e23c242 545 /* Bit fields for ETM ETMPDSR */
glebiuskv 0:2f0e1e23c242 546 #define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */
glebiuskv 0:2f0e1e23c242 547 #define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */
glebiuskv 0:2f0e1e23c242 548 #define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */
glebiuskv 0:2f0e1e23c242 549 #define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */
glebiuskv 0:2f0e1e23c242 550 #define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */
glebiuskv 0:2f0e1e23c242 551 #define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */
glebiuskv 0:2f0e1e23c242 552 #define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */
glebiuskv 0:2f0e1e23c242 553
glebiuskv 0:2f0e1e23c242 554 /* Bit fields for ETM ETMISCIN */
glebiuskv 0:2f0e1e23c242 555 #define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */
glebiuskv 0:2f0e1e23c242 556 #define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */
glebiuskv 0:2f0e1e23c242 557 #define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */
glebiuskv 0:2f0e1e23c242 558 #define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */
glebiuskv 0:2f0e1e23c242 559 #define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
glebiuskv 0:2f0e1e23c242 560 #define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
glebiuskv 0:2f0e1e23c242 561 #define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */
glebiuskv 0:2f0e1e23c242 562 #define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */
glebiuskv 0:2f0e1e23c242 563 #define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */
glebiuskv 0:2f0e1e23c242 564 #define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
glebiuskv 0:2f0e1e23c242 565 #define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
glebiuskv 0:2f0e1e23c242 566
glebiuskv 0:2f0e1e23c242 567 /* Bit fields for ETM ITTRIGOUT */
glebiuskv 0:2f0e1e23c242 568 #define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */
glebiuskv 0:2f0e1e23c242 569 #define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */
glebiuskv 0:2f0e1e23c242 570 #define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */
glebiuskv 0:2f0e1e23c242 571 #define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */
glebiuskv 0:2f0e1e23c242 572 #define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */
glebiuskv 0:2f0e1e23c242 573 #define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */
glebiuskv 0:2f0e1e23c242 574 #define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */
glebiuskv 0:2f0e1e23c242 575
glebiuskv 0:2f0e1e23c242 576 /* Bit fields for ETM ETMITATBCTR2 */
glebiuskv 0:2f0e1e23c242 577 #define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */
glebiuskv 0:2f0e1e23c242 578 #define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */
glebiuskv 0:2f0e1e23c242 579 #define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */
glebiuskv 0:2f0e1e23c242 580 #define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */
glebiuskv 0:2f0e1e23c242 581 #define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */
glebiuskv 0:2f0e1e23c242 582 #define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */
glebiuskv 0:2f0e1e23c242 583 #define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */
glebiuskv 0:2f0e1e23c242 584
glebiuskv 0:2f0e1e23c242 585 /* Bit fields for ETM ETMITATBCTR0 */
glebiuskv 0:2f0e1e23c242 586 #define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */
glebiuskv 0:2f0e1e23c242 587 #define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */
glebiuskv 0:2f0e1e23c242 588 #define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */
glebiuskv 0:2f0e1e23c242 589 #define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */
glebiuskv 0:2f0e1e23c242 590 #define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */
glebiuskv 0:2f0e1e23c242 591 #define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */
glebiuskv 0:2f0e1e23c242 592 #define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */
glebiuskv 0:2f0e1e23c242 593
glebiuskv 0:2f0e1e23c242 594 /* Bit fields for ETM ETMITCTRL */
glebiuskv 0:2f0e1e23c242 595 #define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */
glebiuskv 0:2f0e1e23c242 596 #define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */
glebiuskv 0:2f0e1e23c242 597 #define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */
glebiuskv 0:2f0e1e23c242 598 #define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */
glebiuskv 0:2f0e1e23c242 599 #define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */
glebiuskv 0:2f0e1e23c242 600 #define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */
glebiuskv 0:2f0e1e23c242 601 #define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */
glebiuskv 0:2f0e1e23c242 602
glebiuskv 0:2f0e1e23c242 603 /* Bit fields for ETM ETMCLAIMSET */
glebiuskv 0:2f0e1e23c242 604 #define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */
glebiuskv 0:2f0e1e23c242 605 #define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */
glebiuskv 0:2f0e1e23c242 606 #define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */
glebiuskv 0:2f0e1e23c242 607 #define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */
glebiuskv 0:2f0e1e23c242 608 #define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */
glebiuskv 0:2f0e1e23c242 609 #define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */
glebiuskv 0:2f0e1e23c242 610
glebiuskv 0:2f0e1e23c242 611 /* Bit fields for ETM ETMCLAIMCLR */
glebiuskv 0:2f0e1e23c242 612 #define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */
glebiuskv 0:2f0e1e23c242 613 #define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */
glebiuskv 0:2f0e1e23c242 614 #define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */
glebiuskv 0:2f0e1e23c242 615 #define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */
glebiuskv 0:2f0e1e23c242 616 #define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */
glebiuskv 0:2f0e1e23c242 617 #define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */
glebiuskv 0:2f0e1e23c242 618 #define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */
glebiuskv 0:2f0e1e23c242 619
glebiuskv 0:2f0e1e23c242 620 /* Bit fields for ETM ETMLAR */
glebiuskv 0:2f0e1e23c242 621 #define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */
glebiuskv 0:2f0e1e23c242 622 #define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */
glebiuskv 0:2f0e1e23c242 623 #define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */
glebiuskv 0:2f0e1e23c242 624 #define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */
glebiuskv 0:2f0e1e23c242 625 #define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */
glebiuskv 0:2f0e1e23c242 626 #define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */
glebiuskv 0:2f0e1e23c242 627 #define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */
glebiuskv 0:2f0e1e23c242 628
glebiuskv 0:2f0e1e23c242 629 /* Bit fields for ETM ETMLSR */
glebiuskv 0:2f0e1e23c242 630 #define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */
glebiuskv 0:2f0e1e23c242 631 #define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */
glebiuskv 0:2f0e1e23c242 632 #define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */
glebiuskv 0:2f0e1e23c242 633 #define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */
glebiuskv 0:2f0e1e23c242 634 #define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */
glebiuskv 0:2f0e1e23c242 635 #define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
glebiuskv 0:2f0e1e23c242 636 #define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */
glebiuskv 0:2f0e1e23c242 637 #define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */
glebiuskv 0:2f0e1e23c242 638 #define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */
glebiuskv 0:2f0e1e23c242 639 #define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */
glebiuskv 0:2f0e1e23c242 640 #define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
glebiuskv 0:2f0e1e23c242 641 #define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */
glebiuskv 0:2f0e1e23c242 642
glebiuskv 0:2f0e1e23c242 643 /* Bit fields for ETM ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 644 #define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 645 #define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 646 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */
glebiuskv 0:2f0e1e23c242 647 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */
glebiuskv 0:2f0e1e23c242 648 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 649 #define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 650 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */
glebiuskv 0:2f0e1e23c242 651 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */
glebiuskv 0:2f0e1e23c242 652 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 653 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 654 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 655 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 656 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 657 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 658 #define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */
glebiuskv 0:2f0e1e23c242 659 #define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */
glebiuskv 0:2f0e1e23c242 660 #define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 661 #define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 662 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */
glebiuskv 0:2f0e1e23c242 663 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */
glebiuskv 0:2f0e1e23c242 664 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 665 #define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
glebiuskv 0:2f0e1e23c242 666
glebiuskv 0:2f0e1e23c242 667 /* Bit fields for ETM ETMDEVTYPE */
glebiuskv 0:2f0e1e23c242 668 #define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */
glebiuskv 0:2f0e1e23c242 669 #define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */
glebiuskv 0:2f0e1e23c242 670 #define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */
glebiuskv 0:2f0e1e23c242 671 #define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */
glebiuskv 0:2f0e1e23c242 672 #define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
glebiuskv 0:2f0e1e23c242 673 #define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
glebiuskv 0:2f0e1e23c242 674 #define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */
glebiuskv 0:2f0e1e23c242 675 #define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */
glebiuskv 0:2f0e1e23c242 676 #define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
glebiuskv 0:2f0e1e23c242 677 #define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
glebiuskv 0:2f0e1e23c242 678
glebiuskv 0:2f0e1e23c242 679 /* Bit fields for ETM ETMPIDR4 */
glebiuskv 0:2f0e1e23c242 680 #define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */
glebiuskv 0:2f0e1e23c242 681 #define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */
glebiuskv 0:2f0e1e23c242 682 #define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */
glebiuskv 0:2f0e1e23c242 683 #define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */
glebiuskv 0:2f0e1e23c242 684 #define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
glebiuskv 0:2f0e1e23c242 685 #define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
glebiuskv 0:2f0e1e23c242 686 #define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */
glebiuskv 0:2f0e1e23c242 687 #define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */
glebiuskv 0:2f0e1e23c242 688 #define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
glebiuskv 0:2f0e1e23c242 689 #define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
glebiuskv 0:2f0e1e23c242 690
glebiuskv 0:2f0e1e23c242 691 /* Bit fields for ETM ETMPIDR5 */
glebiuskv 0:2f0e1e23c242 692 #define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */
glebiuskv 0:2f0e1e23c242 693 #define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */
glebiuskv 0:2f0e1e23c242 694
glebiuskv 0:2f0e1e23c242 695 /* Bit fields for ETM ETMPIDR6 */
glebiuskv 0:2f0e1e23c242 696 #define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */
glebiuskv 0:2f0e1e23c242 697 #define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */
glebiuskv 0:2f0e1e23c242 698
glebiuskv 0:2f0e1e23c242 699 /* Bit fields for ETM ETMPIDR7 */
glebiuskv 0:2f0e1e23c242 700 #define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */
glebiuskv 0:2f0e1e23c242 701 #define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */
glebiuskv 0:2f0e1e23c242 702
glebiuskv 0:2f0e1e23c242 703 /* Bit fields for ETM ETMPIDR0 */
glebiuskv 0:2f0e1e23c242 704 #define _ETM_ETMPIDR0_RESETVALUE 0x00000024UL /**< Default value for ETM_ETMPIDR0 */
glebiuskv 0:2f0e1e23c242 705 #define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */
glebiuskv 0:2f0e1e23c242 706 #define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
glebiuskv 0:2f0e1e23c242 707 #define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */
glebiuskv 0:2f0e1e23c242 708 #define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000024UL /**< Mode DEFAULT for ETM_ETMPIDR0 */
glebiuskv 0:2f0e1e23c242 709 #define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */
glebiuskv 0:2f0e1e23c242 710
glebiuskv 0:2f0e1e23c242 711 /* Bit fields for ETM ETMPIDR1 */
glebiuskv 0:2f0e1e23c242 712 #define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */
glebiuskv 0:2f0e1e23c242 713 #define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */
glebiuskv 0:2f0e1e23c242 714 #define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
glebiuskv 0:2f0e1e23c242 715 #define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */
glebiuskv 0:2f0e1e23c242 716 #define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */
glebiuskv 0:2f0e1e23c242 717 #define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
glebiuskv 0:2f0e1e23c242 718 #define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */
glebiuskv 0:2f0e1e23c242 719 #define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */
glebiuskv 0:2f0e1e23c242 720 #define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */
glebiuskv 0:2f0e1e23c242 721 #define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
glebiuskv 0:2f0e1e23c242 722
glebiuskv 0:2f0e1e23c242 723 /* Bit fields for ETM ETMPIDR2 */
glebiuskv 0:2f0e1e23c242 724 #define _ETM_ETMPIDR2_RESETVALUE 0x0000003BUL /**< Default value for ETM_ETMPIDR2 */
glebiuskv 0:2f0e1e23c242 725 #define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */
glebiuskv 0:2f0e1e23c242 726 #define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */
glebiuskv 0:2f0e1e23c242 727 #define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */
glebiuskv 0:2f0e1e23c242 728 #define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
glebiuskv 0:2f0e1e23c242 729 #define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
glebiuskv 0:2f0e1e23c242 730 #define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */
glebiuskv 0:2f0e1e23c242 731 #define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */
glebiuskv 0:2f0e1e23c242 732 #define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */
glebiuskv 0:2f0e1e23c242 733 #define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
glebiuskv 0:2f0e1e23c242 734 #define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
glebiuskv 0:2f0e1e23c242 735 #define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */
glebiuskv 0:2f0e1e23c242 736 #define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */
glebiuskv 0:2f0e1e23c242 737 #define _ETM_ETMPIDR2_REV_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
glebiuskv 0:2f0e1e23c242 738 #define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
glebiuskv 0:2f0e1e23c242 739
glebiuskv 0:2f0e1e23c242 740 /* Bit fields for ETM ETMPIDR3 */
glebiuskv 0:2f0e1e23c242 741 #define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */
glebiuskv 0:2f0e1e23c242 742 #define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */
glebiuskv 0:2f0e1e23c242 743 #define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */
glebiuskv 0:2f0e1e23c242 744 #define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */
glebiuskv 0:2f0e1e23c242 745 #define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
glebiuskv 0:2f0e1e23c242 746 #define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
glebiuskv 0:2f0e1e23c242 747 #define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */
glebiuskv 0:2f0e1e23c242 748 #define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */
glebiuskv 0:2f0e1e23c242 749 #define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
glebiuskv 0:2f0e1e23c242 750 #define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
glebiuskv 0:2f0e1e23c242 751
glebiuskv 0:2f0e1e23c242 752 /* Bit fields for ETM ETMCIDR0 */
glebiuskv 0:2f0e1e23c242 753 #define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */
glebiuskv 0:2f0e1e23c242 754 #define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */
glebiuskv 0:2f0e1e23c242 755 #define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
glebiuskv 0:2f0e1e23c242 756 #define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
glebiuskv 0:2f0e1e23c242 757 #define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */
glebiuskv 0:2f0e1e23c242 758 #define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */
glebiuskv 0:2f0e1e23c242 759
glebiuskv 0:2f0e1e23c242 760 /* Bit fields for ETM ETMCIDR1 */
glebiuskv 0:2f0e1e23c242 761 #define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */
glebiuskv 0:2f0e1e23c242 762 #define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */
glebiuskv 0:2f0e1e23c242 763 #define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
glebiuskv 0:2f0e1e23c242 764 #define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
glebiuskv 0:2f0e1e23c242 765 #define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */
glebiuskv 0:2f0e1e23c242 766 #define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */
glebiuskv 0:2f0e1e23c242 767
glebiuskv 0:2f0e1e23c242 768 /* Bit fields for ETM ETMCIDR2 */
glebiuskv 0:2f0e1e23c242 769 #define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */
glebiuskv 0:2f0e1e23c242 770 #define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */
glebiuskv 0:2f0e1e23c242 771 #define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
glebiuskv 0:2f0e1e23c242 772 #define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
glebiuskv 0:2f0e1e23c242 773 #define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */
glebiuskv 0:2f0e1e23c242 774 #define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */
glebiuskv 0:2f0e1e23c242 775
glebiuskv 0:2f0e1e23c242 776 /* Bit fields for ETM ETMCIDR3 */
glebiuskv 0:2f0e1e23c242 777 #define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */
glebiuskv 0:2f0e1e23c242 778 #define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */
glebiuskv 0:2f0e1e23c242 779 #define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
glebiuskv 0:2f0e1e23c242 780 #define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
glebiuskv 0:2f0e1e23c242 781 #define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */
glebiuskv 0:2f0e1e23c242 782 #define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
glebiuskv 0:2f0e1e23c242 783
glebiuskv 0:2f0e1e23c242 784 /** @} End of group EFM32GG_ETM */
glebiuskv 0:2f0e1e23c242 785 /** @} End of group Parts */
glebiuskv 0:2f0e1e23c242 786