mbed_itm_api.c

00001 /* mbed Microcontroller Library
00002  * Copyright (c) 2017 ARM Limited
00003  *
00004  * Licensed under the Apache License, Version 2.0 (the "License");
00005  * you may not use this file except in compliance with the License.
00006  * You may obtain a copy of the License at
00007  *
00008  *     http://www.apache.org/licenses/LICENSE-2.0
00009  *
00010  * Unless required by applicable law or agreed to in writing, software
00011  * distributed under the License is distributed on an "AS IS" BASIS,
00012  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00013  * See the License for the specific language governing permissions and
00014  * limitations under the License.
00015  */
00016 
00017 #if defined(DEVICE_ITM)
00018 
00019 #include "hal/itm_api.h"
00020 #include "cmsis.h"
00021 
00022 #include <stdbool.h>
00023 
00024 #define ITM_ENABLE_WRITE 0xC5ACCE55 
00025 
00026 #define SWO_NRZ 0x02
00027 #define SWO_STIMULUS_PORT 0x01
00028 
00029 void mbed_itm_init(void)
00030 {
00031     static bool do_init = true;
00032 
00033     if (do_init) {
00034         do_init = false;
00035 
00036         itm_init();
00037 
00038         /* Enable write access to ITM registers. */
00039         ITM->LAR  = ITM_ENABLE_WRITE;
00040 
00041         /* Trace Port Interface Selected Pin Protocol Register. */
00042         TPI->SPPR = (SWO_NRZ << TPI_SPPR_TXMODE_Pos);
00043 
00044         /* Trace Port Interface Formatter and Flush Control Register */
00045         TPI->FFCR = (1 << TPI_FFCR_TrigIn_Pos);
00046 
00047         /* Data Watchpoint and Trace Control Register */
00048         DWT->CTRL = (1 << DWT_CTRL_CYCTAP_Pos)       |
00049                     (0xF << DWT_CTRL_POSTINIT_Pos)   |
00050                     (0xF << DWT_CTRL_POSTPRESET_Pos) |
00051                     (1 << DWT_CTRL_CYCCNTENA_Pos);
00052 
00053         /* Trace Privilege Register.
00054          * Disable access to trace channel configuration from non-privileged mode.
00055          */
00056         ITM->TPR  = 0x0;
00057 
00058         /* Trace Control Register */
00059         ITM->TCR  = (1 << ITM_TCR_TraceBusID_Pos) | 
00060                     (1 << ITM_TCR_DWTENA_Pos)     | 
00061                     (1 << ITM_TCR_SYNCENA_Pos)    |
00062                     (1 << ITM_TCR_ITMENA_Pos);
00063 
00064         /* Trace Enable Register */
00065         ITM->TER = SWO_STIMULUS_PORT;    
00066     }
00067 }
00068 
00069 uint32_t mbed_itm_send(uint32_t port, uint32_t data)
00070 {
00071     /* Check if ITM and port is enabled */
00072     if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
00073         ((ITM->TER & (1UL << port)     ) != 0UL)   )     /* ITM Port enabled */
00074     {
00075         /* write data to port */
00076         ITM->PORT[port].u32 = data;
00077 
00078         /* Wait until data has been clocked out */
00079         while (ITM->PORT[port].u32 == 0UL) {
00080             __NOP();
00081         }
00082     }
00083 
00084     return data;
00085 }
00086 
00087 #endif // defined(DEVICE_ITM)