Gleb Klochkov / Mbed OS Climatcontroll_Main

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Dependencies:   esp8266-driver

mbed-os/targets/TARGET_STM/sleep.c@0:2f0e1e23c242, 2018-04-13 (annotated)

Committer:
glebiuskv
Date:
Fri Apr 13 08:53:46 2018 +0000
Revision:
0:2f0e1e23c242
initial

Who changed what in which revision?

UserRevisionLine numberNew contents of line
glebiuskv 0:2f0e1e23c242 1 /* mbed Microcontroller Library
glebiuskv 0:2f0e1e23c242 2 *******************************************************************************
glebiuskv 0:2f0e1e23c242 3 * Copyright (c) 2016, STMicroelectronics
glebiuskv 0:2f0e1e23c242 4 * All rights reserved.
glebiuskv 0:2f0e1e23c242 5 *
glebiuskv 0:2f0e1e23c242 6 * Redistribution and use in source and binary forms, with or without
glebiuskv 0:2f0e1e23c242 7 * modification, are permitted provided that the following conditions are met:
glebiuskv 0:2f0e1e23c242 8 *
glebiuskv 0:2f0e1e23c242 9 * 1. Redistributions of source code must retain the above copyright notice,
glebiuskv 0:2f0e1e23c242 10 * this list of conditions and the following disclaimer.
glebiuskv 0:2f0e1e23c242 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
glebiuskv 0:2f0e1e23c242 12 * this list of conditions and the following disclaimer in the documentation
glebiuskv 0:2f0e1e23c242 13 * and/or other materials provided with the distribution.
glebiuskv 0:2f0e1e23c242 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
glebiuskv 0:2f0e1e23c242 15 * may be used to endorse or promote products derived from this software
glebiuskv 0:2f0e1e23c242 16 * without specific prior written permission.
glebiuskv 0:2f0e1e23c242 17 *
glebiuskv 0:2f0e1e23c242 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
glebiuskv 0:2f0e1e23c242 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
glebiuskv 0:2f0e1e23c242 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
glebiuskv 0:2f0e1e23c242 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
glebiuskv 0:2f0e1e23c242 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
glebiuskv 0:2f0e1e23c242 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
glebiuskv 0:2f0e1e23c242 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
glebiuskv 0:2f0e1e23c242 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
glebiuskv 0:2f0e1e23c242 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
glebiuskv 0:2f0e1e23c242 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
glebiuskv 0:2f0e1e23c242 28 *******************************************************************************
glebiuskv 0:2f0e1e23c242 29 */
glebiuskv 0:2f0e1e23c242 30 #if DEVICE_SLEEP
glebiuskv 0:2f0e1e23c242 31
glebiuskv 0:2f0e1e23c242 32 #include "sleep_api.h"
glebiuskv 0:2f0e1e23c242 33 #include "rtc_api_hal.h"
glebiuskv 0:2f0e1e23c242 34
glebiuskv 0:2f0e1e23c242 35 extern void HAL_SuspendTick(void);
glebiuskv 0:2f0e1e23c242 36 extern void HAL_ResumeTick(void);
glebiuskv 0:2f0e1e23c242 37
glebiuskv 0:2f0e1e23c242 38 /* Wait loop - assuming tick is 1 us */
glebiuskv 0:2f0e1e23c242 39 static void wait_loop(uint32_t timeout)
glebiuskv 0:2f0e1e23c242 40 {
glebiuskv 0:2f0e1e23c242 41 uint32_t t1, t2, elapsed = 0;
glebiuskv 0:2f0e1e23c242 42 t1 = us_ticker_read();
glebiuskv 0:2f0e1e23c242 43 do {
glebiuskv 0:2f0e1e23c242 44 t2 = us_ticker_read();
glebiuskv 0:2f0e1e23c242 45 elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t)t2 + 0xFFFFFFFF - t1 + 1);
glebiuskv 0:2f0e1e23c242 46 } while (elapsed < timeout);
glebiuskv 0:2f0e1e23c242 47 return;
glebiuskv 0:2f0e1e23c242 48 }
glebiuskv 0:2f0e1e23c242 49
glebiuskv 0:2f0e1e23c242 50 // On L4 platforms we've seen unstable PLL CLK configuraiton
glebiuskv 0:2f0e1e23c242 51 // when DEEP SLEEP exits just few µs after being entered
glebiuskv 0:2f0e1e23c242 52 // So we need to force MSI usage before setting clocks again
glebiuskv 0:2f0e1e23c242 53 static void ForceClockOutofDeepSleep(void)
glebiuskv 0:2f0e1e23c242 54 {
glebiuskv 0:2f0e1e23c242 55 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
glebiuskv 0:2f0e1e23c242 56 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
glebiuskv 0:2f0e1e23c242 57 uint32_t pFLatency = 0;
glebiuskv 0:2f0e1e23c242 58
glebiuskv 0:2f0e1e23c242 59 /* Enable Power Control clock */
glebiuskv 0:2f0e1e23c242 60 __HAL_RCC_PWR_CLK_ENABLE();
glebiuskv 0:2f0e1e23c242 61
glebiuskv 0:2f0e1e23c242 62 #ifdef PWR_FLAG_VOS
glebiuskv 0:2f0e1e23c242 63 /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
glebiuskv 0:2f0e1e23c242 64 //while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
glebiuskv 0:2f0e1e23c242 65 #endif
glebiuskv 0:2f0e1e23c242 66
glebiuskv 0:2f0e1e23c242 67 /* Get the Oscillators configuration according to the internal RCC registers */
glebiuskv 0:2f0e1e23c242 68 HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
glebiuskv 0:2f0e1e23c242 69
glebiuskv 0:2f0e1e23c242 70 #if (TARGET_STM32L4 || TARGET_STM32L1) /* MSI used for L4 */
glebiuskv 0:2f0e1e23c242 71 /**Initializes the CPU, AHB and APB busses clocks
glebiuskv 0:2f0e1e23c242 72 */
glebiuskv 0:2f0e1e23c242 73 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
glebiuskv 0:2f0e1e23c242 74 RCC_OscInitStruct.MSIState = RCC_MSI_ON;
glebiuskv 0:2f0e1e23c242 75 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
glebiuskv 0:2f0e1e23c242 76 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_4; // Intermediate freq, 1MHz range
glebiuskv 0:2f0e1e23c242 77 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
glebiuskv 0:2f0e1e23c242 78 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
glebiuskv 0:2f0e1e23c242 79 error("clock issue\r\n");
glebiuskv 0:2f0e1e23c242 80 }
glebiuskv 0:2f0e1e23c242 81
glebiuskv 0:2f0e1e23c242 82 /* Get the Clocks configuration according to the internal RCC registers */
glebiuskv 0:2f0e1e23c242 83 HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency);
glebiuskv 0:2f0e1e23c242 84
glebiuskv 0:2f0e1e23c242 85 // Select HSI ss system clock source as a first step
glebiuskv 0:2f0e1e23c242 86 #ifdef RCC_CLOCKTYPE_PCLK2
glebiuskv 0:2f0e1e23c242 87 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
glebiuskv 0:2f0e1e23c242 88 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
glebiuskv 0:2f0e1e23c242 89 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
glebiuskv 0:2f0e1e23c242 90 #else
glebiuskv 0:2f0e1e23c242 91 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
glebiuskv 0:2f0e1e23c242 92 | RCC_CLOCKTYPE_PCLK1);
glebiuskv 0:2f0e1e23c242 93 #endif
glebiuskv 0:2f0e1e23c242 94 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
glebiuskv 0:2f0e1e23c242 95 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
glebiuskv 0:2f0e1e23c242 96 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
glebiuskv 0:2f0e1e23c242 97 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) {
glebiuskv 0:2f0e1e23c242 98 error("clock issue\r\n");
glebiuskv 0:2f0e1e23c242 99 }
glebiuskv 0:2f0e1e23c242 100 #else /* HSI used on others */
glebiuskv 0:2f0e1e23c242 101 /**Initializes the CPU, AHB and APB busses clocks
glebiuskv 0:2f0e1e23c242 102 */
glebiuskv 0:2f0e1e23c242 103 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
glebiuskv 0:2f0e1e23c242 104 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
glebiuskv 0:2f0e1e23c242 105 RCC_OscInitStruct.HSICalibrationValue = 16;
glebiuskv 0:2f0e1e23c242 106 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
glebiuskv 0:2f0e1e23c242 107 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
glebiuskv 0:2f0e1e23c242 108 error("clock issue");
glebiuskv 0:2f0e1e23c242 109 }
glebiuskv 0:2f0e1e23c242 110
glebiuskv 0:2f0e1e23c242 111 /* Get the Clocks configuration according to the internal RCC registers */
glebiuskv 0:2f0e1e23c242 112 HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency);
glebiuskv 0:2f0e1e23c242 113
glebiuskv 0:2f0e1e23c242 114 /**Initializes the CPU, AHB and APB busses clocks
glebiuskv 0:2f0e1e23c242 115 */
glebiuskv 0:2f0e1e23c242 116 #ifdef RCC_CLOCKTYPE_PCLK2
glebiuskv 0:2f0e1e23c242 117 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
glebiuskv 0:2f0e1e23c242 118 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2);
glebiuskv 0:2f0e1e23c242 119 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
glebiuskv 0:2f0e1e23c242 120 #else
glebiuskv 0:2f0e1e23c242 121 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
glebiuskv 0:2f0e1e23c242 122 |RCC_CLOCKTYPE_PCLK1);
glebiuskv 0:2f0e1e23c242 123 #endif
glebiuskv 0:2f0e1e23c242 124 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
glebiuskv 0:2f0e1e23c242 125 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
glebiuskv 0:2f0e1e23c242 126 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
glebiuskv 0:2f0e1e23c242 127 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) {
glebiuskv 0:2f0e1e23c242 128 error("clock issue");
glebiuskv 0:2f0e1e23c242 129 }
glebiuskv 0:2f0e1e23c242 130 #endif // TARGET_STM32L4
glebiuskv 0:2f0e1e23c242 131 }
glebiuskv 0:2f0e1e23c242 132
glebiuskv 0:2f0e1e23c242 133 void hal_sleep(void)
glebiuskv 0:2f0e1e23c242 134 {
glebiuskv 0:2f0e1e23c242 135 // Disable IRQs
glebiuskv 0:2f0e1e23c242 136 core_util_critical_section_enter();
glebiuskv 0:2f0e1e23c242 137
glebiuskv 0:2f0e1e23c242 138 // Stop HAL tick to avoid to exit sleep in 1ms
glebiuskv 0:2f0e1e23c242 139 HAL_SuspendTick();
glebiuskv 0:2f0e1e23c242 140 // Request to enter SLEEP mode
glebiuskv 0:2f0e1e23c242 141 HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
glebiuskv 0:2f0e1e23c242 142 // Restart HAL tick
glebiuskv 0:2f0e1e23c242 143 HAL_ResumeTick();
glebiuskv 0:2f0e1e23c242 144
glebiuskv 0:2f0e1e23c242 145 // Enable IRQs
glebiuskv 0:2f0e1e23c242 146 core_util_critical_section_exit();
glebiuskv 0:2f0e1e23c242 147 }
glebiuskv 0:2f0e1e23c242 148
glebiuskv 0:2f0e1e23c242 149 void hal_deepsleep(void)
glebiuskv 0:2f0e1e23c242 150 {
glebiuskv 0:2f0e1e23c242 151 // Disable IRQs
glebiuskv 0:2f0e1e23c242 152 core_util_critical_section_enter();
glebiuskv 0:2f0e1e23c242 153
glebiuskv 0:2f0e1e23c242 154 // Stop HAL tick
glebiuskv 0:2f0e1e23c242 155 HAL_SuspendTick();
glebiuskv 0:2f0e1e23c242 156 uint32_t EnterTimeUS = us_ticker_read();
glebiuskv 0:2f0e1e23c242 157
glebiuskv 0:2f0e1e23c242 158 // Request to enter STOP mode with regulator in low power mode
glebiuskv 0:2f0e1e23c242 159 #if TARGET_STM32L4
glebiuskv 0:2f0e1e23c242 160 int pwrClockEnabled = __HAL_RCC_PWR_IS_CLK_ENABLED();
glebiuskv 0:2f0e1e23c242 161 int lowPowerModeEnabled = PWR->CR1 & PWR_CR1_LPR;
glebiuskv 0:2f0e1e23c242 162
glebiuskv 0:2f0e1e23c242 163 if (!pwrClockEnabled) {
glebiuskv 0:2f0e1e23c242 164 __HAL_RCC_PWR_CLK_ENABLE();
glebiuskv 0:2f0e1e23c242 165 }
glebiuskv 0:2f0e1e23c242 166 if (lowPowerModeEnabled) {
glebiuskv 0:2f0e1e23c242 167 HAL_PWREx_DisableLowPowerRunMode();
glebiuskv 0:2f0e1e23c242 168 }
glebiuskv 0:2f0e1e23c242 169
glebiuskv 0:2f0e1e23c242 170 HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);
glebiuskv 0:2f0e1e23c242 171
glebiuskv 0:2f0e1e23c242 172 if (lowPowerModeEnabled) {
glebiuskv 0:2f0e1e23c242 173 HAL_PWREx_EnableLowPowerRunMode();
glebiuskv 0:2f0e1e23c242 174 }
glebiuskv 0:2f0e1e23c242 175 if (!pwrClockEnabled) {
glebiuskv 0:2f0e1e23c242 176 __HAL_RCC_PWR_CLK_DISABLE();
glebiuskv 0:2f0e1e23c242 177 }
glebiuskv 0:2f0e1e23c242 178 #else /* TARGET_STM32L4 */
glebiuskv 0:2f0e1e23c242 179 HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
glebiuskv 0:2f0e1e23c242 180 #endif /* TARGET_STM32L4 */
glebiuskv 0:2f0e1e23c242 181 // Verify Clock Out of Deep Sleep
glebiuskv 0:2f0e1e23c242 182 ForceClockOutofDeepSleep();
glebiuskv 0:2f0e1e23c242 183
glebiuskv 0:2f0e1e23c242 184 // Restart HAL tick
glebiuskv 0:2f0e1e23c242 185 HAL_ResumeTick();
glebiuskv 0:2f0e1e23c242 186
glebiuskv 0:2f0e1e23c242 187 // After wake-up from STOP reconfigure the PLL
glebiuskv 0:2f0e1e23c242 188 SetSysClock();
glebiuskv 0:2f0e1e23c242 189
glebiuskv 0:2f0e1e23c242 190 /* Wait for clock to be stabilized.
glebiuskv 0:2f0e1e23c242 191 * TO DO: a better way of doing this, would be to rely on
glebiuskv 0:2f0e1e23c242 192 * HW Flag. At least this ensures proper operation out of
glebiuskv 0:2f0e1e23c242 193 * deep sleep */
glebiuskv 0:2f0e1e23c242 194 wait_loop(500);
glebiuskv 0:2f0e1e23c242 195
glebiuskv 0:2f0e1e23c242 196 TIM_HandleTypeDef TimMasterHandle;
glebiuskv 0:2f0e1e23c242 197 TimMasterHandle.Instance = TIM_MST;
glebiuskv 0:2f0e1e23c242 198 __HAL_TIM_SET_COUNTER(&TimMasterHandle, EnterTimeUS);
glebiuskv 0:2f0e1e23c242 199
glebiuskv 0:2f0e1e23c242 200 #if DEVICE_RTC
glebiuskv 0:2f0e1e23c242 201 /* Wait for RTC RSF bit synchro if RTC is configured */
glebiuskv 0:2f0e1e23c242 202 #if (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7)
glebiuskv 0:2f0e1e23c242 203 if (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) {
glebiuskv 0:2f0e1e23c242 204 #else /* (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7) */
glebiuskv 0:2f0e1e23c242 205 if (__HAL_RCC_GET_RTC_SOURCE()) {
glebiuskv 0:2f0e1e23c242 206 #endif /* (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7) */
glebiuskv 0:2f0e1e23c242 207 rtc_synchronize();
glebiuskv 0:2f0e1e23c242 208 }
glebiuskv 0:2f0e1e23c242 209 #endif
glebiuskv 0:2f0e1e23c242 210 // Enable IRQs
glebiuskv 0:2f0e1e23c242 211 core_util_critical_section_exit();
glebiuskv 0:2f0e1e23c242 212 }
glebiuskv 0:2f0e1e23c242 213
glebiuskv 0:2f0e1e23c242 214 #endif