Gleb Klochkov / Mbed OS Climatcontroll_Main

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Dependencies:   esp8266-driver

mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c@0:2f0e1e23c242, 2018-04-13 (annotated)

Committer:
glebiuskv
Date:
Fri Apr 13 08:53:46 2018 +0000
Revision:
0:2f0e1e23c242
initial

Who changed what in which revision?

UserRevisionLine numberNew contents of line
glebiuskv 0:2f0e1e23c242 1 /**
glebiuskv 0:2f0e1e23c242 2 ******************************************************************************
glebiuskv 0:2f0e1e23c242 3 * @file stm32l4xx_ll_adc.c
glebiuskv 0:2f0e1e23c242 4 * @author MCD Application Team
glebiuskv 0:2f0e1e23c242 5 * @brief ADC LL module driver
glebiuskv 0:2f0e1e23c242 6 ******************************************************************************
glebiuskv 0:2f0e1e23c242 7 * @attention
glebiuskv 0:2f0e1e23c242 8 *
glebiuskv 0:2f0e1e23c242 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
glebiuskv 0:2f0e1e23c242 10 *
glebiuskv 0:2f0e1e23c242 11 * Redistribution and use in source and binary forms, with or without modification,
glebiuskv 0:2f0e1e23c242 12 * are permitted provided that the following conditions are met:
glebiuskv 0:2f0e1e23c242 13 * 1. Redistributions of source code must retain the above copyright notice,
glebiuskv 0:2f0e1e23c242 14 * this list of conditions and the following disclaimer.
glebiuskv 0:2f0e1e23c242 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
glebiuskv 0:2f0e1e23c242 16 * this list of conditions and the following disclaimer in the documentation
glebiuskv 0:2f0e1e23c242 17 * and/or other materials provided with the distribution.
glebiuskv 0:2f0e1e23c242 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
glebiuskv 0:2f0e1e23c242 19 * may be used to endorse or promote products derived from this software
glebiuskv 0:2f0e1e23c242 20 * without specific prior written permission.
glebiuskv 0:2f0e1e23c242 21 *
glebiuskv 0:2f0e1e23c242 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
glebiuskv 0:2f0e1e23c242 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
glebiuskv 0:2f0e1e23c242 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
glebiuskv 0:2f0e1e23c242 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
glebiuskv 0:2f0e1e23c242 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
glebiuskv 0:2f0e1e23c242 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
glebiuskv 0:2f0e1e23c242 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
glebiuskv 0:2f0e1e23c242 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
glebiuskv 0:2f0e1e23c242 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
glebiuskv 0:2f0e1e23c242 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
glebiuskv 0:2f0e1e23c242 32 *
glebiuskv 0:2f0e1e23c242 33 ******************************************************************************
glebiuskv 0:2f0e1e23c242 34 */
glebiuskv 0:2f0e1e23c242 35 #if defined(USE_FULL_LL_DRIVER)
glebiuskv 0:2f0e1e23c242 36
glebiuskv 0:2f0e1e23c242 37 /* Includes ------------------------------------------------------------------*/
glebiuskv 0:2f0e1e23c242 38 #include "stm32l4xx_ll_adc.h"
glebiuskv 0:2f0e1e23c242 39 #include "stm32l4xx_ll_bus.h"
glebiuskv 0:2f0e1e23c242 40
glebiuskv 0:2f0e1e23c242 41 #ifdef USE_FULL_ASSERT
glebiuskv 0:2f0e1e23c242 42 #include "stm32_assert.h"
glebiuskv 0:2f0e1e23c242 43 #else
glebiuskv 0:2f0e1e23c242 44 #define assert_param(expr) ((void)0U)
glebiuskv 0:2f0e1e23c242 45 #endif
glebiuskv 0:2f0e1e23c242 46
glebiuskv 0:2f0e1e23c242 47 /** @addtogroup STM32L4xx_LL_Driver
glebiuskv 0:2f0e1e23c242 48 * @{
glebiuskv 0:2f0e1e23c242 49 */
glebiuskv 0:2f0e1e23c242 50
glebiuskv 0:2f0e1e23c242 51 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
glebiuskv 0:2f0e1e23c242 52
glebiuskv 0:2f0e1e23c242 53 /** @addtogroup ADC_LL ADC
glebiuskv 0:2f0e1e23c242 54 * @{
glebiuskv 0:2f0e1e23c242 55 */
glebiuskv 0:2f0e1e23c242 56
glebiuskv 0:2f0e1e23c242 57 /* Private types -------------------------------------------------------------*/
glebiuskv 0:2f0e1e23c242 58 /* Private variables ---------------------------------------------------------*/
glebiuskv 0:2f0e1e23c242 59 /* Private constants ---------------------------------------------------------*/
glebiuskv 0:2f0e1e23c242 60 /** @addtogroup ADC_LL_Private_Constants
glebiuskv 0:2f0e1e23c242 61 * @{
glebiuskv 0:2f0e1e23c242 62 */
glebiuskv 0:2f0e1e23c242 63
glebiuskv 0:2f0e1e23c242 64 /* Definitions of ADC hardware constraints delays */
glebiuskv 0:2f0e1e23c242 65 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
glebiuskv 0:2f0e1e23c242 66 /* not timeout values: */
glebiuskv 0:2f0e1e23c242 67 /* Timeout values for ADC operations are dependent to device clock */
glebiuskv 0:2f0e1e23c242 68 /* configuration (system clock versus ADC clock), */
glebiuskv 0:2f0e1e23c242 69 /* and therefore must be defined in user application. */
glebiuskv 0:2f0e1e23c242 70 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
glebiuskv 0:2f0e1e23c242 71 /* values definition. */
glebiuskv 0:2f0e1e23c242 72 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
glebiuskv 0:2f0e1e23c242 73 /* of device clock setting. */
glebiuskv 0:2f0e1e23c242 74 /* In user application, ADC timeout values should be defined with */
glebiuskv 0:2f0e1e23c242 75 /* temporal values, in function of device clock settings. */
glebiuskv 0:2f0e1e23c242 76 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
glebiuskv 0:2f0e1e23c242 77 /* - ADC clock from synchronous clock with AHB prescaler 512, */
glebiuskv 0:2f0e1e23c242 78 /* APB prescaler 16, ADC prescaler 4. */
glebiuskv 0:2f0e1e23c242 79 /* - ADC clock from asynchronous clock (PLLSAI) with prescaler 1, */
glebiuskv 0:2f0e1e23c242 80 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
glebiuskv 0:2f0e1e23c242 81 /* CPU clock frequency max 72MHz, PLLSAI freq min 26MHz: ratio 4. */
glebiuskv 0:2f0e1e23c242 82 /* Unit: CPU cycles. */
glebiuskv 0:2f0e1e23c242 83 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
glebiuskv 0:2f0e1e23c242 84 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
glebiuskv 0:2f0e1e23c242 85 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
glebiuskv 0:2f0e1e23c242 86
glebiuskv 0:2f0e1e23c242 87 /**
glebiuskv 0:2f0e1e23c242 88 * @}
glebiuskv 0:2f0e1e23c242 89 */
glebiuskv 0:2f0e1e23c242 90
glebiuskv 0:2f0e1e23c242 91 /* Private macros ------------------------------------------------------------*/
glebiuskv 0:2f0e1e23c242 92
glebiuskv 0:2f0e1e23c242 93 /** @addtogroup ADC_LL_Private_Macros
glebiuskv 0:2f0e1e23c242 94 * @{
glebiuskv 0:2f0e1e23c242 95 */
glebiuskv 0:2f0e1e23c242 96
glebiuskv 0:2f0e1e23c242 97 /* Check of parameters for configuration of ADC hierarchical scope: */
glebiuskv 0:2f0e1e23c242 98 /* common to several ADC instances. */
glebiuskv 0:2f0e1e23c242 99 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
glebiuskv 0:2f0e1e23c242 100 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
glebiuskv 0:2f0e1e23c242 101 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
glebiuskv 0:2f0e1e23c242 102 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
glebiuskv 0:2f0e1e23c242 103 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
glebiuskv 0:2f0e1e23c242 104 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
glebiuskv 0:2f0e1e23c242 105 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
glebiuskv 0:2f0e1e23c242 106 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
glebiuskv 0:2f0e1e23c242 107 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
glebiuskv 0:2f0e1e23c242 108 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
glebiuskv 0:2f0e1e23c242 109 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
glebiuskv 0:2f0e1e23c242 110 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
glebiuskv 0:2f0e1e23c242 111 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
glebiuskv 0:2f0e1e23c242 112 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
glebiuskv 0:2f0e1e23c242 113 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
glebiuskv 0:2f0e1e23c242 114 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
glebiuskv 0:2f0e1e23c242 115 )
glebiuskv 0:2f0e1e23c242 116
glebiuskv 0:2f0e1e23c242 117 /* Check of parameters for configuration of ADC hierarchical scope: */
glebiuskv 0:2f0e1e23c242 118 /* ADC instance. */
glebiuskv 0:2f0e1e23c242 119 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
glebiuskv 0:2f0e1e23c242 120 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
glebiuskv 0:2f0e1e23c242 121 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
glebiuskv 0:2f0e1e23c242 122 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
glebiuskv 0:2f0e1e23c242 123 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
glebiuskv 0:2f0e1e23c242 124 )
glebiuskv 0:2f0e1e23c242 125
glebiuskv 0:2f0e1e23c242 126 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
glebiuskv 0:2f0e1e23c242 127 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
glebiuskv 0:2f0e1e23c242 128 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
glebiuskv 0:2f0e1e23c242 129 )
glebiuskv 0:2f0e1e23c242 130
glebiuskv 0:2f0e1e23c242 131 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
glebiuskv 0:2f0e1e23c242 132 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
glebiuskv 0:2f0e1e23c242 133 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
glebiuskv 0:2f0e1e23c242 134 )
glebiuskv 0:2f0e1e23c242 135
glebiuskv 0:2f0e1e23c242 136 /* Check of parameters for configuration of ADC hierarchical scope: */
glebiuskv 0:2f0e1e23c242 137 /* ADC group regular */
glebiuskv 0:2f0e1e23c242 138 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
glebiuskv 0:2f0e1e23c242 139 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
glebiuskv 0:2f0e1e23c242 140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
glebiuskv 0:2f0e1e23c242 141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
glebiuskv 0:2f0e1e23c242 142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
glebiuskv 0:2f0e1e23c242 143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
glebiuskv 0:2f0e1e23c242 144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
glebiuskv 0:2f0e1e23c242 145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
glebiuskv 0:2f0e1e23c242 146 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
glebiuskv 0:2f0e1e23c242 147 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
glebiuskv 0:2f0e1e23c242 148 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
glebiuskv 0:2f0e1e23c242 149 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
glebiuskv 0:2f0e1e23c242 150 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
glebiuskv 0:2f0e1e23c242 151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
glebiuskv 0:2f0e1e23c242 152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
glebiuskv 0:2f0e1e23c242 153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
glebiuskv 0:2f0e1e23c242 154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
glebiuskv 0:2f0e1e23c242 155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
glebiuskv 0:2f0e1e23c242 156 )
glebiuskv 0:2f0e1e23c242 157
glebiuskv 0:2f0e1e23c242 158 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
glebiuskv 0:2f0e1e23c242 159 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
glebiuskv 0:2f0e1e23c242 160 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
glebiuskv 0:2f0e1e23c242 161 )
glebiuskv 0:2f0e1e23c242 162
glebiuskv 0:2f0e1e23c242 163 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
glebiuskv 0:2f0e1e23c242 164 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
glebiuskv 0:2f0e1e23c242 165 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
glebiuskv 0:2f0e1e23c242 166 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
glebiuskv 0:2f0e1e23c242 167 )
glebiuskv 0:2f0e1e23c242 168
glebiuskv 0:2f0e1e23c242 169 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
glebiuskv 0:2f0e1e23c242 170 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
glebiuskv 0:2f0e1e23c242 171 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
glebiuskv 0:2f0e1e23c242 172 )
glebiuskv 0:2f0e1e23c242 173
glebiuskv 0:2f0e1e23c242 174 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
glebiuskv 0:2f0e1e23c242 175 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
glebiuskv 0:2f0e1e23c242 176 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
glebiuskv 0:2f0e1e23c242 177 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
glebiuskv 0:2f0e1e23c242 178 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
glebiuskv 0:2f0e1e23c242 179 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
glebiuskv 0:2f0e1e23c242 180 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
glebiuskv 0:2f0e1e23c242 181 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
glebiuskv 0:2f0e1e23c242 182 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
glebiuskv 0:2f0e1e23c242 183 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
glebiuskv 0:2f0e1e23c242 184 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
glebiuskv 0:2f0e1e23c242 185 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
glebiuskv 0:2f0e1e23c242 186 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
glebiuskv 0:2f0e1e23c242 187 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
glebiuskv 0:2f0e1e23c242 188 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
glebiuskv 0:2f0e1e23c242 189 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
glebiuskv 0:2f0e1e23c242 190 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
glebiuskv 0:2f0e1e23c242 191 )
glebiuskv 0:2f0e1e23c242 192
glebiuskv 0:2f0e1e23c242 193 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
glebiuskv 0:2f0e1e23c242 194 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
glebiuskv 0:2f0e1e23c242 195 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
glebiuskv 0:2f0e1e23c242 196 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
glebiuskv 0:2f0e1e23c242 197 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
glebiuskv 0:2f0e1e23c242 198 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
glebiuskv 0:2f0e1e23c242 199 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
glebiuskv 0:2f0e1e23c242 200 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
glebiuskv 0:2f0e1e23c242 201 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
glebiuskv 0:2f0e1e23c242 202 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
glebiuskv 0:2f0e1e23c242 203 )
glebiuskv 0:2f0e1e23c242 204
glebiuskv 0:2f0e1e23c242 205 /* Check of parameters for configuration of ADC hierarchical scope: */
glebiuskv 0:2f0e1e23c242 206 /* ADC group injected */
glebiuskv 0:2f0e1e23c242 207 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
glebiuskv 0:2f0e1e23c242 208 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
glebiuskv 0:2f0e1e23c242 209 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
glebiuskv 0:2f0e1e23c242 210 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
glebiuskv 0:2f0e1e23c242 211 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
glebiuskv 0:2f0e1e23c242 212 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
glebiuskv 0:2f0e1e23c242 213 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
glebiuskv 0:2f0e1e23c242 214 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
glebiuskv 0:2f0e1e23c242 215 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
glebiuskv 0:2f0e1e23c242 216 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
glebiuskv 0:2f0e1e23c242 217 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
glebiuskv 0:2f0e1e23c242 218 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
glebiuskv 0:2f0e1e23c242 219 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
glebiuskv 0:2f0e1e23c242 220 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
glebiuskv 0:2f0e1e23c242 221 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
glebiuskv 0:2f0e1e23c242 222 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
glebiuskv 0:2f0e1e23c242 223 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
glebiuskv 0:2f0e1e23c242 224 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
glebiuskv 0:2f0e1e23c242 225 )
glebiuskv 0:2f0e1e23c242 226
glebiuskv 0:2f0e1e23c242 227 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
glebiuskv 0:2f0e1e23c242 228 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
glebiuskv 0:2f0e1e23c242 229 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
glebiuskv 0:2f0e1e23c242 230 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
glebiuskv 0:2f0e1e23c242 231 )
glebiuskv 0:2f0e1e23c242 232
glebiuskv 0:2f0e1e23c242 233 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
glebiuskv 0:2f0e1e23c242 234 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
glebiuskv 0:2f0e1e23c242 235 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
glebiuskv 0:2f0e1e23c242 236 )
glebiuskv 0:2f0e1e23c242 237
glebiuskv 0:2f0e1e23c242 238 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
glebiuskv 0:2f0e1e23c242 239 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
glebiuskv 0:2f0e1e23c242 240 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
glebiuskv 0:2f0e1e23c242 241 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
glebiuskv 0:2f0e1e23c242 242 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
glebiuskv 0:2f0e1e23c242 243 )
glebiuskv 0:2f0e1e23c242 244
glebiuskv 0:2f0e1e23c242 245 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
glebiuskv 0:2f0e1e23c242 246 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
glebiuskv 0:2f0e1e23c242 247 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
glebiuskv 0:2f0e1e23c242 248 )
glebiuskv 0:2f0e1e23c242 249
glebiuskv 0:2f0e1e23c242 250 #if defined(ADC_MULTIMODE_SUPPORT)
glebiuskv 0:2f0e1e23c242 251 /* Check of parameters for configuration of ADC hierarchical scope: */
glebiuskv 0:2f0e1e23c242 252 /* multimode. */
glebiuskv 0:2f0e1e23c242 253 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
glebiuskv 0:2f0e1e23c242 254 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
glebiuskv 0:2f0e1e23c242 255 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
glebiuskv 0:2f0e1e23c242 256 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
glebiuskv 0:2f0e1e23c242 257 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
glebiuskv 0:2f0e1e23c242 258 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
glebiuskv 0:2f0e1e23c242 259 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
glebiuskv 0:2f0e1e23c242 260 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
glebiuskv 0:2f0e1e23c242 261 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
glebiuskv 0:2f0e1e23c242 262 )
glebiuskv 0:2f0e1e23c242 263
glebiuskv 0:2f0e1e23c242 264 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
glebiuskv 0:2f0e1e23c242 265 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
glebiuskv 0:2f0e1e23c242 266 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
glebiuskv 0:2f0e1e23c242 267 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
glebiuskv 0:2f0e1e23c242 268 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
glebiuskv 0:2f0e1e23c242 269 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
glebiuskv 0:2f0e1e23c242 270 )
glebiuskv 0:2f0e1e23c242 271
glebiuskv 0:2f0e1e23c242 272 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
glebiuskv 0:2f0e1e23c242 273 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
glebiuskv 0:2f0e1e23c242 274 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
glebiuskv 0:2f0e1e23c242 275 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
glebiuskv 0:2f0e1e23c242 276 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
glebiuskv 0:2f0e1e23c242 277 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
glebiuskv 0:2f0e1e23c242 278 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
glebiuskv 0:2f0e1e23c242 279 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
glebiuskv 0:2f0e1e23c242 280 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
glebiuskv 0:2f0e1e23c242 281 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
glebiuskv 0:2f0e1e23c242 282 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
glebiuskv 0:2f0e1e23c242 283 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
glebiuskv 0:2f0e1e23c242 284 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
glebiuskv 0:2f0e1e23c242 285 )
glebiuskv 0:2f0e1e23c242 286
glebiuskv 0:2f0e1e23c242 287 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
glebiuskv 0:2f0e1e23c242 288 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
glebiuskv 0:2f0e1e23c242 289 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
glebiuskv 0:2f0e1e23c242 290 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
glebiuskv 0:2f0e1e23c242 291 )
glebiuskv 0:2f0e1e23c242 292
glebiuskv 0:2f0e1e23c242 293 #endif /* ADC_MULTIMODE_SUPPORT */
glebiuskv 0:2f0e1e23c242 294 /**
glebiuskv 0:2f0e1e23c242 295 * @}
glebiuskv 0:2f0e1e23c242 296 */
glebiuskv 0:2f0e1e23c242 297
glebiuskv 0:2f0e1e23c242 298
glebiuskv 0:2f0e1e23c242 299 /* Private function prototypes -----------------------------------------------*/
glebiuskv 0:2f0e1e23c242 300
glebiuskv 0:2f0e1e23c242 301 /* Exported functions --------------------------------------------------------*/
glebiuskv 0:2f0e1e23c242 302 /** @addtogroup ADC_LL_Exported_Functions
glebiuskv 0:2f0e1e23c242 303 * @{
glebiuskv 0:2f0e1e23c242 304 */
glebiuskv 0:2f0e1e23c242 305
glebiuskv 0:2f0e1e23c242 306 /** @addtogroup ADC_LL_EF_Init
glebiuskv 0:2f0e1e23c242 307 * @{
glebiuskv 0:2f0e1e23c242 308 */
glebiuskv 0:2f0e1e23c242 309
glebiuskv 0:2f0e1e23c242 310 /**
glebiuskv 0:2f0e1e23c242 311 * @brief De-initialize registers of all ADC instances belonging to
glebiuskv 0:2f0e1e23c242 312 * the same ADC common instance to their default reset values.
glebiuskv 0:2f0e1e23c242 313 * @note This function is performing a hard reset, using high level
glebiuskv 0:2f0e1e23c242 314 * clock source RCC ADC reset.
glebiuskv 0:2f0e1e23c242 315 * Caution: On this STM32 serie, if several ADC instances are available
glebiuskv 0:2f0e1e23c242 316 * on the selected device, RCC ADC reset will reset
glebiuskv 0:2f0e1e23c242 317 * all ADC instances belonging to the common ADC instance.
glebiuskv 0:2f0e1e23c242 318 * To de-initialize only 1 ADC instance, use
glebiuskv 0:2f0e1e23c242 319 * function @ref LL_ADC_DeInit().
glebiuskv 0:2f0e1e23c242 320 * @param ADCxy_COMMON ADC common instance
glebiuskv 0:2f0e1e23c242 321 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
glebiuskv 0:2f0e1e23c242 322 * @retval An ErrorStatus enumeration value:
glebiuskv 0:2f0e1e23c242 323 * - SUCCESS: ADC common registers are de-initialized
glebiuskv 0:2f0e1e23c242 324 * - ERROR: not applicable
glebiuskv 0:2f0e1e23c242 325 */
glebiuskv 0:2f0e1e23c242 326 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
glebiuskv 0:2f0e1e23c242 327 {
glebiuskv 0:2f0e1e23c242 328 /* Check the parameters */
glebiuskv 0:2f0e1e23c242 329 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
glebiuskv 0:2f0e1e23c242 330
glebiuskv 0:2f0e1e23c242 331 /* Force reset of ADC clock (core clock) */
glebiuskv 0:2f0e1e23c242 332 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
glebiuskv 0:2f0e1e23c242 333
glebiuskv 0:2f0e1e23c242 334 /* Release reset of ADC clock (core clock) */
glebiuskv 0:2f0e1e23c242 335 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
glebiuskv 0:2f0e1e23c242 336
glebiuskv 0:2f0e1e23c242 337 return SUCCESS;
glebiuskv 0:2f0e1e23c242 338 }
glebiuskv 0:2f0e1e23c242 339
glebiuskv 0:2f0e1e23c242 340 /**
glebiuskv 0:2f0e1e23c242 341 * @brief Initialize some features of ADC common parameters
glebiuskv 0:2f0e1e23c242 342 * (all ADC instances belonging to the same ADC common instance)
glebiuskv 0:2f0e1e23c242 343 * and multimode (for devices with several ADC instances available).
glebiuskv 0:2f0e1e23c242 344 * @note The setting of ADC common parameters is conditioned to
glebiuskv 0:2f0e1e23c242 345 * ADC instances state:
glebiuskv 0:2f0e1e23c242 346 * All ADC instances belonging to the same ADC common instance
glebiuskv 0:2f0e1e23c242 347 * must be disabled.
glebiuskv 0:2f0e1e23c242 348 * @param ADCxy_COMMON ADC common instance
glebiuskv 0:2f0e1e23c242 349 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
glebiuskv 0:2f0e1e23c242 350 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
glebiuskv 0:2f0e1e23c242 351 * @retval An ErrorStatus enumeration value:
glebiuskv 0:2f0e1e23c242 352 * - SUCCESS: ADC common registers are initialized
glebiuskv 0:2f0e1e23c242 353 * - ERROR: ADC common registers are not initialized
glebiuskv 0:2f0e1e23c242 354 */
glebiuskv 0:2f0e1e23c242 355 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
glebiuskv 0:2f0e1e23c242 356 {
glebiuskv 0:2f0e1e23c242 357 ErrorStatus status = SUCCESS;
glebiuskv 0:2f0e1e23c242 358
glebiuskv 0:2f0e1e23c242 359 /* Check the parameters */
glebiuskv 0:2f0e1e23c242 360 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
glebiuskv 0:2f0e1e23c242 361 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
glebiuskv 0:2f0e1e23c242 362
glebiuskv 0:2f0e1e23c242 363 #if defined(ADC_MULTIMODE_SUPPORT)
glebiuskv 0:2f0e1e23c242 364 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
glebiuskv 0:2f0e1e23c242 365 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
glebiuskv 0:2f0e1e23c242 366 {
glebiuskv 0:2f0e1e23c242 367 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
glebiuskv 0:2f0e1e23c242 368 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
glebiuskv 0:2f0e1e23c242 369 }
glebiuskv 0:2f0e1e23c242 370 #endif /* ADC_MULTIMODE_SUPPORT */
glebiuskv 0:2f0e1e23c242 371
glebiuskv 0:2f0e1e23c242 372 /* Note: Hardware constraint (refer to description of functions */
glebiuskv 0:2f0e1e23c242 373 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
glebiuskv 0:2f0e1e23c242 374 /* On this STM32 serie, setting of these features is conditioned to */
glebiuskv 0:2f0e1e23c242 375 /* ADC state: */
glebiuskv 0:2f0e1e23c242 376 /* All ADC instances of the ADC common group must be disabled. */
glebiuskv 0:2f0e1e23c242 377 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
glebiuskv 0:2f0e1e23c242 378 {
glebiuskv 0:2f0e1e23c242 379 /* Configuration of ADC hierarchical scope: */
glebiuskv 0:2f0e1e23c242 380 /* - common to several ADC */
glebiuskv 0:2f0e1e23c242 381 /* (all ADC instances belonging to the same ADC common instance) */
glebiuskv 0:2f0e1e23c242 382 /* - Set ADC clock (conversion clock) */
glebiuskv 0:2f0e1e23c242 383 /* - multimode (if several ADC instances available on the */
glebiuskv 0:2f0e1e23c242 384 /* selected device) */
glebiuskv 0:2f0e1e23c242 385 /* - Set ADC multimode configuration */
glebiuskv 0:2f0e1e23c242 386 /* - Set ADC multimode DMA transfer */
glebiuskv 0:2f0e1e23c242 387 /* - Set ADC multimode: delay between 2 sampling phases */
glebiuskv 0:2f0e1e23c242 388 #if defined(ADC_MULTIMODE_SUPPORT)
glebiuskv 0:2f0e1e23c242 389 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
glebiuskv 0:2f0e1e23c242 390 {
glebiuskv 0:2f0e1e23c242 391 MODIFY_REG(ADCxy_COMMON->CCR,
glebiuskv 0:2f0e1e23c242 392 ADC_CCR_CKMODE
glebiuskv 0:2f0e1e23c242 393 | ADC_CCR_PRESC
glebiuskv 0:2f0e1e23c242 394 | ADC_CCR_DUAL
glebiuskv 0:2f0e1e23c242 395 | ADC_CCR_MDMA
glebiuskv 0:2f0e1e23c242 396 | ADC_CCR_DELAY
glebiuskv 0:2f0e1e23c242 397 ,
glebiuskv 0:2f0e1e23c242 398 ADC_CommonInitStruct->CommonClock
glebiuskv 0:2f0e1e23c242 399 | ADC_CommonInitStruct->Multimode
glebiuskv 0:2f0e1e23c242 400 | ADC_CommonInitStruct->MultiDMATransfer
glebiuskv 0:2f0e1e23c242 401 | ADC_CommonInitStruct->MultiTwoSamplingDelay
glebiuskv 0:2f0e1e23c242 402 );
glebiuskv 0:2f0e1e23c242 403 }
glebiuskv 0:2f0e1e23c242 404 else
glebiuskv 0:2f0e1e23c242 405 {
glebiuskv 0:2f0e1e23c242 406 MODIFY_REG(ADCxy_COMMON->CCR,
glebiuskv 0:2f0e1e23c242 407 ADC_CCR_CKMODE
glebiuskv 0:2f0e1e23c242 408 | ADC_CCR_PRESC
glebiuskv 0:2f0e1e23c242 409 | ADC_CCR_DUAL
glebiuskv 0:2f0e1e23c242 410 | ADC_CCR_MDMA
glebiuskv 0:2f0e1e23c242 411 | ADC_CCR_DELAY
glebiuskv 0:2f0e1e23c242 412 ,
glebiuskv 0:2f0e1e23c242 413 ADC_CommonInitStruct->CommonClock
glebiuskv 0:2f0e1e23c242 414 | LL_ADC_MULTI_INDEPENDENT
glebiuskv 0:2f0e1e23c242 415 );
glebiuskv 0:2f0e1e23c242 416 }
glebiuskv 0:2f0e1e23c242 417 #else
glebiuskv 0:2f0e1e23c242 418 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
glebiuskv 0:2f0e1e23c242 419 #endif
glebiuskv 0:2f0e1e23c242 420 }
glebiuskv 0:2f0e1e23c242 421 else
glebiuskv 0:2f0e1e23c242 422 {
glebiuskv 0:2f0e1e23c242 423 /* Initialization error: One or several ADC instances belonging to */
glebiuskv 0:2f0e1e23c242 424 /* the same ADC common instance are not disabled. */
glebiuskv 0:2f0e1e23c242 425 status = ERROR;
glebiuskv 0:2f0e1e23c242 426 }
glebiuskv 0:2f0e1e23c242 427
glebiuskv 0:2f0e1e23c242 428 return status;
glebiuskv 0:2f0e1e23c242 429 }
glebiuskv 0:2f0e1e23c242 430
glebiuskv 0:2f0e1e23c242 431 /**
glebiuskv 0:2f0e1e23c242 432 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
glebiuskv 0:2f0e1e23c242 433 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
glebiuskv 0:2f0e1e23c242 434 * whose fields will be set to default values.
glebiuskv 0:2f0e1e23c242 435 * @retval None
glebiuskv 0:2f0e1e23c242 436 */
glebiuskv 0:2f0e1e23c242 437 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
glebiuskv 0:2f0e1e23c242 438 {
glebiuskv 0:2f0e1e23c242 439 /* Set ADC_CommonInitStruct fields to default values */
glebiuskv 0:2f0e1e23c242 440 /* Set fields of ADC common */
glebiuskv 0:2f0e1e23c242 441 /* (all ADC instances belonging to the same ADC common instance) */
glebiuskv 0:2f0e1e23c242 442 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
glebiuskv 0:2f0e1e23c242 443
glebiuskv 0:2f0e1e23c242 444 #if defined(ADC_MULTIMODE_SUPPORT)
glebiuskv 0:2f0e1e23c242 445 /* Set fields of ADC multimode */
glebiuskv 0:2f0e1e23c242 446 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
glebiuskv 0:2f0e1e23c242 447 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
glebiuskv 0:2f0e1e23c242 448 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
glebiuskv 0:2f0e1e23c242 449 #endif /* ADC_MULTIMODE_SUPPORT */
glebiuskv 0:2f0e1e23c242 450 }
glebiuskv 0:2f0e1e23c242 451
glebiuskv 0:2f0e1e23c242 452 /**
glebiuskv 0:2f0e1e23c242 453 * @brief De-initialize registers of the selected ADC instance
glebiuskv 0:2f0e1e23c242 454 * to their default reset values.
glebiuskv 0:2f0e1e23c242 455 * @note To reset all ADC instances quickly (perform a hard reset),
glebiuskv 0:2f0e1e23c242 456 * use function @ref LL_ADC_CommonDeInit().
glebiuskv 0:2f0e1e23c242 457 * @note If this functions returns error status, it means that ADC instance
glebiuskv 0:2f0e1e23c242 458 * is in an unknown state.
glebiuskv 0:2f0e1e23c242 459 * In this case, perform a hard reset using high level
glebiuskv 0:2f0e1e23c242 460 * clock source RCC ADC reset.
glebiuskv 0:2f0e1e23c242 461 * Caution: On this STM32 serie, if several ADC instances are available
glebiuskv 0:2f0e1e23c242 462 * on the selected device, RCC ADC reset will reset
glebiuskv 0:2f0e1e23c242 463 * all ADC instances belonging to the common ADC instance.
glebiuskv 0:2f0e1e23c242 464 * Refer to function @ref LL_ADC_CommonDeInit().
glebiuskv 0:2f0e1e23c242 465 * @param ADCx ADC instance
glebiuskv 0:2f0e1e23c242 466 * @retval An ErrorStatus enumeration value:
glebiuskv 0:2f0e1e23c242 467 * - SUCCESS: ADC registers are de-initialized
glebiuskv 0:2f0e1e23c242 468 * - ERROR: ADC registers are not de-initialized
glebiuskv 0:2f0e1e23c242 469 */
glebiuskv 0:2f0e1e23c242 470 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
glebiuskv 0:2f0e1e23c242 471 {
glebiuskv 0:2f0e1e23c242 472 ErrorStatus status = SUCCESS;
glebiuskv 0:2f0e1e23c242 473
glebiuskv 0:2f0e1e23c242 474 __IO uint32_t timeout_cpu_cycles = 0U;
glebiuskv 0:2f0e1e23c242 475
glebiuskv 0:2f0e1e23c242 476 /* Check the parameters */
glebiuskv 0:2f0e1e23c242 477 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
glebiuskv 0:2f0e1e23c242 478
glebiuskv 0:2f0e1e23c242 479 /* Disable ADC instance if not already disabled. */
glebiuskv 0:2f0e1e23c242 480 if(LL_ADC_IsEnabled(ADCx) == 1U)
glebiuskv 0:2f0e1e23c242 481 {
glebiuskv 0:2f0e1e23c242 482 /* Set ADC group regular trigger source to SW start to ensure to not */
glebiuskv 0:2f0e1e23c242 483 /* have an external trigger event occurring during the conversion stop */
glebiuskv 0:2f0e1e23c242 484 /* ADC disable process. */
glebiuskv 0:2f0e1e23c242 485 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
glebiuskv 0:2f0e1e23c242 486
glebiuskv 0:2f0e1e23c242 487 /* Stop potential ADC conversion on going on ADC group regular. */
glebiuskv 0:2f0e1e23c242 488 if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
glebiuskv 0:2f0e1e23c242 489 {
glebiuskv 0:2f0e1e23c242 490 if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
glebiuskv 0:2f0e1e23c242 491 {
glebiuskv 0:2f0e1e23c242 492 LL_ADC_REG_StopConversion(ADCx);
glebiuskv 0:2f0e1e23c242 493 }
glebiuskv 0:2f0e1e23c242 494 }
glebiuskv 0:2f0e1e23c242 495
glebiuskv 0:2f0e1e23c242 496 /* Set ADC group injected trigger source to SW start to ensure to not */
glebiuskv 0:2f0e1e23c242 497 /* have an external trigger event occurring during the conversion stop */
glebiuskv 0:2f0e1e23c242 498 /* ADC disable process. */
glebiuskv 0:2f0e1e23c242 499 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
glebiuskv 0:2f0e1e23c242 500
glebiuskv 0:2f0e1e23c242 501 /* Stop potential ADC conversion on going on ADC group injected. */
glebiuskv 0:2f0e1e23c242 502 if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U)
glebiuskv 0:2f0e1e23c242 503 {
glebiuskv 0:2f0e1e23c242 504 if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0U)
glebiuskv 0:2f0e1e23c242 505 {
glebiuskv 0:2f0e1e23c242 506 LL_ADC_INJ_StopConversion(ADCx);
glebiuskv 0:2f0e1e23c242 507 }
glebiuskv 0:2f0e1e23c242 508 }
glebiuskv 0:2f0e1e23c242 509
glebiuskv 0:2f0e1e23c242 510 /* Wait for ADC conversions are effectively stopped */
glebiuskv 0:2f0e1e23c242 511 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
glebiuskv 0:2f0e1e23c242 512 while (( LL_ADC_REG_IsStopConversionOngoing(ADCx)
glebiuskv 0:2f0e1e23c242 513 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U)
glebiuskv 0:2f0e1e23c242 514 {
glebiuskv 0:2f0e1e23c242 515 if(timeout_cpu_cycles-- == 0U)
glebiuskv 0:2f0e1e23c242 516 {
glebiuskv 0:2f0e1e23c242 517 /* Time-out error */
glebiuskv 0:2f0e1e23c242 518 status = ERROR;
glebiuskv 0:2f0e1e23c242 519 }
glebiuskv 0:2f0e1e23c242 520 }
glebiuskv 0:2f0e1e23c242 521
glebiuskv 0:2f0e1e23c242 522 /* Flush group injected contexts queue (register JSQR): */
glebiuskv 0:2f0e1e23c242 523 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
glebiuskv 0:2f0e1e23c242 524 /* contexts queue is maintained with the last active context). */
glebiuskv 0:2f0e1e23c242 525 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
glebiuskv 0:2f0e1e23c242 526
glebiuskv 0:2f0e1e23c242 527 /* Disable the ADC instance */
glebiuskv 0:2f0e1e23c242 528 LL_ADC_Disable(ADCx);
glebiuskv 0:2f0e1e23c242 529
glebiuskv 0:2f0e1e23c242 530 /* Wait for ADC instance is effectively disabled */
glebiuskv 0:2f0e1e23c242 531 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
glebiuskv 0:2f0e1e23c242 532 while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
glebiuskv 0:2f0e1e23c242 533 {
glebiuskv 0:2f0e1e23c242 534 if(timeout_cpu_cycles-- == 0U)
glebiuskv 0:2f0e1e23c242 535 {
glebiuskv 0:2f0e1e23c242 536 /* Time-out error */
glebiuskv 0:2f0e1e23c242 537 status = ERROR;
glebiuskv 0:2f0e1e23c242 538 }
glebiuskv 0:2f0e1e23c242 539 }
glebiuskv 0:2f0e1e23c242 540 }
glebiuskv 0:2f0e1e23c242 541
glebiuskv 0:2f0e1e23c242 542 /* Check whether ADC state is compliant with expected state */
glebiuskv 0:2f0e1e23c242 543 if(READ_BIT(ADCx->CR,
glebiuskv 0:2f0e1e23c242 544 ( ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
glebiuskv 0:2f0e1e23c242 545 | ADC_CR_ADDIS | ADC_CR_ADEN )
glebiuskv 0:2f0e1e23c242 546 )
glebiuskv 0:2f0e1e23c242 547 == 0U)
glebiuskv 0:2f0e1e23c242 548 {
glebiuskv 0:2f0e1e23c242 549 /* ========== Reset ADC registers ========== */
glebiuskv 0:2f0e1e23c242 550 /* Reset register IER */
glebiuskv 0:2f0e1e23c242 551 CLEAR_BIT(ADCx->IER,
glebiuskv 0:2f0e1e23c242 552 ( LL_ADC_IT_ADRDY
glebiuskv 0:2f0e1e23c242 553 | LL_ADC_IT_EOC
glebiuskv 0:2f0e1e23c242 554 | LL_ADC_IT_EOS
glebiuskv 0:2f0e1e23c242 555 | LL_ADC_IT_OVR
glebiuskv 0:2f0e1e23c242 556 | LL_ADC_IT_EOSMP
glebiuskv 0:2f0e1e23c242 557 | LL_ADC_IT_JEOC
glebiuskv 0:2f0e1e23c242 558 | LL_ADC_IT_JEOS
glebiuskv 0:2f0e1e23c242 559 | LL_ADC_IT_JQOVF
glebiuskv 0:2f0e1e23c242 560 | LL_ADC_IT_AWD1
glebiuskv 0:2f0e1e23c242 561 | LL_ADC_IT_AWD2
glebiuskv 0:2f0e1e23c242 562 | LL_ADC_IT_AWD3 )
glebiuskv 0:2f0e1e23c242 563 );
glebiuskv 0:2f0e1e23c242 564
glebiuskv 0:2f0e1e23c242 565 /* Reset register ISR */
glebiuskv 0:2f0e1e23c242 566 SET_BIT(ADCx->ISR,
glebiuskv 0:2f0e1e23c242 567 ( LL_ADC_FLAG_ADRDY
glebiuskv 0:2f0e1e23c242 568 | LL_ADC_FLAG_EOC
glebiuskv 0:2f0e1e23c242 569 | LL_ADC_FLAG_EOS
glebiuskv 0:2f0e1e23c242 570 | LL_ADC_FLAG_OVR
glebiuskv 0:2f0e1e23c242 571 | LL_ADC_FLAG_EOSMP
glebiuskv 0:2f0e1e23c242 572 | LL_ADC_FLAG_JEOC
glebiuskv 0:2f0e1e23c242 573 | LL_ADC_FLAG_JEOS
glebiuskv 0:2f0e1e23c242 574 | LL_ADC_FLAG_JQOVF
glebiuskv 0:2f0e1e23c242 575 | LL_ADC_FLAG_AWD1
glebiuskv 0:2f0e1e23c242 576 | LL_ADC_FLAG_AWD2
glebiuskv 0:2f0e1e23c242 577 | LL_ADC_FLAG_AWD3 )
glebiuskv 0:2f0e1e23c242 578 );
glebiuskv 0:2f0e1e23c242 579
glebiuskv 0:2f0e1e23c242 580 /* Reset register CR */
glebiuskv 0:2f0e1e23c242 581 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
glebiuskv 0:2f0e1e23c242 582 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
glebiuskv 0:2f0e1e23c242 583 /* access mode "read-set": no direct reset applicable. */
glebiuskv 0:2f0e1e23c242 584 /* - Reset Calibration mode to default setting (single ended). */
glebiuskv 0:2f0e1e23c242 585 /* - Disable ADC internal voltage regulator. */
glebiuskv 0:2f0e1e23c242 586 /* - Enable ADC deep power down. */
glebiuskv 0:2f0e1e23c242 587 /* Note: ADC internal voltage regulator disable and ADC deep power */
glebiuskv 0:2f0e1e23c242 588 /* down enable are conditioned to ADC state disabled: */
glebiuskv 0:2f0e1e23c242 589 /* already done above. */
glebiuskv 0:2f0e1e23c242 590 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
glebiuskv 0:2f0e1e23c242 591 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
glebiuskv 0:2f0e1e23c242 592
glebiuskv 0:2f0e1e23c242 593 /* Reset register CFGR */
glebiuskv 0:2f0e1e23c242 594 MODIFY_REG(ADCx->CFGR,
glebiuskv 0:2f0e1e23c242 595 ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
glebiuskv 0:2f0e1e23c242 596 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
glebiuskv 0:2f0e1e23c242 597 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
glebiuskv 0:2f0e1e23c242 598 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
glebiuskv 0:2f0e1e23c242 599 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
glebiuskv 0:2f0e1e23c242 600 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ),
glebiuskv 0:2f0e1e23c242 601 ADC_CFGR_JQDIS
glebiuskv 0:2f0e1e23c242 602 );
glebiuskv 0:2f0e1e23c242 603
glebiuskv 0:2f0e1e23c242 604 /* Reset register CFGR2 */
glebiuskv 0:2f0e1e23c242 605 CLEAR_BIT(ADCx->CFGR2,
glebiuskv 0:2f0e1e23c242 606 ( ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
glebiuskv 0:2f0e1e23c242 607 | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
glebiuskv 0:2f0e1e23c242 608 );
glebiuskv 0:2f0e1e23c242 609
glebiuskv 0:2f0e1e23c242 610 /* Reset register SMPR1 */
glebiuskv 0:2f0e1e23c242 611 CLEAR_BIT(ADCx->SMPR1,
glebiuskv 0:2f0e1e23c242 612 ( ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
glebiuskv 0:2f0e1e23c242 613 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
glebiuskv 0:2f0e1e23c242 614 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
glebiuskv 0:2f0e1e23c242 615 );
glebiuskv 0:2f0e1e23c242 616
glebiuskv 0:2f0e1e23c242 617 /* Reset register SMPR2 */
glebiuskv 0:2f0e1e23c242 618 CLEAR_BIT(ADCx->SMPR2,
glebiuskv 0:2f0e1e23c242 619 ( ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
glebiuskv 0:2f0e1e23c242 620 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
glebiuskv 0:2f0e1e23c242 621 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
glebiuskv 0:2f0e1e23c242 622 );
glebiuskv 0:2f0e1e23c242 623
glebiuskv 0:2f0e1e23c242 624 /* Reset register TR1 */
glebiuskv 0:2f0e1e23c242 625 MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
glebiuskv 0:2f0e1e23c242 626
glebiuskv 0:2f0e1e23c242 627 /* Reset register TR2 */
glebiuskv 0:2f0e1e23c242 628 MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
glebiuskv 0:2f0e1e23c242 629
glebiuskv 0:2f0e1e23c242 630 /* Reset register TR3 */
glebiuskv 0:2f0e1e23c242 631 MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
glebiuskv 0:2f0e1e23c242 632
glebiuskv 0:2f0e1e23c242 633 /* Reset register SQR1 */
glebiuskv 0:2f0e1e23c242 634 CLEAR_BIT(ADCx->SQR1,
glebiuskv 0:2f0e1e23c242 635 ( ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
glebiuskv 0:2f0e1e23c242 636 | ADC_SQR1_SQ1 | ADC_SQR1_L)
glebiuskv 0:2f0e1e23c242 637 );
glebiuskv 0:2f0e1e23c242 638
glebiuskv 0:2f0e1e23c242 639 /* Reset register SQR2 */
glebiuskv 0:2f0e1e23c242 640 CLEAR_BIT(ADCx->SQR2,
glebiuskv 0:2f0e1e23c242 641 ( ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
glebiuskv 0:2f0e1e23c242 642 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
glebiuskv 0:2f0e1e23c242 643 );
glebiuskv 0:2f0e1e23c242 644
glebiuskv 0:2f0e1e23c242 645 /* Reset register SQR3 */
glebiuskv 0:2f0e1e23c242 646 CLEAR_BIT(ADCx->SQR3,
glebiuskv 0:2f0e1e23c242 647 ( ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
glebiuskv 0:2f0e1e23c242 648 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
glebiuskv 0:2f0e1e23c242 649 );
glebiuskv 0:2f0e1e23c242 650
glebiuskv 0:2f0e1e23c242 651 /* Reset register SQR4 */
glebiuskv 0:2f0e1e23c242 652 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
glebiuskv 0:2f0e1e23c242 653
glebiuskv 0:2f0e1e23c242 654 /* Reset register JSQR */
glebiuskv 0:2f0e1e23c242 655 CLEAR_BIT(ADCx->JSQR,
glebiuskv 0:2f0e1e23c242 656 ( ADC_JSQR_JL
glebiuskv 0:2f0e1e23c242 657 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
glebiuskv 0:2f0e1e23c242 658 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
glebiuskv 0:2f0e1e23c242 659 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
glebiuskv 0:2f0e1e23c242 660 );
glebiuskv 0:2f0e1e23c242 661
glebiuskv 0:2f0e1e23c242 662 /* Reset register DR */
glebiuskv 0:2f0e1e23c242 663 /* Note: bits in access mode read only, no direct reset applicable */
glebiuskv 0:2f0e1e23c242 664
glebiuskv 0:2f0e1e23c242 665 /* Reset register OFR1 */
glebiuskv 0:2f0e1e23c242 666 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
glebiuskv 0:2f0e1e23c242 667 /* Reset register OFR2 */
glebiuskv 0:2f0e1e23c242 668 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
glebiuskv 0:2f0e1e23c242 669 /* Reset register OFR3 */
glebiuskv 0:2f0e1e23c242 670 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
glebiuskv 0:2f0e1e23c242 671 /* Reset register OFR4 */
glebiuskv 0:2f0e1e23c242 672 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
glebiuskv 0:2f0e1e23c242 673
glebiuskv 0:2f0e1e23c242 674 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
glebiuskv 0:2f0e1e23c242 675 /* Note: bits in access mode read only, no direct reset applicable */
glebiuskv 0:2f0e1e23c242 676
glebiuskv 0:2f0e1e23c242 677 /* Reset register AWD2CR */
glebiuskv 0:2f0e1e23c242 678 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
glebiuskv 0:2f0e1e23c242 679
glebiuskv 0:2f0e1e23c242 680 /* Reset register AWD3CR */
glebiuskv 0:2f0e1e23c242 681 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
glebiuskv 0:2f0e1e23c242 682
glebiuskv 0:2f0e1e23c242 683 /* Reset register DIFSEL */
glebiuskv 0:2f0e1e23c242 684 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
glebiuskv 0:2f0e1e23c242 685
glebiuskv 0:2f0e1e23c242 686 /* Reset register CALFACT */
glebiuskv 0:2f0e1e23c242 687 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
glebiuskv 0:2f0e1e23c242 688 }
glebiuskv 0:2f0e1e23c242 689 else
glebiuskv 0:2f0e1e23c242 690 {
glebiuskv 0:2f0e1e23c242 691 /* ADC instance is in an unknown state */
glebiuskv 0:2f0e1e23c242 692 /* Need to performing a hard reset of ADC instance, using high level */
glebiuskv 0:2f0e1e23c242 693 /* clock source RCC ADC reset. */
glebiuskv 0:2f0e1e23c242 694 /* Caution: On this STM32 serie, if several ADC instances are available */
glebiuskv 0:2f0e1e23c242 695 /* on the selected device, RCC ADC reset will reset */
glebiuskv 0:2f0e1e23c242 696 /* all ADC instances belonging to the common ADC instance. */
glebiuskv 0:2f0e1e23c242 697 /* Caution: On this STM32 serie, if several ADC instances are available */
glebiuskv 0:2f0e1e23c242 698 /* on the selected device, RCC ADC reset will reset */
glebiuskv 0:2f0e1e23c242 699 /* all ADC instances belonging to the common ADC instance. */
glebiuskv 0:2f0e1e23c242 700 status = ERROR;
glebiuskv 0:2f0e1e23c242 701 }
glebiuskv 0:2f0e1e23c242 702
glebiuskv 0:2f0e1e23c242 703 return status;
glebiuskv 0:2f0e1e23c242 704 }
glebiuskv 0:2f0e1e23c242 705
glebiuskv 0:2f0e1e23c242 706 /**
glebiuskv 0:2f0e1e23c242 707 * @brief Initialize some features of ADC instance.
glebiuskv 0:2f0e1e23c242 708 * @note These parameters have an impact on ADC scope: ADC instance.
glebiuskv 0:2f0e1e23c242 709 * Affects both group regular and group injected (availability
glebiuskv 0:2f0e1e23c242 710 * of ADC group injected depends on STM32 families).
glebiuskv 0:2f0e1e23c242 711 * Refer to corresponding unitary functions into
glebiuskv 0:2f0e1e23c242 712 * @ref ADC_LL_EF_Configuration_ADC_Instance .
glebiuskv 0:2f0e1e23c242 713 * @note The setting of these parameters by function @ref LL_ADC_Init()
glebiuskv 0:2f0e1e23c242 714 * is conditioned to ADC state:
glebiuskv 0:2f0e1e23c242 715 * ADC instance must be disabled.
glebiuskv 0:2f0e1e23c242 716 * This condition is applied to all ADC features, for efficiency
glebiuskv 0:2f0e1e23c242 717 * and compatibility over all STM32 families. However, the different
glebiuskv 0:2f0e1e23c242 718 * features can be set under different ADC state conditions
glebiuskv 0:2f0e1e23c242 719 * (setting possible with ADC enabled without conversion on going,
glebiuskv 0:2f0e1e23c242 720 * ADC enabled with conversion on going, ...)
glebiuskv 0:2f0e1e23c242 721 * Each feature can be updated afterwards with a unitary function
glebiuskv 0:2f0e1e23c242 722 * and potentially with ADC in a different state than disabled,
glebiuskv 0:2f0e1e23c242 723 * refer to description of each function for setting
glebiuskv 0:2f0e1e23c242 724 * conditioned to ADC state.
glebiuskv 0:2f0e1e23c242 725 * @note After using this function, some other features must be configured
glebiuskv 0:2f0e1e23c242 726 * using LL unitary functions.
glebiuskv 0:2f0e1e23c242 727 * The minimum configuration remaining to be done is:
glebiuskv 0:2f0e1e23c242 728 * - Set ADC group regular or group injected sequencer:
glebiuskv 0:2f0e1e23c242 729 * map channel on the selected sequencer rank.
glebiuskv 0:2f0e1e23c242 730 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
glebiuskv 0:2f0e1e23c242 731 * - Set ADC channel sampling time
glebiuskv 0:2f0e1e23c242 732 * Refer to function LL_ADC_SetChannelSamplingTime();
glebiuskv 0:2f0e1e23c242 733 * @param ADCx ADC instance
glebiuskv 0:2f0e1e23c242 734 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
glebiuskv 0:2f0e1e23c242 735 * @retval An ErrorStatus enumeration value:
glebiuskv 0:2f0e1e23c242 736 * - SUCCESS: ADC registers are initialized
glebiuskv 0:2f0e1e23c242 737 * - ERROR: ADC registers are not initialized
glebiuskv 0:2f0e1e23c242 738 */
glebiuskv 0:2f0e1e23c242 739 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
glebiuskv 0:2f0e1e23c242 740 {
glebiuskv 0:2f0e1e23c242 741 ErrorStatus status = SUCCESS;
glebiuskv 0:2f0e1e23c242 742
glebiuskv 0:2f0e1e23c242 743 /* Check the parameters */
glebiuskv 0:2f0e1e23c242 744 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
glebiuskv 0:2f0e1e23c242 745
glebiuskv 0:2f0e1e23c242 746 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
glebiuskv 0:2f0e1e23c242 747 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
glebiuskv 0:2f0e1e23c242 748 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
glebiuskv 0:2f0e1e23c242 749
glebiuskv 0:2f0e1e23c242 750 /* Note: Hardware constraint (refer to description of this function): */
glebiuskv 0:2f0e1e23c242 751 /* ADC instance must be disabled. */
glebiuskv 0:2f0e1e23c242 752 if(LL_ADC_IsEnabled(ADCx) == 0U)
glebiuskv 0:2f0e1e23c242 753 {
glebiuskv 0:2f0e1e23c242 754 /* Configuration of ADC hierarchical scope: */
glebiuskv 0:2f0e1e23c242 755 /* - ADC instance */
glebiuskv 0:2f0e1e23c242 756 /* - Set ADC data resolution */
glebiuskv 0:2f0e1e23c242 757 /* - Set ADC conversion data alignment */
glebiuskv 0:2f0e1e23c242 758 /* - Set ADC low power mode */
glebiuskv 0:2f0e1e23c242 759 MODIFY_REG(ADCx->CFGR,
glebiuskv 0:2f0e1e23c242 760 ADC_CFGR_RES
glebiuskv 0:2f0e1e23c242 761 | ADC_CFGR_ALIGN
glebiuskv 0:2f0e1e23c242 762 | ADC_CFGR_AUTDLY
glebiuskv 0:2f0e1e23c242 763 ,
glebiuskv 0:2f0e1e23c242 764 ADC_InitStruct->Resolution
glebiuskv 0:2f0e1e23c242 765 | ADC_InitStruct->DataAlignment
glebiuskv 0:2f0e1e23c242 766 | ADC_InitStruct->LowPowerMode
glebiuskv 0:2f0e1e23c242 767 );
glebiuskv 0:2f0e1e23c242 768
glebiuskv 0:2f0e1e23c242 769 }
glebiuskv 0:2f0e1e23c242 770 else
glebiuskv 0:2f0e1e23c242 771 {
glebiuskv 0:2f0e1e23c242 772 /* Initialization error: ADC instance is not disabled. */
glebiuskv 0:2f0e1e23c242 773 status = ERROR;
glebiuskv 0:2f0e1e23c242 774 }
glebiuskv 0:2f0e1e23c242 775 return status;
glebiuskv 0:2f0e1e23c242 776 }
glebiuskv 0:2f0e1e23c242 777
glebiuskv 0:2f0e1e23c242 778 /**
glebiuskv 0:2f0e1e23c242 779 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
glebiuskv 0:2f0e1e23c242 780 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
glebiuskv 0:2f0e1e23c242 781 * whose fields will be set to default values.
glebiuskv 0:2f0e1e23c242 782 * @retval None
glebiuskv 0:2f0e1e23c242 783 */
glebiuskv 0:2f0e1e23c242 784 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
glebiuskv 0:2f0e1e23c242 785 {
glebiuskv 0:2f0e1e23c242 786 /* Set ADC_InitStruct fields to default values */
glebiuskv 0:2f0e1e23c242 787 /* Set fields of ADC instance */
glebiuskv 0:2f0e1e23c242 788 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
glebiuskv 0:2f0e1e23c242 789 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
glebiuskv 0:2f0e1e23c242 790 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
glebiuskv 0:2f0e1e23c242 791
glebiuskv 0:2f0e1e23c242 792 }
glebiuskv 0:2f0e1e23c242 793
glebiuskv 0:2f0e1e23c242 794 /**
glebiuskv 0:2f0e1e23c242 795 * @brief Initialize some features of ADC group regular.
glebiuskv 0:2f0e1e23c242 796 * @note These parameters have an impact on ADC scope: ADC group regular.
glebiuskv 0:2f0e1e23c242 797 * Refer to corresponding unitary functions into
glebiuskv 0:2f0e1e23c242 798 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
glebiuskv 0:2f0e1e23c242 799 * (functions with prefix "REG").
glebiuskv 0:2f0e1e23c242 800 * @note The setting of these parameters by function @ref LL_ADC_Init()
glebiuskv 0:2f0e1e23c242 801 * is conditioned to ADC state:
glebiuskv 0:2f0e1e23c242 802 * ADC instance must be disabled.
glebiuskv 0:2f0e1e23c242 803 * This condition is applied to all ADC features, for efficiency
glebiuskv 0:2f0e1e23c242 804 * and compatibility over all STM32 families. However, the different
glebiuskv 0:2f0e1e23c242 805 * features can be set under different ADC state conditions
glebiuskv 0:2f0e1e23c242 806 * (setting possible with ADC enabled without conversion on going,
glebiuskv 0:2f0e1e23c242 807 * ADC enabled with conversion on going, ...)
glebiuskv 0:2f0e1e23c242 808 * Each feature can be updated afterwards with a unitary function
glebiuskv 0:2f0e1e23c242 809 * and potentially with ADC in a different state than disabled,
glebiuskv 0:2f0e1e23c242 810 * refer to description of each function for setting
glebiuskv 0:2f0e1e23c242 811 * conditioned to ADC state.
glebiuskv 0:2f0e1e23c242 812 * @note After using this function, other features must be configured
glebiuskv 0:2f0e1e23c242 813 * using LL unitary functions.
glebiuskv 0:2f0e1e23c242 814 * The minimum configuration remaining to be done is:
glebiuskv 0:2f0e1e23c242 815 * - Set ADC group regular or group injected sequencer:
glebiuskv 0:2f0e1e23c242 816 * map channel on the selected sequencer rank.
glebiuskv 0:2f0e1e23c242 817 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
glebiuskv 0:2f0e1e23c242 818 * - Set ADC channel sampling time
glebiuskv 0:2f0e1e23c242 819 * Refer to function LL_ADC_SetChannelSamplingTime();
glebiuskv 0:2f0e1e23c242 820 * @param ADCx ADC instance
glebiuskv 0:2f0e1e23c242 821 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
glebiuskv 0:2f0e1e23c242 822 * @retval An ErrorStatus enumeration value:
glebiuskv 0:2f0e1e23c242 823 * - SUCCESS: ADC registers are initialized
glebiuskv 0:2f0e1e23c242 824 * - ERROR: ADC registers are not initialized
glebiuskv 0:2f0e1e23c242 825 */
glebiuskv 0:2f0e1e23c242 826 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
glebiuskv 0:2f0e1e23c242 827 {
glebiuskv 0:2f0e1e23c242 828 ErrorStatus status = SUCCESS;
glebiuskv 0:2f0e1e23c242 829
glebiuskv 0:2f0e1e23c242 830 /* Check the parameters */
glebiuskv 0:2f0e1e23c242 831 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
glebiuskv 0:2f0e1e23c242 832 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
glebiuskv 0:2f0e1e23c242 833 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
glebiuskv 0:2f0e1e23c242 834 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
glebiuskv 0:2f0e1e23c242 835 {
glebiuskv 0:2f0e1e23c242 836 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
glebiuskv 0:2f0e1e23c242 837 }
glebiuskv 0:2f0e1e23c242 838 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
glebiuskv 0:2f0e1e23c242 839 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
glebiuskv 0:2f0e1e23c242 840 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
glebiuskv 0:2f0e1e23c242 841
glebiuskv 0:2f0e1e23c242 842 /* Note: Hardware constraint (refer to description of this function): */
glebiuskv 0:2f0e1e23c242 843 /* ADC instance must be disabled. */
glebiuskv 0:2f0e1e23c242 844 if(LL_ADC_IsEnabled(ADCx) == 0U)
glebiuskv 0:2f0e1e23c242 845 {
glebiuskv 0:2f0e1e23c242 846 /* Configuration of ADC hierarchical scope: */
glebiuskv 0:2f0e1e23c242 847 /* - ADC group regular */
glebiuskv 0:2f0e1e23c242 848 /* - Set ADC group regular trigger source */
glebiuskv 0:2f0e1e23c242 849 /* - Set ADC group regular sequencer length */
glebiuskv 0:2f0e1e23c242 850 /* - Set ADC group regular sequencer discontinuous mode */
glebiuskv 0:2f0e1e23c242 851 /* - Set ADC group regular continuous mode */
glebiuskv 0:2f0e1e23c242 852 /* - Set ADC group regular conversion data transfer: no transfer or */
glebiuskv 0:2f0e1e23c242 853 /* transfer by DMA, and DMA requests mode */
glebiuskv 0:2f0e1e23c242 854 /* - Set ADC group regular overrun behavior */
glebiuskv 0:2f0e1e23c242 855 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
glebiuskv 0:2f0e1e23c242 856 /* setting of trigger source to SW start. */
glebiuskv 0:2f0e1e23c242 857 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
glebiuskv 0:2f0e1e23c242 858 {
glebiuskv 0:2f0e1e23c242 859 MODIFY_REG(ADCx->CFGR,
glebiuskv 0:2f0e1e23c242 860 ADC_CFGR_EXTSEL
glebiuskv 0:2f0e1e23c242 861 | ADC_CFGR_EXTEN
glebiuskv 0:2f0e1e23c242 862 | ADC_CFGR_DISCEN
glebiuskv 0:2f0e1e23c242 863 | ADC_CFGR_DISCNUM
glebiuskv 0:2f0e1e23c242 864 | ADC_CFGR_CONT
glebiuskv 0:2f0e1e23c242 865 | ADC_CFGR_DMAEN
glebiuskv 0:2f0e1e23c242 866 | ADC_CFGR_DMACFG
glebiuskv 0:2f0e1e23c242 867 | ADC_CFGR_OVRMOD
glebiuskv 0:2f0e1e23c242 868 ,
glebiuskv 0:2f0e1e23c242 869 ADC_REG_InitStruct->TriggerSource
glebiuskv 0:2f0e1e23c242 870 | ADC_REG_InitStruct->SequencerDiscont
glebiuskv 0:2f0e1e23c242 871 | ADC_REG_InitStruct->ContinuousMode
glebiuskv 0:2f0e1e23c242 872 | ADC_REG_InitStruct->DMATransfer
glebiuskv 0:2f0e1e23c242 873 | ADC_REG_InitStruct->Overrun
glebiuskv 0:2f0e1e23c242 874 );
glebiuskv 0:2f0e1e23c242 875 }
glebiuskv 0:2f0e1e23c242 876 else
glebiuskv 0:2f0e1e23c242 877 {
glebiuskv 0:2f0e1e23c242 878 MODIFY_REG(ADCx->CFGR,
glebiuskv 0:2f0e1e23c242 879 ADC_CFGR_EXTSEL
glebiuskv 0:2f0e1e23c242 880 | ADC_CFGR_EXTEN
glebiuskv 0:2f0e1e23c242 881 | ADC_CFGR_DISCEN
glebiuskv 0:2f0e1e23c242 882 | ADC_CFGR_DISCNUM
glebiuskv 0:2f0e1e23c242 883 | ADC_CFGR_CONT
glebiuskv 0:2f0e1e23c242 884 | ADC_CFGR_DMAEN
glebiuskv 0:2f0e1e23c242 885 | ADC_CFGR_DMACFG
glebiuskv 0:2f0e1e23c242 886 | ADC_CFGR_OVRMOD
glebiuskv 0:2f0e1e23c242 887 ,
glebiuskv 0:2f0e1e23c242 888 ADC_REG_InitStruct->TriggerSource
glebiuskv 0:2f0e1e23c242 889 | LL_ADC_REG_SEQ_DISCONT_DISABLE
glebiuskv 0:2f0e1e23c242 890 | ADC_REG_InitStruct->ContinuousMode
glebiuskv 0:2f0e1e23c242 891 | ADC_REG_InitStruct->DMATransfer
glebiuskv 0:2f0e1e23c242 892 | ADC_REG_InitStruct->Overrun
glebiuskv 0:2f0e1e23c242 893 );
glebiuskv 0:2f0e1e23c242 894 }
glebiuskv 0:2f0e1e23c242 895
glebiuskv 0:2f0e1e23c242 896 /* Set ADC group regular sequencer length and scan direction */
glebiuskv 0:2f0e1e23c242 897 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
glebiuskv 0:2f0e1e23c242 898 }
glebiuskv 0:2f0e1e23c242 899 else
glebiuskv 0:2f0e1e23c242 900 {
glebiuskv 0:2f0e1e23c242 901 /* Initialization error: ADC instance is not disabled. */
glebiuskv 0:2f0e1e23c242 902 status = ERROR;
glebiuskv 0:2f0e1e23c242 903 }
glebiuskv 0:2f0e1e23c242 904 return status;
glebiuskv 0:2f0e1e23c242 905 }
glebiuskv 0:2f0e1e23c242 906
glebiuskv 0:2f0e1e23c242 907 /**
glebiuskv 0:2f0e1e23c242 908 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
glebiuskv 0:2f0e1e23c242 909 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
glebiuskv 0:2f0e1e23c242 910 * whose fields will be set to default values.
glebiuskv 0:2f0e1e23c242 911 * @retval None
glebiuskv 0:2f0e1e23c242 912 */
glebiuskv 0:2f0e1e23c242 913 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
glebiuskv 0:2f0e1e23c242 914 {
glebiuskv 0:2f0e1e23c242 915 /* Set ADC_REG_InitStruct fields to default values */
glebiuskv 0:2f0e1e23c242 916 /* Set fields of ADC group regular */
glebiuskv 0:2f0e1e23c242 917 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
glebiuskv 0:2f0e1e23c242 918 /* setting of trigger source to SW start. */
glebiuskv 0:2f0e1e23c242 919 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
glebiuskv 0:2f0e1e23c242 920 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
glebiuskv 0:2f0e1e23c242 921 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
glebiuskv 0:2f0e1e23c242 922 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
glebiuskv 0:2f0e1e23c242 923 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
glebiuskv 0:2f0e1e23c242 924 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
glebiuskv 0:2f0e1e23c242 925 }
glebiuskv 0:2f0e1e23c242 926
glebiuskv 0:2f0e1e23c242 927 /**
glebiuskv 0:2f0e1e23c242 928 * @brief Initialize some features of ADC group injected.
glebiuskv 0:2f0e1e23c242 929 * @note These parameters have an impact on ADC scope: ADC group injected.
glebiuskv 0:2f0e1e23c242 930 * Refer to corresponding unitary functions into
glebiuskv 0:2f0e1e23c242 931 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
glebiuskv 0:2f0e1e23c242 932 * (functions with prefix "INJ").
glebiuskv 0:2f0e1e23c242 933 * @note The setting of these parameters by function @ref LL_ADC_Init()
glebiuskv 0:2f0e1e23c242 934 * is conditioned to ADC state:
glebiuskv 0:2f0e1e23c242 935 * ADC instance must be disabled.
glebiuskv 0:2f0e1e23c242 936 * This condition is applied to all ADC features, for efficiency
glebiuskv 0:2f0e1e23c242 937 * and compatibility over all STM32 families. However, the different
glebiuskv 0:2f0e1e23c242 938 * features can be set under different ADC state conditions
glebiuskv 0:2f0e1e23c242 939 * (setting possible with ADC enabled without conversion on going,
glebiuskv 0:2f0e1e23c242 940 * ADC enabled with conversion on going, ...)
glebiuskv 0:2f0e1e23c242 941 * Each feature can be updated afterwards with a unitary function
glebiuskv 0:2f0e1e23c242 942 * and potentially with ADC in a different state than disabled,
glebiuskv 0:2f0e1e23c242 943 * refer to description of each function for setting
glebiuskv 0:2f0e1e23c242 944 * conditioned to ADC state.
glebiuskv 0:2f0e1e23c242 945 * @note After using this function, other features must be configured
glebiuskv 0:2f0e1e23c242 946 * using LL unitary functions.
glebiuskv 0:2f0e1e23c242 947 * The minimum configuration remaining to be done is:
glebiuskv 0:2f0e1e23c242 948 * - Set ADC group injected sequencer:
glebiuskv 0:2f0e1e23c242 949 * map channel on the selected sequencer rank.
glebiuskv 0:2f0e1e23c242 950 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
glebiuskv 0:2f0e1e23c242 951 * - Set ADC channel sampling time
glebiuskv 0:2f0e1e23c242 952 * Refer to function LL_ADC_SetChannelSamplingTime();
glebiuskv 0:2f0e1e23c242 953 * @param ADCx ADC instance
glebiuskv 0:2f0e1e23c242 954 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
glebiuskv 0:2f0e1e23c242 955 * @retval An ErrorStatus enumeration value:
glebiuskv 0:2f0e1e23c242 956 * - SUCCESS: ADC registers are initialized
glebiuskv 0:2f0e1e23c242 957 * - ERROR: ADC registers are not initialized
glebiuskv 0:2f0e1e23c242 958 */
glebiuskv 0:2f0e1e23c242 959 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
glebiuskv 0:2f0e1e23c242 960 {
glebiuskv 0:2f0e1e23c242 961 ErrorStatus status = SUCCESS;
glebiuskv 0:2f0e1e23c242 962
glebiuskv 0:2f0e1e23c242 963 /* Check the parameters */
glebiuskv 0:2f0e1e23c242 964 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
glebiuskv 0:2f0e1e23c242 965 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
glebiuskv 0:2f0e1e23c242 966 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
glebiuskv 0:2f0e1e23c242 967 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
glebiuskv 0:2f0e1e23c242 968 {
glebiuskv 0:2f0e1e23c242 969 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
glebiuskv 0:2f0e1e23c242 970 }
glebiuskv 0:2f0e1e23c242 971 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
glebiuskv 0:2f0e1e23c242 972
glebiuskv 0:2f0e1e23c242 973 /* Note: Hardware constraint (refer to description of this function): */
glebiuskv 0:2f0e1e23c242 974 /* ADC instance must be disabled. */
glebiuskv 0:2f0e1e23c242 975 if(LL_ADC_IsEnabled(ADCx) == 0U)
glebiuskv 0:2f0e1e23c242 976 {
glebiuskv 0:2f0e1e23c242 977 /* Configuration of ADC hierarchical scope: */
glebiuskv 0:2f0e1e23c242 978 /* - ADC group injected */
glebiuskv 0:2f0e1e23c242 979 /* - Set ADC group injected trigger source */
glebiuskv 0:2f0e1e23c242 980 /* - Set ADC group injected sequencer length */
glebiuskv 0:2f0e1e23c242 981 /* - Set ADC group injected sequencer discontinuous mode */
glebiuskv 0:2f0e1e23c242 982 /* - Set ADC group injected conversion trigger: independent or */
glebiuskv 0:2f0e1e23c242 983 /* from ADC group regular */
glebiuskv 0:2f0e1e23c242 984 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
glebiuskv 0:2f0e1e23c242 985 /* setting of trigger source to SW start. */
glebiuskv 0:2f0e1e23c242 986 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
glebiuskv 0:2f0e1e23c242 987 {
glebiuskv 0:2f0e1e23c242 988 MODIFY_REG(ADCx->CFGR,
glebiuskv 0:2f0e1e23c242 989 ADC_CFGR_JDISCEN
glebiuskv 0:2f0e1e23c242 990 | ADC_CFGR_JAUTO
glebiuskv 0:2f0e1e23c242 991 ,
glebiuskv 0:2f0e1e23c242 992 ADC_INJ_InitStruct->SequencerDiscont
glebiuskv 0:2f0e1e23c242 993 | ADC_INJ_InitStruct->TrigAuto
glebiuskv 0:2f0e1e23c242 994 );
glebiuskv 0:2f0e1e23c242 995 }
glebiuskv 0:2f0e1e23c242 996 else
glebiuskv 0:2f0e1e23c242 997 {
glebiuskv 0:2f0e1e23c242 998 MODIFY_REG(ADCx->CFGR,
glebiuskv 0:2f0e1e23c242 999 ADC_CFGR_JDISCEN
glebiuskv 0:2f0e1e23c242 1000 | ADC_CFGR_JAUTO
glebiuskv 0:2f0e1e23c242 1001 ,
glebiuskv 0:2f0e1e23c242 1002 LL_ADC_REG_SEQ_DISCONT_DISABLE
glebiuskv 0:2f0e1e23c242 1003 | ADC_INJ_InitStruct->TrigAuto
glebiuskv 0:2f0e1e23c242 1004 );
glebiuskv 0:2f0e1e23c242 1005 }
glebiuskv 0:2f0e1e23c242 1006
glebiuskv 0:2f0e1e23c242 1007 MODIFY_REG(ADCx->JSQR,
glebiuskv 0:2f0e1e23c242 1008 ADC_JSQR_JEXTSEL
glebiuskv 0:2f0e1e23c242 1009 | ADC_JSQR_JEXTEN
glebiuskv 0:2f0e1e23c242 1010 | ADC_JSQR_JL
glebiuskv 0:2f0e1e23c242 1011 ,
glebiuskv 0:2f0e1e23c242 1012 ADC_INJ_InitStruct->TriggerSource
glebiuskv 0:2f0e1e23c242 1013 | ADC_INJ_InitStruct->SequencerLength
glebiuskv 0:2f0e1e23c242 1014 );
glebiuskv 0:2f0e1e23c242 1015 }
glebiuskv 0:2f0e1e23c242 1016 else
glebiuskv 0:2f0e1e23c242 1017 {
glebiuskv 0:2f0e1e23c242 1018 /* Initialization error: ADC instance is not disabled. */
glebiuskv 0:2f0e1e23c242 1019 status = ERROR;
glebiuskv 0:2f0e1e23c242 1020 }
glebiuskv 0:2f0e1e23c242 1021 return status;
glebiuskv 0:2f0e1e23c242 1022 }
glebiuskv 0:2f0e1e23c242 1023
glebiuskv 0:2f0e1e23c242 1024 /**
glebiuskv 0:2f0e1e23c242 1025 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
glebiuskv 0:2f0e1e23c242 1026 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
glebiuskv 0:2f0e1e23c242 1027 * whose fields will be set to default values.
glebiuskv 0:2f0e1e23c242 1028 * @retval None
glebiuskv 0:2f0e1e23c242 1029 */
glebiuskv 0:2f0e1e23c242 1030 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
glebiuskv 0:2f0e1e23c242 1031 {
glebiuskv 0:2f0e1e23c242 1032 /* Set ADC_INJ_InitStruct fields to default values */
glebiuskv 0:2f0e1e23c242 1033 /* Set fields of ADC group injected */
glebiuskv 0:2f0e1e23c242 1034 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
glebiuskv 0:2f0e1e23c242 1035 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
glebiuskv 0:2f0e1e23c242 1036 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
glebiuskv 0:2f0e1e23c242 1037 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
glebiuskv 0:2f0e1e23c242 1038 }
glebiuskv 0:2f0e1e23c242 1039
glebiuskv 0:2f0e1e23c242 1040 /**
glebiuskv 0:2f0e1e23c242 1041 * @}
glebiuskv 0:2f0e1e23c242 1042 */
glebiuskv 0:2f0e1e23c242 1043
glebiuskv 0:2f0e1e23c242 1044 /**
glebiuskv 0:2f0e1e23c242 1045 * @}
glebiuskv 0:2f0e1e23c242 1046 */
glebiuskv 0:2f0e1e23c242 1047
glebiuskv 0:2f0e1e23c242 1048 /**
glebiuskv 0:2f0e1e23c242 1049 * @}
glebiuskv 0:2f0e1e23c242 1050 */
glebiuskv 0:2f0e1e23c242 1051
glebiuskv 0:2f0e1e23c242 1052 #endif /* ADC1 || ADC2 || ADC3 */
glebiuskv 0:2f0e1e23c242 1053
glebiuskv 0:2f0e1e23c242 1054 /**
glebiuskv 0:2f0e1e23c242 1055 * @}
glebiuskv 0:2f0e1e23c242 1056 */
glebiuskv 0:2f0e1e23c242 1057
glebiuskv 0:2f0e1e23c242 1058 #endif /* USE_FULL_LL_DRIVER */
glebiuskv 0:2f0e1e23c242 1059
glebiuskv 0:2f0e1e23c242 1060 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/