George Roussos / BLE_Temperature

BLE temperature profile using digital DS1820 or analog LM35 sensors

Dependencies:   DS1820

mbed/TARGET_NRF51822/nrf51.h@0:637031152314, 2015-03-07 (annotated)

Committer:
gkroussos
Date:
Sat Mar 07 16:23:41 2015 +0000
Revision:
0:637031152314
Working version 1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gkroussos 0:637031152314 1 /* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
gkroussos 0:637031152314 2 *
gkroussos 0:637031152314 3 * The information contained herein is property of Nordic Semiconductor ASA.
gkroussos 0:637031152314 4 * Terms and conditions of usage are described in detail in NORDIC
gkroussos 0:637031152314 5 * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
gkroussos 0:637031152314 6 *
gkroussos 0:637031152314 7 * Licensees are granted free, non-transferable use of the information. NO
gkroussos 0:637031152314 8 * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
gkroussos 0:637031152314 9 * the file.
gkroussos 0:637031152314 10 *
gkroussos 0:637031152314 11 */
gkroussos 0:637031152314 12
gkroussos 0:637031152314 13
gkroussos 0:637031152314 14
gkroussos 0:637031152314 15 /** @addtogroup Nordic Semiconductor
gkroussos 0:637031152314 16 * @{
gkroussos 0:637031152314 17 */
gkroussos 0:637031152314 18
gkroussos 0:637031152314 19 /** @addtogroup nRF51
gkroussos 0:637031152314 20 * @{
gkroussos 0:637031152314 21 */
gkroussos 0:637031152314 22
gkroussos 0:637031152314 23 #ifndef NRF51_H
gkroussos 0:637031152314 24 #define NRF51_H
gkroussos 0:637031152314 25
gkroussos 0:637031152314 26 #ifdef __cplusplus
gkroussos 0:637031152314 27 extern "C" {
gkroussos 0:637031152314 28 #endif
gkroussos 0:637031152314 29
gkroussos 0:637031152314 30
gkroussos 0:637031152314 31 /* ------------------------- Interrupt Number Definition ------------------------ */
gkroussos 0:637031152314 32
gkroussos 0:637031152314 33 typedef enum {
gkroussos 0:637031152314 34 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
gkroussos 0:637031152314 35 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
gkroussos 0:637031152314 36 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
gkroussos 0:637031152314 37 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
gkroussos 0:637031152314 38 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
gkroussos 0:637031152314 39 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
gkroussos 0:637031152314 40 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
gkroussos 0:637031152314 41 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
gkroussos 0:637031152314 42 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
gkroussos 0:637031152314 43 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
gkroussos 0:637031152314 44 RADIO_IRQn = 1, /*!< 1 RADIO */
gkroussos 0:637031152314 45 UART0_IRQn = 2, /*!< 2 UART0 */
gkroussos 0:637031152314 46 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
gkroussos 0:637031152314 47 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
gkroussos 0:637031152314 48 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
gkroussos 0:637031152314 49 ADC_IRQn = 7, /*!< 7 ADC */
gkroussos 0:637031152314 50 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
gkroussos 0:637031152314 51 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
gkroussos 0:637031152314 52 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
gkroussos 0:637031152314 53 RTC0_IRQn = 11, /*!< 11 RTC0 */
gkroussos 0:637031152314 54 TEMP_IRQn = 12, /*!< 12 TEMP */
gkroussos 0:637031152314 55 RNG_IRQn = 13, /*!< 13 RNG */
gkroussos 0:637031152314 56 ECB_IRQn = 14, /*!< 14 ECB */
gkroussos 0:637031152314 57 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
gkroussos 0:637031152314 58 WDT_IRQn = 16, /*!< 16 WDT */
gkroussos 0:637031152314 59 RTC1_IRQn = 17, /*!< 17 RTC1 */
gkroussos 0:637031152314 60 QDEC_IRQn = 18, /*!< 18 QDEC */
gkroussos 0:637031152314 61 LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */
gkroussos 0:637031152314 62 SWI0_IRQn = 20, /*!< 20 SWI0 */
gkroussos 0:637031152314 63 SWI1_IRQn = 21, /*!< 21 SWI1 */
gkroussos 0:637031152314 64 SWI2_IRQn = 22, /*!< 22 SWI2 */
gkroussos 0:637031152314 65 SWI3_IRQn = 23, /*!< 23 SWI3 */
gkroussos 0:637031152314 66 SWI4_IRQn = 24, /*!< 24 SWI4 */
gkroussos 0:637031152314 67 SWI5_IRQn = 25 /*!< 25 SWI5 */
gkroussos 0:637031152314 68 } IRQn_Type;
gkroussos 0:637031152314 69
gkroussos 0:637031152314 70
gkroussos 0:637031152314 71 /** @addtogroup Configuration_of_CMSIS
gkroussos 0:637031152314 72 * @{
gkroussos 0:637031152314 73 */
gkroussos 0:637031152314 74
gkroussos 0:637031152314 75
gkroussos 0:637031152314 76 /* ================================================================================ */
gkroussos 0:637031152314 77 /* ================ Processor and Core Peripheral Section ================ */
gkroussos 0:637031152314 78 /* ================================================================================ */
gkroussos 0:637031152314 79
gkroussos 0:637031152314 80 /* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */
gkroussos 0:637031152314 81 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
gkroussos 0:637031152314 82 #define __MPU_PRESENT 0 /*!< MPU present or not */
gkroussos 0:637031152314 83 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
gkroussos 0:637031152314 84 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
gkroussos 0:637031152314 85 /** @} */ /* End of group Configuration_of_CMSIS */
gkroussos 0:637031152314 86
gkroussos 0:637031152314 87 #include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
gkroussos 0:637031152314 88 #include "system_nrf51822.h" /*!< nRF51 System */
gkroussos 0:637031152314 89
gkroussos 0:637031152314 90
gkroussos 0:637031152314 91 /* ================================================================================ */
gkroussos 0:637031152314 92 /* ================ Device Specific Peripheral Section ================ */
gkroussos 0:637031152314 93 /* ================================================================================ */
gkroussos 0:637031152314 94
gkroussos 0:637031152314 95
gkroussos 0:637031152314 96 /** @addtogroup Device_Peripheral_Registers
gkroussos 0:637031152314 97 * @{
gkroussos 0:637031152314 98 */
gkroussos 0:637031152314 99
gkroussos 0:637031152314 100
gkroussos 0:637031152314 101 /* ------------------- Start of section using anonymous unions ------------------ */
gkroussos 0:637031152314 102 #if defined(__CC_ARM)
gkroussos 0:637031152314 103 #pragma push
gkroussos 0:637031152314 104 #pragma anon_unions
gkroussos 0:637031152314 105 #elif defined(__ICCARM__)
gkroussos 0:637031152314 106 #pragma language=extended
gkroussos 0:637031152314 107 #elif defined(__GNUC__)
gkroussos 0:637031152314 108 /* anonymous unions are enabled by default */
gkroussos 0:637031152314 109 #elif defined(__TMS470__)
gkroussos 0:637031152314 110 /* anonymous unions are enabled by default */
gkroussos 0:637031152314 111 #elif defined(__TASKING__)
gkroussos 0:637031152314 112 #pragma warning 586
gkroussos 0:637031152314 113 #else
gkroussos 0:637031152314 114 #warning Not supported compiler type
gkroussos 0:637031152314 115 #endif
gkroussos 0:637031152314 116
gkroussos 0:637031152314 117
gkroussos 0:637031152314 118 typedef struct {
gkroussos 0:637031152314 119 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
gkroussos 0:637031152314 120 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
gkroussos 0:637031152314 121 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
gkroussos 0:637031152314 122 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
gkroussos 0:637031152314 123 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
gkroussos 0:637031152314 124 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
gkroussos 0:637031152314 125 } AMLI_RAMPRI_Type;
gkroussos 0:637031152314 126
gkroussos 0:637031152314 127 typedef struct {
gkroussos 0:637031152314 128 __O uint32_t EN; /*!< Enable channel group. */
gkroussos 0:637031152314 129 __O uint32_t DIS; /*!< Disable channel group. */
gkroussos 0:637031152314 130 } PPI_TASKS_CHG_Type;
gkroussos 0:637031152314 131
gkroussos 0:637031152314 132 typedef struct {
gkroussos 0:637031152314 133 __IO uint32_t EEP; /*!< Channel event end-point. */
gkroussos 0:637031152314 134 __IO uint32_t TEP; /*!< Channel task end-point. */
gkroussos 0:637031152314 135 } PPI_CH_Type;
gkroussos 0:637031152314 136
gkroussos 0:637031152314 137
gkroussos 0:637031152314 138 /* ================================================================================ */
gkroussos 0:637031152314 139 /* ================ POWER ================ */
gkroussos 0:637031152314 140 /* ================================================================================ */
gkroussos 0:637031152314 141
gkroussos 0:637031152314 142
gkroussos 0:637031152314 143 /**
gkroussos 0:637031152314 144 * @brief Power Control. (POWER)
gkroussos 0:637031152314 145 */
gkroussos 0:637031152314 146
gkroussos 0:637031152314 147 typedef struct { /*!< POWER Structure */
gkroussos 0:637031152314 148 __I uint32_t RESERVED0[30];
gkroussos 0:637031152314 149 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
gkroussos 0:637031152314 150 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
gkroussos 0:637031152314 151 __I uint32_t RESERVED1[34];
gkroussos 0:637031152314 152 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
gkroussos 0:637031152314 153 __I uint32_t RESERVED2[126];
gkroussos 0:637031152314 154 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 155 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 156 __I uint32_t RESERVED3[61];
gkroussos 0:637031152314 157 __IO uint32_t RESETREAS; /*!< Reset reason. */
gkroussos 0:637031152314 158 __I uint32_t RESERVED4[63];
gkroussos 0:637031152314 159 __O uint32_t SYSTEMOFF; /*!< System off register. */
gkroussos 0:637031152314 160 __I uint32_t RESERVED5[3];
gkroussos 0:637031152314 161 __IO uint32_t POFCON; /*!< Power failure configuration. */
gkroussos 0:637031152314 162 __I uint32_t RESERVED6[2];
gkroussos 0:637031152314 163 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
gkroussos 0:637031152314 164 register. */
gkroussos 0:637031152314 165 __I uint32_t RESERVED7;
gkroussos 0:637031152314 166 __IO uint32_t RAMON; /*!< Ram on/off. */
gkroussos 0:637031152314 167 __I uint32_t RESERVED8[7];
gkroussos 0:637031152314 168 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
gkroussos 0:637031152314 169 is a retained register. */
gkroussos 0:637031152314 170 __I uint32_t RESERVED9[12];
gkroussos 0:637031152314 171 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
gkroussos 0:637031152314 172 } NRF_POWER_Type;
gkroussos 0:637031152314 173
gkroussos 0:637031152314 174
gkroussos 0:637031152314 175 /* ================================================================================ */
gkroussos 0:637031152314 176 /* ================ CLOCK ================ */
gkroussos 0:637031152314 177 /* ================================================================================ */
gkroussos 0:637031152314 178
gkroussos 0:637031152314 179
gkroussos 0:637031152314 180 /**
gkroussos 0:637031152314 181 * @brief Clock control. (CLOCK)
gkroussos 0:637031152314 182 */
gkroussos 0:637031152314 183
gkroussos 0:637031152314 184 typedef struct { /*!< CLOCK Structure */
gkroussos 0:637031152314 185 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
gkroussos 0:637031152314 186 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
gkroussos 0:637031152314 187 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
gkroussos 0:637031152314 188 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
gkroussos 0:637031152314 189 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
gkroussos 0:637031152314 190 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
gkroussos 0:637031152314 191 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
gkroussos 0:637031152314 192 __I uint32_t RESERVED0[57];
gkroussos 0:637031152314 193 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
gkroussos 0:637031152314 194 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
gkroussos 0:637031152314 195 __I uint32_t RESERVED1;
gkroussos 0:637031152314 196 __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */
gkroussos 0:637031152314 197 __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */
gkroussos 0:637031152314 198 __I uint32_t RESERVED2[124];
gkroussos 0:637031152314 199 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 200 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 201 __I uint32_t RESERVED3[64];
gkroussos 0:637031152314 202 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
gkroussos 0:637031152314 203 __I uint32_t RESERVED4[2];
gkroussos 0:637031152314 204 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
gkroussos 0:637031152314 205 __I uint32_t RESERVED5[63];
gkroussos 0:637031152314 206 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
gkroussos 0:637031152314 207 __I uint32_t RESERVED6[7];
gkroussos 0:637031152314 208 __IO uint32_t CTIV; /*!< Calibration timer interval. */
gkroussos 0:637031152314 209 __I uint32_t RESERVED7[5];
gkroussos 0:637031152314 210 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
gkroussos 0:637031152314 211 } NRF_CLOCK_Type;
gkroussos 0:637031152314 212
gkroussos 0:637031152314 213
gkroussos 0:637031152314 214 /* ================================================================================ */
gkroussos 0:637031152314 215 /* ================ MPU ================ */
gkroussos 0:637031152314 216 /* ================================================================================ */
gkroussos 0:637031152314 217
gkroussos 0:637031152314 218
gkroussos 0:637031152314 219 /**
gkroussos 0:637031152314 220 * @brief Memory Protection Unit. (MPU)
gkroussos 0:637031152314 221 */
gkroussos 0:637031152314 222
gkroussos 0:637031152314 223 typedef struct { /*!< MPU Structure */
gkroussos 0:637031152314 224 __I uint32_t RESERVED0[330];
gkroussos 0:637031152314 225 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
gkroussos 0:637031152314 226 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
gkroussos 0:637031152314 227 __I uint32_t RESERVED1[52];
gkroussos 0:637031152314 228 __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */
gkroussos 0:637031152314 229 __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */
gkroussos 0:637031152314 230 __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */
gkroussos 0:637031152314 231 } NRF_MPU_Type;
gkroussos 0:637031152314 232
gkroussos 0:637031152314 233
gkroussos 0:637031152314 234 /* ================================================================================ */
gkroussos 0:637031152314 235 /* ================ PU ================ */
gkroussos 0:637031152314 236 /* ================================================================================ */
gkroussos 0:637031152314 237
gkroussos 0:637031152314 238
gkroussos 0:637031152314 239 /**
gkroussos 0:637031152314 240 * @brief Patch unit. (PU)
gkroussos 0:637031152314 241 */
gkroussos 0:637031152314 242
gkroussos 0:637031152314 243 typedef struct { /*!< PU Structure */
gkroussos 0:637031152314 244 __I uint32_t RESERVED0[448];
gkroussos 0:637031152314 245 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
gkroussos 0:637031152314 246 __I uint32_t RESERVED1[24];
gkroussos 0:637031152314 247 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
gkroussos 0:637031152314 248 __I uint32_t RESERVED2[24];
gkroussos 0:637031152314 249 __IO uint32_t PATCHEN; /*!< Patch enable register. */
gkroussos 0:637031152314 250 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
gkroussos 0:637031152314 251 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
gkroussos 0:637031152314 252 } NRF_PU_Type;
gkroussos 0:637031152314 253
gkroussos 0:637031152314 254
gkroussos 0:637031152314 255 /* ================================================================================ */
gkroussos 0:637031152314 256 /* ================ AMLI ================ */
gkroussos 0:637031152314 257 /* ================================================================================ */
gkroussos 0:637031152314 258
gkroussos 0:637031152314 259
gkroussos 0:637031152314 260 /**
gkroussos 0:637031152314 261 * @brief AHB Multi-Layer Interface. (AMLI)
gkroussos 0:637031152314 262 */
gkroussos 0:637031152314 263
gkroussos 0:637031152314 264 typedef struct { /*!< AMLI Structure */
gkroussos 0:637031152314 265 __I uint32_t RESERVED0[896];
gkroussos 0:637031152314 266 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
gkroussos 0:637031152314 267 } NRF_AMLI_Type;
gkroussos 0:637031152314 268
gkroussos 0:637031152314 269
gkroussos 0:637031152314 270 /* ================================================================================ */
gkroussos 0:637031152314 271 /* ================ RADIO ================ */
gkroussos 0:637031152314 272 /* ================================================================================ */
gkroussos 0:637031152314 273
gkroussos 0:637031152314 274
gkroussos 0:637031152314 275 /**
gkroussos 0:637031152314 276 * @brief The radio. (RADIO)
gkroussos 0:637031152314 277 */
gkroussos 0:637031152314 278
gkroussos 0:637031152314 279 typedef struct { /*!< RADIO Structure */
gkroussos 0:637031152314 280 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
gkroussos 0:637031152314 281 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
gkroussos 0:637031152314 282 __O uint32_t TASKS_START; /*!< Start radio. */
gkroussos 0:637031152314 283 __O uint32_t TASKS_STOP; /*!< Stop radio. */
gkroussos 0:637031152314 284 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
gkroussos 0:637031152314 285 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
gkroussos 0:637031152314 286 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
gkroussos 0:637031152314 287 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
gkroussos 0:637031152314 288 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
gkroussos 0:637031152314 289 __I uint32_t RESERVED0[55];
gkroussos 0:637031152314 290 __IO uint32_t EVENTS_READY; /*!< Ready event. */
gkroussos 0:637031152314 291 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
gkroussos 0:637031152314 292 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
gkroussos 0:637031152314 293 __IO uint32_t EVENTS_END; /*!< End event. */
gkroussos 0:637031152314 294 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
gkroussos 0:637031152314 295 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
gkroussos 0:637031152314 296 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
gkroussos 0:637031152314 297 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
gkroussos 0:637031152314 298 sample is ready for readout at the RSSISAMPLE register. */
gkroussos 0:637031152314 299 __I uint32_t RESERVED1[2];
gkroussos 0:637031152314 300 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
gkroussos 0:637031152314 301 __I uint32_t RESERVED2[53];
gkroussos 0:637031152314 302 __IO uint32_t SHORTS; /*!< Shortcut for the radio. */
gkroussos 0:637031152314 303 __I uint32_t RESERVED3[64];
gkroussos 0:637031152314 304 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 305 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 306 __I uint32_t RESERVED4[61];
gkroussos 0:637031152314 307 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
gkroussos 0:637031152314 308 __I uint32_t RESERVED5;
gkroussos 0:637031152314 309 __I uint32_t RXMATCH; /*!< Received address. */
gkroussos 0:637031152314 310 __I uint32_t RXCRC; /*!< Received CRC. */
gkroussos 0:637031152314 311 __IO uint32_t DAI; /*!< Device address match index. */
gkroussos 0:637031152314 312 __I uint32_t RESERVED6[60];
gkroussos 0:637031152314 313 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
gkroussos 0:637031152314 314 __IO uint32_t FREQUENCY; /*!< Frequency. */
gkroussos 0:637031152314 315 __IO uint32_t TXPOWER; /*!< Output power. */
gkroussos 0:637031152314 316 __IO uint32_t MODE; /*!< Data rate and modulation. */
gkroussos 0:637031152314 317 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
gkroussos 0:637031152314 318 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
gkroussos 0:637031152314 319 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
gkroussos 0:637031152314 320 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
gkroussos 0:637031152314 321 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
gkroussos 0:637031152314 322 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
gkroussos 0:637031152314 323 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
gkroussos 0:637031152314 324 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
gkroussos 0:637031152314 325 __IO uint32_t CRCCNF; /*!< CRC configuration. */
gkroussos 0:637031152314 326 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
gkroussos 0:637031152314 327 __IO uint32_t CRCINIT; /*!< CRC initial value. */
gkroussos 0:637031152314 328 __IO uint32_t TEST; /*!< Test features enable register. */
gkroussos 0:637031152314 329 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
gkroussos 0:637031152314 330 __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */
gkroussos 0:637031152314 331 __I uint32_t RESERVED7;
gkroussos 0:637031152314 332 __I uint32_t STATE; /*!< Current radio state. */
gkroussos 0:637031152314 333 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
gkroussos 0:637031152314 334 __I uint32_t RESERVED8[2];
gkroussos 0:637031152314 335 __IO uint32_t BCC; /*!< Bit counter compare. */
gkroussos 0:637031152314 336 __I uint32_t RESERVED9[39];
gkroussos 0:637031152314 337 __IO uint32_t DAB[8]; /*!< Device address base segment. */
gkroussos 0:637031152314 338 __IO uint32_t DAP[8]; /*!< Device address prefix. */
gkroussos 0:637031152314 339 __IO uint32_t DACNF; /*!< Device address match configuration. */
gkroussos 0:637031152314 340 __I uint32_t RESERVED10[56];
gkroussos 0:637031152314 341 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
gkroussos 0:637031152314 342 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
gkroussos 0:637031152314 343 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
gkroussos 0:637031152314 344 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
gkroussos 0:637031152314 345 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
gkroussos 0:637031152314 346 __I uint32_t RESERVED11[561];
gkroussos 0:637031152314 347 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 348 } NRF_RADIO_Type;
gkroussos 0:637031152314 349
gkroussos 0:637031152314 350
gkroussos 0:637031152314 351 /* ================================================================================ */
gkroussos 0:637031152314 352 /* ================ UART ================ */
gkroussos 0:637031152314 353 /* ================================================================================ */
gkroussos 0:637031152314 354
gkroussos 0:637031152314 355
gkroussos 0:637031152314 356 /**
gkroussos 0:637031152314 357 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
gkroussos 0:637031152314 358 */
gkroussos 0:637031152314 359
gkroussos 0:637031152314 360 typedef struct { /*!< UART Structure */
gkroussos 0:637031152314 361 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
gkroussos 0:637031152314 362 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
gkroussos 0:637031152314 363 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
gkroussos 0:637031152314 364 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
gkroussos 0:637031152314 365 __I uint32_t RESERVED0[3];
gkroussos 0:637031152314 366 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
gkroussos 0:637031152314 367 __I uint32_t RESERVED1[56];
gkroussos 0:637031152314 368 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
gkroussos 0:637031152314 369 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
gkroussos 0:637031152314 370 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
gkroussos 0:637031152314 371 __I uint32_t RESERVED2[4];
gkroussos 0:637031152314 372 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
gkroussos 0:637031152314 373 __I uint32_t RESERVED3;
gkroussos 0:637031152314 374 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
gkroussos 0:637031152314 375 __I uint32_t RESERVED4[7];
gkroussos 0:637031152314 376 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
gkroussos 0:637031152314 377 __I uint32_t RESERVED5[46];
gkroussos 0:637031152314 378 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
gkroussos 0:637031152314 379 __I uint32_t RESERVED6[64];
gkroussos 0:637031152314 380 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 381 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 382 __I uint32_t RESERVED7[93];
gkroussos 0:637031152314 383 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
gkroussos 0:637031152314 384 __I uint32_t RESERVED8[31];
gkroussos 0:637031152314 385 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
gkroussos 0:637031152314 386 __I uint32_t RESERVED9;
gkroussos 0:637031152314 387 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
gkroussos 0:637031152314 388 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
gkroussos 0:637031152314 389 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
gkroussos 0:637031152314 390 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
gkroussos 0:637031152314 391 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
gkroussos 0:637031152314 392 Once read the character is consummed. If read when no character
gkroussos 0:637031152314 393 available, the UART will stop working. */
gkroussos 0:637031152314 394 __O uint32_t TXD; /*!< TXD register. */
gkroussos 0:637031152314 395 __I uint32_t RESERVED10;
gkroussos 0:637031152314 396 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
gkroussos 0:637031152314 397 __I uint32_t RESERVED11[17];
gkroussos 0:637031152314 398 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
gkroussos 0:637031152314 399 __I uint32_t RESERVED12[675];
gkroussos 0:637031152314 400 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 401 } NRF_UART_Type;
gkroussos 0:637031152314 402
gkroussos 0:637031152314 403
gkroussos 0:637031152314 404 /* ================================================================================ */
gkroussos 0:637031152314 405 /* ================ SPI ================ */
gkroussos 0:637031152314 406 /* ================================================================================ */
gkroussos 0:637031152314 407
gkroussos 0:637031152314 408
gkroussos 0:637031152314 409 /**
gkroussos 0:637031152314 410 * @brief SPI master 0. (SPI)
gkroussos 0:637031152314 411 */
gkroussos 0:637031152314 412
gkroussos 0:637031152314 413 typedef struct { /*!< SPI Structure */
gkroussos 0:637031152314 414 __I uint32_t RESERVED0[66];
gkroussos 0:637031152314 415 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
gkroussos 0:637031152314 416 __I uint32_t RESERVED1[126];
gkroussos 0:637031152314 417 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 418 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 419 __I uint32_t RESERVED2[125];
gkroussos 0:637031152314 420 __IO uint32_t ENABLE; /*!< Enable SPI. */
gkroussos 0:637031152314 421 __I uint32_t RESERVED3;
gkroussos 0:637031152314 422 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
gkroussos 0:637031152314 423 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
gkroussos 0:637031152314 424 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
gkroussos 0:637031152314 425 __I uint32_t RESERVED4;
gkroussos 0:637031152314 426 __IO uint32_t RXD; /*!< RX data. */
gkroussos 0:637031152314 427 __IO uint32_t TXD; /*!< TX data. */
gkroussos 0:637031152314 428 __I uint32_t RESERVED5;
gkroussos 0:637031152314 429 __IO uint32_t FREQUENCY; /*!< SPI frequency */
gkroussos 0:637031152314 430 __I uint32_t RESERVED6[11];
gkroussos 0:637031152314 431 __IO uint32_t CONFIG; /*!< Configuration register. */
gkroussos 0:637031152314 432 __I uint32_t RESERVED7[681];
gkroussos 0:637031152314 433 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 434 } NRF_SPI_Type;
gkroussos 0:637031152314 435
gkroussos 0:637031152314 436
gkroussos 0:637031152314 437 /* ================================================================================ */
gkroussos 0:637031152314 438 /* ================ TWI ================ */
gkroussos 0:637031152314 439 /* ================================================================================ */
gkroussos 0:637031152314 440
gkroussos 0:637031152314 441
gkroussos 0:637031152314 442 /**
gkroussos 0:637031152314 443 * @brief Two-wire interface master 0. (TWI)
gkroussos 0:637031152314 444 */
gkroussos 0:637031152314 445
gkroussos 0:637031152314 446 typedef struct { /*!< TWI Structure */
gkroussos 0:637031152314 447 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
gkroussos 0:637031152314 448 __I uint32_t RESERVED0;
gkroussos 0:637031152314 449 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
gkroussos 0:637031152314 450 __I uint32_t RESERVED1[2];
gkroussos 0:637031152314 451 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
gkroussos 0:637031152314 452 __I uint32_t RESERVED2;
gkroussos 0:637031152314 453 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
gkroussos 0:637031152314 454 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
gkroussos 0:637031152314 455 __I uint32_t RESERVED3[56];
gkroussos 0:637031152314 456 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
gkroussos 0:637031152314 457 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
gkroussos 0:637031152314 458 __I uint32_t RESERVED4[4];
gkroussos 0:637031152314 459 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
gkroussos 0:637031152314 460 __I uint32_t RESERVED5;
gkroussos 0:637031152314 461 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
gkroussos 0:637031152314 462 __I uint32_t RESERVED6[4];
gkroussos 0:637031152314 463 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
gkroussos 0:637031152314 464 __I uint32_t RESERVED7[49];
gkroussos 0:637031152314 465 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
gkroussos 0:637031152314 466 __I uint32_t RESERVED8[64];
gkroussos 0:637031152314 467 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 468 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 469 __I uint32_t RESERVED9[110];
gkroussos 0:637031152314 470 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
gkroussos 0:637031152314 471 __I uint32_t RESERVED10[14];
gkroussos 0:637031152314 472 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
gkroussos 0:637031152314 473 __I uint32_t RESERVED11;
gkroussos 0:637031152314 474 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
gkroussos 0:637031152314 475 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
gkroussos 0:637031152314 476 __I uint32_t RESERVED12[2];
gkroussos 0:637031152314 477 __IO uint32_t RXD; /*!< RX data register. */
gkroussos 0:637031152314 478 __IO uint32_t TXD; /*!< TX data register. */
gkroussos 0:637031152314 479 __I uint32_t RESERVED13;
gkroussos 0:637031152314 480 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
gkroussos 0:637031152314 481 __I uint32_t RESERVED14[24];
gkroussos 0:637031152314 482 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
gkroussos 0:637031152314 483 __I uint32_t RESERVED15[668];
gkroussos 0:637031152314 484 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 485 } NRF_TWI_Type;
gkroussos 0:637031152314 486
gkroussos 0:637031152314 487
gkroussos 0:637031152314 488 /* ================================================================================ */
gkroussos 0:637031152314 489 /* ================ SPIS ================ */
gkroussos 0:637031152314 490 /* ================================================================================ */
gkroussos 0:637031152314 491
gkroussos 0:637031152314 492
gkroussos 0:637031152314 493 /**
gkroussos 0:637031152314 494 * @brief SPI slave 1. (SPIS)
gkroussos 0:637031152314 495 */
gkroussos 0:637031152314 496
gkroussos 0:637031152314 497 typedef struct { /*!< SPIS Structure */
gkroussos 0:637031152314 498 __I uint32_t RESERVED0[9];
gkroussos 0:637031152314 499 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
gkroussos 0:637031152314 500 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
gkroussos 0:637031152314 501 __I uint32_t RESERVED1[54];
gkroussos 0:637031152314 502 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
gkroussos 0:637031152314 503 __I uint32_t RESERVED2[8];
gkroussos 0:637031152314 504 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
gkroussos 0:637031152314 505 __I uint32_t RESERVED3[53];
gkroussos 0:637031152314 506 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
gkroussos 0:637031152314 507 __I uint32_t RESERVED4[64];
gkroussos 0:637031152314 508 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 509 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 510 __I uint32_t RESERVED5[61];
gkroussos 0:637031152314 511 __I uint32_t SEMSTAT; /*!< Semaphore status. */
gkroussos 0:637031152314 512 __I uint32_t RESERVED6[15];
gkroussos 0:637031152314 513 __IO uint32_t STATUS; /*!< Status from last transaction. */
gkroussos 0:637031152314 514 __I uint32_t RESERVED7[47];
gkroussos 0:637031152314 515 __IO uint32_t ENABLE; /*!< Enable SPIS. */
gkroussos 0:637031152314 516 __I uint32_t RESERVED8;
gkroussos 0:637031152314 517 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
gkroussos 0:637031152314 518 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
gkroussos 0:637031152314 519 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
gkroussos 0:637031152314 520 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
gkroussos 0:637031152314 521 __I uint32_t RESERVED9[7];
gkroussos 0:637031152314 522 __IO uint32_t RXDPTR; /*!< RX data pointer. */
gkroussos 0:637031152314 523 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
gkroussos 0:637031152314 524 __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
gkroussos 0:637031152314 525 __I uint32_t RESERVED10;
gkroussos 0:637031152314 526 __IO uint32_t TXDPTR; /*!< TX data pointer. */
gkroussos 0:637031152314 527 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
gkroussos 0:637031152314 528 __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
gkroussos 0:637031152314 529 __I uint32_t RESERVED11;
gkroussos 0:637031152314 530 __IO uint32_t CONFIG; /*!< Configuration register. */
gkroussos 0:637031152314 531 __I uint32_t RESERVED12;
gkroussos 0:637031152314 532 __IO uint32_t DEF; /*!< Default character. */
gkroussos 0:637031152314 533 __I uint32_t RESERVED13[24];
gkroussos 0:637031152314 534 __IO uint32_t ORC; /*!< Over-read character. */
gkroussos 0:637031152314 535 __I uint32_t RESERVED14[654];
gkroussos 0:637031152314 536 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 537 } NRF_SPIS_Type;
gkroussos 0:637031152314 538
gkroussos 0:637031152314 539
gkroussos 0:637031152314 540 /* ================================================================================ */
gkroussos 0:637031152314 541 /* ================ GPIOTE ================ */
gkroussos 0:637031152314 542 /* ================================================================================ */
gkroussos 0:637031152314 543
gkroussos 0:637031152314 544
gkroussos 0:637031152314 545 /**
gkroussos 0:637031152314 546 * @brief GPIO tasks and events. (GPIOTE)
gkroussos 0:637031152314 547 */
gkroussos 0:637031152314 548
gkroussos 0:637031152314 549 typedef struct { /*!< GPIOTE Structure */
gkroussos 0:637031152314 550 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
gkroussos 0:637031152314 551 __I uint32_t RESERVED0[60];
gkroussos 0:637031152314 552 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
gkroussos 0:637031152314 553 __I uint32_t RESERVED1[27];
gkroussos 0:637031152314 554 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
gkroussos 0:637031152314 555 __I uint32_t RESERVED2[97];
gkroussos 0:637031152314 556 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 557 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 558 __I uint32_t RESERVED3[129];
gkroussos 0:637031152314 559 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
gkroussos 0:637031152314 560 __I uint32_t RESERVED4[695];
gkroussos 0:637031152314 561 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 562 } NRF_GPIOTE_Type;
gkroussos 0:637031152314 563
gkroussos 0:637031152314 564
gkroussos 0:637031152314 565 /* ================================================================================ */
gkroussos 0:637031152314 566 /* ================ ADC ================ */
gkroussos 0:637031152314 567 /* ================================================================================ */
gkroussos 0:637031152314 568
gkroussos 0:637031152314 569
gkroussos 0:637031152314 570 /**
gkroussos 0:637031152314 571 * @brief Analog to digital converter. (ADC)
gkroussos 0:637031152314 572 */
gkroussos 0:637031152314 573
gkroussos 0:637031152314 574 typedef struct { /*!< ADC Structure */
gkroussos 0:637031152314 575 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
gkroussos 0:637031152314 576 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
gkroussos 0:637031152314 577 __I uint32_t RESERVED0[62];
gkroussos 0:637031152314 578 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
gkroussos 0:637031152314 579 __I uint32_t RESERVED1[128];
gkroussos 0:637031152314 580 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 581 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 582 __I uint32_t RESERVED2[61];
gkroussos 0:637031152314 583 __I uint32_t BUSY; /*!< ADC busy register. */
gkroussos 0:637031152314 584 __I uint32_t RESERVED3[63];
gkroussos 0:637031152314 585 __IO uint32_t ENABLE; /*!< ADC enable. */
gkroussos 0:637031152314 586 __IO uint32_t CONFIG; /*!< ADC configuration register. */
gkroussos 0:637031152314 587 __I uint32_t RESULT; /*!< Result of ADC conversion. */
gkroussos 0:637031152314 588 __I uint32_t RESERVED4[700];
gkroussos 0:637031152314 589 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 590 } NRF_ADC_Type;
gkroussos 0:637031152314 591
gkroussos 0:637031152314 592
gkroussos 0:637031152314 593 /* ================================================================================ */
gkroussos 0:637031152314 594 /* ================ TIMER ================ */
gkroussos 0:637031152314 595 /* ================================================================================ */
gkroussos 0:637031152314 596
gkroussos 0:637031152314 597
gkroussos 0:637031152314 598 /**
gkroussos 0:637031152314 599 * @brief Timer 0. (TIMER)
gkroussos 0:637031152314 600 */
gkroussos 0:637031152314 601
gkroussos 0:637031152314 602 typedef struct { /*!< TIMER Structure */
gkroussos 0:637031152314 603 __O uint32_t TASKS_START; /*!< Start Timer. */
gkroussos 0:637031152314 604 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
gkroussos 0:637031152314 605 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
gkroussos 0:637031152314 606 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
gkroussos 0:637031152314 607 __I uint32_t RESERVED0[12];
gkroussos 0:637031152314 608 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
gkroussos 0:637031152314 609 __I uint32_t RESERVED1[60];
gkroussos 0:637031152314 610 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
gkroussos 0:637031152314 611 __I uint32_t RESERVED2[44];
gkroussos 0:637031152314 612 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
gkroussos 0:637031152314 613 __I uint32_t RESERVED3[64];
gkroussos 0:637031152314 614 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 615 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 616 __I uint32_t RESERVED4[126];
gkroussos 0:637031152314 617 __IO uint32_t MODE; /*!< Timer Mode selection. */
gkroussos 0:637031152314 618 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
gkroussos 0:637031152314 619 __I uint32_t RESERVED5;
gkroussos 0:637031152314 620 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
gkroussos 0:637031152314 621 clock frequency is divided by 2^SCALE. */
gkroussos 0:637031152314 622 __I uint32_t RESERVED6[11];
gkroussos 0:637031152314 623 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
gkroussos 0:637031152314 624 __I uint32_t RESERVED7[683];
gkroussos 0:637031152314 625 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 626 } NRF_TIMER_Type;
gkroussos 0:637031152314 627
gkroussos 0:637031152314 628
gkroussos 0:637031152314 629 /* ================================================================================ */
gkroussos 0:637031152314 630 /* ================ RTC ================ */
gkroussos 0:637031152314 631 /* ================================================================================ */
gkroussos 0:637031152314 632
gkroussos 0:637031152314 633
gkroussos 0:637031152314 634 /**
gkroussos 0:637031152314 635 * @brief Real time counter 0. (RTC)
gkroussos 0:637031152314 636 */
gkroussos 0:637031152314 637
gkroussos 0:637031152314 638 typedef struct { /*!< RTC Structure */
gkroussos 0:637031152314 639 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
gkroussos 0:637031152314 640 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
gkroussos 0:637031152314 641 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
gkroussos 0:637031152314 642 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
gkroussos 0:637031152314 643 __I uint32_t RESERVED0[60];
gkroussos 0:637031152314 644 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
gkroussos 0:637031152314 645 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
gkroussos 0:637031152314 646 __I uint32_t RESERVED1[14];
gkroussos 0:637031152314 647 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
gkroussos 0:637031152314 648 __I uint32_t RESERVED2[109];
gkroussos 0:637031152314 649 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 650 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 651 __I uint32_t RESERVED3[13];
gkroussos 0:637031152314 652 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
gkroussos 0:637031152314 653 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
gkroussos 0:637031152314 654 the value of EVTEN. */
gkroussos 0:637031152314 655 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
gkroussos 0:637031152314 656 gives the value of EVTEN. */
gkroussos 0:637031152314 657 __I uint32_t RESERVED4[110];
gkroussos 0:637031152314 658 __IO uint32_t COUNTER; /*!< Current COUNTER value. */
gkroussos 0:637031152314 659 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
gkroussos 0:637031152314 660 Must be written when RTC is STOPed. */
gkroussos 0:637031152314 661 __I uint32_t RESERVED5[13];
gkroussos 0:637031152314 662 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
gkroussos 0:637031152314 663 __I uint32_t RESERVED6[683];
gkroussos 0:637031152314 664 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 665 } NRF_RTC_Type;
gkroussos 0:637031152314 666
gkroussos 0:637031152314 667
gkroussos 0:637031152314 668 /* ================================================================================ */
gkroussos 0:637031152314 669 /* ================ TEMP ================ */
gkroussos 0:637031152314 670 /* ================================================================================ */
gkroussos 0:637031152314 671
gkroussos 0:637031152314 672
gkroussos 0:637031152314 673 /**
gkroussos 0:637031152314 674 * @brief Temperature Sensor. (TEMP)
gkroussos 0:637031152314 675 */
gkroussos 0:637031152314 676
gkroussos 0:637031152314 677 typedef struct { /*!< TEMP Structure */
gkroussos 0:637031152314 678 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
gkroussos 0:637031152314 679 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
gkroussos 0:637031152314 680 __I uint32_t RESERVED0[62];
gkroussos 0:637031152314 681 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
gkroussos 0:637031152314 682 __I uint32_t RESERVED1[128];
gkroussos 0:637031152314 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 685 __I uint32_t RESERVED2[127];
gkroussos 0:637031152314 686 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
gkroussos 0:637031152314 687 __I uint32_t RESERVED3[700];
gkroussos 0:637031152314 688 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 689 } NRF_TEMP_Type;
gkroussos 0:637031152314 690
gkroussos 0:637031152314 691
gkroussos 0:637031152314 692 /* ================================================================================ */
gkroussos 0:637031152314 693 /* ================ RNG ================ */
gkroussos 0:637031152314 694 /* ================================================================================ */
gkroussos 0:637031152314 695
gkroussos 0:637031152314 696
gkroussos 0:637031152314 697 /**
gkroussos 0:637031152314 698 * @brief Random Number Generator. (RNG)
gkroussos 0:637031152314 699 */
gkroussos 0:637031152314 700
gkroussos 0:637031152314 701 typedef struct { /*!< RNG Structure */
gkroussos 0:637031152314 702 __O uint32_t TASKS_START; /*!< Start the random number generator. */
gkroussos 0:637031152314 703 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
gkroussos 0:637031152314 704 __I uint32_t RESERVED0[62];
gkroussos 0:637031152314 705 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
gkroussos 0:637031152314 706 __I uint32_t RESERVED1[63];
gkroussos 0:637031152314 707 __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */
gkroussos 0:637031152314 708 __I uint32_t RESERVED2[64];
gkroussos 0:637031152314 709 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
gkroussos 0:637031152314 710 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
gkroussos 0:637031152314 711 __I uint32_t RESERVED3[126];
gkroussos 0:637031152314 712 __IO uint32_t CONFIG; /*!< Configuration register. */
gkroussos 0:637031152314 713 __I uint32_t VALUE; /*!< RNG random number. */
gkroussos 0:637031152314 714 __I uint32_t RESERVED4[700];
gkroussos 0:637031152314 715 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 716 } NRF_RNG_Type;
gkroussos 0:637031152314 717
gkroussos 0:637031152314 718
gkroussos 0:637031152314 719 /* ================================================================================ */
gkroussos 0:637031152314 720 /* ================ ECB ================ */
gkroussos 0:637031152314 721 /* ================================================================================ */
gkroussos 0:637031152314 722
gkroussos 0:637031152314 723
gkroussos 0:637031152314 724 /**
gkroussos 0:637031152314 725 * @brief AES ECB Mode Encryption. (ECB)
gkroussos 0:637031152314 726 */
gkroussos 0:637031152314 727
gkroussos 0:637031152314 728 typedef struct { /*!< ECB Structure */
gkroussos 0:637031152314 729 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
gkroussos 0:637031152314 730 will not initiate a new encryption and the ERRORECB event will
gkroussos 0:637031152314 731 be triggered. */
gkroussos 0:637031152314 732 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
gkroussos 0:637031152314 733 this will will trigger the ERRORECB event. */
gkroussos 0:637031152314 734 __I uint32_t RESERVED0[62];
gkroussos 0:637031152314 735 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
gkroussos 0:637031152314 736 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
gkroussos 0:637031152314 737 error. */
gkroussos 0:637031152314 738 __I uint32_t RESERVED1[127];
gkroussos 0:637031152314 739 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 740 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 741 __I uint32_t RESERVED2[126];
gkroussos 0:637031152314 742 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
gkroussos 0:637031152314 743 __I uint32_t RESERVED3[701];
gkroussos 0:637031152314 744 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 745 } NRF_ECB_Type;
gkroussos 0:637031152314 746
gkroussos 0:637031152314 747
gkroussos 0:637031152314 748 /* ================================================================================ */
gkroussos 0:637031152314 749 /* ================ AAR ================ */
gkroussos 0:637031152314 750 /* ================================================================================ */
gkroussos 0:637031152314 751
gkroussos 0:637031152314 752
gkroussos 0:637031152314 753 /**
gkroussos 0:637031152314 754 * @brief Accelerated Address Resolver. (AAR)
gkroussos 0:637031152314 755 */
gkroussos 0:637031152314 756
gkroussos 0:637031152314 757 typedef struct { /*!< AAR Structure */
gkroussos 0:637031152314 758 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
gkroussos 0:637031152314 759 data structure. */
gkroussos 0:637031152314 760 __I uint32_t RESERVED0;
gkroussos 0:637031152314 761 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
gkroussos 0:637031152314 762 __I uint32_t RESERVED1[61];
gkroussos 0:637031152314 763 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
gkroussos 0:637031152314 764 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
gkroussos 0:637031152314 765 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
gkroussos 0:637031152314 766 __I uint32_t RESERVED2[126];
gkroussos 0:637031152314 767 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 768 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 769 __I uint32_t RESERVED3[61];
gkroussos 0:637031152314 770 __I uint32_t STATUS; /*!< Resolution status. */
gkroussos 0:637031152314 771 __I uint32_t RESERVED4[63];
gkroussos 0:637031152314 772 __IO uint32_t ENABLE; /*!< Enable AAR. */
gkroussos 0:637031152314 773 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
gkroussos 0:637031152314 774 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
gkroussos 0:637031152314 775 __I uint32_t RESERVED5;
gkroussos 0:637031152314 776 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
gkroussos 0:637031152314 777 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
gkroussos 0:637031152314 778 resolution. A minimum of 3 bytes must be reserved. */
gkroussos 0:637031152314 779 __I uint32_t RESERVED6[697];
gkroussos 0:637031152314 780 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 781 } NRF_AAR_Type;
gkroussos 0:637031152314 782
gkroussos 0:637031152314 783
gkroussos 0:637031152314 784 /* ================================================================================ */
gkroussos 0:637031152314 785 /* ================ CCM ================ */
gkroussos 0:637031152314 786 /* ================================================================================ */
gkroussos 0:637031152314 787
gkroussos 0:637031152314 788
gkroussos 0:637031152314 789 /**
gkroussos 0:637031152314 790 * @brief AES CCM Mode Encryption. (CCM)
gkroussos 0:637031152314 791 */
gkroussos 0:637031152314 792
gkroussos 0:637031152314 793 typedef struct { /*!< CCM Structure */
gkroussos 0:637031152314 794 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
gkroussos 0:637031152314 795 itself when completed. */
gkroussos 0:637031152314 796 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
gkroussos 0:637031152314 797 completed. */
gkroussos 0:637031152314 798 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
gkroussos 0:637031152314 799 __I uint32_t RESERVED0[61];
gkroussos 0:637031152314 800 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
gkroussos 0:637031152314 801 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
gkroussos 0:637031152314 802 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
gkroussos 0:637031152314 803 __I uint32_t RESERVED1[61];
gkroussos 0:637031152314 804 __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */
gkroussos 0:637031152314 805 __I uint32_t RESERVED2[64];
gkroussos 0:637031152314 806 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 807 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 808 __I uint32_t RESERVED3[61];
gkroussos 0:637031152314 809 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
gkroussos 0:637031152314 810 __I uint32_t RESERVED4[63];
gkroussos 0:637031152314 811 __IO uint32_t ENABLE; /*!< CCM enable. */
gkroussos 0:637031152314 812 __IO uint32_t MODE; /*!< Operation mode. */
gkroussos 0:637031152314 813 __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */
gkroussos 0:637031152314 814 __IO uint32_t INPTR; /*!< Pointer to input packet. */
gkroussos 0:637031152314 815 __IO uint32_t OUTPTR; /*!< Pointer to output packet. */
gkroussos 0:637031152314 816 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
gkroussos 0:637031152314 817 resolution. A minimum of 43 bytes must be reserved. */
gkroussos 0:637031152314 818 __I uint32_t RESERVED5[697];
gkroussos 0:637031152314 819 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 820 } NRF_CCM_Type;
gkroussos 0:637031152314 821
gkroussos 0:637031152314 822
gkroussos 0:637031152314 823 /* ================================================================================ */
gkroussos 0:637031152314 824 /* ================ WDT ================ */
gkroussos 0:637031152314 825 /* ================================================================================ */
gkroussos 0:637031152314 826
gkroussos 0:637031152314 827
gkroussos 0:637031152314 828 /**
gkroussos 0:637031152314 829 * @brief Watchdog Timer. (WDT)
gkroussos 0:637031152314 830 */
gkroussos 0:637031152314 831
gkroussos 0:637031152314 832 typedef struct { /*!< WDT Structure */
gkroussos 0:637031152314 833 __O uint32_t TASKS_START; /*!< Start the watchdog. */
gkroussos 0:637031152314 834 __I uint32_t RESERVED0[63];
gkroussos 0:637031152314 835 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
gkroussos 0:637031152314 836 __I uint32_t RESERVED1[128];
gkroussos 0:637031152314 837 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 838 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 839 __I uint32_t RESERVED2[61];
gkroussos 0:637031152314 840 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
gkroussos 0:637031152314 841 __I uint32_t REQSTATUS; /*!< Request status. */
gkroussos 0:637031152314 842 __I uint32_t RESERVED3[63];
gkroussos 0:637031152314 843 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
gkroussos 0:637031152314 844 __IO uint32_t RREN; /*!< Reload request enable. */
gkroussos 0:637031152314 845 __IO uint32_t CONFIG; /*!< Configuration register. */
gkroussos 0:637031152314 846 __I uint32_t RESERVED4[60];
gkroussos 0:637031152314 847 __O uint32_t RR[8]; /*!< Reload requests registers. */
gkroussos 0:637031152314 848 __I uint32_t RESERVED5[631];
gkroussos 0:637031152314 849 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 850 } NRF_WDT_Type;
gkroussos 0:637031152314 851
gkroussos 0:637031152314 852
gkroussos 0:637031152314 853 /* ================================================================================ */
gkroussos 0:637031152314 854 /* ================ QDEC ================ */
gkroussos 0:637031152314 855 /* ================================================================================ */
gkroussos 0:637031152314 856
gkroussos 0:637031152314 857
gkroussos 0:637031152314 858 /**
gkroussos 0:637031152314 859 * @brief Rotary decoder. (QDEC)
gkroussos 0:637031152314 860 */
gkroussos 0:637031152314 861
gkroussos 0:637031152314 862 typedef struct { /*!< QDEC Structure */
gkroussos 0:637031152314 863 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
gkroussos 0:637031152314 864 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
gkroussos 0:637031152314 865 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
gkroussos 0:637031152314 866 and clears the ACC registers. */
gkroussos 0:637031152314 867 __I uint32_t RESERVED0[61];
gkroussos 0:637031152314 868 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
gkroussos 0:637031152314 869 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
gkroussos 0:637031152314 870 ACC register different than zero. */
gkroussos 0:637031152314 871 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
gkroussos 0:637031152314 872 __I uint32_t RESERVED1[61];
gkroussos 0:637031152314 873 __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */
gkroussos 0:637031152314 874 __I uint32_t RESERVED2[64];
gkroussos 0:637031152314 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 877 __I uint32_t RESERVED3[125];
gkroussos 0:637031152314 878 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
gkroussos 0:637031152314 879 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
gkroussos 0:637031152314 880 __IO uint32_t SAMPLEPER; /*!< Sample period. */
gkroussos 0:637031152314 881 __I int32_t SAMPLE; /*!< Motion sample value. */
gkroussos 0:637031152314 882 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
gkroussos 0:637031152314 883 __I int32_t ACC; /*!< Accumulated valid transitions register. */
gkroussos 0:637031152314 884 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
gkroussos 0:637031152314 885 task. */
gkroussos 0:637031152314 886 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
gkroussos 0:637031152314 887 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
gkroussos 0:637031152314 888 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
gkroussos 0:637031152314 889 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
gkroussos 0:637031152314 890 __I uint32_t RESERVED4[5];
gkroussos 0:637031152314 891 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
gkroussos 0:637031152314 892 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
gkroussos 0:637031152314 893 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
gkroussos 0:637031152314 894 task. */
gkroussos 0:637031152314 895 __I uint32_t RESERVED5[684];
gkroussos 0:637031152314 896 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 897 } NRF_QDEC_Type;
gkroussos 0:637031152314 898
gkroussos 0:637031152314 899
gkroussos 0:637031152314 900 /* ================================================================================ */
gkroussos 0:637031152314 901 /* ================ LPCOMP ================ */
gkroussos 0:637031152314 902 /* ================================================================================ */
gkroussos 0:637031152314 903
gkroussos 0:637031152314 904
gkroussos 0:637031152314 905 /**
gkroussos 0:637031152314 906 * @brief Wakeup Comparator. (LPCOMP)
gkroussos 0:637031152314 907 */
gkroussos 0:637031152314 908
gkroussos 0:637031152314 909 typedef struct { /*!< LPCOMP Structure */
gkroussos 0:637031152314 910 __O uint32_t TASKS_START; /*!< Start the comparator. */
gkroussos 0:637031152314 911 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
gkroussos 0:637031152314 912 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
gkroussos 0:637031152314 913 __I uint32_t RESERVED0[61];
gkroussos 0:637031152314 914 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
gkroussos 0:637031152314 915 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
gkroussos 0:637031152314 916 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
gkroussos 0:637031152314 917 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
gkroussos 0:637031152314 918 __I uint32_t RESERVED1[60];
gkroussos 0:637031152314 919 __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */
gkroussos 0:637031152314 920 __I uint32_t RESERVED2[64];
gkroussos 0:637031152314 921 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 922 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 923 __I uint32_t RESERVED3[61];
gkroussos 0:637031152314 924 __I uint32_t RESULT; /*!< Result of last compare. */
gkroussos 0:637031152314 925 __I uint32_t RESERVED4[63];
gkroussos 0:637031152314 926 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
gkroussos 0:637031152314 927 __IO uint32_t PSEL; /*!< Input pin select. */
gkroussos 0:637031152314 928 __IO uint32_t REFSEL; /*!< Reference select. */
gkroussos 0:637031152314 929 __IO uint32_t EXTREFSEL; /*!< External reference select. */
gkroussos 0:637031152314 930 __I uint32_t RESERVED5[4];
gkroussos 0:637031152314 931 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
gkroussos 0:637031152314 932 __I uint32_t RESERVED6[694];
gkroussos 0:637031152314 933 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 934 } NRF_LPCOMP_Type;
gkroussos 0:637031152314 935
gkroussos 0:637031152314 936
gkroussos 0:637031152314 937 /* ================================================================================ */
gkroussos 0:637031152314 938 /* ================ COMP ================ */
gkroussos 0:637031152314 939 /* ================================================================================ */
gkroussos 0:637031152314 940
gkroussos 0:637031152314 941
gkroussos 0:637031152314 942 /**
gkroussos 0:637031152314 943 * @brief Comparator. (COMP)
gkroussos 0:637031152314 944 */
gkroussos 0:637031152314 945
gkroussos 0:637031152314 946 typedef struct { /*!< COMP Structure */
gkroussos 0:637031152314 947 __O uint32_t TASKS_START; /*!< Start the comparator. */
gkroussos 0:637031152314 948 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
gkroussos 0:637031152314 949 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
gkroussos 0:637031152314 950 __I uint32_t RESERVED0[61];
gkroussos 0:637031152314 951 __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */
gkroussos 0:637031152314 952 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
gkroussos 0:637031152314 953 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
gkroussos 0:637031152314 954 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
gkroussos 0:637031152314 955 __I uint32_t RESERVED1[60];
gkroussos 0:637031152314 956 __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */
gkroussos 0:637031152314 957 __I uint32_t RESERVED2[64];
gkroussos 0:637031152314 958 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
gkroussos 0:637031152314 959 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
gkroussos 0:637031152314 960 __I uint32_t RESERVED3[61];
gkroussos 0:637031152314 961 __I uint32_t RESULT; /*!< Compare result. */
gkroussos 0:637031152314 962 __I uint32_t RESERVED4[63];
gkroussos 0:637031152314 963 __IO uint32_t ENABLE; /*!< Enable the COMP. */
gkroussos 0:637031152314 964 __IO uint32_t PSEL; /*!< Input pin select. */
gkroussos 0:637031152314 965 __IO uint32_t REFSEL; /*!< Reference select. */
gkroussos 0:637031152314 966 __IO uint32_t EXTREFSEL; /*!< External reference select. */
gkroussos 0:637031152314 967 __I uint32_t RESERVED5[8];
gkroussos 0:637031152314 968 __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */
gkroussos 0:637031152314 969 __IO uint32_t MODE; /*!< Mode configuration. */
gkroussos 0:637031152314 970 __I uint32_t RESERVED6[689];
gkroussos 0:637031152314 971 __IO uint32_t POWER; /*!< Peripheral power control. */
gkroussos 0:637031152314 972 } NRF_COMP_Type;
gkroussos 0:637031152314 973
gkroussos 0:637031152314 974
gkroussos 0:637031152314 975 /* ================================================================================ */
gkroussos 0:637031152314 976 /* ================ SWI ================ */
gkroussos 0:637031152314 977 /* ================================================================================ */
gkroussos 0:637031152314 978
gkroussos 0:637031152314 979
gkroussos 0:637031152314 980 /**
gkroussos 0:637031152314 981 * @brief SW Interrupts. (SWI)
gkroussos 0:637031152314 982 */
gkroussos 0:637031152314 983
gkroussos 0:637031152314 984 typedef struct { /*!< SWI Structure */
gkroussos 0:637031152314 985 __I uint32_t UNUSED; /*!< Unused. */
gkroussos 0:637031152314 986 } NRF_SWI_Type;
gkroussos 0:637031152314 987
gkroussos 0:637031152314 988
gkroussos 0:637031152314 989 /* ================================================================================ */
gkroussos 0:637031152314 990 /* ================ NVMC ================ */
gkroussos 0:637031152314 991 /* ================================================================================ */
gkroussos 0:637031152314 992
gkroussos 0:637031152314 993
gkroussos 0:637031152314 994 /**
gkroussos 0:637031152314 995 * @brief Non Volatile Memory Controller. (NVMC)
gkroussos 0:637031152314 996 */
gkroussos 0:637031152314 997
gkroussos 0:637031152314 998 typedef struct { /*!< NVMC Structure */
gkroussos 0:637031152314 999 __I uint32_t RESERVED0[256];
gkroussos 0:637031152314 1000 __I uint32_t READY; /*!< Ready flag. */
gkroussos 0:637031152314 1001 __I uint32_t RESERVED1[64];
gkroussos 0:637031152314 1002 __IO uint32_t CONFIG; /*!< Configuration register. */
gkroussos 0:637031152314 1003 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
gkroussos 0:637031152314 1004 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
gkroussos 0:637031152314 1005 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
gkroussos 0:637031152314 1006 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
gkroussos 0:637031152314 1007 } NRF_NVMC_Type;
gkroussos 0:637031152314 1008
gkroussos 0:637031152314 1009
gkroussos 0:637031152314 1010 /* ================================================================================ */
gkroussos 0:637031152314 1011 /* ================ PPI ================ */
gkroussos 0:637031152314 1012 /* ================================================================================ */
gkroussos 0:637031152314 1013
gkroussos 0:637031152314 1014
gkroussos 0:637031152314 1015 /**
gkroussos 0:637031152314 1016 * @brief PPI controller. (PPI)
gkroussos 0:637031152314 1017 */
gkroussos 0:637031152314 1018
gkroussos 0:637031152314 1019 typedef struct { /*!< PPI Structure */
gkroussos 0:637031152314 1020 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
gkroussos 0:637031152314 1021 __I uint32_t RESERVED0[312];
gkroussos 0:637031152314 1022 __IO uint32_t CHEN; /*!< Channel enable. */
gkroussos 0:637031152314 1023 __IO uint32_t CHENSET; /*!< Channel enable set. */
gkroussos 0:637031152314 1024 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
gkroussos 0:637031152314 1025 __I uint32_t RESERVED1;
gkroussos 0:637031152314 1026 PPI_CH_Type CH[16]; /*!< PPI Channel. */
gkroussos 0:637031152314 1027 __I uint32_t RESERVED2[156];
gkroussos 0:637031152314 1028 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
gkroussos 0:637031152314 1029 } NRF_PPI_Type;
gkroussos 0:637031152314 1030
gkroussos 0:637031152314 1031
gkroussos 0:637031152314 1032 /* ================================================================================ */
gkroussos 0:637031152314 1033 /* ================ FICR ================ */
gkroussos 0:637031152314 1034 /* ================================================================================ */
gkroussos 0:637031152314 1035
gkroussos 0:637031152314 1036
gkroussos 0:637031152314 1037 /**
gkroussos 0:637031152314 1038 * @brief Factory Information Configuration. (FICR)
gkroussos 0:637031152314 1039 */
gkroussos 0:637031152314 1040
gkroussos 0:637031152314 1041 typedef struct { /*!< FICR Structure */
gkroussos 0:637031152314 1042 __I uint32_t RESERVED0[4];
gkroussos 0:637031152314 1043 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
gkroussos 0:637031152314 1044 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
gkroussos 0:637031152314 1045 __I uint32_t RESERVED1[4];
gkroussos 0:637031152314 1046 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
gkroussos 0:637031152314 1047 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
gkroussos 0:637031152314 1048 __I uint32_t RESERVED2;
gkroussos 0:637031152314 1049 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
gkroussos 0:637031152314 1050 __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */
gkroussos 0:637031152314 1051 __I uint32_t RESERVED3[5];
gkroussos 0:637031152314 1052 __I uint32_t CONFIGID; /*!< Configuration identifier. */
gkroussos 0:637031152314 1053 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
gkroussos 0:637031152314 1054 __I uint32_t RESERVED4[6];
gkroussos 0:637031152314 1055 __I uint32_t ER[4]; /*!< Encryption root. */
gkroussos 0:637031152314 1056 __I uint32_t IR[4]; /*!< Identity root. */
gkroussos 0:637031152314 1057 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
gkroussos 0:637031152314 1058 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
gkroussos 0:637031152314 1059 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
gkroussos 0:637031152314 1060 __I uint32_t RESERVED5[15];
gkroussos 0:637031152314 1061 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
gkroussos 0:637031152314 1062 mode. */
gkroussos 0:637031152314 1063 } NRF_FICR_Type;
gkroussos 0:637031152314 1064
gkroussos 0:637031152314 1065
gkroussos 0:637031152314 1066 /* ================================================================================ */
gkroussos 0:637031152314 1067 /* ================ UICR ================ */
gkroussos 0:637031152314 1068 /* ================================================================================ */
gkroussos 0:637031152314 1069
gkroussos 0:637031152314 1070
gkroussos 0:637031152314 1071 /**
gkroussos 0:637031152314 1072 * @brief User Information Configuration. (UICR)
gkroussos 0:637031152314 1073 */
gkroussos 0:637031152314 1074
gkroussos 0:637031152314 1075 typedef struct { /*!< UICR Structure */
gkroussos 0:637031152314 1076 __IO uint32_t CLENR0; /*!< Length of code region 0. */
gkroussos 0:637031152314 1077 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
gkroussos 0:637031152314 1078 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
gkroussos 0:637031152314 1079 __I uint32_t RESERVED0;
gkroussos 0:637031152314 1080 __I uint32_t FWID; /*!< Firmware ID. */
gkroussos 0:637031152314 1081 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
gkroussos 0:637031152314 1082 } NRF_UICR_Type;
gkroussos 0:637031152314 1083
gkroussos 0:637031152314 1084
gkroussos 0:637031152314 1085 /* ================================================================================ */
gkroussos 0:637031152314 1086 /* ================ GPIO ================ */
gkroussos 0:637031152314 1087 /* ================================================================================ */
gkroussos 0:637031152314 1088
gkroussos 0:637031152314 1089
gkroussos 0:637031152314 1090 /**
gkroussos 0:637031152314 1091 * @brief General purpose input and output. (GPIO)
gkroussos 0:637031152314 1092 */
gkroussos 0:637031152314 1093
gkroussos 0:637031152314 1094 typedef struct { /*!< GPIO Structure */
gkroussos 0:637031152314 1095 __I uint32_t RESERVED0[321];
gkroussos 0:637031152314 1096 __IO uint32_t OUT; /*!< Write GPIO port. */
gkroussos 0:637031152314 1097 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
gkroussos 0:637031152314 1098 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
gkroussos 0:637031152314 1099 __I uint32_t IN; /*!< Read GPIO port. */
gkroussos 0:637031152314 1100 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
gkroussos 0:637031152314 1101 __IO uint32_t DIRSET; /*!< DIR set register. */
gkroussos 0:637031152314 1102 __IO uint32_t DIRCLR; /*!< DIR clear register. */
gkroussos 0:637031152314 1103 __I uint32_t RESERVED1[120];
gkroussos 0:637031152314 1104 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
gkroussos 0:637031152314 1105 } NRF_GPIO_Type;
gkroussos 0:637031152314 1106
gkroussos 0:637031152314 1107
gkroussos 0:637031152314 1108 /* -------------------- End of section using anonymous unions ------------------- */
gkroussos 0:637031152314 1109 #if defined(__CC_ARM)
gkroussos 0:637031152314 1110 #pragma pop
gkroussos 0:637031152314 1111 #elif defined(__ICCARM__)
gkroussos 0:637031152314 1112 /* leave anonymous unions enabled */
gkroussos 0:637031152314 1113 #elif defined(__GNUC__)
gkroussos 0:637031152314 1114 /* anonymous unions are enabled by default */
gkroussos 0:637031152314 1115 #elif defined(__TMS470__)
gkroussos 0:637031152314 1116 /* anonymous unions are enabled by default */
gkroussos 0:637031152314 1117 #elif defined(__TASKING__)
gkroussos 0:637031152314 1118 #pragma warning restore
gkroussos 0:637031152314 1119 #else
gkroussos 0:637031152314 1120 #warning Not supported compiler type
gkroussos 0:637031152314 1121 #endif
gkroussos 0:637031152314 1122
gkroussos 0:637031152314 1123
gkroussos 0:637031152314 1124
gkroussos 0:637031152314 1125
gkroussos 0:637031152314 1126 /* ================================================================================ */
gkroussos 0:637031152314 1127 /* ================ Peripheral memory map ================ */
gkroussos 0:637031152314 1128 /* ================================================================================ */
gkroussos 0:637031152314 1129
gkroussos 0:637031152314 1130 #define NRF_POWER_BASE 0x40000000UL
gkroussos 0:637031152314 1131 #define NRF_CLOCK_BASE 0x40000000UL
gkroussos 0:637031152314 1132 #define NRF_MPU_BASE 0x40000000UL
gkroussos 0:637031152314 1133 #define NRF_PU_BASE 0x40000000UL
gkroussos 0:637031152314 1134 #define NRF_AMLI_BASE 0x40000000UL
gkroussos 0:637031152314 1135 #define NRF_RADIO_BASE 0x40001000UL
gkroussos 0:637031152314 1136 #define NRF_UART0_BASE 0x40002000UL
gkroussos 0:637031152314 1137 #define NRF_SPI0_BASE 0x40003000UL
gkroussos 0:637031152314 1138 #define NRF_TWI0_BASE 0x40003000UL
gkroussos 0:637031152314 1139 #define NRF_SPI1_BASE 0x40004000UL
gkroussos 0:637031152314 1140 #define NRF_TWI1_BASE 0x40004000UL
gkroussos 0:637031152314 1141 #define NRF_SPIS1_BASE 0x40004000UL
gkroussos 0:637031152314 1142 #define NRF_GPIOTE_BASE 0x40006000UL
gkroussos 0:637031152314 1143 #define NRF_ADC_BASE 0x40007000UL
gkroussos 0:637031152314 1144 #define NRF_TIMER0_BASE 0x40008000UL
gkroussos 0:637031152314 1145 #define NRF_TIMER1_BASE 0x40009000UL
gkroussos 0:637031152314 1146 #define NRF_TIMER2_BASE 0x4000A000UL
gkroussos 0:637031152314 1147 #define NRF_RTC0_BASE 0x4000B000UL
gkroussos 0:637031152314 1148 #define NRF_TEMP_BASE 0x4000C000UL
gkroussos 0:637031152314 1149 #define NRF_RNG_BASE 0x4000D000UL
gkroussos 0:637031152314 1150 #define NRF_ECB_BASE 0x4000E000UL
gkroussos 0:637031152314 1151 #define NRF_AAR_BASE 0x4000F000UL
gkroussos 0:637031152314 1152 #define NRF_CCM_BASE 0x4000F000UL
gkroussos 0:637031152314 1153 #define NRF_WDT_BASE 0x40010000UL
gkroussos 0:637031152314 1154 #define NRF_RTC1_BASE 0x40011000UL
gkroussos 0:637031152314 1155 #define NRF_QDEC_BASE 0x40012000UL
gkroussos 0:637031152314 1156 #define NRF_LPCOMP_BASE 0x40013000UL
gkroussos 0:637031152314 1157 #define NRF_COMP_BASE 0x40013000UL
gkroussos 0:637031152314 1158 #define NRF_SWI_BASE 0x40014000UL
gkroussos 0:637031152314 1159 #define NRF_NVMC_BASE 0x4001E000UL
gkroussos 0:637031152314 1160 #define NRF_PPI_BASE 0x4001F000UL
gkroussos 0:637031152314 1161 #define NRF_FICR_BASE 0x10000000UL
gkroussos 0:637031152314 1162 #define NRF_UICR_BASE 0x10001000UL
gkroussos 0:637031152314 1163 #define NRF_GPIO_BASE 0x50000000UL
gkroussos 0:637031152314 1164
gkroussos 0:637031152314 1165
gkroussos 0:637031152314 1166 /* ================================================================================ */
gkroussos 0:637031152314 1167 /* ================ Peripheral declaration ================ */
gkroussos 0:637031152314 1168 /* ================================================================================ */
gkroussos 0:637031152314 1169
gkroussos 0:637031152314 1170 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
gkroussos 0:637031152314 1171 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
gkroussos 0:637031152314 1172 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
gkroussos 0:637031152314 1173 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
gkroussos 0:637031152314 1174 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
gkroussos 0:637031152314 1175 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
gkroussos 0:637031152314 1176 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
gkroussos 0:637031152314 1177 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
gkroussos 0:637031152314 1178 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
gkroussos 0:637031152314 1179 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
gkroussos 0:637031152314 1180 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
gkroussos 0:637031152314 1181 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
gkroussos 0:637031152314 1182 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
gkroussos 0:637031152314 1183 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
gkroussos 0:637031152314 1184 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
gkroussos 0:637031152314 1185 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
gkroussos 0:637031152314 1186 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
gkroussos 0:637031152314 1187 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
gkroussos 0:637031152314 1188 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
gkroussos 0:637031152314 1189 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
gkroussos 0:637031152314 1190 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
gkroussos 0:637031152314 1191 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
gkroussos 0:637031152314 1192 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
gkroussos 0:637031152314 1193 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
gkroussos 0:637031152314 1194 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
gkroussos 0:637031152314 1195 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
gkroussos 0:637031152314 1196 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
gkroussos 0:637031152314 1197 #define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
gkroussos 0:637031152314 1198 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
gkroussos 0:637031152314 1199 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
gkroussos 0:637031152314 1200 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
gkroussos 0:637031152314 1201 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
gkroussos 0:637031152314 1202 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
gkroussos 0:637031152314 1203 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
gkroussos 0:637031152314 1204
gkroussos 0:637031152314 1205
gkroussos 0:637031152314 1206 /** @} */ /* End of group Device_Peripheral_Registers */
gkroussos 0:637031152314 1207 /** @} */ /* End of group nRF51 */
gkroussos 0:637031152314 1208 /** @} */ /* End of group Nordic Semiconductor */
gkroussos 0:637031152314 1209
gkroussos 0:637031152314 1210 #ifdef __cplusplus
gkroussos 0:637031152314 1211 }
gkroussos 0:637031152314 1212 #endif
gkroussos 0:637031152314 1213
gkroussos 0:637031152314 1214
gkroussos 0:637031152314 1215 #endif /* nRF51_H */
gkroussos 0:637031152314 1216