George Roussos / BLE_Temperature

BLE temperature profile using digital DS1820 or analog LM35 sensors

Dependencies:   DS1820

mbed/TARGET_NRF51822/core_cm4_simd.h@0:637031152314, 2015-03-07 (annotated)

Committer:
gkroussos
Date:
Sat Mar 07 16:23:41 2015 +0000
Revision:
0:637031152314
Working version 1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gkroussos 0:637031152314 1 /**************************************************************************//**
gkroussos 0:637031152314 2 * @file core_cm4_simd.h
gkroussos 0:637031152314 3 * @brief CMSIS Cortex-M4 SIMD Header File
gkroussos 0:637031152314 4 * @version V3.20
gkroussos 0:637031152314 5 * @date 25. February 2013
gkroussos 0:637031152314 6 *
gkroussos 0:637031152314 7 * @note
gkroussos 0:637031152314 8 *
gkroussos 0:637031152314 9 ******************************************************************************/
gkroussos 0:637031152314 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
gkroussos 0:637031152314 11
gkroussos 0:637031152314 12 All rights reserved.
gkroussos 0:637031152314 13 Redistribution and use in source and binary forms, with or without
gkroussos 0:637031152314 14 modification, are permitted provided that the following conditions are met:
gkroussos 0:637031152314 15 - Redistributions of source code must retain the above copyright
gkroussos 0:637031152314 16 notice, this list of conditions and the following disclaimer.
gkroussos 0:637031152314 17 - Redistributions in binary form must reproduce the above copyright
gkroussos 0:637031152314 18 notice, this list of conditions and the following disclaimer in the
gkroussos 0:637031152314 19 documentation and/or other materials provided with the distribution.
gkroussos 0:637031152314 20 - Neither the name of ARM nor the names of its contributors may be used
gkroussos 0:637031152314 21 to endorse or promote products derived from this software without
gkroussos 0:637031152314 22 specific prior written permission.
gkroussos 0:637031152314 23 *
gkroussos 0:637031152314 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
gkroussos 0:637031152314 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
gkroussos 0:637031152314 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
gkroussos 0:637031152314 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
gkroussos 0:637031152314 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
gkroussos 0:637031152314 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
gkroussos 0:637031152314 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
gkroussos 0:637031152314 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
gkroussos 0:637031152314 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
gkroussos 0:637031152314 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
gkroussos 0:637031152314 34 POSSIBILITY OF SUCH DAMAGE.
gkroussos 0:637031152314 35 ---------------------------------------------------------------------------*/
gkroussos 0:637031152314 36
gkroussos 0:637031152314 37
gkroussos 0:637031152314 38 #ifdef __cplusplus
gkroussos 0:637031152314 39 extern "C" {
gkroussos 0:637031152314 40 #endif
gkroussos 0:637031152314 41
gkroussos 0:637031152314 42 #ifndef __CORE_CM4_SIMD_H
gkroussos 0:637031152314 43 #define __CORE_CM4_SIMD_H
gkroussos 0:637031152314 44
gkroussos 0:637031152314 45
gkroussos 0:637031152314 46 /*******************************************************************************
gkroussos 0:637031152314 47 * Hardware Abstraction Layer
gkroussos 0:637031152314 48 ******************************************************************************/
gkroussos 0:637031152314 49
gkroussos 0:637031152314 50
gkroussos 0:637031152314 51 /* ################### Compiler specific Intrinsics ########################### */
gkroussos 0:637031152314 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
gkroussos 0:637031152314 53 Access to dedicated SIMD instructions
gkroussos 0:637031152314 54 @{
gkroussos 0:637031152314 55 */
gkroussos 0:637031152314 56
gkroussos 0:637031152314 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
gkroussos 0:637031152314 58 /* ARM armcc specific functions */
gkroussos 0:637031152314 59
gkroussos 0:637031152314 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:637031152314 61 #define __SADD8 __sadd8
gkroussos 0:637031152314 62 #define __QADD8 __qadd8
gkroussos 0:637031152314 63 #define __SHADD8 __shadd8
gkroussos 0:637031152314 64 #define __UADD8 __uadd8
gkroussos 0:637031152314 65 #define __UQADD8 __uqadd8
gkroussos 0:637031152314 66 #define __UHADD8 __uhadd8
gkroussos 0:637031152314 67 #define __SSUB8 __ssub8
gkroussos 0:637031152314 68 #define __QSUB8 __qsub8
gkroussos 0:637031152314 69 #define __SHSUB8 __shsub8
gkroussos 0:637031152314 70 #define __USUB8 __usub8
gkroussos 0:637031152314 71 #define __UQSUB8 __uqsub8
gkroussos 0:637031152314 72 #define __UHSUB8 __uhsub8
gkroussos 0:637031152314 73 #define __SADD16 __sadd16
gkroussos 0:637031152314 74 #define __QADD16 __qadd16
gkroussos 0:637031152314 75 #define __SHADD16 __shadd16
gkroussos 0:637031152314 76 #define __UADD16 __uadd16
gkroussos 0:637031152314 77 #define __UQADD16 __uqadd16
gkroussos 0:637031152314 78 #define __UHADD16 __uhadd16
gkroussos 0:637031152314 79 #define __SSUB16 __ssub16
gkroussos 0:637031152314 80 #define __QSUB16 __qsub16
gkroussos 0:637031152314 81 #define __SHSUB16 __shsub16
gkroussos 0:637031152314 82 #define __USUB16 __usub16
gkroussos 0:637031152314 83 #define __UQSUB16 __uqsub16
gkroussos 0:637031152314 84 #define __UHSUB16 __uhsub16
gkroussos 0:637031152314 85 #define __SASX __sasx
gkroussos 0:637031152314 86 #define __QASX __qasx
gkroussos 0:637031152314 87 #define __SHASX __shasx
gkroussos 0:637031152314 88 #define __UASX __uasx
gkroussos 0:637031152314 89 #define __UQASX __uqasx
gkroussos 0:637031152314 90 #define __UHASX __uhasx
gkroussos 0:637031152314 91 #define __SSAX __ssax
gkroussos 0:637031152314 92 #define __QSAX __qsax
gkroussos 0:637031152314 93 #define __SHSAX __shsax
gkroussos 0:637031152314 94 #define __USAX __usax
gkroussos 0:637031152314 95 #define __UQSAX __uqsax
gkroussos 0:637031152314 96 #define __UHSAX __uhsax
gkroussos 0:637031152314 97 #define __USAD8 __usad8
gkroussos 0:637031152314 98 #define __USADA8 __usada8
gkroussos 0:637031152314 99 #define __SSAT16 __ssat16
gkroussos 0:637031152314 100 #define __USAT16 __usat16
gkroussos 0:637031152314 101 #define __UXTB16 __uxtb16
gkroussos 0:637031152314 102 #define __UXTAB16 __uxtab16
gkroussos 0:637031152314 103 #define __SXTB16 __sxtb16
gkroussos 0:637031152314 104 #define __SXTAB16 __sxtab16
gkroussos 0:637031152314 105 #define __SMUAD __smuad
gkroussos 0:637031152314 106 #define __SMUADX __smuadx
gkroussos 0:637031152314 107 #define __SMLAD __smlad
gkroussos 0:637031152314 108 #define __SMLADX __smladx
gkroussos 0:637031152314 109 #define __SMLALD __smlald
gkroussos 0:637031152314 110 #define __SMLALDX __smlaldx
gkroussos 0:637031152314 111 #define __SMUSD __smusd
gkroussos 0:637031152314 112 #define __SMUSDX __smusdx
gkroussos 0:637031152314 113 #define __SMLSD __smlsd
gkroussos 0:637031152314 114 #define __SMLSDX __smlsdx
gkroussos 0:637031152314 115 #define __SMLSLD __smlsld
gkroussos 0:637031152314 116 #define __SMLSLDX __smlsldx
gkroussos 0:637031152314 117 #define __SEL __sel
gkroussos 0:637031152314 118 #define __QADD __qadd
gkroussos 0:637031152314 119 #define __QSUB __qsub
gkroussos 0:637031152314 120
gkroussos 0:637031152314 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
gkroussos 0:637031152314 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
gkroussos 0:637031152314 123
gkroussos 0:637031152314 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
gkroussos 0:637031152314 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
gkroussos 0:637031152314 126
gkroussos 0:637031152314 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
gkroussos 0:637031152314 128 ((int64_t)(ARG3) << 32) ) >> 32))
gkroussos 0:637031152314 129
gkroussos 0:637031152314 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:637031152314 131
gkroussos 0:637031152314 132
gkroussos 0:637031152314 133
gkroussos 0:637031152314 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
gkroussos 0:637031152314 135 /* IAR iccarm specific functions */
gkroussos 0:637031152314 136
gkroussos 0:637031152314 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:637031152314 138 #include <cmsis_iar.h>
gkroussos 0:637031152314 139
gkroussos 0:637031152314 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:637031152314 141
gkroussos 0:637031152314 142
gkroussos 0:637031152314 143
gkroussos 0:637031152314 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
gkroussos 0:637031152314 145 /* TI CCS specific functions */
gkroussos 0:637031152314 146
gkroussos 0:637031152314 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:637031152314 148 #include <cmsis_ccs.h>
gkroussos 0:637031152314 149
gkroussos 0:637031152314 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:637031152314 151
gkroussos 0:637031152314 152
gkroussos 0:637031152314 153
gkroussos 0:637031152314 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
gkroussos 0:637031152314 155 /* GNU gcc specific functions */
gkroussos 0:637031152314 156
gkroussos 0:637031152314 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:637031152314 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 159 {
gkroussos 0:637031152314 160 uint32_t result;
gkroussos 0:637031152314 161
gkroussos 0:637031152314 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 163 return(result);
gkroussos 0:637031152314 164 }
gkroussos 0:637031152314 165
gkroussos 0:637031152314 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 167 {
gkroussos 0:637031152314 168 uint32_t result;
gkroussos 0:637031152314 169
gkroussos 0:637031152314 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 171 return(result);
gkroussos 0:637031152314 172 }
gkroussos 0:637031152314 173
gkroussos 0:637031152314 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 175 {
gkroussos 0:637031152314 176 uint32_t result;
gkroussos 0:637031152314 177
gkroussos 0:637031152314 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 179 return(result);
gkroussos 0:637031152314 180 }
gkroussos 0:637031152314 181
gkroussos 0:637031152314 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 183 {
gkroussos 0:637031152314 184 uint32_t result;
gkroussos 0:637031152314 185
gkroussos 0:637031152314 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 187 return(result);
gkroussos 0:637031152314 188 }
gkroussos 0:637031152314 189
gkroussos 0:637031152314 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 191 {
gkroussos 0:637031152314 192 uint32_t result;
gkroussos 0:637031152314 193
gkroussos 0:637031152314 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 195 return(result);
gkroussos 0:637031152314 196 }
gkroussos 0:637031152314 197
gkroussos 0:637031152314 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 199 {
gkroussos 0:637031152314 200 uint32_t result;
gkroussos 0:637031152314 201
gkroussos 0:637031152314 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 203 return(result);
gkroussos 0:637031152314 204 }
gkroussos 0:637031152314 205
gkroussos 0:637031152314 206
gkroussos 0:637031152314 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 208 {
gkroussos 0:637031152314 209 uint32_t result;
gkroussos 0:637031152314 210
gkroussos 0:637031152314 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 212 return(result);
gkroussos 0:637031152314 213 }
gkroussos 0:637031152314 214
gkroussos 0:637031152314 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 216 {
gkroussos 0:637031152314 217 uint32_t result;
gkroussos 0:637031152314 218
gkroussos 0:637031152314 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 220 return(result);
gkroussos 0:637031152314 221 }
gkroussos 0:637031152314 222
gkroussos 0:637031152314 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 224 {
gkroussos 0:637031152314 225 uint32_t result;
gkroussos 0:637031152314 226
gkroussos 0:637031152314 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 228 return(result);
gkroussos 0:637031152314 229 }
gkroussos 0:637031152314 230
gkroussos 0:637031152314 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 232 {
gkroussos 0:637031152314 233 uint32_t result;
gkroussos 0:637031152314 234
gkroussos 0:637031152314 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 236 return(result);
gkroussos 0:637031152314 237 }
gkroussos 0:637031152314 238
gkroussos 0:637031152314 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 240 {
gkroussos 0:637031152314 241 uint32_t result;
gkroussos 0:637031152314 242
gkroussos 0:637031152314 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 244 return(result);
gkroussos 0:637031152314 245 }
gkroussos 0:637031152314 246
gkroussos 0:637031152314 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 248 {
gkroussos 0:637031152314 249 uint32_t result;
gkroussos 0:637031152314 250
gkroussos 0:637031152314 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 252 return(result);
gkroussos 0:637031152314 253 }
gkroussos 0:637031152314 254
gkroussos 0:637031152314 255
gkroussos 0:637031152314 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 257 {
gkroussos 0:637031152314 258 uint32_t result;
gkroussos 0:637031152314 259
gkroussos 0:637031152314 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 261 return(result);
gkroussos 0:637031152314 262 }
gkroussos 0:637031152314 263
gkroussos 0:637031152314 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 265 {
gkroussos 0:637031152314 266 uint32_t result;
gkroussos 0:637031152314 267
gkroussos 0:637031152314 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 269 return(result);
gkroussos 0:637031152314 270 }
gkroussos 0:637031152314 271
gkroussos 0:637031152314 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 273 {
gkroussos 0:637031152314 274 uint32_t result;
gkroussos 0:637031152314 275
gkroussos 0:637031152314 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 277 return(result);
gkroussos 0:637031152314 278 }
gkroussos 0:637031152314 279
gkroussos 0:637031152314 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 281 {
gkroussos 0:637031152314 282 uint32_t result;
gkroussos 0:637031152314 283
gkroussos 0:637031152314 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 285 return(result);
gkroussos 0:637031152314 286 }
gkroussos 0:637031152314 287
gkroussos 0:637031152314 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 289 {
gkroussos 0:637031152314 290 uint32_t result;
gkroussos 0:637031152314 291
gkroussos 0:637031152314 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 293 return(result);
gkroussos 0:637031152314 294 }
gkroussos 0:637031152314 295
gkroussos 0:637031152314 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 297 {
gkroussos 0:637031152314 298 uint32_t result;
gkroussos 0:637031152314 299
gkroussos 0:637031152314 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 301 return(result);
gkroussos 0:637031152314 302 }
gkroussos 0:637031152314 303
gkroussos 0:637031152314 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 305 {
gkroussos 0:637031152314 306 uint32_t result;
gkroussos 0:637031152314 307
gkroussos 0:637031152314 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 309 return(result);
gkroussos 0:637031152314 310 }
gkroussos 0:637031152314 311
gkroussos 0:637031152314 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 313 {
gkroussos 0:637031152314 314 uint32_t result;
gkroussos 0:637031152314 315
gkroussos 0:637031152314 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 317 return(result);
gkroussos 0:637031152314 318 }
gkroussos 0:637031152314 319
gkroussos 0:637031152314 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 321 {
gkroussos 0:637031152314 322 uint32_t result;
gkroussos 0:637031152314 323
gkroussos 0:637031152314 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 325 return(result);
gkroussos 0:637031152314 326 }
gkroussos 0:637031152314 327
gkroussos 0:637031152314 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 329 {
gkroussos 0:637031152314 330 uint32_t result;
gkroussos 0:637031152314 331
gkroussos 0:637031152314 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 333 return(result);
gkroussos 0:637031152314 334 }
gkroussos 0:637031152314 335
gkroussos 0:637031152314 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 337 {
gkroussos 0:637031152314 338 uint32_t result;
gkroussos 0:637031152314 339
gkroussos 0:637031152314 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 341 return(result);
gkroussos 0:637031152314 342 }
gkroussos 0:637031152314 343
gkroussos 0:637031152314 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 345 {
gkroussos 0:637031152314 346 uint32_t result;
gkroussos 0:637031152314 347
gkroussos 0:637031152314 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 349 return(result);
gkroussos 0:637031152314 350 }
gkroussos 0:637031152314 351
gkroussos 0:637031152314 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 353 {
gkroussos 0:637031152314 354 uint32_t result;
gkroussos 0:637031152314 355
gkroussos 0:637031152314 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 357 return(result);
gkroussos 0:637031152314 358 }
gkroussos 0:637031152314 359
gkroussos 0:637031152314 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 361 {
gkroussos 0:637031152314 362 uint32_t result;
gkroussos 0:637031152314 363
gkroussos 0:637031152314 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 365 return(result);
gkroussos 0:637031152314 366 }
gkroussos 0:637031152314 367
gkroussos 0:637031152314 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 369 {
gkroussos 0:637031152314 370 uint32_t result;
gkroussos 0:637031152314 371
gkroussos 0:637031152314 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 373 return(result);
gkroussos 0:637031152314 374 }
gkroussos 0:637031152314 375
gkroussos 0:637031152314 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 377 {
gkroussos 0:637031152314 378 uint32_t result;
gkroussos 0:637031152314 379
gkroussos 0:637031152314 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 381 return(result);
gkroussos 0:637031152314 382 }
gkroussos 0:637031152314 383
gkroussos 0:637031152314 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 385 {
gkroussos 0:637031152314 386 uint32_t result;
gkroussos 0:637031152314 387
gkroussos 0:637031152314 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 389 return(result);
gkroussos 0:637031152314 390 }
gkroussos 0:637031152314 391
gkroussos 0:637031152314 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 393 {
gkroussos 0:637031152314 394 uint32_t result;
gkroussos 0:637031152314 395
gkroussos 0:637031152314 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 397 return(result);
gkroussos 0:637031152314 398 }
gkroussos 0:637031152314 399
gkroussos 0:637031152314 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 401 {
gkroussos 0:637031152314 402 uint32_t result;
gkroussos 0:637031152314 403
gkroussos 0:637031152314 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 405 return(result);
gkroussos 0:637031152314 406 }
gkroussos 0:637031152314 407
gkroussos 0:637031152314 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 409 {
gkroussos 0:637031152314 410 uint32_t result;
gkroussos 0:637031152314 411
gkroussos 0:637031152314 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 413 return(result);
gkroussos 0:637031152314 414 }
gkroussos 0:637031152314 415
gkroussos 0:637031152314 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 417 {
gkroussos 0:637031152314 418 uint32_t result;
gkroussos 0:637031152314 419
gkroussos 0:637031152314 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 421 return(result);
gkroussos 0:637031152314 422 }
gkroussos 0:637031152314 423
gkroussos 0:637031152314 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 425 {
gkroussos 0:637031152314 426 uint32_t result;
gkroussos 0:637031152314 427
gkroussos 0:637031152314 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 429 return(result);
gkroussos 0:637031152314 430 }
gkroussos 0:637031152314 431
gkroussos 0:637031152314 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 433 {
gkroussos 0:637031152314 434 uint32_t result;
gkroussos 0:637031152314 435
gkroussos 0:637031152314 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 437 return(result);
gkroussos 0:637031152314 438 }
gkroussos 0:637031152314 439
gkroussos 0:637031152314 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 441 {
gkroussos 0:637031152314 442 uint32_t result;
gkroussos 0:637031152314 443
gkroussos 0:637031152314 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 445 return(result);
gkroussos 0:637031152314 446 }
gkroussos 0:637031152314 447
gkroussos 0:637031152314 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 449 {
gkroussos 0:637031152314 450 uint32_t result;
gkroussos 0:637031152314 451
gkroussos 0:637031152314 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 453 return(result);
gkroussos 0:637031152314 454 }
gkroussos 0:637031152314 455
gkroussos 0:637031152314 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
gkroussos 0:637031152314 457 {
gkroussos 0:637031152314 458 uint32_t result;
gkroussos 0:637031152314 459
gkroussos 0:637031152314 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gkroussos 0:637031152314 461 return(result);
gkroussos 0:637031152314 462 }
gkroussos 0:637031152314 463
gkroussos 0:637031152314 464 #define __SSAT16(ARG1,ARG2) \
gkroussos 0:637031152314 465 ({ \
gkroussos 0:637031152314 466 uint32_t __RES, __ARG1 = (ARG1); \
gkroussos 0:637031152314 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
gkroussos 0:637031152314 468 __RES; \
gkroussos 0:637031152314 469 })
gkroussos 0:637031152314 470
gkroussos 0:637031152314 471 #define __USAT16(ARG1,ARG2) \
gkroussos 0:637031152314 472 ({ \
gkroussos 0:637031152314 473 uint32_t __RES, __ARG1 = (ARG1); \
gkroussos 0:637031152314 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
gkroussos 0:637031152314 475 __RES; \
gkroussos 0:637031152314 476 })
gkroussos 0:637031152314 477
gkroussos 0:637031152314 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
gkroussos 0:637031152314 479 {
gkroussos 0:637031152314 480 uint32_t result;
gkroussos 0:637031152314 481
gkroussos 0:637031152314 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
gkroussos 0:637031152314 483 return(result);
gkroussos 0:637031152314 484 }
gkroussos 0:637031152314 485
gkroussos 0:637031152314 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 487 {
gkroussos 0:637031152314 488 uint32_t result;
gkroussos 0:637031152314 489
gkroussos 0:637031152314 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 491 return(result);
gkroussos 0:637031152314 492 }
gkroussos 0:637031152314 493
gkroussos 0:637031152314 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
gkroussos 0:637031152314 495 {
gkroussos 0:637031152314 496 uint32_t result;
gkroussos 0:637031152314 497
gkroussos 0:637031152314 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
gkroussos 0:637031152314 499 return(result);
gkroussos 0:637031152314 500 }
gkroussos 0:637031152314 501
gkroussos 0:637031152314 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 503 {
gkroussos 0:637031152314 504 uint32_t result;
gkroussos 0:637031152314 505
gkroussos 0:637031152314 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 507 return(result);
gkroussos 0:637031152314 508 }
gkroussos 0:637031152314 509
gkroussos 0:637031152314 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 511 {
gkroussos 0:637031152314 512 uint32_t result;
gkroussos 0:637031152314 513
gkroussos 0:637031152314 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 515 return(result);
gkroussos 0:637031152314 516 }
gkroussos 0:637031152314 517
gkroussos 0:637031152314 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 519 {
gkroussos 0:637031152314 520 uint32_t result;
gkroussos 0:637031152314 521
gkroussos 0:637031152314 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 523 return(result);
gkroussos 0:637031152314 524 }
gkroussos 0:637031152314 525
gkroussos 0:637031152314 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
gkroussos 0:637031152314 527 {
gkroussos 0:637031152314 528 uint32_t result;
gkroussos 0:637031152314 529
gkroussos 0:637031152314 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gkroussos 0:637031152314 531 return(result);
gkroussos 0:637031152314 532 }
gkroussos 0:637031152314 533
gkroussos 0:637031152314 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
gkroussos 0:637031152314 535 {
gkroussos 0:637031152314 536 uint32_t result;
gkroussos 0:637031152314 537
gkroussos 0:637031152314 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gkroussos 0:637031152314 539 return(result);
gkroussos 0:637031152314 540 }
gkroussos 0:637031152314 541
gkroussos 0:637031152314 542 #define __SMLALD(ARG1,ARG2,ARG3) \
gkroussos 0:637031152314 543 ({ \
gkroussos 0:637031152314 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
gkroussos 0:637031152314 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
gkroussos 0:637031152314 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
gkroussos 0:637031152314 547 })
gkroussos 0:637031152314 548
gkroussos 0:637031152314 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
gkroussos 0:637031152314 550 ({ \
gkroussos 0:637031152314 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
gkroussos 0:637031152314 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
gkroussos 0:637031152314 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
gkroussos 0:637031152314 554 })
gkroussos 0:637031152314 555
gkroussos 0:637031152314 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 557 {
gkroussos 0:637031152314 558 uint32_t result;
gkroussos 0:637031152314 559
gkroussos 0:637031152314 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 561 return(result);
gkroussos 0:637031152314 562 }
gkroussos 0:637031152314 563
gkroussos 0:637031152314 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 565 {
gkroussos 0:637031152314 566 uint32_t result;
gkroussos 0:637031152314 567
gkroussos 0:637031152314 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 569 return(result);
gkroussos 0:637031152314 570 }
gkroussos 0:637031152314 571
gkroussos 0:637031152314 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
gkroussos 0:637031152314 573 {
gkroussos 0:637031152314 574 uint32_t result;
gkroussos 0:637031152314 575
gkroussos 0:637031152314 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gkroussos 0:637031152314 577 return(result);
gkroussos 0:637031152314 578 }
gkroussos 0:637031152314 579
gkroussos 0:637031152314 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
gkroussos 0:637031152314 581 {
gkroussos 0:637031152314 582 uint32_t result;
gkroussos 0:637031152314 583
gkroussos 0:637031152314 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gkroussos 0:637031152314 585 return(result);
gkroussos 0:637031152314 586 }
gkroussos 0:637031152314 587
gkroussos 0:637031152314 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
gkroussos 0:637031152314 589 ({ \
gkroussos 0:637031152314 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
gkroussos 0:637031152314 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
gkroussos 0:637031152314 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
gkroussos 0:637031152314 593 })
gkroussos 0:637031152314 594
gkroussos 0:637031152314 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
gkroussos 0:637031152314 596 ({ \
gkroussos 0:637031152314 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
gkroussos 0:637031152314 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
gkroussos 0:637031152314 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
gkroussos 0:637031152314 600 })
gkroussos 0:637031152314 601
gkroussos 0:637031152314 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 603 {
gkroussos 0:637031152314 604 uint32_t result;
gkroussos 0:637031152314 605
gkroussos 0:637031152314 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 607 return(result);
gkroussos 0:637031152314 608 }
gkroussos 0:637031152314 609
gkroussos 0:637031152314 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 611 {
gkroussos 0:637031152314 612 uint32_t result;
gkroussos 0:637031152314 613
gkroussos 0:637031152314 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 615 return(result);
gkroussos 0:637031152314 616 }
gkroussos 0:637031152314 617
gkroussos 0:637031152314 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
gkroussos 0:637031152314 619 {
gkroussos 0:637031152314 620 uint32_t result;
gkroussos 0:637031152314 621
gkroussos 0:637031152314 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gkroussos 0:637031152314 623 return(result);
gkroussos 0:637031152314 624 }
gkroussos 0:637031152314 625
gkroussos 0:637031152314 626 #define __PKHBT(ARG1,ARG2,ARG3) \
gkroussos 0:637031152314 627 ({ \
gkroussos 0:637031152314 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
gkroussos 0:637031152314 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
gkroussos 0:637031152314 630 __RES; \
gkroussos 0:637031152314 631 })
gkroussos 0:637031152314 632
gkroussos 0:637031152314 633 #define __PKHTB(ARG1,ARG2,ARG3) \
gkroussos 0:637031152314 634 ({ \
gkroussos 0:637031152314 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
gkroussos 0:637031152314 636 if (ARG3 == 0) \
gkroussos 0:637031152314 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
gkroussos 0:637031152314 638 else \
gkroussos 0:637031152314 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
gkroussos 0:637031152314 640 __RES; \
gkroussos 0:637031152314 641 })
gkroussos 0:637031152314 642
gkroussos 0:637031152314 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
gkroussos 0:637031152314 644 {
gkroussos 0:637031152314 645 int32_t result;
gkroussos 0:637031152314 646
gkroussos 0:637031152314 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
gkroussos 0:637031152314 648 return(result);
gkroussos 0:637031152314 649 }
gkroussos 0:637031152314 650
gkroussos 0:637031152314 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:637031152314 652
gkroussos 0:637031152314 653
gkroussos 0:637031152314 654
gkroussos 0:637031152314 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
gkroussos 0:637031152314 656 /* TASKING carm specific functions */
gkroussos 0:637031152314 657
gkroussos 0:637031152314 658
gkroussos 0:637031152314 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:637031152314 660 /* not yet supported */
gkroussos 0:637031152314 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gkroussos 0:637031152314 662
gkroussos 0:637031152314 663
gkroussos 0:637031152314 664 #endif
gkroussos 0:637031152314 665
gkroussos 0:637031152314 666 /*@} end of group CMSIS_SIMD_intrinsics */
gkroussos 0:637031152314 667
gkroussos 0:637031152314 668
gkroussos 0:637031152314 669 #endif /* __CORE_CM4_SIMD_H */
gkroussos 0:637031152314 670
gkroussos 0:637031152314 671 #ifdef __cplusplus
gkroussos 0:637031152314 672 }
gkroussos 0:637031152314 673 #endif