Mike Moore / Mbed 2 deprecated USB_device_project

USB Device Programming class project. This project allows a Python/Tk program running on a PC host to monitor/control a test-CPU programmed into an altera development board.

Dependencies:   C12832_lcd USBDevice mbed-rtos mbed mmSPI

mmRTL/main_memory.txt@12:d10f526ca443, 2013-09-01 (annotated)

Committer:
gatedClock
Date:
Sun Sep 01 22:02:19 2013 +0000
Revision:
12:d10f526ca443
Parent:
7:d1aca9ccbab8 
cpu add comments.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 3:659ffc90b59e 1 /*----------------------------------copyright---------------------------------*/
gatedClock 7:d1aca9ccbab8 2 // licensed for personal and academic use.
gatedClock 7:d1aca9ccbab8 3 // commercial use must be approved by the account-holder of
gatedClock 7:d1aca9ccbab8 4 // gated.clock@gmail.com
gatedClock 3:659ffc90b59e 5 /*-----------------------------------module-----------------------------------*/
gatedClock 7:d1aca9ccbab8 6 module main_memory
gatedClock 3:659ffc90b59e 7 (
gatedClock 7:d1aca9ccbab8 8 iReadAddress1, // read-address 1.
gatedClock 7:d1aca9ccbab8 9 iReadAddress0, // read-address 0.
gatedClock 7:d1aca9ccbab8 10 iWriteAddress, // write-address.
gatedClock 7:d1aca9ccbab8 11 oReadData1, // read-data 1.
gatedClock 7:d1aca9ccbab8 12 oReadData0, // read-data 0.
gatedClock 7:d1aca9ccbab8 13 iWriteData, // write-data.
gatedClock 7:d1aca9ccbab8 14 iWE, // write-enable.
gatedClock 7:d1aca9ccbab8 15 iCPUclk // cpu clock.
gatedClock 3:659ffc90b59e 16 );
gatedClock 3:659ffc90b59e 17 /*--------------------------------description-----------------------------------
gatedClock 7:d1aca9ccbab8 18 CPU main memory.
gatedClock 7:d1aca9ccbab8 19 two read-ports, one write-port.
gatedClock 3:659ffc90b59e 20 -------------------------------------notes--------------------------------------
gatedClock 7:d1aca9ccbab8 21 level-sensitive write-enable.
gatedClock 7:d1aca9ccbab8 22 the memory needs to be sixteen bits wide in order to hold
gatedClock 7:d1aca9ccbab8 23 immediate data for the instruction set.
gatedClock 3:659ffc90b59e 24 ------------------------------------defines-----------------------------------*/
gatedClock 3:659ffc90b59e 25 /*-----------------------------------ports------------------------------------*/
gatedClock 7:d1aca9ccbab8 26 input [ 7:0] iReadAddress1; // read-address 1.
gatedClock 7:d1aca9ccbab8 27 input [ 7:0] iReadAddress0; // read-address 0.
gatedClock 7:d1aca9ccbab8 28 input [ 7:0] iWriteAddress; // write-address.
gatedClock 7:d1aca9ccbab8 29 output [15:0] oReadData1; // read-data 1.
gatedClock 7:d1aca9ccbab8 30 output [15:0] oReadData0; // read-data 0.
gatedClock 7:d1aca9ccbab8 31 input [15:0] iWriteData; // write-data.
gatedClock 7:d1aca9ccbab8 32 input iWE; // write-enable.
gatedClock 7:d1aca9ccbab8 33 input iCPUclk; // cpu clock.
gatedClock 3:659ffc90b59e 34 /*-----------------------------------wires------------------------------------*/
gatedClock 7:d1aca9ccbab8 35 wire [ 7:0] iReadAddress1; // read-address 1.
gatedClock 7:d1aca9ccbab8 36 wire [ 7:0] iReadAddress0; // read-address 0.
gatedClock 7:d1aca9ccbab8 37 wire [ 7:0] iWriteAddress; // write-address.
gatedClock 7:d1aca9ccbab8 38 wire [15:0] oReadData1; // read-data 1.
gatedClock 7:d1aca9ccbab8 39 wire [15:0] oReadData0; // read-data 0.
gatedClock 7:d1aca9ccbab8 40 wire [15:0] iWriteData; // write-data.
gatedClock 7:d1aca9ccbab8 41 wire iWE; // write-enable.
gatedClock 7:d1aca9ccbab8 42 wire iCPUclk; // cpu clock.
gatedClock 3:659ffc90b59e 43 /*---------------------------------registers----------------------------------*/
gatedClock 7:d1aca9ccbab8 44 reg [15:0] mem_bank [0:255]; // memory bank.
gatedClock 7:d1aca9ccbab8 45 reg [15:0] rData1; // data-out-1 register.
gatedClock 7:d1aca9ccbab8 46 reg [15:0] rData0; // data-out-0 register.
gatedClock 3:659ffc90b59e 47 /*---------------------------------variables----------------------------------*/
gatedClock 3:659ffc90b59e 48 /*---------------------------------parameters---------------------------------*/
gatedClock 3:659ffc90b59e 49 /*-----------------------------------clocks-----------------------------------*/
gatedClock 3:659ffc90b59e 50 /*---------------------------------instances----------------------------------*/
gatedClock 3:659ffc90b59e 51 /*-----------------------------------logic------------------------------------*/
gatedClock 7:d1aca9ccbab8 52 always @ (posedge iCPUclk)
gatedClock 7:d1aca9ccbab8 53 if (iWE) mem_bank[iWriteAddress] = iWriteData;
gatedClock 7:d1aca9ccbab8 54 else mem_bank[iWriteAddress] = mem_bank[iWriteAddress];
gatedClock 3:659ffc90b59e 55
gatedClock 7:d1aca9ccbab8 56 assign oReadData1 = mem_bank[iReadAddress1];
gatedClock 7:d1aca9ccbab8 57 assign oReadData0 = mem_bank[iReadAddress0];
gatedClock 3:659ffc90b59e 58 /*-------------------------------*/endmodule/*--------------------------------*/
gatedClock 3:659ffc90b59e 59
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