Mike Moore / Mbed 2 deprecated RTOS_project_fork_01

embedded RTOS class project.

Fork of RTOS_project by Mike Moore

mmRTL/reg_16.txt@0:8e898e1270d6, 2013-09-17 (annotated)

Committer:
gatedClock
Date:
Tue Sep 17 19:42:49 2013 +0000
Revision:
0:8e898e1270d6
title.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 0:8e898e1270d6 1 /*----------------------------------copyright---------------------------------*/
gatedClock 0:8e898e1270d6 2 // licensed for personal and academic use.
gatedClock 0:8e898e1270d6 3 // commercial use must be approved by the account-holder of
gatedClock 0:8e898e1270d6 4 // gated.clock@gmail.com
gatedClock 0:8e898e1270d6 5 /*-----------------------------------module-----------------------------------*/
gatedClock 0:8e898e1270d6 6 module reg_16
gatedClock 0:8e898e1270d6 7 (
gatedClock 0:8e898e1270d6 8 oParallel, // parallel-output data.
gatedClock 0:8e898e1270d6 9 iParallel1, // parallel-input data.
gatedClock 0:8e898e1270d6 10 iParallel0, // parallel-input data.
gatedClock 0:8e898e1270d6 11 iSel, // select the parallel input.
gatedClock 0:8e898e1270d6 12 oSerial, // serial-output data.
gatedClock 0:8e898e1270d6 13 iSerial, // serial-input data.
gatedClock 0:8e898e1270d6 14 iLoadEnable, // parallel-load-enable.
gatedClock 0:8e898e1270d6 15 iShiftEnable, // serial-shift-enable.
gatedClock 0:8e898e1270d6 16 iResetN, // synchronous reset*.
gatedClock 0:8e898e1270d6 17 iClk // module clock.
gatedClock 0:8e898e1270d6 18 );
gatedClock 0:8e898e1270d6 19 /*--------------------------------description-----------------------------------
gatedClock 0:8e898e1270d6 20 a 16-bit parallel shift-register with 2 selectable input buses.
gatedClock 0:8e898e1270d6 21 -------------------------------------notes--------------------------------------
gatedClock 0:8e898e1270d6 22 shifting is LSB->MSB.
gatedClock 0:8e898e1270d6 23 ------------------------------------defines-----------------------------------*/
gatedClock 0:8e898e1270d6 24 /*-----------------------------------ports------------------------------------*/
gatedClock 0:8e898e1270d6 25 output [15:0] oParallel; // parallel-output data.
gatedClock 0:8e898e1270d6 26 input [15:0] iParallel1; // parallel-input data.
gatedClock 0:8e898e1270d6 27 input [15:0] iParallel0; // parallel-input data.
gatedClock 0:8e898e1270d6 28 input iSel; // select the parallel input.
gatedClock 0:8e898e1270d6 29 output oSerial; // serial-output data.
gatedClock 0:8e898e1270d6 30 input iSerial; // serial-input data.
gatedClock 0:8e898e1270d6 31 input iLoadEnable; // parallel-load-enable.
gatedClock 0:8e898e1270d6 32 input iShiftEnable; // serial-shift-enable.
gatedClock 0:8e898e1270d6 33 input iResetN; // synchronous reset*.
gatedClock 0:8e898e1270d6 34 input iClk; // module clock.
gatedClock 0:8e898e1270d6 35 /*-----------------------------------wires------------------------------------*/
gatedClock 0:8e898e1270d6 36 wire [15:0] oParallel; // parallel-output data.
gatedClock 0:8e898e1270d6 37 wire [15:0] iParallel1; // parallel-input data.
gatedClock 0:8e898e1270d6 38 wire [15:0] iParallel0; // parallel-input data.
gatedClock 0:8e898e1270d6 39 wire iSel; // select the parallel input.
gatedClock 0:8e898e1270d6 40 wire [15:0] wParallelIn; // select the parallel input.
gatedClock 0:8e898e1270d6 41 wire oSerial; // serial-output data.
gatedClock 0:8e898e1270d6 42 wire iSerial; // serial-input data.
gatedClock 0:8e898e1270d6 43 wire iLoadEnable; // parallel-load-enable.
gatedClock 0:8e898e1270d6 44 wire iShiftEnable; // serial-shift-enable.
gatedClock 0:8e898e1270d6 45 wire iResetN; // synchronous reset*.
gatedClock 0:8e898e1270d6 46 wire iClk; // module clock.
gatedClock 0:8e898e1270d6 47 /*---------------------------------registers----------------------------------*/
gatedClock 0:8e898e1270d6 48 reg [15:0] rRegister; // the register.
gatedClock 0:8e898e1270d6 49 /*---------------------------------variables----------------------------------*/
gatedClock 0:8e898e1270d6 50 /*---------------------------------parameters---------------------------------*/
gatedClock 0:8e898e1270d6 51 /*-----------------------------------clocks-----------------------------------*/
gatedClock 0:8e898e1270d6 52 /*---------------------------------instances----------------------------------*/
gatedClock 0:8e898e1270d6 53 mux16x2 U0_mux16x2 // data-input selection.
gatedClock 0:8e898e1270d6 54 (
gatedClock 0:8e898e1270d6 55 .iDin1(iParallel1),
gatedClock 0:8e898e1270d6 56 .iDin0(iParallel0),
gatedClock 0:8e898e1270d6 57 .iSel (iSel),
gatedClock 0:8e898e1270d6 58 .oDout(wParallelIn)
gatedClock 0:8e898e1270d6 59 );
gatedClock 0:8e898e1270d6 60 /*-----------------------------------logic------------------------------------*/
gatedClock 0:8e898e1270d6 61 always @ (posedge iClk or negedge iResetN)
gatedClock 0:8e898e1270d6 62 begin
gatedClock 0:8e898e1270d6 63 if (!iResetN) rRegister <= 16'h0000;
gatedClock 0:8e898e1270d6 64 else if (iLoadEnable) rRegister <= wParallelIn;
gatedClock 0:8e898e1270d6 65 else if (iShiftEnable) rRegister <= {rRegister[14:0], iSerial};
gatedClock 0:8e898e1270d6 66 else rRegister <= rRegister;
gatedClock 0:8e898e1270d6 67 end
gatedClock 0:8e898e1270d6 68
gatedClock 0:8e898e1270d6 69 assign oParallel = rRegister; // propagate parallel-out.
gatedClock 0:8e898e1270d6 70 assign oSerial = rRegister[15]; // propagate serial-out.
gatedClock 0:8e898e1270d6 71 /*-------------------------------*/endmodule/*--------------------------------*/
gatedClock 0:8e898e1270d6 72