Mike Moore / Mbed 2 deprecated RTOS_project_fork_01

embedded RTOS class project.

Fork of RTOS_project by Mike Moore

mmRTL/mux16x2.txt@0:8e898e1270d6, 2013-09-17 (annotated)

Committer:
gatedClock
Date:
Tue Sep 17 19:42:49 2013 +0000
Revision:
0:8e898e1270d6
title.

Who changed what in which revision?

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gatedClock 0:8e898e1270d6 1 /*----------------------------------copyright---------------------------------*/
gatedClock 0:8e898e1270d6 2 // licensed for personal and academic use.
gatedClock 0:8e898e1270d6 3 // commercial use must be approved by the account-holder of
gatedClock 0:8e898e1270d6 4 // gated.clock@gmail.com
gatedClock 0:8e898e1270d6 5 /*-----------------------------------module-----------------------------------*/
gatedClock 0:8e898e1270d6 6 module mux16x2
gatedClock 0:8e898e1270d6 7 (
gatedClock 0:8e898e1270d6 8 iDin1, // data-input 1.
gatedClock 0:8e898e1270d6 9 iDin0, // data-input 0.
gatedClock 0:8e898e1270d6 10 iSel, // multiplexor select.
gatedClock 0:8e898e1270d6 11 oDout // data-out.
gatedClock 0:8e898e1270d6 12 );
gatedClock 0:8e898e1270d6 13 /*--------------------------------description-----------------------------------
gatedClock 0:8e898e1270d6 14 a 16-bit-wide, 2-selection multiplexor.
gatedClock 0:8e898e1270d6 15 -------------------------------------notes--------------------------------------
gatedClock 0:8e898e1270d6 16 ------------------------------------defines-----------------------------------*/
gatedClock 0:8e898e1270d6 17 /*-----------------------------------ports------------------------------------*/
gatedClock 0:8e898e1270d6 18 input [15:0] iDin1; // data-input 1.
gatedClock 0:8e898e1270d6 19 input [15:0] iDin0; // data-input 0.
gatedClock 0:8e898e1270d6 20 input iSel; // multiplexor select.
gatedClock 0:8e898e1270d6 21 output [15:0] oDout; // data-out.
gatedClock 0:8e898e1270d6 22 /*-----------------------------------wires------------------------------------*/
gatedClock 0:8e898e1270d6 23 wire [15:0] iDin1; // data-input 1.
gatedClock 0:8e898e1270d6 24 wire [15:0] iDin0; // data-input 0.
gatedClock 0:8e898e1270d6 25 wire iSel; // multiplexor select.
gatedClock 0:8e898e1270d6 26 wire [15:0] oDout; // data-out.
gatedClock 0:8e898e1270d6 27 /*---------------------------------registers----------------------------------*/
gatedClock 0:8e898e1270d6 28 reg [15:0] rDout; // output register.
gatedClock 0:8e898e1270d6 29 /*---------------------------------variables----------------------------------*/
gatedClock 0:8e898e1270d6 30 /*---------------------------------parameters---------------------------------*/
gatedClock 0:8e898e1270d6 31 /*-----------------------------------clocks-----------------------------------*/
gatedClock 0:8e898e1270d6 32 /*---------------------------------instances----------------------------------*/
gatedClock 0:8e898e1270d6 33 /*-----------------------------------logic------------------------------------*/
gatedClock 0:8e898e1270d6 34 always @ (iDin1 or iDin0 or iSel)
gatedClock 0:8e898e1270d6 35 case (iSel)
gatedClock 0:8e898e1270d6 36 1 : rDout = iDin1;
gatedClock 0:8e898e1270d6 37 0 : rDout = iDin0;
gatedClock 0:8e898e1270d6 38 endcase
gatedClock 0:8e898e1270d6 39
gatedClock 0:8e898e1270d6 40 assign oDout = rDout; // propagate output.
gatedClock 0:8e898e1270d6 41 /*-------------------------------*/endmodule/*--------------------------------*/
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